POLYCRYSTALLINE SILICON CARBIDE SUPPORT FOR A SUBSTRATE INTENDED TO RECEIVE POWER SEMICONDUCTOR DEVICES AND SUBSTRATE COMPRISING SUCH A SUPPORT.

Abstract

The invention relates to a polycrystalline silicon carbide support for a substrate intended to receive a power semiconductor device. The support has a first face, designated "front face" and a second face designated "back face" and comprises a first surface layer arranged directly under the front face and having a resistivity greater than or equal to 1 ohm.cm and a second surface layer arranged directly under the back face and having a resistivity strictly less than 1 ohm.cm. Figure 3

Description

Title of the invention: POLYCRYSTALLINE SILICON CARBIDE SUPPORT FOR A SUBSTRATE INTENDED TO RECEIVE POWER SEMICONDUCTOR DEVICES AND SUBSTRATE COMPRISING SUCH A SUPPORT. FIELD OF THE INVENTION

[0001] The present invention relates to substrates intended to receive semiconductor devices, in particular devices serving applications requiring high electrical power. These may be devices based on IILN materials, such as gallium nitride. The invention also relates to a support particularly suitable for forming such a substrate. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] Transistors based on IILN materials, of the HEMT type ("High Electron Mobility Transistor" according to the Anglo-Saxon terminology or high electron mobility transistor) find some of their applications in the field of management of significant electrical power, for example as switches in power converters.

[0003] As shown schematically in [Fig.l], such a component 1 puts conventionally implemented: - a substrate 2 which may typically be a silicon, sapphire or silicon carbide wafer; - a buffer layer 3, generally doped to be semi-insulating, formed on the substrate 2; - a heterojunction consisting of a GaN channel layer 5 and a layer 6 AlGaN barriers successively formed on the buffer layer; - source S, drain D and gate G electrode structures on / in the heterojunction. - A metal sheet M in ohmic contact with the rear face of the support 2. The sheet M may be the copper lead frame of a semiconductor chip package. An adhesion layer B, for example a sintered silver paste, may be used to reliably adhere the rear face of the support 2 to the metal sheet M.

[0004] The metal sheet M helps to promote the evacuation of the heat produced at the heterojunction during operation of the device. Generally, the source electrode S is electrically connected to the substrate 2, so as to prevent the potential of this substrate remains floating. The electrically on state of the transistor between the source S and the drain D is controlled by the voltage applied to the gate G. In the case of power application, the voltage VDS which applies to the terminals of the electrodes of source S and drain D can then reach a few hundred volts to several thousand volts when the transistor is blocked. The leakage current flowing between the source S and the drain D in the blocked state is low, of the order of a few nanoamperes. In the on state, on the contrary, several amperes can flow between the source S and the drain D. In addition, the switching between the on state and the blocking state is very fast, of the order of a few nanoseconds.

[0005] However, several problems limit the diffusion of this technology.

[0006] As seen, in the blocking state, a high voltage is applied to the terminals of the source electrodes S and drain D. This leads to the formation of an electric field whose lines penetrate very deeply into the buffer layer 3 and the substrate 2. An electric field then develops between the drain electrode D and the substrate 2, in particular in the thickness of the buffer layer 3, and between the source S and the drain D. In order to prevent the intensity of this field from exceeding the critical value (called the breakdown field) beyond which the material can no longer support it, provision must be made to separate the drain D and the source S by a sufficient distance d so that, for a given voltage VDs, the intensity of the field E = VDs / d is less than the breakdown field.In the same way, it is possible to provide a buffer layer 3 of sufficient thickness so that the value of the electric field at the interface between the buffer layer 3 and the substrate 2 is lower than the limit admissible by the materials in question.

[0007] It is relatively easy to choose the distance d separating the drain electrode D from the source S when designing the transistor. Thus, for a voltage VDS of the order of 400 V to 2000 V, a distance d of the order of 5 to 20 microns can be chosen. But increasing this distance has limits, because this tends to increase the size of the HEMT device and therefore to make it more expensive and less compact.

[0008] Providing a device 1 having a buffer layer 3 made of sufficiently thick IILN materials (of the order of 3 microns or more) is however much more difficult, in particular when the substrate 2 is chosen from large silicon (200 mm in diameter) rather than sapphire, for reasons of availability and cost. This is notably due to the difference between the coefficient of thermal expansion of silicon and that of the IILN material which forms the buffer layer. This layer is produced by high-temperature deposition on the silicon substrate, and returning to ambient temperature leads to putting this layer under very high stresses, which can lead to cracking, or even breaking the substrate, if the stresses are too high. It is generally difficult to provide a buffer layer more than 3 microns thick on a silicon substrate in the form of a 200 mm wafer.

[0009] One could naturally seek to replace the silicon substrate with a substrate having a thermal expansion coefficient closer to that of the buffer layer material in order to remove this constraint. This could for example involve using a silicon carbide substrate. But, in addition to the fact that this material in its crystalline form is particularly unavailable and expensive, it must also be metallized and treated to form an ohmic contact with the metal sheet M. The document "Ohmic contacts to SiC" International Journal of High Speed ​​Electronics and Systems, Vol. 15, No. 04, pp. 781-820 (2005) points out that a metal layer-SiC contact is generally non-ohmic in nature just after the deposition of the metal layer.It is then necessary to thermally treat, for example by a laser, this interface to promote the formation of silicides, carbides or ternary phases leading to making the contact effectively ohmic in nature. It would be desirable to simplify the packaging of the device. SUBJECT OF THE INVENTION

[0010] An aim of the invention is to propose a support for a substrate intended to receive a power semiconductor device which addresses, at least in part, these problems. More particularly, an aim of the invention is to propose a support for a substrate capable of receiving a relatively thick buffer layer, preferably having a thickness greater than or equal to 5 microns, and which can be integrated into a package with simplicity, without requiring the application of heat treatment to the face which receives the adhesion layer. An aim of the invention is to propose a substrate which exploits such a support and a semiconductor component formed on / in such a substrate. BRIEF DESCRIPTION OF THE INVENTION

[0011] With a view to achieving one of these aims, the subject of the invention provides a polycrystalline silicon carbide support for a substrate intended to receive a power semiconductor device. The support comprises a first face, designated "front face" and a second face opposite the first and designated "rear face". The support comprises: - a first surface layer placed directly under the front face and having a resistivity greater than or equal to 1 ohm.cm and; - a second surface layer placed directly under the rear face and having a resistivity strictly less than 1 ohm.cm.

[0012] According to other advantageous and non-limiting characteristics of the invention, taken alone or in any technically feasible combination: the second layer has a minimum thickness of 10 micrometers or more; • the second layer having a concentration of n-type dopants, such as nitrogen, greater than 10A20 at / cmA3; • the n-type dopant concentration increases monotonically from the front face to the second surface layer; • the first layer is not intentionally doped or has a vanadium concentration greater than 10A15 at / cmA3; • the support has a total thickness, between the first face and the second face, of between 200 micrometers and 1 mm; • the support comes in the form of a circular plate, advantageously 200 mm in diameter

[0013] According to another aspect, the object of the invention provides a substrate intended to receive a semiconductor device comprising a support as described previously and a seed layer, transferred onto the front face of the support.

[0014] According to other advantageous and non-limiting characteristics of this aspect of the invention, taken alone or in any technically feasible combination: - the seed layer is made of gallium nitride, silicon carbide, sapphire or silicon (1,1,1); - the substrate comprises a dielectric bonding layer arranged between, and in contact with, the support and the seed layer, preferably a dielectric bonding layer made of silicon nitride; - the seed layer directly contacts the support; - a buffer layer based on gallium nitride, preferably semi-insulating, is arranged on the seed layer; - the buffer layer has a thickness greater than 3 microns, preferably greater than 5 micrometers and even more preferably between 5 micrometers and 10 micrometers; - the substrate comprises a heterojunction arranged on the buffer layer, the heterojunction comprising a channel layer and a barrier layer and being capable of forming a 2D electron gas.

[0015] According to yet another aspect, the invention provides a semiconductor component comprising a substrate as described above and a source structure, a drain structure and a gate structure arranged on the heterojunction.

[0016] Advantageously, a metal sheet is arranged under the rear face of the support, in ohmic contact with a metal layer deposited on the second surface layer. An adhesion layer, such as a layer of sintered silver paste, may be arranged between the metal sheet and the metal layer deposited on the second surface layer. Brief description of the drawings

[0017] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which:

[0018] [Fig.l]

[0019] [Fig.l] represents a substrate provided with a HEMT transistor according to the state of the art;

[0020] [Fig.2a][Fig.2b]

[0021] Figures 2a, 2b represent two substrates intended to receive semiconductor devices according to the invention;

[0022] [Fig.3]

[0023] [Fig. 3] represents a semiconductor component formed from a substrate according to the invention. DETAILED DESCRIPTION OF THE INVENTION

[0024] For the sake of simplification of the description to come, the same references are used for identical elements or elements ensuring the same function in the different modes of implementation of the invention or in the presentation of the state of the art.

[0025] Figures 2a, 2b show two embodiments of a substrate 2 intended to receive a power semiconductor device and which is the subject of the present description. As briefly explained in the introduction to this application, this substrate 2 is intended to receive at least one device comprising a buffer layer made of IILN material several microns thick, a heterojunction comprising a channel layer and a barrier layer on the buffer layer and source, drain and gate structures arranged on the heterojunction.

[0026] The substrate 2, when it is still devoid of devices, is advantageously in the form of a circular wafer, the diameter of which is standardized so that it can be handled by standard equipment in the semiconductor industry. Advantageously, a diameter of 200 mm will be chosen.

[0027] After the steps of forming the devices and their singularization, chips are formed, as is well known per se, which are intended to integrate packages to form a semiconductor component. The substrate 2, when incorporated into a chip, then takes the form of a rectangular parallelepiped whose sides are of the order of mm or cm. General presentation of substrate 2

[0028] Whatever the form adopted by the substrate 2, it comprises in a very general manner a support 2a and a seed layer 2c transferred onto the support 2a. In the embodiment of [Fig.2a], a dielectric bonding layer 2b is arranged between, and in contact with, the support 2a and the seed layer 2c. In the embodiment of [Fig.2a], a dielectric bonding layer 2b is arranged between, and in contact with, the support 2a and the seed layer 2c. lization of [Fig.2b], the substrate 2 is devoid of a dielectric bonding layer and the seed layer 2c is transferred directly onto the support 2a, in contact with this support 2a.

[0029] The support 2a is entirely made of polycrystalline silicon carbide. It comprises a first face, designated the “front face” and a second face opposite the first and designated the “back face”. The seed layer is transferred onto the front face of the support, directly or via the dielectric bonding layer 2c. The main function of the support 2a is to mechanically support the rest of the stack leading to the formation of a functional semiconductor component, as will be explained in a later section of this detailed description. For this purpose, it has a thickness, taken between its front face and its back face, which is relatively large and typically between 200 micrometers and 1 mm.

[0030] The seed layer 2c, for its part, has the function of providing an exposed surface of the support 2 which is capable of receiving the buffer layer 3 of the device. The nature of this layer is therefore chosen to offer a lattice parameter adapted to that of the IILN material forming the buffer layer 3, typically gallium nitride, in order to facilitate its growth by epitaxy on the support 2. It can therefore be gallium nitride, silicon carbide, sapphire, silicon (1,1,1), in all cases in their monocrystalline form. It is not necessary for this seed layer 2c to be thick, because only its surface properties are exploited, and a relatively small thickness will therefore be chosen, less than 2 micrometers.

[0031] The function of the dielectric bonding layer 2c is to facilitate the manufacture of the substrate 2, as will be explained later. It will be preferable to choose a dielectric material having a good thermal diffusion coefficient, such as silicon nitride, and its thickness will be minimized, preferably less than 1 micrometer, so as not to affect the thermal properties of the substrate 2, as will be presented a little later.

[0032] It is noted that the seed layer 2c is significantly less thick than the thickness of the support 2a. Consequently, and by compliance effect, it undergoes the deformations imposed on it by the support 2a, when for example the substrate 2 is exposed to significant temperature variations of several hundred degrees as is the case during the epitaxial formation of the buffer layer 3. In other words, the deformation of the substrate 2 caused by its exposure to a significant temperature variation is dictated by the behavior of the support 2a. It is to favor this compliance effect that it is preferred to choose the thickness of the seed layer relatively low, less than 2 micrometers as already specified.

[0033] It is also noted that the polycrystalline silicon carbide from which the support 2a is formed has a coefficient of thermal expansion close to the IILN material from which the support 2a is formed. composed of the buffer layer 3, in particular when this buffer layer 3 is made of gallium nitride. Also, after the formation by high-temperature epitaxy of the buffer layer 3 and when the substrate 2 provided with this layer is brought back to room temperature, few stresses develop in the structure. It is therefore possible to form a buffer layer 3 much thicker than that which can be formed on a substrate of the state of the art, made of silicon. In particular, it is possible to form a buffer layer 3 having a thickness of at least 3 micrometers, preferably greater than 5 micrometers and even more preferably between 5 micrometers and 10 micrometers.

[0034] Finally, the polycrystalline silicon carbide from which the support 2a is formed (which represents the major part of the substrate 2), has thermal diffusion properties which allow efficient evacuation of the heat produced at the device. It is recalled that this device being preferably intended to process a significant electrical power, it has a tendency to heat up, and it is necessary to evacuate the heat produced so as not to affect its proper operation. Thus, the thermal diffusion coefficient of the polycrystalline silicon carbide is approximately three times greater than that of the silicon from which a substrate of the prior art is made. By improving the thermal conductivity of the substrate 2 in comparison with a substrate of the prior art, it is also possible to increase the power density processed at the device.

[0035] According to an important characteristic of the support 2a, the latter comprises a first surface layer Cl, arranged directly under the front face, which has a resistivity greater than or equal to 1 ohm.cm, and advantageously greater than 10A3 ohms.cm. In the presence of a high intensity electric field whose lines extend into the depth of the substrate 2, and in particular in this first surface layer Cl of the support, the resistive nature of this first surface layer Cl makes it possible to raise the breakdown voltage. The device can therefore withstand high drain-source voltages, of more than 1000V, without risking damage to the device.

[0036] To obtain these resistivity values, the first Cl layer is of intrinsic nature, that is to say that it is not intentionally doped. Alternatively, it can be doped with vanadium in a concentration greater than 10A15 at / cmA3, in order to further increase its resistivity.

[0037] The support 2a also comprises a second surface layer C2, this time arranged directly under the rear face. This second surface layer C2 has a resistivity strictly less than 1 ohm.cm, and may be less than 50 milliohm.cm or 10 milliohm.cm. This low resistivity, which can be obtained by n-type doping in a concentration of dopants (for example nitrogen) greater than 10A20 at / cmA3, makes it possible to give the rear face of the substrate an almost metallic behavior, and therefore to receive a layer of metal or metal alloys, by deposition, without the need for heat treatment before applying a process for assembling this face to a metal sheet, during the packaging step.

[0038] It is not necessary for this second surface layer C2 to be very thick, it nevertheless has a thickness greater than 10 micrometers.

[0039] Preferably, the first layer C1 extends in the depth of the support 2 up to the second heavily doped layer C2. There may of course be a transition zone between these two layers C1, C2, in order to control the doping gradient necessary for this transition. It is in particular possible to envisage that the concentration of n-type dopant in the support 2a increases monotonically from the front face to the second surface layer C2.

[0040] But in all cases, and whatever the way in which the dopants are distributed in the thickness of the support 2a, the latter has a first surface layer C1 arranged directly under the front face, as close as possible to the device, resistive or highly resistive to counter the effects of the electric fields which can develop there. The support 2a also has a second surface layer C2, arranged directly under the rear face, very weakly resistive to give it a metallic behavior favoring its robust assembly to a metal sheet when the device is packaged.

[0041] Manufacture of the polycrystalline silicon carbide support

[0042] The manufacture of a polycrystalline silicon carbide support in accordance with the invention, and therefore having the first and second surface layers C1, C2, uses a chemical vapor deposition (CVD) technique. This technique involves a gas mixture comprising at least one silicon precursor gas (such as a silane or a chlorosilane) and / or at least one carbon precursor gas (such as an alkane or an alkene), and / or at least one silicon and carbon precursor gas (such as methyltrichlorosilane, abbreviated MTCS) to form the bulk part of the support 2a.

[0043] It also involves at least one n-type doping gas to, at a minimum, form the second surface layer C2. In the case of nitrogen doping of this second surface layer C2, the doping gas could for example be NH3, N2H4, N2).

[0044] For the vanadium doping of the first surface layer Cl, in the case where such doping is planned, it will be possible to take, for example, a doping gas of vanadium chloride (VC12, for example).

[0045] These gases may be diluted in a carrier gas, which may be a reducing gas such as hydrogen and / or an inert gas such as argon. From this gas mixture, the layer of polycrystalline silicon carbide forms on a so-called “growth” substrate.

[0046] The gas mixture is admitted into a reactor located at high temperature where the precursor gases are decomposed and react on the surface of the growth substrate, preferably made of purified fine-grained isostatic graphite, to form a layer of polycrystalline silicon carbide, for example polytype 3C, whose mechanical and thermal resistance properties, thermal expansion coefficient and purity are perfectly suited to its use as support 2a of the substrate 2. The polytype 3C can, moreover, be doped with nitrogen up to very high levels, of the order of 1020 atoms / cm3, and thus have a resistivity of less than 10 mOhm.cm.

[0047] The temperature of the reactor during CVD deposition of silicon carbide must be between approximately 1000°C and approximately 1600°C, preferably between approximately 1100°C and approximately 1400°C, or even between approximately 1200°C and approximately 1400°C. In this temperature range, the deposition rates can vary within fairly wide ranges, from micrometer / h to more than 100 micrometers / h. Advantageously, the total pressure in the reactor does not exceed 350 mbar, or even 300 mbar.

[0048] To form a support 2a according to the invention, the flow of n-type doping gas is controlled, to form at the start of the growth process, possibly after the formation of a seed thickness on the graphite surface, a layer of doped polycrystalline silicon carbide sufficiently thick to ultimately constitute, after all the finishing steps described below, the second surface layer C2 of the support 2a. This may involve forming an n-type doped layer during this growth, which is 2 to 10 times thicker than the thickness expected in this support, which is recalled to be typically greater than 10 micrometers after possible thinning of the substrate.

[0049] During this deposition phase, after having formed the heavily n-doped thickness, the flow of n-type doping gas can either be interrupted to form the remainder of the thickness in intrinsic, non-intentionally doped polycrystalline silicon carbide. Alternatively, a flow of vanadium-based doping gas can be circulated, in order to further increase the resistivity of the material intended to form the first CL surface layer.

[0050] At the end of this deposition phase, the graphite growth substrate, coated with a layer of polycrystalline silicon carbide deposition, is machined, then oxidized in air typically at 900°C to remove any graphite residue and provide a raw polycrystalline silicon carbide disc. Note that the removal of the graphite could also be carried out by purely mechanical machining techniques or even essentially by burning / oxidation.

[0051] It is noted that it is possible to form, during the deposition phase, a very significant thickness of polycrystalline silicon carbide to constitute an ingot of material. It is then possible to take slices from this ingot, by cutting, each slice forming a raw silicon carbide disc. In this approach, care will be taken to insert, during the growth of the ingot, highly n-doped intercalary layers (which will be intended to form second surface layers C2) between intrinsic or vanadium-based doped layers (which will be intended to form first surface layers Cl). The ingot will be chosen to be cut in positions allowing, after all the finishing steps described below, to form supports in accordance with the invention.

[0052] In any event, a raw polycrystalline silicon carbide disc resulting from the deposition phase is then mechanically and thermally treated to form the support 2a to the chosen dimensions. These may involve thinning steps by coarse then fine grinding. They may be followed by a polishing step, in order to provide a satisfactory surface condition, in terms of roughness. These grinding or polishing steps, known from the state of the art, aim in particular to eliminate a sufficient thickness from the side of the face of the disc which was in contact with the graphite, to remove the initial growth zone of the crystals, generating high stresses.They also make it possible, by removing material from both sides of the raw disc, to obtain a support 2a of polycrystalline silicon carbide which is in the form of a wafer, for example a wafer having a diameter of 200 mm and a thickness typically between 350 micrometers and 500 micrometers, but which can extend for example between 200 nm and 1 mm. Manufacture of the substrate 2.

[0053] Very generally, the substrate 2 can be produced by a manufacturing method by transferring a seed layer onto the support 2a, the preparation of which has just been described. Such a transfer method comprises: - the assembly, possibly via a dielectric bonding layer 2b, of the first face of the support 2a and a main face of a donor substrate in order to constitute an intermediate structure; - the elimination of a part of the donor substrate from the intermediate structure to define the seed layer 2c, transferred to the support 2a.

[0054] The dielectric bonding layer 2b can be formed, by deposition and prior to the assembly step, on the donor substrate or on the front face of the support 2a or partly on one and the other of these two elements. The dielectric bonding layer 2b can thus be produced using an LPCVD technique (acronym for the English expression "Low Pressure Chemical Vapor Deposition" or chemical vapor deposition at subatmospheric pressure) or PECVD (acronym for the English expression Saxon "Plasma Enhanced Chemical Vapor Deposition" or plasma-assisted chemical vapor deposition). As already mentioned, this layer is advantageously made of silicon nitride, for reasons of thermal diffusivity.

[0055] By "donor substrate", we mean a substrate made of the material of the seed layer 2c, or comprising a surface thickness of this material. Thus, the donor substrate may, for example, be formed from a solid substrate of monocrystalline gallium nitride, monocrystalline (1,1,1) silicon, sapphire or monocrystalline silicon carbide. As a further example, it may be in the form of a composite substrate formed from a first substrate on which rests a thickness (at least equal to that of the seed layer 2c) of material of which it is sought to constitute the seed layer. It may in particular be a thickness of a III-N material such as gallium nitride formed on a (1,1,1) silicon substrate.

[0056] The assembly step of the manufacturing process by layer transfer is advantageously implemented by molecular adhesion. As is well known per se, during a molecular adhesion process, the first face of the support 2a and one face of the donor substrate (possibly one and / or the other covered with a dielectric layer intended to form the dielectric bonding layer 2b), perfectly clean, flat and smooth, are brought into intimate contact to promote the development of molecular bonds, for example of the van der Waals or covalent type. The assembly of the two bodies is then obtained without the use of an adhesive. These bonds can be reinforced by applying a heat treatment to the intermediate structure thus formed.When it is desired to form a substrate 2 devoid of a dielectric bonding layer, the first face of the support 2a and the face of the donor substrate are not provided with a dielectric layer, and are placed in direct intimate contact with each other.

[0057] The step of removing a portion of the donor substrate can be carried out by mechanical-chemical thinning of this substrate.

[0058] Preferably, however, the substrate 2 is manufactured by applying Smart Cut™ technology, according to which a layer intended to form the seed layer 2c is delimited by means of a weakening plane formed by implantation of so-called “light” species (typically hydrogen and / or helium) in the donor substrate. After the assembly step, this layer is removed from the donor substrate by fracture at the weakening plane and thus transferred to the support 2a.

[0059] Whether the removal of a portion of the thickness of the donor substrate is achieved by thinning or by fracture, any type of finishing treatment can be applied to the substrate thus formed to conform the seed layer 2c to specifications of thickness, thickness uniformity, roughness or any other type of specifications.

[0060] In the substrate 2 thus formed, the rear face of the support 2, under which the second surface layer C2 is arranged, also forms the rear face of the substrate. The first surface layer C1 is arranged directly under the seed layer 2c (or directly under the dielectric bonding layer 2b, when this layer is present).

[0061] It is noted that when the material of the donor substrate is a polar material, it is then necessary to carry out a double transfer of the seed layer 2c which is taken from it, by first transferring this seed layer 2c onto an intermediate substrate then, during a second transfer, onto the support 2a made of polycrystalline silicon carbide. In this way, the seed layer 2c has, on this support 2a, its initial polarity. This is particularly the case when the donor substrate comprises gallium nitride, this material having in its most available form, a gallium face which it is generally desired to expose, and a nitrogen face. Manufacturing of the semiconductor component

[0062] The substrate 2, in the form of a wafer, is used to form at least one semiconductor component. Thus, and as has been explained in a previous passage and illustrated in [Fig. 3], a buffer layer 3 based on IILN material is formed by epitaxy on the exposed face of the seed layer 2c of the substrate 2. Preferably, the main layer 3 is doped to make it semi-insulating. This may for example be carbon doping, the concentration of which in the main layer may be between 5. 10A18 and 5. 10A19 at / cmA3. It may also be another p-type doping, for example iron or magnesium.

[0063] It is possible to position in the buffer layer 3 mainly made of gallium nitride one or more intercalary layers, for example made of AlGaN or more generally made of AlInGaN. In all cases, the lattice parameter of the seed layer 2c and the thermal expansion coefficient of the polycrystalline silicon carbide support 2a are particularly suited to the nature of the material of the buffer layer 3 made of IILN material. It is consequently possible to form a relatively large thickness of this buffer layer 3 on the substrate 2, for example a thickness greater than 3 microns, preferably greater than 5 micrometers and even more preferably between 5 micrometers and 10 micrometers.

[0064] In a following step of preparation of the semiconductor component 1, a heterojunction is formed on the buffer layer 3. As is well known per se, such a heterojunction combines at least one channel layer 5 (for example in GaN) and one barrier layer 6 (for example in AlGaN). A 2D electron gas is likely to develop at the interface of these two layers. Then, a source structure S, a drain structure D and a gate structure G are arranged on the heterojunction 5.

[0065] In certain cases, it is possible to thin the substrate 2, by eliminating a thickness of the support 2a on the side of the second surface layer C2. However, care will be taken to preserve a sufficient thickness of this layer C2, greater than or equal to 10 microns.

[0066] In a following step, a metal layer is formed on the rear face of the support 2a, in contact with the second surface layer C2. This metal layer can be of any suitable nature, for example titanium, aluminum, nickel, gold or a stack made up of these materials. Due to the high doping of the second surface layer C2 and its low resistivity, the contact with the metal layer is of an ohmic nature, without it being necessary to heat treat this interface, which forms a particularly advantageous characteristic of a support according to the invention.

[0067] A large number of devices are usually formed collectively on the substrate 2 in the form of wafers. These devices are then singled out, by cutting the wafer on which they rest, to form semiconductor chips. These chips are packaged to form semiconductor components 1, assembled to a metal sheet M using an adhesive, such as a sintered silver paste, forming a particularly reliable adhesion layer B for a power component.

[0068] Of course, the invention is not limited to the embodiments described and variant embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

Claims

1. Support (2a) made of polycrystalline silicon carbide for a substrate (2) intended to receive a power semiconductor device, the support comprising a first face, designated "front face" and a second face opposite the first and designated "rear face", the support comprising: - a first surface layer (Cl) arranged directly under the front face and having a resistivity greater than or equal to 1 ohm.cm and; - a second surface layer (C2) arranged directly under the rear face and having a resistivity strictly less than 1 ohm.cm.

2. A polycrystalline silicon carbide support (2a) according to the preceding claim wherein the second surface layer (C2) has a thickness of 10 micrometers or more.

3. Support (2a) made of polycrystalline silicon carbide according to one of the preceding claims in which the second surface layer (C2) has a concentration of n-type dopants, such as nitrogen, greater than 10A20 at / cmA3.

4. Support (2a) made of polycrystalline silicon carbide according to the preceding claim in which the concentration of n-type dopant increases monotonically from the front face to the second surface layer (C2).

5. Support (2a) made of polycrystalline silicon carbide according to one of the preceding claims in which the first surface layer (Cl) is not intentionally doped or has a vanadium concentration greater than 10A15 at / cmA3.

6. Support (2a) made of polycrystalline silicon carbide according to one of the preceding claims having a total thickness, between the first face and the second face, of between 200 micrometers and 1 mm.

7. Support (2a) made of polycrystalline silicon carbide according to one of the preceding claims in the form of a circular plate, advantageously 200 mm in diameter.

8. Substrate (2) intended to receive a semiconductor device comprising a support (2a) according to one of the preceding claims and a seed layer (2c) transferred to the front face of the support (2a).

9. Substrate (2) according to the preceding claim in which the seed layer (2c) is made of gallium nitride, silicon carbide, sapphire or silicon (1,1,1).

10. Substrate (2) according to one of the two preceding claims comprising a dielectric bonding layer (2b) arranged between, and in contact with, the support (2a) and the seed layer (2c), preferably a dielectric bonding layer (2b) made of silicon nitride.

11. Substrate (2) according to claim 8 or 9, wherein the seed layer (2c) directly contacts the support (2a).

12. Substrate (2) according to one of claims 8 to 11 comprising a buffer layer (3) based on gallium nitride, preferably semi-insulating, arranged on the seed layer (2c).

13. Substrate (2) according to the preceding claim in which the buffer layer (3) has a thickness greater than 3 microns, preferably greater than 5 micrometers and even more preferably between 5 micrometers and 10 micrometers.

14. Substrate (2) according to one of claims 12 and 13 comprising a heterojunction arranged on the buffer layer (3), the heterojunction comprising a channel layer (5) and a barrier layer (6) and being capable of forming a 2D electron gas.

15. Semiconductor component (1) comprising a substrate (2) according to the preceding claim and a source structure (S), a drain structure (D) and a gate structure (G) arranged on the heterojunction.

16. Semiconductor component (1) according to the preceding claim comprising a metal sheet (M) arranged under the rear face of the support, in ohmic contact with the second surface layer (C2).

17. Semiconductor component (1) according to the preceding claim comprising an adhesion layer (B), such as a sintered silver paste layer, arranged between the metal sheet (M) and the second surface layer (C2).

18. Semiconductor component (1) according to one of the two preceding claims comprising a metal layer arranged against the second surface layer (C2).

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