Integrated circuit comprising a capacitive element, and corresponding manufacturing process

Abstract

Integrated circuit comprising a substrate (STI) having a front face (FA), and at least one capacitive element (LCAP) comprising, on a surface at the front face (FA), a stack of a first conductive plate (E1) having a gate metal layer (TIN) located on a layer of material with a high dielectric constant "high-κ" (HK), a dielectric interface region (HTO1, HVO) on the first conductive plate (E1), and a second conductive plate (E2) on the dielectric region (HTO1, HVO). Figure for the abbreviation: Fig 1

Description

Title of the invention: Integrated circuit comprising a capacitive element, and corresponding manufacturing method

[0001] Embodiments and implementations relate to integrated circuits and in particular to technologies of integrated capacitive elements, especially in integrated circuits comprising transistors benefiting from gate structures of the "high-K / metal gate" type.

[0002] A transistor gate structure is conventionally designated by the English terms "high-K / metal gate" when the gate dielectric of the transistor comprises a material with a large dielectric constant K, which will be described here as "high-K" (usually in English "high-K"), and when the gate conductive region of the transistor comprises a layer of so-called "gate" metal (usually in English "metal gate").

[0003] Conventionally also, the term high-K dielectric refers to semiconductor industry materials having a high dielectric constant K compared to that of silicon dioxide.

[0004] The gate metal typically allows the gate output work to be parameterized, the gate also comprising a volume of another gate material suitable for receiving contact and polarization (typically polycrystalline silicon).

[0005] Finally, "high-K / metal gate" type gate structures are found in particular but not necessarily in "SOI" type circuits, i.e. of the "semiconductor on insulator" type (usually in English "semiconductor on insulator").

[0006] In general, there is a need in integrated circuits to have linear capacitive elements adapted to operate in accumulation and inversion regimes, i.e. having a substantially constant capacitive value for biases at positive and negative voltages.

[0007] In addition, it is desirable that the manufacture of the capacitive elements be or be able to be co-integrated with the manufacture of other circuit elements, such as MOS transistors (for "Metal Oxide Semiconductor"), i.e. carried out "free of charge" during the same manufacturing steps.

[0008] The embodiments and implementations proposed below make it possible to manufacture capacitive elements of the "MIM" type (for "Metal-Insulator-Metal") and therefore linear in accumulation and inversion, and produced in a cointegrated manner free of charge or at a lower cost in a "high-K / metal gate" transistor manufacturing process by reusing the gate metal for the manufacture of a armature of the capacitive element, and the grid conductive material for the other armature of the capacitive element.

[0009] According to one aspect, an integrated circuit is proposed in this regard comprising a region having a front face, for example a region of a semiconductor substrate, and at least one capacitive element comprising, on a surface at the level of the front face, a stack of a first conductive armature comprising a layer of gate metal located on a layer of material with a large dielectric constant "large-K", a dielectric interface region on the first conductive armature, and a second conductive armature on the dielectric region.

[0010] According to one embodiment, the grid metal layer comprises a titanium nitride composition.

[0011] According to one embodiment, the high-K dielectric layer comprises a composition of hafnium or zirconium oxide and / or silicide, i.e. for example a composition of hafnium oxide, or hafnium silicide, or hafnium oxisilicide, or a composition of zirconium oxide, or zirconium silicide, or zirconium oxisilicide.

[0012] According to one embodiment, the second conductive armature comprises a polycrystalline silicon composition.

[0013] According to one embodiment, the first conductive armature comprises a polycrystalline silicon encapsulation layer, enveloping the gate metal layer.

[0014] According to one embodiment, the first conductive armature comprises a local region of polycrystalline silicon in contact with the gate metal layer, and adapted for ohmic coupling with a metallic contact.

[0015] According to one embodiment, the integrated circuit further comprises at least one MOS transistor (i.e. a transistor of the classic and known per se "Metal Oxide Semiconductor" type), comprising a gate region comprising a stacking of a formation identical to said second conductive armature on a layer formation identical to said first conductive armature.

[0016] According to one embodiment, the integrated circuit further comprises at least one high-voltage MOS transistor, comprising a gate dielectric region comprising a formation identical to said dielectric interface region, on a surface at the front face.

[0017] According to one embodiment, said region having a front face is: a shallow insulation trench region; or a region of a semiconductor thin film; or a region of a volume of a semiconductor substrate.

[0018] According to one embodiment, said at least one capacitive element further comprises, between said a surface at the front face and said layer of material with a high dielectric constant "high-K", at least one dielectric layer of grid.

[0019] According to another aspect, a method for realizing at least one capacitive element in an integrated circuit is proposed, comprising, starting from a front face of a region, for example a region of a semiconductor substrate, the fabrication of a first conductive armature comprising a step of forming a layer of material with a high dielectric constant "high-K" on a surface of said front face and a step of forming a layer of gate metal on the layer of material with high -k; the fabrication of a dielectric interface stacked on the first conductive armature, and the fabrication of a second conductive armature stacked on the dielectric region.

[0020] According to one embodiment, the step of forming the grid metal layer includes the formation of a titanium nitride composition.

[0021] According to one embodiment, the high-K dielectric layer step comprises the formation of a hafnium or zirconium oxide and / or silicide composition.

[0022] According to one embodiment, the manufacture of the second conductive armature comprises a formation of a polycrystalline silicon composition.

[0023] According to one embodiment, the manufacture of the first conductive armature further comprises a step of forming a polycrystalline silicon encapsulation layer, enveloping the gate metal layer.

[0024] According to one embodiment, the manufacture of the first conductive armature further comprises a step of forming a local region of polycrystalline silicon in contact with the gate metal layer, and adapted to ohmic coupling with a metallic contact.

[0025] According to one embodiment, the method further comprises jointly an embodiment of at least one MOS transistor comprising a gate region, the fabrication of the gate region comprising a fabrication of layers identical to said fabrication of the first conductive armature, and a fabrication identical to said fabrication of the second conductive armature on said layer formation.

[0026] According to one embodiment, the method further comprises jointly an embodiment of at least one high-voltage MOS transistor comprising a fabrication of a gate dielectric region identical to said fabrication of the dielectric interface region, on a surface at the front face.

[0027] Depending on the embodiment, said region having a front face is: a shallow insulation trench region; or a region of a semiconductor thin film; or a region of a volume of a semiconductor substrate.

[0028] According to one embodiment, the manufacture of the first conductive armature further comprises a step of forming at least one dielectric layer of grid, between said surface at the front face and said layer of material with high dielectric constant "high-K".

[0029] Other advantages and features of the invention will become apparent from an examination of the detailed description of embodiments and implementations, which are by no means limiting, and the accompanying drawings, in which the figures:

[0030] [Fig.1] ;

[0031] [Fig.2] ;

[0032] [Fig.3] ;

[0033] [Fig.4] ;

[0034] [Fig.5] illustrate embodiments and implementations of the invention.

[0035] Fig. 1 illustrates a first example of a method for forming an LCAP capacitive element in an integrated circuit.

[0036] Steps 101, 102, 103, 104 of the LCAP capacitive element formation process are advantageously compatible with manufacturing steps of MOS transistor gate structures, comprising a "high-K / metal gate" type structure (usually "high-K / metal gate" in English) having typical voltage range characteristics.

[0037] Steps 101, 102, 103, 104 of the formation of the capacitive element LCAP make it possible to manufacture a low voltage gate structure SGT of transistors adapted to logic operations, a medium voltage gate structure EG of transistors adapted to signal communications, and a high-voltage gate structure eZG of transistors adapted to the generation and transmission of high voltages.

[0038] The formations of steps 101-104 are carried out from a front face FA of a SUB semiconductor substrate.

[0039] For example, the low voltage gate structures SG and the medium voltage gate structures EG are formed in regions of the substrate SUB of the completely depleted silicon-on-insulator type FDSOI.

[0040] For example, high voltage grid structures eZG can be formed on a region of the BLK volume (usually "bulk" in English) of the SUB substrate.

[0041] The capacitive element is advantageously formed at the front face FA, on a shallow isolation region STI, typically formed at the beginning of the production line by a shallow trench isolation technique allowing the lateral delimitation of active regions (typically the channel regions of transistors) of devices made in and on the substrate SUB.

[0042] In step 101, three thicknesses of gate dielectrics, typically silicon oxide, were deposited for the high-voltage eZG, medium-voltage EG, and low-voltage SG gate structures, the thicknesses decreasing in that order. (corresponding to the voltage ranges of the transistors).

[0043] In this regard, for example, a first dielectric layer HTO1 was formed on the front face FA in the high-voltage region eZG; then a second dielectric layer HTO2 was formed on the first dielectric layer in the high-voltage region and on the front face FA in the medium-voltage region EG; and then a low-voltage dielectric interface layer SGO was formed, particularly in the high-voltage eZG, medium-voltage EG, and low-voltage SG regions, and possibly over the entire front face FA. The thickness of the dielectric interface layer SGO is considered negligible compared to the thickness of the first layer HTO1 and the thickness of the second layer HTO2.

[0044] In step 102, the "large-K / gate metal" type structures were formed on the dielectric layers HTO1, HTO2, SGO of the gate structures SG, EG, eZG; and, simultaneously, a first TIN conductive armature (El - figures 3 to 5) of the LCAP capacitive element was fabricated.

[0045] On the one hand, step 102 involves, in this respect, the formation of a layer of material with a high dielectric constant, "high-K", on the dielectric layers HTO1, HTO2, SGO produced in step 101 of the grid structures SG, EG, eZG; and on the front face FA in the shallow insulation region that accommodates the capacitive element LCAP. For example, the high-K dielectric layer HK comprises a composition of hafnium oxide and / or silicide or a composition of zirconium oxide and / or silicide.

[0046] On the other hand, step 102 involves in this respect the formation of a grid metal layer TIN over the high-K material layer HK. For example, the grid metal layer has a titanium nitride composition TIN.

[0047] In a particular embodiment, corresponding for example to [Fig.3], the step of forming the TIN gate metal layer can be accompanied by the formation of an associated PE encapsulation polycrystalline silicon conductive layer, intended to wrap, i.e. cover on top and on the edges, the TIN gate metal layer.

[0048] The TIN gate metal layer, and the optional polycrystalline silicon encapsulation layer, form the first conductive armature of the LCAP capacitive element, at the front face FA on the shallow insulation trench STI.

[0049] In step 103, the HVO dielectric interface of the LCAP capacitive element is fabricated, over the first TIN conductive armature, for example by an additional formation step of a dielectric layer such as silicon oxide, stacked on the TIN gate metal layer such as titanium nitride.

[0050] It should be noted that this first embodiment provides for an additional step of forming a dielectric layer for the realization of the capacitive element LCAP. This presents an additional manufacturing cost, but also the advantage of not modifying the stacking of HT01, HT02, HK, TIN layers of the eZG high voltage grid structure (compared in particular to the implementation method described in relation to [Fig.2]) and also the possibility of producing a second type of HVG high voltage grid structure free of charge.

[0051] Indeed, step 103 provides for the fabrication of a HVO grid dielectric layer adapted to a second high-voltage range, but possibly different from the high-voltage range of the eZG grid structure. In fact, the HVO layer can be formed with a thickness different from that of the HTO1, HTO2 stack, and independently of the realizations of the medium-voltage EG (HTO2) grid structures.

[0052] The second type of high voltage HVG transistor does not have a "big-K / gate metal" structure, but this is not necessarily harmful in high voltage applications, and is for example formed on a volume of the BLK semiconductor substrate.

[0053] In step 104, the second conductive armature PO (E2 - figures 3 to 5) is manufactured, stacked on top of the dielectric region HVO, at the same time as the conductive regions of the gates HV, eZG, EG, SG of the transistors are manufactured, typically formed by a polycrystalline silicon composition PO.

[0054] Conventional "big-K / gate metal" transistors SG, EG have thus been manufactured, that is to say transistors whose gate dielectric layers include a big-K dielectric layer and are of thicknesses adapted to different voltage ranges, and whose gate conductive regions include a TIN metallic layer at the interface of the big-K dielectric HK.

[0055] During the same steps, it was possible to form a capacitive LCAP element of the "MIM" type for Metal-Insulator-Metal, where the first metallic armature is made by the TIN gate metal, where the insulator is made by the HVO dielectric layer, and where the second conductive PO armature is made by the polycrystalline silicon of the PO gates. Thus, the capacitive LCAP element is linear in accumulation and inversion.

[0056] In addition, a second conventional HVG high-voltage transistor can be manufactured free of charge without the "big-K / gate metal" structure.

[0057] Fig. 2 illustrates a second example of the process of forming an LCAP capacitive element of an integrated circuit.

[0058] Steps 201, 202, 203, 204 of the formation of the LCAP capacitive element are again advantageously compatible with manufacturing steps of low voltage SG, medium voltage EG and high voltage ZG gate structures of MOS transistors.

[0059] The second example of implementation of process 201-204 actually allows for a completely free cointegration of the manufacturing process of the capacitive element LCAP, in a manufacturing process for SG, EG, ZG gate structures of MOS transistors.

[0060] In this second example, the low voltage grid structures SG are identical to those of the first example, while the realizations of the medium voltage grid structures EG and high voltage grid structures ZG are slightly modified.

[0061] Step 201 corresponds to step 101 described previously, but in which the first dielectric layer HTO1 has not been formed on the front face FA in the high voltage region eZG.

[0062] Thus, only the second dielectric layer HTO2 was formed on the front face FA in the medium voltage region EG, and then the dielectric interface layer SGO.

[0063] Step 202 corresponds to step 102, in which the "large-K HK / TIN gate metal" type structures are formed on the HTO2, SGO dielectric layers of the SG, EG gate structures; enabling the first TIN conductive armature (El - figures 3 to 5) of the LCAP capacitive element to be manufactured simultaneously, in the same way as described previously in relation to [Fig.1].

[0064] It will be noted in particular that the stacking of the high-K dielectric layers HK and gate metal TIN is not carried out in the part hosting the high-voltage gate ZG.

[0065] In step 203, the first dielectric layer HTO1 is then formed in the high-voltage gate part ZG, and simultaneously over the first conductive armature TIN of the capacitive element LCAP, thus forming the dielectric interface layer HTO1 of the capacitive element LCAP.

[0066] Step 204 corresponds to step 104, in which the second conductive armature PO is manufactured, stacked on top of the dielectric region HVO, at the same time as the conductive regions of the gates ZG, EG, SG of the transistors are manufactured, typically with a polycrystalline silicon composition PO.

[0067] It should be noted that this second embodiment does not involve an additional step of forming a dielectric layer for the fabrication of the LCAP capacitive element. Thus, the second example of the implementation of the 201-204 process is advantageously fully cointegrated into the fabrication of the SG, EG, ZG transistors, and therefore entirely free of charge.

[0068] Indeed, the formation step of the first gate dielectric layer HTO1 of the high-voltage transistor ZG has advantageously been "moved" after the formation steps of the high-K dielectric layer and the gate metal layer TIN. Consequently, the high-voltage gate structure ZG does not benefit from the "high-K / gate metal" structure, but, as mentioned previously, this is not detrimental in the high-voltage ranges.

[0069] Furthermore, given that the first dielectric layer HTO1 does not define of a different thickness than that of the grid dielectric of the high voltage structure ZG, it is possible to plan in step 203 the fabrication of the first layer HTO1 with a different desired thickness and independently of the realizations of the other grid structures.

[0070] Conventional low voltage SG and medium voltage EG "big-K / gate metal" transistors have thus been manufactured; a conventional high voltage HVG transistor without the "big-K / gate metal" structure; and the LCAP capacitive element of the "MIM" type, where the first metal armature is made by the gate metal TIN, where the insulator is made by the first dielectric layer HTO1, and where the second conductive PO armature is made by the polycrystalline silicon of the PO gates.

[0071] Figures 3, 4 and 5 illustrate examples of realization of the LCAP capacitive element thus obtained by the manufacturing processes described in relation to Figures 1 and 2.

[0072] Thus, in the three examples, the capacitive element LCAP comprises, on a surface at the front face FA, a stack of a first conductive armature El comprising a layer of gate metal TIN located on a layer of material with a large dielectric constant "large-K" HK, of a dielectric interface region HTO1, HVO on the first conductive armature El, and of a second conductive armature E2 on the dielectric interface region HTO1, HVO.

[0073] The gate metal layer TIN may comprise a titanium nitride composition. The high-K dielectric layer HK may comprise a hafnium oxide and / or silicide composition, or a zirconium oxide and / or silicide composition. The second conductive armature E2 may comprise a polycrystalline silicon composition PO.

[0074] Figure 3 illustrates the embodiment in which the first conductive armature El comprises a layer of polycrystalline silicon encapsulation PE, enveloping the gate metal layer TIN.

[0075] The formation of the polycrystalline silicon encapsulation layer PE can be provided as standard with the formation of the gate metal layer TIN of the transistors SG, EG, ZG, and does not generate any additional cost dedicated to the formation of the capacitive element LCAP.

[0076] For example, the polycrystalline silicon PE encapsulation layer may be intended to protect the TIN gate metal (for example from oxidation), and be intended to be etched later, for example.

[0077] That being said, in the LCAP capacitive element, the PE encapsulation polycrystalline silicon layer advantageously allows a CO contact, usually made of copper or aluminum, to be connected by an ohmic coupling with a conventional silicification of an exposed surface of the PE polycrystalline silicon.

[0078] Indeed, the thickness of the TIN gate metal layer is thin compared to the thicknesses of the polycrystalline silicon volumes usually connected by the contacts.

[0079] For example, the orders of magnitude of said thicknesses (vertically in the direction of the drawing) can be 3.5 nm (nanometers) for the TIN gate metal, 12 nm for the PE encapsulating polycrystalline silicon, and 48 nm for the PO polycrystalline silicon of the second E2 armature

[0080] Furthermore, in this embodiment and in the method examples described in relation to Figures 1 and 2, the LCAP capacitive element is located on a surface at the front face FA of a dielectric volume STI. The dielectric volume STI is, for example, a shallow insulation trench.

[0081] This allows us to benefit from a linear capacitive value (i.e. substantially constant) in the inversion and accumulation regimes.

[0082] Figure 4 illustrates another embodiment in which the PE encapsulating polycrystalline silicon layer is absent. In this case, to connect the first armature El of the LCAP capacitive element, a local region of PO polycrystalline silicon can be formed in an opening made in the dielectric interface HTO1 up to the first armature El during step 104 / 204 of manufacturing the second armature E2.

[0083] Thus, the local PO region of polycrystalline silicon allows the CO contact to be connected by an ohmic coupling with a conventional silicification of a surface of the PO region.

[0084] This alternative where the polycrystalline silicon encapsulation layer PE is absent and comprising the local PO region of polycrystalline silicon is perfectly applicable if the LCAP capacitive element is located on a surface at the front face FA, of a dielectric volume STI, as described in relation to [Fig.3], in particular to benefit from the linearity of the capacitive value in the inversion and accumulation regimes.

[0085] Furthermore, in this other embodiment, the first TIN armature of the LCAP capacitive element is formed on the one hand above the second dielectric layer of the HTO2 gate (for example made in the manner obtained in steps 103 / 203 for the medium voltage gate structure EG), and on the other hand opposite a region of the substrate comprising a thin semiconductor film TSI on a buried insulating volume BOX, i.e. of the "SOI" type ("semiconductor on insulator").

[0086] Thus, a second capacitive interface, of the "MOS" type (a well-known acronym for "Metal Oxide Semiconductor"), is created between the first TIN armature and the TSI semiconductor film. This additional "MOS" capacitive element can be combined with the LCAP "MIM" type capacitive element by means of a connection in parallel of the TSI thin film with the PO polycrystalline silicon of the second E2 armature. The TSI semiconductor thin film can be conventionally connected by CO contacts to heavily doped P+ regions of the same type of dopants as the film.

[0087] [Fig.5] illustrates the same structure as [Fig.4], but on a volume of the BLK semiconductor substrate, instead of the semiconductor thin film.

[0088] Thus, the second capacitive interface, of the "MOS" type, is made between the first TIN armature and the volume of the BLK semiconductor substrate.

[0089] The accumulation of the additional “MOS” capacitive element in parallel with the “MIM” type LCAP capacitive element, as described in relation to figures 4 and 5, makes it possible to increase the surface capacitance value, but at the expense of the linearity of the capacitance value in the inversion and accumulation regimes.

Claims

Claims

1. Integrated circuit comprising a region (STI, TSI, BLK) having a front face (FA), and at least one capacitive element (LCAP) comprising, on a surface at the front face (FA), a stack of a first conductive armature (El) comprising a gate metal layer (TIN) located on a layer of material with a large dielectric constant "large-K" (HK), a dielectric interface region (HT01, HVO) on the first conductive armature (El), and a second conductive armature (E2) on the dielectric region (HT01, HVO).

2. The integrated circuit of claim 1, wherein the gate metal layer comprises a titanium nitride (TIN) composition.

3. Integrated circuit according to one of claims 1 or 2, in which the high-K (HK) dielectric layer comprises a composition of hafnium or zirconium oxide and / or silicide.

4. Integrated circuit according to one of claims 1 to 3, in which the second conductive armature (E2) comprises a polycrystalline silicon (PO) composition.

5. Integrated circuit according to one of claims 1 to 4, in which the first conductive armature (El) comprises a layer of polycrystalline silicon encapsulation (PE), enveloping the layer of gate metal (TIN).

6. Integrated circuit according to one of claims 1 to 4, in which the first conductive armature (El) comprises a local region of polycrystalline silicon in contact with the gate metal layer (TIN), and adapted to ohmic coupling with a metal contact.

7. Integrated circuit according to one of claims 1 to 6, further comprising at least one MOS transistor, comprising a gate region (eZG, EG, SG) comprising a stack of a formation identical to said second conductive armature (E2) on a formation of layers identical to said first conductive armature (El).

8. Integrated circuit according to one of claims 1 to 7, further comprising at least one high-voltage MOS transistor (ZT, HVT), comprising a gate dielectric region comprising a formation identical to said dielectric interface region (HT01), on a surface at the front face (FA).

9. Integrated circuit according to one of claims 1 to 8, wherein said region having a front face (FA) is: a shallow isolation trench (STI) region; or a region of a semiconductor thin film (TSI); or a region of a volume of a semiconductor substrate (BLK).

10. Integrated circuit according to one of claims 1 to 9, in which said at least one capacitive element (LCAP) further comprises, between said one surface at the front face (FA) and said layer of high-K material (HK), at least one layer of gate dielectric (HTO2, SGO).

11. Method for producing at least one capacitive element (LCAP) in an integrated circuit, comprising, from a front face (FA) of a region (STI, TSI, BLK), a fabrication of a first conductive armature (El) comprising a step of forming a layer of material with a large dielectric constant "large-K" (HK) on a surface of said front face (FA) and a step of forming a layer of gate metal (TIN) on the layer of large-K material (HK); a fabrication of a dielectric interface (HTO1, HVO) stacked on the first conductive armature (El), and a fabrication of a second conductive armature (E2) stacked on the dielectric region (HTO1, HVO).

12. The method of claim 11, wherein the step of forming the gate metal layer comprises forming a titanium nitride (TIN) composition.

13. A method according to either of claims 11 or 12, wherein the high-K (HK) dielectric layer step comprises forming a hafnium or zirconium oxide and / or silicide composition.

14. Method according to one of claims 11 to 13, in which the manufacture of the second conductive armature (E2) comprises a formation of a polycrystalline silicon (PO) composition.

15. Method according to one of claims 11 to 14, in which the manufacture of the first conductive armature (El) further comprises a step of forming a layer of polycrystalline silicon encapsulation (PE), enveloping the layer of gate metal (TIN).

16. Method according to one of claims 11 to 15, in which the manufacture of the first conductive armature (El) further comprises a step of forming a local region of polycrystalline silicon in contact with the gate metal layer (TIN), and adapted to ohmic coupling with a metal contact.

17. Method according to one of claims 11 to 16, further comprising jointly a production of at least one MOS transistor comprising a gate region (eZG, EG, SG), the manufacturing of the gate region (eZG, EG, SG) comprising a manufacturing of layers identical to said manufacturing of the first conductive armature (El), and a manufacturing identical to said manufacturing of the second conductive armature (E2) on said formation of layers.

18. Method according to one of claims 11 to 17, further comprising jointly producing at least one high-voltage MOS transistor (ZT, HVT) comprising manufacturing a gate dielectric region identical to said manufacturing of the dielectric interface region (HTO1), on a surface at the level of the front face (FA).

19. A method according to one of claims 11 to 18, wherein said region having a front face (FA) is: a shallow isolation trench region (STI); or a region of a semiconductor thin film (TSI); or a region of a volume of a semiconductor substrate (BLK).

20. Method according to one of claims 11 to 19, the manufacture of the first conductive armature (El) further comprises a step of forming at least one layer of gate dielectric (HTO2, SGO), between said surface at the level of the front face (FA) and said layer of high-K material (HK).

Images