Ultrasound imaging probe

Abstract

Ultrasonic Imaging Probe This description relates to an ultrasonic imaging probe (100) comprising first (110), second (120), and third (130) circuits, wherein: - the first circuit (110) is an ultrasonic transduction circuit comprising an array of elementary ultrasonic transduction chips (111), each comprising an array of elementary ultrasonic transducers (113); - the second circuit (120) is a transmit-receive circuit comprising, for each elementary ultrasonic transduction chip (111), an elementary transmit-receive chip (121); - the third circuit (130) is a digital preprocessing circuit comprising, for each elementary transmit-receive chip (121), an elementary digital preprocessing chip (131). Figure for the abstract: Fig. 1

Description

Title of the invention: Ultrasound imaging probe Technical field

[0001] The present description relates to the field of ultrasound imaging, and more particularly relates to an ultrasound imaging probe intended to be connected to an external control and processing system via a cable, the probe integrating a plurality of ultrasound transducers and electronic circuits for controlling these transducers. Prior art

[0002] Various architectures of ultrasound imaging probes have already been proposed.

[0003] It would be desirable to improve at least in part certain aspects of known ultrasound imaging probes.

[0004] The focus here is more particularly on the production of ultrasound imaging probes suitable for implementing, as close as possible to the ultrasound sensor, digital and / or analog processing such as, for example, micro-beamforming processing, for example in the context of ultra-fast acquisition scenarios. Summary of the invention

[0005] One embodiment provides an ultrasound imaging wave having first, second, and third circuits, wherein: - the first circuit is an ultrasonic transduction circuit comprising a matrix of elementary ultrasonic transduction chips each comprising a matrix of elementary ultrasonic transducers; - the second circuit is a transmission-reception circuit comprising, for each elementary ultrasonic transduction chip, an elementary transmission-reception chip comprising, for each elementary ultrasonic transducer of the elementary ultrasonic transduction chip, an elementary transmission-reception cell electrically connected to an electrode of the transducer; - in each elementary transmission-reception chip, the elementary transmission-reception cells of the chip are distributed into several elementary transmission-reception groups each comprising N elementary transmission-reception cells, with N being an integer greater than or equal to 1; - the probe comprises, for each elementary transmission-reception chip, for each elementary transmission-reception group of the chip, an analog preprocessing circuit comprising N input terminals connected respectively to an output terminal of each elementary transmission-reception cell of the elementary group transmission-reception, and M output terminals, with M less than or equal to NN; - the probe comprises, for each elementary transmission-reception group of each elementary transmission-reception chip, M analog-digital converters each having an input terminal and an output terminal, the input terminals of the M analog-digital converters being connected respectively to the M output terminals of the analog pre-processing circuit of the elementary transmission-reception group; - the third circuit is a digital pre-processing circuit comprising, for each elementary transmission-reception chip, an elementary digital pre-processing chip comprising, for each elementary transmission-reception group of the elementary transmission-reception chip, M elementary digital pre-processing cells connected respectively to the output terminals of the M analog-digital converters associated with the elementary transmission-reception group; - each elementary digital preprocessing chip comprises one or more binary connection elements each intended to provide a serialized digital signal, connected to all of the elementary digital preprocessing cells of the chip via one or more serialization circuits.

[0006] According to one embodiment, each elementary digital preprocessing cell comprises an elementary memory circuit and a calculation unit.

[0007] According to one embodiment, each analog pre-processing circuit is a combiner selector circuit adapted to provide, on each of its M output terminals, an analog summation, or superposition, of all or part of the signals applied to its N input terminals.

[0008] According to one embodiment, each transmission-reception cell comprises a transmission circuit adapted to generate an electrical excitation signal applied to the electrode of the associated elementary transducer.

[0009] According to one embodiment, each transmission-reception cell comprises a reception circuit comprising an amplifier having an input node connected to the electrode of the elementary transducer and an output node connected to the output terminal of the transmission-reception cell.

[0010] According to one embodiment, each transmission-reception cell, the reception circuit further comprises a delay circuit configured to apply a delay of an adjustable duration to the electrical output signal of the transducer.

[0011] According to one embodiment, each elementary digital preprocessing cell comprises data input-output ports allowing data to be exchanged between the elementary memory circuit of the cell and the elementary memory circuits of neighboring elementary cells.

[0012] According to one embodiment, the first, second and third circuits are stacked vertically, the second circuit being arranged between the first and third circuits.

[0013] According to one embodiment, two of the first, second and third circuits are stacked vertically, the remaining circuit of the first, second and third circuits being offset laterally.

[0014] According to one embodiment, M is strictly less than N.

[0015] Another embodiment provides an ultrasound imaging system comprising an ultrasound imaging probe as defined above, an external processing device, and a digital data transmission channel connecting the probe to the external processing device.

[0016] According to one embodiment, the digital data transmission channel comprises one or more wired electrical or optical data transmission elements per elementary digital preprocessing chip, electrically connected respectively to said one or more binary connection elements of the elementary chip.

[0017] According to one embodiment, the external processing device is configured to apply delays and combine signals from the analog-digital converters. Brief description of the drawings

[0018] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0019] [Fig.l] is a perspective view schematically and partially representing an example of an ultrasound imaging system according to one embodiment;

[0020] [Fig.2] schematically and partially represents an exemplary embodiment of a transmission-reception circuit of an ultrasound imaging probe according to one embodiment;

[0021] [Fig.3] schematically and partially represents an exemplary embodiment of a digital preprocessing circuit of an ultrasound imaging probe according to one embodiment;

[0022] [Fig.4] is a perspective view schematically and partially representing a variant of an ultrasound imaging system according to one embodiment; and

[0023] [Fig. 5] is a sectional view schematically and partially showing another variant of an ultrasound imaging system according to one embodiment. Description of the embodiments

[0024] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0025] For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed. In particular, the various applications that the ultrasound imaging probes and systems described may have have not been detailed, the embodiments described being compatible with the usual applications of ultrasound imaging probes. In addition, the properties (frequencies, shapes, amplitudes, etc.) of the electrical excitation signals applied to the ultrasound transducers have not been detailed, the embodiments described being compatible with the excitation signals usually used in ultrasound imaging systems, which can be chosen according to the application considered and in particular the nature of the body to be analyzed and the type of information that one seeks to acquire.Similarly, the various processing operations applied to the electrical signals provided by the ultrasonic transducers and read by the control circuit to extract useful information on the body to be analyzed have not been detailed, the embodiments described being compatible with the processing operations usually used in ultrasonic imaging systems. In addition, the production of the ultrasonic transducers and the electronic circuits for controlling the transducers has not been described in detail, the detailed production of these elements being within the reach of those skilled in the art from the indications of the present description, using known techniques for producing ultrasonic transducers and electronic circuits.

[0026] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0027] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0028] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0029] [Fig. 1] is a perspective view schematically and partially representing an example of an ultrasound imaging system according to one embodiment.

[0030] The system of [Fig.l] comprises an ultrasound imaging probe 100 intended to be electrically connected to an external control and processing device 160, for example a computer, via an electrical connection cable 150.

[0031] The probe 100 comprises a plurality of elementary ultrasonic transducers, and electronic transducer control circuits.

[0032] In operation, all of the ultrasonic transducers of the probe are arranged facing a body of which an image is to be acquired. The electronic control circuits are configured to apply electrical excitation signals to the transducers, so as to cause the emission of ultrasonic waves by the transducers, in the direction of the body to be analyzed. The ultrasonic waves emitted by the transducers are reflected in whole or in part by the body to be analyzed (by its internal and / or superficial structure), then return to the transducers which convert them again into electrical signals. These electrical response signals are read, digitized and preprocessed by the electronic control circuits. The digital output signals of the electronic control circuits are transmitted to the external device 160 via the connecting cable 150.These signals can be stored and analyzed by the external device 160 to deduce information about the body studied.

[0033] The probe 100 is for example a portable probe intended to be positioned and, possibly moved, manually, on the body of a patient.

[0034] In the example of [Fig.l], the ultrasound imaging probe 100 comprises a stack of an ultrasound transduction circuit 110, a transmission-reception circuit 120, and a digital preprocessing circuit 130.

[0035] The set of circuits 110, 120 and 130 is for example arranged in a housing, not shown, of the probe.

[0036] The ultrasonic transduction circuit 110 comprises a plurality of elementary ultrasonic transducers (not detailed in the figures), for example arranged in a matrix according to rows and columns. By way of example, the ultrasonic transduction circuit 110 comprises several thousand to several hundred thousand elementary ultrasonic transducers that can be individually addressed, for example of the order of one hundred thousand elementary ultrasonic transducers.

[0037] More particularly, in this example, the ultrasonic transduction circuit 110 comprises a matrix of AxB elementary ultrasonic transduction chips 111 that are identical (apart from manufacturing dispersions) or similar. In the example shown, A=B=4. The embodiments described are however not limited to this particular case. As a variant, A may be different from B and A and B may be different from 4. As an example, A may be greater than 10, for example between 10 and 100, or even greater than 100. Similarly, B may be greater than 10, for example between 10 and 100, or even greater than 100. As an example, A=120 and B=60.

[0038] Each chip 111 comprises a matrix of identical (apart from manufacturing dispersions) or similar elementary CxD transducers 113, integrated in and on a same support substrate, for example silicon. For example, each chip 111 comprises a few tens to a few thousand elementary ultrasonic transducers 113. For example, C=D=32, each elementary chip 111 thus comprising 1024 elementary ultrasonic transducers.

[0039] By way of example, in each elementary chip 111, the inter-transducer pitch is of the order of a few tens to a few hundreds of micrometers in the direction of the lines and in the direction of the columns, for example of the order of 150 μm in the direction of the lines and in the direction of the columns.

[0040] The elementary chips 111 are preferably joined, so as to respect, between two neighboring transducers of two neighboring elementary chips 111, an intertransducer pitch identical or substantially identical to the pitch internal to the chip in the direction considered.

[0041] The elementary transducers of the chips 111 are for example transducers of the CMUT type (capacitive membrane ultrasonic transducers), piezoelectric transducers, for example of the PMUT type (piezoelectric micromachined ultrasonic transducer), piezoelectric crystal transducers, or any other type of ultrasonic transducers.

[0042] Each elementary transducer comprises two electrodes for applying an electrical excitation signal to the transducer and for reading an electrical response signal from the transducer. For example, the elementary transducers of each chip 111 are individually controllable. For this, each elementary chip 111 comprises, for example, a matrix of individual CxD contact metallizations electrically insulated from one another, connected respectively to a first electrode of each of the CxD elementary transducers of the chip. Each chip 111 may further comprise a common contact metallization connected to a second electrode of each of the CxD elementary transducers of the chip.

[0043] In the example shown, the ultrasonic transduction circuit 110 comprises a support and interconnection structure 115, for example a rigid or flexible printed circuit board, on which the elementary ultrasonic transduction chips 110 are fixed and electrically connected. By way of example, the elementary chips 111 are surface-mount chips (or flip-chip chips), having all their contact metallizations arranged on the same face, called the connection face, of the chip (lower face in the representation of [Fig. 1]). The support and interconnection structure 115 is for example a plate consisting of a stack of metallic and insulating levels (not detailed in the figure), in which electrically conductive elements are formed forming an interconnection network (not visible in the figure). The structure 115 comprises for example, on the side of one face (upper face in the representation of [Fig.l]), a set of metallizations of . contact intended to be fixed and electrically connected to the contact metallizations of the chips 111. For example, the chips 111 are formed in parallel in and / or on one or more semiconductor substrates, for example silicon, then the substrate(s) are cut so as to individualize the chips 111. The chips 111 are then fixed and electrically connected, by their contact metallizations, to the structure 115, for example using a pick and place tool. During this step, the contact metallizations of the chips 111 are positioned opposite the corresponding contact metallizations of the upper face of the support and interconnection structure 115.

[0044] The transmission-reception circuit 120 comprises, for each elementary ultrasonic transduction chip 111, an elementary transmission-reception chip 121 comprising, for each elementary ultrasonic transducer 113 of the chip 111, an elementary transmission-reception cell 123 electrically connected to an electrode of the elementary ultrasonic transducer to allow individual control of the transducer in transmission and in reception. An exemplary embodiment of an elementary transmission-reception cell 123 will be described in more detail below in relation to [Fig. 2],

[0045] Thus, the circuit 120 comprises a matrix of AxB elementary transmission-reception chips 121, each elementary chip 121 comprising a matrix of CxD elementary transmission-reception cells 123.

[0046] By way of example, each elementary transceiver chip 121 comprises, on the side of a first connection face (upper face in the representation of [Fig.l]), a matrix of CxD contact metallizations (not visible in the figure) connected respectively to the CxD elementary transducers of the corresponding chip 111 via the support and interconnection structure 115. The transceiver chips 121 are for example fixed and electrically connected to the face of the structure 115 opposite the chips 111, namely its lower face in the representation of [Fig.l]. By way of example, the structure 115 comprises an electrically conductive via per elementary transducer of the circuit 110, electrically and individually connecting an electrode of the transducer to the corresponding elementary transceiver cell of the circuit 120.

[0047] In each elementary transceiver chip, the elementary transceiver cells 123 are distributed into several elementary transceiver groups each comprising N elementary transceiver cells, with N being an integer, for example greater than or equal to 4. In this example, each elementary transceiver cell 123 belongs to one and only one elementary transceiver group. Thus, in this example, each elementary transceiver chip 121 comprises CxD / N elementary groups of N elementary cells. each. The N elementary cells of each group are, for example, adjacent. The N elementary cells of each group are, for example, arranged in a row, column, or matrix. As a non-limiting example, N is equal to 16.

[0048] Each elementary chip 121 further comprises a switching circuit 125 ( [Fig.2]) per elementary group, i.e. CxD / N switching circuits 125. The switching circuit 125 comprises a programmable switching matrix network from N inputs to M outputs, with M being an integer, for example greater than or equal to 2 and less than N. For example, M is equal to 4. The switching circuit 125 is for example adapted to provide, on each of its M output terminals, an analog summation, or superposition, of all or part of the signals applied to its N input terminals. In other words, the circuit 125 implements a combiner selector function. The input and output signals of the switching circuit 125 are in this example analog signals, for example voltages.

[0049] Each elementary transceiver chip 121 further comprises M analog-digital conversion circuits 127 ([Fig.2]) per summing circuit 125 connected respectively to the M output terminals of the switching circuit. Thus, each transceiver chip 121 comprises (CxD / N)xM analog-digital conversion circuits 127 (ADC). Each analog-conversion circuit comprises an analog input terminal connected, for example connected, to an output terminal of a switching circuit 125, and a digital output terminal, providing a serialized binary digital signal, for example on 8, 10 or 12 bits, representative of the signal applied to its analog input terminal. Thus, each elementary transceiver chip 121 comprises (CxD / N)xM digital output terminals.

[0050] By way of example, each elementary transceiver chip 121 comprises, on the side of a second connection face (lower face in the representation of [Fig.l]), (CxD / N)xM contact metallizations e2 connected, for example connected, respectively to the digital output terminals of the (CxD / N)xM analog-digital converters 127 of the chip. Each chip 121 comprises for example a silicon substrate, for example monocrystalline, in and on which the components of the chip are integrated, laterally insulated electrically conductive vias passing vertically through the substrate (TSV - from the English "Through Silicon Via") and connecting the lower face metallizations e2 to upper face metallizations of the chip.

[0051] By way of example, the transceiver chips 121 are formed in parallel in and / or on one or more semiconductor substrates, for example in silicon, then the substrate(s) are cut into elementary chips 121. The chips 121 are then fixed and electrically connected, by their contact metallizations, to the lower face of the structure 115, for example using a picking tool and placement (“pick and place” in English). During this step, the upper face contact metallizations of the chips 121 are positioned opposite corresponding contact metallizations of the lower face of the support and interconnection structure 115.

[0052] The digital preprocessing circuit 130 comprises, for each elementary transmission-reception chip 121 of the analog transmission-reception circuit 120, an elementary digital preprocessing chip 131.

[0053] Each chip 131 comprises, for each elementary transmission-reception group of the corresponding elementary transmission-reception chip 121, M elementary digital pre-processing cells 133 connected, for example connected, respectively to the output terminals e2 of the M analog-digital converters associated with the elementary transmission-reception group.

[0054] Thus, the circuit 130 comprises a matrix of AxB elementary digital preprocessing chips 131, each elementary chip 131 comprising a set of (CxD / N)xM elementary digital preprocessing cells 133, for example arranged in matrix form.

[0055] An example of embodiment of an elementary digital preprocessing chip 131 will be described in more detail below in relation to [Fig.3].

[0056] In this example, each elementary digital preprocessing chip 131 comprises a single output terminal e3 ([Fig.3]) intended to provide a serialized binary digital signal. Each chip 131 further comprises a serialization circuit 301 ([Fig.3]) connecting respective output nodes of the (CxD / N)xM elementary cells 133 of the chip to the single digital output terminal of the chip.

[0057] By way of example, each elementary digital preprocessing chip 131 comprises, on the side of a first connection face (upper face in the representation of [Fig.l]), a matrix of (CxD / N)xM contact metallizations (not visible in the figure) connected respectively to the output terminals e2 of the (CxD / N)xM analog-digital converters of the corresponding chip 121. Each analog preprocessing chip 131 is for example fixed and electrically connected directly to the lower face of the associated transceiver chip 121. By way of example, the inter-chip pitch 121 (center-to-center distance between two neighboring chips 121) is identical to the inter-chip pitch 131, in the direction of the rows and in the direction of the columns.

[0058] In each elementary digital preprocessing chip 131, the digital output terminal e3 of the chip is for example connected to a contact metallization arranged on the side of a face of the chip opposite the analog transmission-reception chips 121, namely on the side of the lower face of the chip 131. Each chip 131 comprises for example a silicon substrate, for example monocrystalline, in and on which the chip components are integrated, laterally insulated electrically conductive vias, of the TSV type, passing vertically through the substrate and connecting the lower face metallizations to the upper face metallizations of the chip.

[0059] By way of example, the digital preprocessing chips 131 are formed in parallel in and / or on one or more semiconductor substrates, for example silicon, then the substrate(s) are cut into elementary chips 131. The chips 131 are then fixed and electrically connected, by their contact metallizations, to the lower face of the chips 121. During this step, the upper face contact metallizations of the chips 131 are positioned opposite corresponding contact metallizations of the lower face of the chips 121.

[0060] The probe 100 is intended to be electrically connected to an external control and processing device 160, for example a computer, via a digital data transmission channel, for example an electrical connection cable 150. More particularly, in this example, the electrical connection cable 150 comprises a single conductive wire for transmitting 1-bit serialized digital data 151 per elementary digital preprocessing chip 131, electrically connected to the digital output terminal e3 of the chip. As a variant, the terminal e3 can be replaced by any other connection element suitable for providing a 1-bit serialized digital signal, for example a pair of differential terminals. The conductive wire 151 can be replaced by any wire element for transmitting 1-bit serialized digital data, for example a shielded coaxial cable or a twisted pair of wires.Alternatively, the digital data transmission conductor wires may be replaced by optical fibers. In this case, an electrical-optical conversion component may be provided between terminal e3 and wire 151, for example via board 115.

[0061] Thus, in this example, the cable 150 comprises only AxB elementary conductive wires for transmitting digital output data 151 from the probe, connected respectively to the digital output terminals e3 of the AxB elementary digital preprocessing chips 131 of the probe.

[0062] The cable 150 may further comprise conductive wires intended to carry electrical power supply signals for the circuits of the probe 100.

[0063] The cable 150 may further comprise conductive wires intended to carry electrical signals for controlling the circuits of the probe 100.

[0064] Preferably, the electrical control signals of the probe are carried by the same AxB conductive wires 151 as the digital output data signals of the probe, and pass through the digital preprocessing chips 131.

[0065] [Fig.2] schematically and partially represents an example of the embodiment of the circuits of an elementary chip 121 of the analog transmission-reception circuit 120 of the probe 100 of [Fig.l].

[0066] In [Fig.2], an elementary transmission-reception cell 123 has been represented, a switching circuit 125, and an analog-to-digital converter 127. As explained above, each chip 121 comprises in practice CxD elementary cells 123, CxD / N switching circuits 125, and (CxD / N)xM analog-to-digital converters 127.

[0067] In this example, each elementary transmission-reception cell 123 comprises a transmission circuit 210, a reception circuit 220, and a switching circuit 230 (T / R SW).

[0068] The transmission circuit 210 is adapted to apply an electrical excitation signal to the corresponding elementary transducer 113 during a phase of transmission of an ultrasonic wave. The reception circuit 220 is adapted to condition and amplify an electrical response signal generated by the transducer 113 during a phase of reception of an ultrasonic wave.

[0069] The transmission circuit 210 comprises an output terminal ni intended to be connected, for example connected, to an electrode el of the associated transducer 113. In this example, the transmission circuit 210 comprises a TX pulse generator having an input node in intended to receive a logic control signal, and an output node out connected, for example connected, to the terminal ni. The input node in of the TX pulse generator can be connected, for example connected, to an output node of a logic control circuit, not shown, of the probe. When the logic signal applied to the input node in of the TX generator is in a first state, the TX generator provides a high level voltage on its output node out, and, when the logic signal applied to the node in of the TX generator is in a second state, the TX generator provides a low level voltage on its output node out.The output signal of the TX pulse generator corresponds to an excitation signal of the transducer 113, which can be applied directly to the electrode el of the transducer.

[0070] As a variant, the TX pulse generator is adapted to provide on its output node several distinct voltage levels generated from the same HV supply voltage. The TX pulse generator is then adapted to generate an excitation signal whose shape can be controlled by means of a control signal on several bits applied to its input in.

[0071] The reception circuit 220 comprises an input terminal n2 intended to be connected, for example connected, to the electrode el of the transducer 113, and an output node n3 intended to be connected, for example connected, to one of the N input nodes of the switching circuit 125 of the elementary transmission-reception group to which the cell 123 belongs.

[0072] In this example, the reception circuit 220 comprises a reception amplifier 221, preferably low noise (LNA), having an input node connected to terminal n2 and an output node connected to terminal n3. The amplifier 221 is for example a linear amplifier. In addition, in this example, the reception circuit 220 further comprises, between terminal n2 and the input of the amplifier 221, a time gain adjustment (TGC) circuit 223. The circuit 223 is configured to apply a time-variable analog gain to the response signal of the transducer applied to terminal n2, during a reception phase.More particularly, during a reception phase of a return ultrasonic wave by the transducer 113, the gain applied by the circuit 223 to the response signal of the transducer increases progressively as a function of time, and therefore as a function of the depth of the explored zone, so as to compensate for the attenuation of the ultrasonic signal by the explored medium. This makes it possible to make the best use of the dynamics of the analog-digital converter 127 throughout the duration of the reception phase, and thus to limit the quantization noise introduced by the analog-digital converter 127, in particular for the most distant ultrasonic echoes. As a variant, not shown, the time gain adjustment circuit 223 can be placed between the output of the amplifier 221 and the output terminal n3 of the reception circuit 220.In another variant, not shown, the time gain adjustment circuit can be omitted, and the amplifier 221 replaced by a non-linear amplifier.

[0073] In the example of [Fig.2], the reception circuit 220 further comprises a circuit 225 for applying a controllable delay or time to the response signal of the ultrasonic transducer. In the example shown, the circuit 225 is placed downstream of the amplification circuit 221, between the output of the amplification circuit 221 and terminal n3. As a variant, the circuit 225 can be placed upstream of the amplification circuit 221.

[0074] In each elementary transmission-reception cell 123, the switching circuit 205 is adapted to electrically connect the electrode el of the associated elementary transducer 113 either to the output terminal ni of the transmission circuit 210 or to the input terminal n2 of the reception circuit 220. By way of example, the switching circuit 205 comprises a first switch K1 having a first conduction node connected, for example connected, to the electrode el and a second conduction node connected, for example connected, to the terminal ni, and a second switch K2 having a first conduction node connected, for example connected, to the electrode el and a second conduction node connected, for example connected, to the terminal n2.

[0075] The signals for controlling the shape of the emitted pulses applied to the input in of the pulse generator TX are for example generated by control circuits (not shown) internal to the probe 100, or transmitted by dedicated conductive wires (not shown) of the cable 150.

[0076] As a variant, the pulse shape control signals, applied to the input in of the pulse generator TX, are transmitted via the data transmission wires 151 ([Fig.l]), the elementary digital preprocessing chips 131, and the switching circuits 125. For this, additional routing circuits, not detailed, can be provided in the transmission-reception chips 121 and in particular in the elementary transmission-reception cells 123.

[0077] Similarly, the control signals of the delay or delay applied by the analog circuit 225 to the electrical response signal of the ultrasonic transducer are for example generated by control circuits (not shown) internal to the probe 100, or transmitted by dedicated conductive wires (not shown) of the cable 150. Similarly, control signals of the circuit 223 can be generated by control circuits (not shown) internal to the probe 100, or transmitted by dedicated conductive wires (not shown) of the cable 150.

[0078] As a variant, the delay control signals applied by the analog circuit 225 are transmitted by the data transmission wires 151 ([Fig.l]), the elementary digital preprocessing chips 131, and the switching circuits 125, so as to limit the number of conductive wires of the cable 150.

[0079] [Fig. 3] schematically and partially represents an example of embodiment of an elementary digital preprocessing chip 131 of the digital preprocessing circuit 130 of the probe 100 of [Fig. 1].

[0080] The elementary chip 131 of [Fig. 3] comprises a plurality of elementary digital preprocessing cells 133 (PE). In [Fig. 3], 16 elementary cells 133 arranged in a matrix have been shown. In practice, each elementary chip 131 comprises (CxD / N)xM elementary cells 133, for example arranged in a matrix.

[0081] An enlarged and more detailed view of a cell 133 has further been shown in [Fig.3],

[0082] The elementary chip 131 further comprises a serialization circuit 301 (SERDES) connecting respective output nodes of the (CxD / N)xM elementary cells 133 of the chip to the single digital output terminal e3 of the chip. For example, each elementary cell 133 comprises a digital output node n4 connected, for example, to a specific input terminal of the circuit 301 via a data transmission bus 305. Thus, the circuit 301 receives in parallel digital signals supplied by the (CxD / N)xM elementary cells 133 on their respective nodes n4, and supplies a serialized digital signal applied to the single output terminal e3 of the chip.

[0083] The circuit 301 can further be adapted to implement a deserialization function to transmit in parallel on the nodes n4 (CxD / N)xM elem- 133 chip components, serialized control signals applied to terminal e3.

[0084] The elementary chip 131 further comprises a global control circuit 303 (GCTRL) connected, for example, to respective control nodes n5 of the (CxD / N)xM elementary cells 133 via one or more control buses 307.

[0085] Each elementary digital preprocessing cell 133 comprises for example an elementary memory circuit 311 (MEM) adapted to memorize control data and data supplied by the analog-digital converter 127 connected to the cell 131. By way of example, the elementary memory circuit 311 is adapted to memorize data read on the nodes e2, n4 and / or n5 of the cell, or to write data on the nodes e2, n4 and / or n5 of the cell.

[0086] Each elementary digital preprocessing cell 133 may further comprise an elementary calculation unit 313 adapted to implement calculation operations having as operands data stored in the elementary memory circuit 311 of the cell.

[0087] In this example, each elementary digital preprocessing cell 133 further comprises data input-output ports 315 for exchanging data between the elementary memory circuit 311 of the cell and the elementary memory circuits 311 of the neighboring elementary cells 133 of the cell. By neighboring cells, we mean here cells that are adjacent or separated by a number of cells that is significantly lower than the total number of cells of the circuit 131 in the direction considered, for example cells separated by a maximum of one cell (i.e. the immediate neighbor of an immediate neighbor) or by a maximum of two cells (i.e. the immediate neighbor of an immediate neighbor of an immediate neighbor).

[0088] An advantage of the ultrasound imaging probe 100 described in relation to FIGS. 1 to 3 is that it integrates close electronic control circuits making it possible to implement micro-beamforming processing in the context of ultra-fast acquisition scenarios, and thus to considerably limit the number of electrically conductive wires necessary to connect the probe to an external processing device, for example a computer.

[0089] By way of example, during a phase of acquiring data characteristic of a body to be analyzed, an ultrasonic wave is first sent towards the body to be analyzed during a transmission phase, then a return ultrasonic wave, reflected by the body to be analyzed, is measured during a reception phase.

[0090] During the emission phase, the emission-reception cells 123 are for example controlled in parallel to emit an ultrasonic excitation pulse, for example in the form of a plane wave, in the direction of the body to be analyzed. As for example, during the emission phase, also called ultrasonic firing, all the elementary transducers 113 can be controlled simultaneously in the same way (via the respective associated emission circuits 210).

[0091] During the reception phase, an acoustic signal reflected by the surface or internal structure of the body to be analyzed is measured by means of each elementary transducer 113, during an acquisition time window of determined duration (via the respective associated reception circuits 220).

[0092] Summations of the response signals supplied on the output nodes n3 of the reception circuits 220 of the transmission-reception cells 123 of each elementary transmission-reception group of each chip 121 are carried out by the switching circuits 125, thus carrying out micro-beam formation processing at the level of the elementary groups. The delay laws applied in the different elementary groups by the circuits 225 of each group are for example all identical. This results in a relatively low storage requirement for storing the delays.

[0093] After digitization by the analog-digital conversion circuits 127, the signals supplied by the different combiner circuits 125 can undergo various conditioning treatments in the digital preprocessing chips 131 before being transmitted to a processing device external to the probe via the cable 150. For example, in each elementary digital preprocessing cell 133, the memory circuit 311 of the cell is adapted to store a few thousand to a few tens of thousands of samples of the output signal of the associated analog-digital converter 127. For example, the memory circuit 311 is adapted to store the complete signal supplied by the analog-digital converter 127 during the reception window following an ultrasonic shot.The memory circuit 311 can be adapted to memorize the complete signal provided by the analog-digital converter 127 during several reception windows following respectively several successive ultrasonic shots.

[0094] Other delays, called macro-delays, may be applied by the external processing device 160, outside the probe 100, to perform macro-beamforming operations, by combining signals provided by the different analog-to-digital converters 127.

[0095] For example, each elementary group of emission cells 123 addresses one and only one column of ultrasonic transducers 113 of the associated ultrasonic transduction chip 111. The delay laws applied in the different elementary groups are for example identical. In each column, the delay law applied by the circuits 225 of the column are for example chosen to point or focus the reception at a point of elevation fixed in the plane of the column. For example for example, the reception is focused on the same elevation in all the columns.

[0096] Other combinations can then be carried out post-acquisition outside the probe (macro-beamforming operations), by means of the external device 160, to focus the reception on the different azimuths of the elevation line fixed during the acquisition.

[0097] Thus, the implementation of micro-beamforming operations inside the probe makes it possible to achieve a compromise on the quantity of data to be transmitted outside the probe and thus to implement varied and complete acquisition scenarios with great flexibility.

[0098] It will be noted that the embodiments described are not limited to the example detailed above in which the ultrasonic transduction circuit 110, the transmission-reception circuit 120 and the digital preprocessing circuit 130 are stacked vertically.

[0099] Given the large number of electrical connections between the circuits 110 and 120, the circuits 110 and 120 are preferably stacked vertically, on either side of the interconnection structure 115. The digital pre-processing circuit 130 can be offset laterally.

[0100] [Fig.4] is an exploded perspective view schematically showing and partial an alternative embodiment of the ultrasound imaging system of [Fig.l].

[0101] In this variant, the ultrasonic transduction circuit 110 and the transmission-reception circuit 120 are stacked vertically on either side of the interconnection support 115 in a manner similar to that described previously in relation to [Fig.l].

[0102] In the variant of [Fig. 4], the interconnection support 115 extends laterally beyond the circuits 110 and 120. The digital preprocessing circuit 130 is fixed and electrically connected to one face of the interconnection support 115, next to the circuit 110 or 120. In the example shown, the circuit 130 on the same side of the support 115 as the circuit 120, namely on the side of the lower face of the support 115 in the orientation of the figures. The circuit 130 is connected to the circuit 120 by conductive tracks of the interconnection support 115.

[0103] The conductors 151 of the cable 150 are for example connected on the side of the face of the support 115 opposite the circuit 130, directly above the circuit 130.

[0104] In the example shown, the interconnection support 115 is substantially planar. As a variant, not shown, the interconnection support 115 can be folded so that the connection plane of the circuit 130 forms an angle, for example of the order of 90°, with the connection planes of the circuits 110 and 120. This allows a different arrangement of the circuits, for example to promote heat dissipation.

[0105] [Fig.5] is a sectional view schematically and partially showing a another variant embodiment of the ultrasound imaging system of [Fig. 1].

[0106] In this variant, the digital preprocessing circuit 130 is fixed next to the transmission-reception circuit 120, on the same face of the interconnection support 115 as the transmission-reception circuit 120, in a manner similar to that described in relation to [Fig. 4]. The interconnection support 115 is then folded by 180° so as to place the circuit 130 opposite the circuit 120 and obtain a vertical stacking of the circuits 110, 120 and 130.

[0107] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the described embodiments are not limited to the numerical examples mentioned in this description.

[0108] Furthermore, as a variant, the analog-to-digital converters 127 may be integrated in the elementary chips 131 of the circuit 130 rather than in the elementary chips 121 of the circuit 120.

[0109] Furthermore, as a variant, the number N of elementary transmission-reception cells 123 in each elementary transmission-reception group of each elementary transmission-reception chip 121 may be less than 4, or even equal to 1 (i.e. a single elementary transmission-reception cell 123 per elementary group).

[0110] Furthermore, as a variant, in each elementary transceiver chip 121, the number M of outputs of the switching circuit 125 may be equal to N.

[0111] In the examples described above, the analog preprocessing circuit integrated in each transceiver chip 121, including in particular the switch 125, implements an analog micro-beamforming processing making it possible to reduce the number of channels at the input of the digital preprocessing circuit 131. As a variant, other analog processing operations can be implemented within the chips 121, replacing or supplementing the micro-beamforming processing. In the case where N is equal to 1, the switching circuit 125 can be omitted. In the case where N is equal to 1, the analog preprocessing circuits can be integrated in the elementary chips 131 of the digital preprocessing circuit 130.

[0112] Furthermore, in the examples described above, each elementary chip 131 of the digital preprocessing circuit comprises a single output terminal or a single element for supplying a binary data signal e3. The embodiments described are not limited to this particular case. As a variant, the number of output terminals or binary connection elements e3 per elementary chip 131 may be other than 1. Preferably, the number of output terminals or binary connection elements binary connection e3 of each elementary chip 131 is less than the number of elementary digital preprocessing cells 133 of the chip.

Claims

1. Claims An ultrasound imaging probe (100) comprising first (110), second (120) and third (130) circuits, wherein: - the first circuit (110) is an ultrasonic transduction circuit comprising a matrix of elementary ultrasonic transduction chips (111) each comprising a matrix of elementary ultrasonic transducers (113); - the second circuit (120) is a transmission-reception circuit comprising, for each elementary ultrasonic transduction chip (111), an elementary transmission-reception chip (121) comprising, for each elementary ultrasonic transducer (113) of the elementary ultrasonic transduction chip (111), an elementary transmission-reception cell (123) electrically connected to an electrode (el) of the transducer (113); - in each elementary transmission-reception chip (121), the elementary transmission-reception cells (123) of the chip are distributed into several elementary transmission-reception groups each comprising N elementary transmission-reception cells (123), with N being an integer greater than or equal to 1; - the probe comprises, for each elementary transmission-reception chip (121), for each elementary transmission-reception group of the chip, an analog preprocessing circuit (125) comprising N input terminals connected respectively to an output terminal (n3) of each elementary transmission-reception cell (123) of the elementary transmission-reception group, and M output terminals, with M less than or equal to NN; - the probe comprises, for each elementary transmission-reception group of each elementary transmission-reception chip (121), M analog-digital converters (127) each having an input terminal and an output terminal (e2), the input terminals of the M analog-digital converters (127) being connected respectively to the M output terminals of the analog pre-processing circuit (125) of the elementary transmission-reception group; - the third circuit (130) is a digital preprocessing circuit comprising, for each elementary transmission-reception chip (121), an elementary digital preprocessing chip (131) comprising, for each elementary transmission-reception group of the elementary chip- elementary transmission-reception group (121), M elementary digital pre-processing cells (133) connected respectively to the output terminals of the M analog-digital converters (127) associated with the elementary transmission-reception group; - each elementary digital pre-processing chip (131) comprises one or more binary connection elements (e3) each intended to provide a serialized digital signal, connected to all the elementary digital pre-processing cells of the chip via one or more serialization circuits (301).

2. Probe (100) according to claim 1, in which each elementary digital preprocessing cell (133) comprises an elementary memory circuit (311) and a calculation unit (313).

3. Probe (100) according to claim 1 or 2, in which each analog pre-processing circuit (125) is a combiner selector circuit adapted to provide, on each of its M output terminals, an analog summation, or superposition, of all or part of the signals applied to its N input terminals.

4. Probe (100) according to any one of claims 1 to 3, in which each transmission-reception cell (123) comprises a transmission circuit (210) adapted to generate an electrical excitation signal applied to the electrode (el) of the associated elementary transducer (113).

5. Probe (100) according to any one of claims 1 to 4, in which each transmission-reception cell (123) comprises a reception circuit (220) comprising an amplifier (221) having an input node connected to the electrode (el) of the elementary transducer (113) and an output node connected to the output terminal (n3) of the transmission-reception cell (123).

6. The probe (100) of claim 5, wherein, in each transceiver cell (123), the receiving circuit (220) further comprises a delay circuit (225) configured to apply a delay of adjustable duration to the output electrical signal of the transducer (113).

7. Probe (100) according to claim 6, in which each elementary digital preprocessing cell (133) comprises data input-output ports (315) allowing data to be exchanged between the elementary memory circuit (311) of the cell and the elementary memory circuits (311) of neighboring elementary cells (133).

8. A probe (100) according to any one of claims 1 to 7, wherein the first (110), second (120) and third (130) circuits are stacked vertically, the second circuit (120) being disposed between the first (110) and third (130) circuits.

9. A probe according to any one of claims 1 to 7, wherein two (110, 120) of the first (110), second (120) and third (130) circuits are stacked vertically, the remaining circuit (130) of the first (110), second (120) and third (130) circuits being laterally offset.

10. Probe (100) according to any one of claims 1 to 9, in which M is strictly less than N.

11. An ultrasound imaging system comprising an ultrasound imaging probe (100) according to any one of claims 1 to 10, an external processing device (160), and a digital data transmission channel (150) connecting the probe to the external processing device (160).

12. System according to claim 11, in which the digital data transmission channel (150) comprises one or more wired electrical or optical data transmission elements (151) per elementary digital preprocessing chip (131), electrically connected respectively to said one or more binary connection elements (e3) of the elementary chip.

13. The system of claim 11 or 12, wherein the external processing device (160) is configured to apply delays and combine signals from the analog-to-digital converters (127).

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