Device for measuring a power current delivered by a power FET transistor
The device addresses measurement inaccuracies in power FET transistors by optimizing transistor dimensions and ratios, ensuring precise and stable power current measurement despite temperature fluctuations.
Patent Information
- Application Number
- FR2023006826
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2023-06-28
- Publication Date
- 2025-07-11
- Estimated Expiration
- 2043-06-28
AI Technical Summary
Existing methods for measuring power current in power FET transistors face issues such as dynamic behavior differences and temperature-dependent responses due to edge effects and small transistor dimensions, leading to inaccurate measurements.
A device comprising a current measuring power FET transistor with specific semiconductor surface area and channel widths, coupled with additional FET transistors and a comparator, to accurately measure power current by optimizing transistor dimensions and ratios.
The solution provides accurate power current measurement with minimal temperature-dependent variations, ensuring the measured current closely resembles the actual load current, thus improving measurement precision and reliability.
Smart Images
Figure 00000020_0000 
Figure 00000020_0001 
Figure 00000021_0000
Abstract
Description
Title of the invention: Device for measuring a power current delivered by a power FET transistor Technical field
[0001] The present description generally relates to a device for measuring a power current delivered by a power FET transistor. Prior art
[0002] A measurement of the current delivered by a power FET transistor driving an electrical load can be implemented in particular to efficiently drive the electrical load, diagnose a problem on the load, or even to protect the load and the circuit to which it belongs.
[0003] To measure the current delivered by a power FET transistor driving an electrical load, it is possible to use another power FET transistor dedicated to this measurement, and coupled in a branch of the circuit parallel to that comprising the main power FET transistor.
[0004] In order for the current delivered by the measuring FET transistor to be very low compared to the current delivered by the main power FET transistor, the measuring FET transistor is produced by occupying a semiconductor surface area much smaller than that occupied by the main power FET transistor. The value of the ratio between the semiconductor surface area of the main power FET transistor and that of the measuring FET transistor can be chosen in particular as a function of the functionalities to be fulfilled by the power circuit in which the main power transistor is located and the values sought for the power current.
[0005] The characteristics of the measurement FET transistor, in particular the form factor, can be optimized at the level of each of its regions in order to avoid the problems encountered with power transistors of too small dimensions (difference in dynamic behavior compared to that expected, modification of the response of the transistor as a function of the operating temperature) and which are due in particular to edge effects and variations in the form factor of the edge and corner cells of the transistor. Summary of the invention
[0006] There is a need to propose a device for measuring a power current delivered by a main power FET transistor which does not have the drawbacks of existing solutions.
[0007] A particular embodiment addresses at least some of these problems and proposes a device for measuring a power current intended to be delivered by a main power FET transistor, comprising at least:
[0008] - a current measuring power FET transistor comprising a first source or drain electrode configured to be coupled to a first source or drain electrode of the main power FET transistor;
[0009] - first and second FET transistors whose gates are coupled electrically to each other, a first source or drain electrode of the first FET transistor being coupled to a second source or drain electrode of the current measuring power FET transistor,
[0010] wherein a first source or drain electrode of the second FET transistor is coupled to the first source or drain electrode of the first FET transistor, or
[0011] wherein the first source or drain electrode of the second FET transistor is configured to be coupled to a second source or drain electrode of the main power FET transistor or to a voltage source or load external to the device, and second source or drain electrodes of the first and second FET transistors are electrically coupled to each other.
[0012] According to a particular embodiment, a semiconductor surface of the current measuring power FET transistor and channel widths of the first and second FET transistors are such that the value of a ratio between a load current intended to be delivered on the second source or drain electrode of the main power FET transistor and an output current intended to be delivered on the second source or drain electrode of the first FET transistor is different from that of a ratio between a semiconductor surface of the main power FET transistor and the semiconductor surface of the current measuring power FET transistor.
[0013] According to a particular embodiment, the current measurement power FET transistor is of the VDMOSFET type, and the first and second FET transistors are of the MOSFET type.
[0014] According to a particular embodiment, the first and second FET transistors have channel widths that are different from each other.
[0015] According to a particular embodiment, the device further comprises a comparator having a first input configured to be coupled to the second source or drain electrode of the main power FET transistor, a second input coupled to the second source or drain electrode of the current measuring power FET transistor, and an output coupled to the gates of the first and second FET transistors.
[0016] According to a particular embodiment, the device further comprises at least one third FET transistor whose gate is coupled to the gates of the first and second FET transistors and whose first source or drain electrode is coupled to the first source or drain electrode of the first FET transistor or to the second source or drain electrode of the main power FET transistor.
[0017] According to a particular embodiment, the device further comprises:
[0018] - a fourth FET transistor of which a first source or drain electrode is coupled to the second source or drain electrode of the current measuring power FET transistor, and having a second source or drain electrode coupled to the first source or drain electrode of the first FET transistor;
[0019] - a comparator having a first input coupled to the second electrode source or drain electrode of the current measuring power FET transistor, a second input configured to be coupled to the second source or drain electrode of the main power FET transistor, and an output coupled to the gate of the fourth FET transistor.
[0020] In a particular embodiment, the first and second FET transistors are mounted in current mirror.
[0021] According to a particular embodiment:
[0022] - the first and second FET transistors are P-type;
[0023] - the gates of the first and second FET transistors are coupled to the second source and drain electrode of the first FET transistor;
[0024] - the first source or drain electrode of the second FET transistor is coupled to the first source or drain electrode of the first FET transistor.
[0025] In a particular embodiment:
[0026] - the first and second FET transistors are N-type;
[0027] - the gates of the first and second FET transistors are coupled to the first source and drain electrode of the first FET transistor;
[0028] - the second source or drain electrodes of the first and second transistors FETs are electrically coupled to each other.
[0029] According to a particular embodiment, a power control circuit for an electrical load is proposed, comprising at least:
[0030] - a main power FET transistor comprising a first electrode of source or drain electrode configured to be coupled to a source of electrical energy and a second source or drain electrode configured to be coupled to a terminal of the electrical load;
[0031] - a device for measuring a power current delivered by the FET transistor of main power as described above.
[0032] In a particular embodiment, the main power FET transistor and the current measuring power FET transistor are of the same conductivity type.
[0033] According to a particular embodiment, a method is proposed for producing a power control circuit for an electrical load, comprising at least one embodiment of a main power FET transistor comprising a first source or drain electrode configured to be coupled to a source of electrical energy and a second source or drain electrode configured to be coupled to a terminal of the electrical load, and a device for measuring a power current delivered by the main power FET transistor as described above.
[0034] According to a particular embodiment, the method further comprises, prior to the production of the main power FET transistor and the device for measuring the power current delivered by the main power FET transistor,a step of determining a semiconductor surface area of the current measuring power FET transistor and channel widths of the first and second FET transistors of the device for measuring the power current delivered by the main power FET transistor such that the value of a ratio between a load current intended to be delivered on the second source or drain electrode of the main power FET transistor and an output current intended to be delivered on the second source or drain electrode of the first FET transistor is different from that of a ratio between a semiconductor surface area of the main power FET transistor and the semiconductor surface area of the current measuring power FET transistor;
[0035] and at least the current measuring power FET transistor and the first and second FET transistors of the device are then made in accordance with the semiconductor surface area of the current measuring power FET transistor and the channel widths of the first and second FET transistors previously determined. Brief description of the drawings
[0036] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:
[0037] - [Fig.l] schematically represents an example of an embodiment of a device for measuring a power current delivered by a main power FET transistor, according to a first embodiment;
[0038] - [Fig.2] schematically represents an alternative embodiment of the device of measuring a power current delivered by a main power FET transistor, according to the first embodiment;
[0039] - [Fig.3] schematically represents an example of an embodiment of a device for measuring a power current delivered by a main power FET transistor, according to a second embodiment;
[0040] - [Fig.4] schematically represents an example of embodiment of the device of measuring a power current delivered by a main power FET transistor, according to a third embodiment;
[0041] - [Fig.5] schematically represents an example of an embodiment of a device for measuring a power current delivered by a main power FET transistor, according to a fourth embodiment;
[0042] - [Fig.6] schematically represents an alternative embodiment of the device of measuring a power current delivered by a main power FET transistor, according to the fourth embodiment;
[0043] - [Fig.7] schematically represents steps of a production method of a device for measuring a power current delivered by a main power FET transistor. Description of the embodiments
[0044] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.
[0045] For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed. In particular, the various transistors and the comparator of the power current measuring device are not detailed. Those skilled in the art will be able to produce these elements in detail from the functional description given here.
[0046] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected or coupled to each other, this means that these two elements can be connected or be linked by means of one or more other elements.
[0047] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.
[0048] In all the embodiments described, for each transistor, the first and second source or drain electrodes correspond to two electrodes different from each other of the same transistor, one of them corresponding to the source electrode and the other corresponding to the drain electrode.
[0049] A first example of a device 100 for measuring a power current delivered by a main power FET transistor 102 according to a first embodiment is described below in connection with [Fig.l].
[0050] In this first embodiment, the transistor 102 supplies an electrical load 104 by delivering a charging current called “I_load”. For example, the electrical load 104 corresponds to a motor or a lamp or any other electrical element intended to be powered by a power electrical current. The expression “power electrical current”, which applies to the charging current delivered by the transistor 102, designates for example an electrical current whose intensity is between a few milliamps and several tens of amps, this value being a function of the size of the transistor 102.
[0051] The transistor 102 and the device 100 are for example part of a power control circuit 1000 whose other components (converter, regulator, etc.) are not visible in [Fig.l]. In the example of [Fig.l], the power control circuit 1000 is of the “High Side” type, that is to say corresponds to a power control circuit interposed between the electrical load 104 and the positive electrical supply potential of this electrical load 104. Thus, the transistor 102 comprises a first source or drain electrode 106 coupled to an electrical supply potential “+V”, and a second source or drain electrode 108 coupled to a terminal of the electrical load 104 and on which the current I_load is delivered. The transistor 102 is intended to receive on its gate a signal controlling the electrical supply of the load 104.
[0052] In the first embodiment of [Fig.l], the transistor 102 is of type N. The first electrode 106 therefore corresponds to the drain of the transistor 102 and the second electrode 108 corresponds to the source of the transistor 102.
[0053] The device 100 comprises a current measuring power FET transistor 110 comprising a first source or drain electrode 112 coupled to the first electrode 106 of the transistor 102, and therefore to the electrical supply potential +V. The transistor 110 is intended to receive on its gate the same signal as that applied to the gate of the transistor 102. The transistors 102 and 110 are therefore put in the on or off state simultaneously.
[0054] In the embodiment example of [Fig.l], the transistor 110 is of type N, and therefore of the same type as that of the transistor 102. The first electrode 112 therefore corresponds to the drain of the transistor 110.
[0055] The device 100 also comprises first and second FET transistors, respectively referenced 114 and 116 and which, unlike the transistors 102, 110, are not power transistors. A first source or drain electrode 118 of the transistor 114 is coupled to a second source or drain electrode 120 of transistor 110, i.e. the source of transistor 110 in the embodiment described here.
[0056] In the exemplary embodiment of [Fig. 1], a first source or drain electrode 122 of the transistor 116 is coupled to the first electrode 118 of the transistor 114. The transistor 114 also comprises a second source or drain electrode 124 on which a measurement current called “Isense” is intended to be delivered. The transistor 116 also comprises a second source or drain electrode 126 on which a current is intended to be delivered, the characteristics of which are detailed later.
[0057] In the embodiment of [Fig. 1], the transistors 114, 116 are of P type, and therefore the first electrodes 118, 122 correspond to the sources of these transistors 114, 116 and the second electrodes 124, 126 correspond to the drains of these transistors 114, 116.
[0058] In this first embodiment, the device 100 also comprises a comparator 128 provided with a first input 130 coupled to the second electrode 108 of the transistor 102, a second input 132 coupled to the second electrode 120 of the transistor 110, and an output 134 coupled to the gates of the transistors 114, 116 which are therefore electrically coupled to each other. In this configuration, the voltages VGs of the transistors 114, 116 are therefore identical.
[0059] The transistors 110, 114, 116 of the device 100 are produced with a semiconductor surface of the transistor 110 and channel widths of the transistors 114, 116 which are such that the value of a ratio K_target = I_load / Isense is different from that of a ratio Kref between a semiconductor surface of the transistor 102 and the semiconductor surface of the transistor 110.
[0060] In the embodiment of [Fig. 1], the transistors 110, 114, 116 are dimensioned such that the value of the ratio K_target is greater than that of the ratio Kref between the semiconductor surfaces of the transistors 102 and 110. The transistor 110 therefore delivers, on its second electrode 120, a current Isense_ref = I_load / Kref of greater value than that of the current Isense.
[0061] Obtaining the current Isense from the current Isense_ref is possible thanks to the fact that the transistors 114, 116 both receive the current Isense_ref as input on their first electrode 118, 122 and deliver on their second electrode 124, 126 a part of this current Isense_ref. The transistor 114 has a channel width called “W1” and the transistor 116 has a channel width called “W2” which are such that W2 = K * Wl, with K a real number greater than 0. In the exemplary embodiment of [Fig.l], K corresponds to an integer greater than or equal to 1. According to a particular exemplary embodiment, the transistors 114, 116 may comprise channel widths different from each other, meaning that the value of K is different from 1, and for example greater than 1.
[0062] The current Isense delivered on the second electrode 124 of the transistor 114 is therefore such that Isense = I_load / K_target with K_target = Kref*(l+K), and the current delivered on the second electrode 126 of the transistor 116 is therefore equal to K*Isense. These currents verify the relationship Isense_ref = (l+K)*Isense.
[0063] From the measurement current Isense obtained, and knowing the values of the ratios Kref and K, it is therefore possible to determine the value of the current I_load. The measurement of the current Isense and the calculation of the current I_load can be carried out by elements of the device 100 not visible in [Fig.l].
[0064] Thus, the transistor 110 is produced with a larger semiconductor surface area than that which would allow the transistor 110 alone, without the presence of the transistors 114, 116, to deliver the current Isense.
[0065] In a particular exemplary embodiment, the current K*Isense delivered on the second electrode 126 of the transistor 116 can be reused for an application other than the measurement of the current I_load.
[0066] A variant of the device 100 according to the first embodiment is described below in connection with [Fig.2].
[0067] The device 100 according to this variant comprises all the elements and components of the device 100 previously described in connection with [Fig.l].
[0068] Furthermore, the device 100 visible in [Fig.2] comprises at least one third FET transistor 136 whose gate is coupled to the output 134 of the comparator 128 and therefore also to the gates of the transistors 114, 116. A first source or drain electrode 138 of the transistor 136 is coupled to the first electrode 118 of the transistor 114 (which is itself coupled to the first electrode 122 of the transistor 116 and to the second electrode 120 of the transistor 110).
[0069] In the embodiment described here, the transistor 136 is of the same type as the transistors 114, 116, i.e. P-type. Thus, the first electrode 138 corresponds to the source of the transistor 136, and the second electrode 140 corresponds to the drain of the transistor 136.
[0070] In the embodiment shown in [Fig.2], the transistors 114, 116, 136 are such that:
[0071] - transistor 114 has a channel width W1 and delivers on its second electrode 124 a currentIsense1;
[0072] - transistor 116 has a channel width W2 and delivers on its second electrode 126 an Isense2 current;
[0073] - transistor 136 has a channel width W3 and delivers on its second electrode source or drain 140 a current Isense3.
[0074] Thus, in the example of [Fig.2], the transistors 114, 116, 136 receive as input the current Isense_ref on their first electrode 118, 122, 138 and deliver on their second electrode 124, 126, 140 a part of this current Isense_ref. The currents Isensel, Isense2 and Isense3 delivered on the second electrodes 124, 126, 140 of these transistors 114, 116, 136 therefore verify the following relationships:
[0075] Isense_ref = Isensel + Isense2 + Isense3
[0076] Isensel = (W1 / (W1+W2+W3)) * Isense_ref
[0077] Isense2 = (W2 / (W1+W2+W3)) * Isense_ref
[0078] Isense3 = (W3 / (W1+W2+W3)) * Isense_ref
[0079] The different currents Isensel, Isense2, Isense3 can for example be used for distinct functions: diagnosis of the load 104, protection of the electrical harness coupled to the transistor 102, protection against current peaks, etc.
[0080] According to another variant, the device 100 could comprise a greater number of FET transistors comprising their first source or drain electrode coupled to the second electrode 120 of the transistor 110 and their second source or drain electrode on which a measurement current is obtained.
[0081] An example of a device 100 for measuring a power current delivered by the main power FET transistor 102 according to a second embodiment is described below in connection with [Fig.3].
[0082] The device 100 according to this second embodiment comprises all the elements and components of the device 100 previously described in connection with [Fig.l].
[0083] Unlike the device 100 according to the first embodiment, the first electrode 122 of the transistor 116 is not coupled to the first electrode 118 of the transistor 114, but to the second electrode 108 of the transistor 102. In addition, the second electrodes 124, 126 of the transistors 114, 116 are electrically coupled to each other.
[0084] Thus, unlike the first embodiment in which the current Isense delivered by the second transistor 114 is lower than the current Isense_ref delivered by the transistor 110, the current delivered by the second transistor 114 is equal to Isense_ref, to which is added, at the junction of the second electrodes 124, 126, the current delivered on the second electrode 126 of the transistor 116. The device 100 according to the second embodiment therefore makes it possible to obtain, at the junction of the second electrodes 124, 126 of the transistors 114, 116, a current Isense_target greater than the current Isense_ref delivered by the transistor 110.
[0085] In this second embodiment, the comparator 128 regulates the current flowing in the transistor 110 so as to have the potential on the second electrode 120 of the transistor 110 which is similar, or substantially equal, to that on the second electrode 108 of the transistor 102. The potential on the first electrode 118 of the transistor 114 (which is equal to that on the second electrode 120 of the transistor 110) is therefore similar, or substantially equal, to that on the first electrode 122 of the transistor 116 (which is equal to that on the second electrode 108 of the transistor 102). The voltages VGs of the transistors 114, 116 being similar, or substantially equal, due to the presence of the comparator 128, the values of the currents supplied by the transistors 114, 116 are therefore proportional to their respective sizes.
[0086] Thus, considering the channel width W1 of the transistor 114 and the channel width W2 of the transistor 116 which are such that W2 = K * Wl, the current Isense_target delivered to the junction of the second electrodes 124, 126 of the transistors 114, 116 is therefore such that Isense_target = I_sense_ref * (1+K), because the current delivered on the second electrode 124 of the transistor 114 is equal to Isense_ref and the current delivered on the second electrode 126 of the transistor 116 is equal to K * Isense_ref.
[0087] In this second embodiment, because the second electrodes 118, 122 of the transistors 114, 116 are not electrically coupled to each other, it is possible that the potentials applied to the second electrodes 118, 122 are not perfectly equal. A difference in potentials, for example equal to a few mV, may therefore appear on the inputs 130, 132 of the comparator 128, resulting in a variation in the current delivered by the transistor 116 relative to the current delivered by the transistor 114. However, the various components of the device 100 are sized and optimized (in particular the offset of the comparator 128 and the ratio of the dimensions of the transistors 114 and 116) in order to minimize this possible difference in potentials as much as possible.
[0088] An example of a device 100 for measuring a power current delivered by the main power FET transistor 102 according to a third embodiment is described below in connection with [Fig.4].
[0089] The device 100 according to this third embodiment comprises all the elements and components of the device 100 previously described in connection with [Fig.l].
[0090] Furthermore, the device 100 visible in [Fig.4] comprises the third FET transistor 136 whose gate is coupled to the output 134 of the comparator 128 and therefore also to the gates of the transistors 114, 116. The first source or drain electrode 138 of the transistor 136 is coupled to the second electrode 108 of the transistor 102.
[0091] As in the first embodiment, the transistors 114, 116 both receive as input the current Isense_ref on their first electrode 118, 122 and deliver on their second electrode 124, 126 a part of this current Isense_ref. The currents Isensel and Isense2 delivered on the second electrodes 124, 126 of these transistors 114, 116 therefore verify the following relationships:
[0092] Isense_ref = Isensel + Isense2
[0093] Isensel = (W1 / (W1+W2)) * Isense_ref
[0094] Isense2 = (W2 / (W1+W2)) * Isense_ref
[0095] with W1 corresponding to the channel width of transistor 114 and W2 corresponding to the channel width of transistor 116.
[0096] The transistor 136 also makes it possible to deliver, on its second electrode 140, a current Isense3 proportional to the current I_load.
[0097] Alternatively, it is possible for the second electrode 140 of the transistor 136 to be coupled to the second electrode 124, 126 of one of the transistors 114, 116 in order to obtain, at the injunction of the two second electrodes coupled to each other, a current corresponding to the sum of the current Isense3 with one of the currents Isensel or Isense2.
[0098] Alternatively, the device 100 may comprise one or more other FET transistors of which a first source or drain electrode is coupled to the first electrode 118 of the first transistor 114.
[0099] An example of a device 100 for measuring a power current delivered by the main power FET transistor 102 according to a fourth embodiment is described below in connection with [Fig.5].
[0100] The device 100 according to this fourth embodiment comprises all the elements and components of the device 100 previously described in connection with [Fig.l].
[0101] The device 100 according to this fourth embodiment also comprises another FET transistor 142 of which a first source or drain electrode 144 is coupled to the second electrode of the transistor 110, and of which a second source or drain electrode 146 is coupled to the first electrodes 118, 122 of the transistors 114, 116 which are electrically coupled to each other. In the exemplary embodiment of [Fig.5], the transistor 142 is of type P, the first electrode 144 corresponding to the source of the transistor 142 and the second electrode 146 corresponding to the drain of the transistor 142.
[0102] Unlike the embodiments and examples previously described, the output 134 of the comparator 128 is not electrically coupled to the gates of the transistors 114, 116 but to the gate of the transistor 142.
[0103] The transistors 114, 116 are mounted in a current mirror. Thus, the gates of the transistors 114, 116 are electrically coupled to each other and to the second electrode 124 of the transistor 114. A current Isensel is delivered to the second electrode 124 of the transistor 114 and a current Isense2 is delivered to the second electrode 126 of the transistor 116.
[0104] As in the first embodiment, the transistor 114 has a channel width W1 and the transistor 116 has a channel width W2 such that W2 = K * Wl, with K a real number greater than 0. In the exemplary embodiment of [Fig.l], K corresponds to an integer greater than or equal to 1. According to an exemplary embodiment In particular, the transistors 114, 116 may have channel widths that are different from each other, which means that the value of K is different from 1, and for example greater than 1.
[0105] As in the first embodiment, the transistors 114, 116 both receive as input the current Isense_ref on their first electrode 118, 122 and deliver on their second electrode 124, 126 a part of this current Isense_ref. The currents Isensel and Isense2 delivered on the second electrodes 124, 126 of these transistors 114, 116 mounted in current mirror therefore verify the following relationships:
[0106] Isense_ref = Isensel + Isense2
[0107] Isensel = (W1 / (W1+W2)) * Isense_ref
[0108] Isense2 = (W2 / (W1+W2)) * Isense_ref
[0109] A variant of the device 100 according to the fourth embodiment is described below in connection with [Fig.6].
[0110] The device 100 according to this variant comprises all the elements and components of the device 100 previously described in connection with [Fig.5].
[0111] However, in the device 100 according to the variant shown in [Fig.6], the transistors 114, 116 (mounted in current mirror) are of type N, their first electrode 118, 122 corresponding to the drain and their second electrode 124, 126 corresponding to the source of these transistors 114, 116. The gates of the transistors 114, 116 are electrically coupled to each other and to the first electrode 118 of the transistor 114. The first electrode 122 of the transistor 116 is coupled to a voltage source or a load (not visible in [Fig.6]) capable of delivering a current K*Isense_ref on the first electrode 122 of the transistor 116. The second electrodes 124, 126 of the transistors 114, 116 are electrically coupled to each other.
[0112] In this variant, the current Isense_target is equal to the current K * Isense_ref flowing in the first electrode 122 of the transistor 116, and the current Isensel flowing in the first electrode 118 of the transistor 114 is equal to the current Isense_ref. As in the previous examples, the transistor 114 has a channel width W1 and the transistor 116 has a channel width W2 such that W2 = K * Wl.
[0113] In all the embodiments, examples and variants described above, the current measurement accuracy obtained using the device 100 is for example less than or equal to 5% of the nominal value of the current I_load, throughout the operating temperature range of the device 100.
[0114] The proposed circuit makes it possible to use a current measuring power FET transistor of larger dimensions compared to existing solutions, and thus avoids the problems encountered with a transistor of too small dimensions, such as for example differences in dynamic behavior compared to that expected, or a change in the response of the measuring transistor as a function of the operating temperature, the effects of which would be similar to a change in the value of the K_target ratio as a function of the operating temperature. The behavior of the current measuring power FET transistor is also closer to that of the main power FET transistor, regardless of the values of external parameters such as temperature or VGs voltages applied to these transistors.
[0115] In all embodiments, examples and variants, the transistors are sized according to the desired values of the different ratios K_target, Kref and K, themselves being a function of the characteristics and functionalities of the electrical environment in which the device 100 and the circuit 1000 are used. For example, the value of the ratio K_target (which can be set according to the application of the device 100) can be greater than or equal to 1000, or for example to one of the following values: 1000, 2000, 10000, 40000. For example, the value of the ratio K_target can be 4 to 10 times greater than that of the ratio Kref.
[0116] In all embodiments, examples and variants, the main power FET transistor 102 and the current measuring power FET transistor may be, for example, VDMOSFET (Vertical Double diffused Metal-Oxide-Semiconductor Field-Effect Transistor) type transistors.
[0117] In all embodiments, examples and variants, the FET transistors 114, 116, 136, 142 may be, for example, MOSFET type transistors. Furthermore, these FET transistors 114, 116, 136, 142 may be N or P type.
[0118] In all embodiments, examples and variants, the FET transistors 114, 116, 136, 142 form an output stage making it possible to obtain at the output the measurement current having, relative to the load current, the desired ratio.
[0119] In all embodiments and variants, the main power FET transistor 102 and / or the current measuring power FET transistor 110 are of the same type, N or P.
[0120] As a variant of the previously described embodiments, the transistor 102 and the device 100 may be part of a power control circuit 1000 of the “Low Side” type, i.e. corresponding to a control circuit interposed between the electrical load 104 and the reference electrical potential of this electrical load 104. In this case, the first electrodes of the power transistors 102, 110 are not coupled to the supply electrode potential but to one of the terminals of the electrical load 104, and the second electrode 108 of the transistor 102 is coupled to the reference electrical potential.
[0121] The measuring device 100 and the control circuit 1000 can be produced in the form of independent modules or be integrated into chips or integrated circuits including other functions and for example produced using technology integrating power components and CMOS components, and / or bipolar (analog), CMOS (digital) and DMOS (“Double-Diffused MOS” in English, or double-diffused MOS, which are power components).
[0122] [Fig.7] schematically represents the steps of an example of a method for producing the circuit 1000 for controlling the power of the electrical load 104.
[0123] During a first step 200, the semiconductor surface area of the transistor 110 and the channel widths of the transistors 114, 116 are determined such that the value of the ratio K_target between the load current I_load and the output current Isense is different from that of the ratio Kref between the semiconductor surface area of the transistor 102 and the semiconductor surface area of the transistor 110. During this step, any other elements or components of the device 100 are also sized according to the characteristics desired for the device 100.
[0124] During a step 300, the main power FET transistor 102 and the various components of the device 100 are then produced. In particular, the transistors 110, 114 and 116 are produced in accordance with the previously determined channel surfaces and widths.
[0125] The measuring device 100 and the control circuit 1000 can be advantageously applied to the automotive field, for example in an electrical circuit for power distribution and management of a vehicle. The measuring device 100 and the control circuit 1000 can also be used in other fields, for example in the industrial field.
[0126] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.
[0127] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.
Claims
1. Claims Device (100) for measuring a power current intended to be delivered by a main power FET transistor (102), comprising at least: - a current measuring power FET transistor (110) comprising a first source or drain electrode (112) configured to be coupled to a first source or drain electrode (106) of the main power FET transistor (102); - first and second FET transistors (114, 116) whose gates are electrically coupled to each other, a first source or drain electrode (118) of the first FET transistor (114) being coupled to a second source or drain electrode (120) of the current measuring power FET transistor (110), wherein a first source or drain electrode (122) of the second FET transistor (116) is coupled to the first source or drain electrode (118) of the first FET transistor (114) so as to divide a current to be obtained on the second source or drain electrode (120) of the current-sensing power FET transistor (110), or wherein the first source or drain electrode (122) of the second FET transistor (116) is configured to be coupled to a second source or drain electrode (108) of the main power FET transistor (102) or to a voltage source or load external to the device (100), and second source or drain electrodes (124, 126) of the first and second FET transistors (114, 116) are electrically coupled to each other, and wherein a semiconductor surface of the current-sensing power FET transistor (110) and channel widths of the first and second FET transistors (114, 116) are such that the value of a ratio between a load current intended to be delivered to the second source or drain electrode (108) of the main power FET transistor (102) and an output current intended to be delivered to the second source or drain electrode (124) of the first FET transistor (114) is different from that of a report between a semiconductor surface of the main power FET transistor (102) and the semiconductor surface of the current measuring power FET transistor (110).
2. Device (100) according to one of the preceding claims, in which the current measuring power FET transistor (110) is of the VDMOSFET type, and in which the first and second FET transistors (114, 116) are of the MOSFET type.
3. Device (100) according to one of the preceding claims, wherein the first and second FET transistors (114, 116) have channel widths different from each other.
4. The device (100) of one of the preceding claims, further comprising a comparator (128) having a first input (130) configured to be coupled to the second source or drain electrode (108) of the main power FET transistor (102), a second input (132) coupled to the second source or drain electrode (120) of the current-sensing power FET transistor (110), and an output coupled to the gates of the first and second FET transistors (114, 116).
5. Device (100) according to one of the preceding claims, further comprising at least one third FET transistor (136) whose gate is coupled to the gates of the first and second FET transistors (114, 116) and whose first source or drain electrode (138) is coupled to the first source or drain electrode (118) of the first FET transistor (114) or to the second source or drain electrode (108) of the main power FET transistor (102).
6. Device (100) according to one of claims 1 to 3, further comprising: - a fourth FET transistor (142) having a first source or drain electrode (144) coupled to the second source or drain electrode (120) of the current-sensing power FET transistor (110), and having a second source or drain electrode (146) coupled to the first source or drain electrode (118) of the first FET transistor (114); - a comparator (128) having a first input (130) coupled to the second source or drain electrode (120) of the current-sensing power FET transistor (110), a second input (132) configured to be coupled to the second source or drain electrode (108) of the main power FET transistor (102), and an output (134) coupled to the gate of the fourth FET transistor (142).
7. The device (100) of claim 6, wherein the first and second FET transistors (114, 116) are connected in current mirror.
8. Device (100) according to claim 7, wherein: - the first and second FET transistors (114, 116) are P-type; - the gates of the first and second FET transistors (114, 116) are coupled to the second source or drain electrode (124) of the first FET transistor (114); - the first source or drain electrode (122) of the second FET transistor (116) is coupled to the first source or drain electrode (118) of the first FET transistor (114).
9. Device (100) according to claim 7, wherein: - the first and second FET transistors (114, 116) are N-type; - the gates of the first and second FET transistors (114, 116) are coupled to the first source or drain electrode (118) of the first FET transistor (114); - the second source or drain electrodes (124, 126) of the first and second FET transistors (114, 116) are electrically coupled to each other.
10. Circuit (1000) for controlling the power of an electrical load (104), comprising at least: - a main power FET transistor (102) comprising a first source or drain electrode (106) configured to be coupled to a source of electrical energy and a second source or drain electrode (108) configured to be coupled to a terminal of the electrical load (104); - a device (100) for measuring a power current delivered by the main power FET transistor (102), according to one of the preceding claims.
11. The circuit (1000) of claim 10, wherein the main power FET transistor (102) and the current measuring power FET transistor (110) are of the same conductivity type.
12. Method for producing a circuit (1000) for controlling the power of an electrical load (104), comprising at least one embodiment (200) of a main power FET transistor (102) comprising a first source or drain electrode (106) configured to be coupled to a source of electrical energy and a second source or drain electrode (108) configured to be coupled to a terminal of the electrical load (104), and a device (100) for measuring a power current delivered by the main power FET transistor (102), according to one of claims 1 to 9.
13. Method according to claim 12, further comprising, prior to the production (200) of the main power FET transistor (102) and the device (100) for measuring the power current delivered by the main power FET transistor (102), a step of determining (300) the semiconductor surface of the current measuring power FET transistor (110) and the channel widths of the first and second FET transistors (114, 116) of the device (100) for measuring the power current delivered by the main power FET transistor (102); and wherein at least the current measuring power FET transistor (110) and the first and second FET transistors (114, 116) of the device (100) are then made in accordance with the semiconductor surface area of the current measuring power FET transistor (110) and the channel widths of the first and second FET transistors (114, 116) previously determined.