Electronic device

Abstract

Electronic Device This description relates to an electronic device (10) comprising at least two three-dimensional capacitors (12), each capacitor (12) being surrounded by a trench (27) comprising a gas pocket (37). Figure for abbreviation: Fig. 1

Description

Title of the invention: Electronic device Technical field

[0001] This description relates generally to electronic devices and their manufacturing processes. More specifically, this description relates to devices comprising three-dimensional capacitors. Prior art

[0002] There are several types of capacitors. A particularly widespread type of capacitor is the so-called MOM, or Metal-Oxide-Metal, capacitor. Such capacitors comprise a stack of two conductive layers, preferably made of metal, separated by an insulating layer, preferably made of oxide, for example silicon oxide.

[0003] MOM capacitors can, for example, be planar, meaning that the stack covers a flat layer. MOM capacitors can also be three-dimensional, meaning that they cover a non-planar layer, for example, one containing cavities. Thus, a three-dimensional capacitor can have a significantly higher capacitance than a planar capacitor for the same chip area. Summary of the invention

[0004] An embodiment overcomes all or part of the drawbacks of known electronic devices.

[0005] One embodiment provides for an electronic device comprising at least two three-dimensional capacitors, each capacitor being surrounded by a trench comprising a gas pocket.

[0006] Another embodiment provides for a method of manufacturing an electronic device comprising the formation of at least two three-dimensional capacitors, each capacitor being surrounded by a trench comprising a gas pocket.

[0007] According to one embodiment, the capacitors and trenches are in a first insulating layer.

[0008] According to one embodiment, each capacitor is located in a first region of the first layer, each trench being located in a second region of the first layer separated from the first region by a third region of the first layer.

[0009] According to one embodiment, each third region is not covered with conductive material.

[0010] According to one embodiment, each capacitor comprises a first em stacking of two conductive layers separated by an insulating layer, the first stack extending conformally over the first region of the first layer, the first region comprising at least two first cavities, the first stack filling the first cavities.

[0011] According to one embodiment, each trench comprises a second stack of layers identical to the first stack, extending conformably into a second cavity, the gas pocket being located in the second cavity, partially delimited by the second stack.

[0012] According to one embodiment, the device includes a second layer closing each second cavity, and partially delimiting the gas pocket located in the second cavity.

[0013] According to one embodiment, each first region is covered with a third layer of the same material as the second layer.

[0014] According to one embodiment, the second layer extends, in the second cavity, over less than 20% of the height of the second cavity.

[0015] According to one embodiment, each gas pocket extends over at least half the height of the first cavities.

[0016] According to one embodiment, the trenches surrounding at least two neighboring capacitors include common portions.

[0017] According to one embodiment, the trenches surrounding at least two neighboring capacitors are separated from each other by portions of the first layer.

[0018] According to one embodiment, the device includes a filter, the capacitors being part of the filter.

[0019] According to one embodiment, the process comprises: the formation in the first layer of the first and second cavities; the formation of a third stack of two conductive layers separated by an insulating layer in a conforming manner, the first cavities being filled, the second cavities not being filled, the formation of a fourth non-conforming layer closing the second cavities; the etching of the third stack and the fourth layer in the third regions so as to form the first and second stacks and the second and third layers.

[0020] According to one embodiment, the formation of the fourth layer is carried out by a physical vapor phase deposition process or by a plasma-activated chemical vapor phase deposition process. Brief description of the drawings

[0021] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example. relationship with the attached figures, among which:

[0022] [Fig.1A] represents a cross-sectional view of an embodiment of a device comprising a three-dimensional capacitor;

[0023] [Fig.1B] represents a top view of the embodiment of [Fig.1A];

[0024] [Fig. 2A] represents a step in a manufacturing process for the device of the figures IA and IB;

[0025] [Fig.2B] represents another step in a manufacturing process for the device of figures IA and IB;

[0026] [Fig.2C] represents another step in a manufacturing process for the device of figures IA and IB;

[0027] [Fig.3] represents two views illustrating two arrangements of the capacitors of figures IA and IB. Description of the embodiments

[0028] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0029] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0030] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0031] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0032] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0033] Fig. 1A represents a cross-sectional view of an embodiment of a device 10 comprising a three-dimensional capacitor 12. Fig. 1B represents a top view of the embodiment of Fig. 1A.

[0034] The device 10 includes an insulating layer 14. The layer 14 is, for example, made of an electrically insulating material, for example silicon oxide. The layer 14 corresponds, for example, to a layer of a metallization level of a lattice interconnection. Thus, layer 14, for example, covers a semiconductor substrate not shown. Layer 14, for example, covers one or more other insulating layers, each including, for example, metallizations or conductive vias.

[0035] The layer 14 comprises a set of cavities 16. The cavities 16, for example, have identical dimensions. Each cavity 16 extends from an upper face of the layer 14 to an internal level of the layer 14. In other words, each trench does not cross the layer 14. In other words, the height of the cavities 16 is less than the height of the layer 14.

[0036] The cavities 16 of the set are all present in a region 17 of the layer 14. The cavities 16 of the set are, for example, arranged in a matrix in the region 17. Each set of cavities 16 comprises, for example, at least two cavities, for example, between 2 and 3000 cavities. Each cavity 16 is, for example, separated from the nearest cavity 16 of the same set only by a portion of the layer 14.

[0037] The capacitor 12 is formed in and on the cavities 16. The capacitor 12 is, for example, a metal-insulator-metal type capacitor. In other words, the capacitor 12 comprises a conductive layer 18, an insulating layer 20, and a conductive layer 22. The conductive layers 18 and 22 are, for example, made of metal. The layer 20 is made of a dielectric material.

[0038] Layer 18, corresponding to a lower electrode of the capacitor 12, covers the walls and bottom of the cavities 16 of the assembly. Layer 18 also covers the portions of the upper surface of layer 14 located between the cavities 16 and covers portions of the upper surface of layer 14 around the cavities 16. In other words, layer 18 completely covers the upper surface of region 17 of layer 14 and the interior of the cavities 16. Layer 18 thus conformally covers region 17 of layer 14.

[0039] Layer 20 extends over layer 18, for example over the whole of layer 18. Layer 20 extends conformally over layer 18. Layer 20 extends over the portions of layer 18 located in the cavities 16 and over the portions of layer 18 located on the upper face of layer 14.

[0040] Layer 22, corresponding to an upper electrode of the capacitor 12, extends over layer 20, for example over the entire layer 20. Layer 22 extends in particular into the cavities 16, preferably over at least half the height of the cavities 16. The dimensions of the cavities 16 and of the layers 18, 20, 22 are chosen such that the cavities 16 are completely filled by the layers 18, 20, 22.

[0041] Layers 18, 20, 22 extend only in region 17. Region 17 is surrounded by a region 24 of layer 14. Layers 18, 20, 22 do not extend over the upper face of region 24.

[0042] Region 24 is preferably made entirely of the material of layer 14. Region 24 preferably does not include any conductive material. Region 24 is preferably not covered with conductive material.

[0043] Layer 14 further includes a region 26. Region 26 surrounds region 24. Region 26 therefore surrounds region 17. Region 26 is separated from region 17 by region 24, preferably at every point.

[0044] The device 10 includes a trench 27. The trench 27 includes a cavity 28 located in the region 26. The cavity 28 forms a ring. The cavity 28 surrounds the regions 17 and 24. Thus, the cavity 28 surrounds the set of cavities 16.

[0045] The dimensions of the cavity 28 are preferably greater than the dimensions of one of the cavities 16. More specifically, the height of the cavity 28 is preferably greater than the height of one of the cavities 16. At least one of the dimensions of the opening of the cavity 28, i.e. the dimensions of the cavity 28 in the plane of the upper face of the layer 14, is greater than the dimensions of the opening of one of the cavities 16. Preferably, all the dimensions of the opening of the cavity 28 are greater than the dimensions of the opening of a cavity 16.

[0046] The trench 27 comprises a stack of layers 30, 32, 34 extending conformably in the region 26. Layer 30 is made of the same material as layer 18 and has a thickness substantially equal to the thickness of layer 18. Similarly, layer 32 is made of the same material as layer 20 and has a thickness substantially equal to the thickness of layer 20. Similarly, layer 34 is made of the same material as layer 22 and has a thickness substantially equal to the thickness of layer 22.

[0047] Layer 30 conforms to the region 26. Thus, layer 30 covers the lateral walls and the bottom of the cavity 28. Layer 30 also covers the portions of the upper face of layer 14 located in the region 26.

[0048] Layer 32 conformally covers layer 30. Preferably, layer 30 is completely covered by layer 32. Thus, layer 32 extends into cavity 28 and over the upper face of region 28.

[0049] Layer 34 conforms to layer 32. Preferably, layer 32 is completely covered by layer 34. Thus, layer 34 extends into cavity 28 and over the upper face of region 26.

[0050] Layers 30, 32, 34 extend only in region 26. Layers 30, 32, 34 do not extend over the upper face of region 24.

[0051] The trench 27 further comprises a layer 36. Layer 36 extends over the portions of layer 34 located outside the cavity 28. Thus, layer 36 extends opposite the upper face of region 26. Layer 36 also extends at the level of the opening of the cavity 28. The cavity 28 is thus closed by layer 36. The layer 36 preferably comprises a first portion extending in the plane of the upper face of layer 14 and second portions extending into an upper portion of the cavity. Preferably, the second portions extend, from the opening of cavity 28, to a height less than 20% of the height of cavity 28, and preferably less than 10% of the height of cavity 28. Layer 36 does not fill cavity 28. Thus, a cavity, or pocket, 37 filled with gas, for example air, is maintained within cavity 28. The pocket 37 is delimited by layer 34 and layer 36. The pocket 37 preferably extends over at least 50% of the height of cavities 16, and preferably over at least 75% of the height of cavities 16.

[0052] The device 10 further comprises a layer 38 made of the same material as layer 36. Layer 38 preferably completely covers layer 22.

[0053] Layer 36 preferably does not extend over the upper face of region 24. Similarly, layer 38 preferably does not extend over the upper face of region 24.

[0054] Layers 36 and 38 are for example made of an insulating material or of a conductive material, for example of a metal.

[0055] The device 10 includes, for example, connecting elements (not shown) for connecting the upper electrode 22 and lower electrode 18 of the capacitor 12 to a circuit. The connecting elements correspond, for example, to conductive vias passing through layer 38 to reach layer 22, or passing through layers 20 and 38 at a portion of layer 20 not covered by layer 22, to reach layer 18.

[0056] Filling the cavities 16 with layers of material induces stress on layer 14. More precisely, filling the cavities 16 with layers of material induces lateral stress on layer 14, represented by arrows in Figures IA and IB. Filling each cavity 16 induces stress that is added to the stress generated by the other cavities 16. During the formation of a plate consisting solely of filled cavities 16, the filling of the cavities 16 can induce stress sufficient to warp the plate and thus disrupt the manufacturing steps. A warped plate may not be able to be fed into a machine performing a step of the manufacturing process.

[0057] The pockets 37 allow the stress generated by the layers 18, 20, 22 to be absorbed in the cavities 16. Thus, the regions 17 and 24 are subjected to the stress generated by the layers 18, 20, 22 located in the cavities 16 of the region 17, but are not subjected to the stress generated by other regions 17 located outside the trench 27.

[0058] The trenches 27 are preferably electrically insulated. In other words, the layers 30, 32, 34 are preferably not connected to any electronic component or conductive element. The trenches 27, for example, serve only to absorb the stress generated by the capacitors 12.

[0059] The presence of gas in the pocket 37 can lead to the presence of undesirable elements in the cavity and in contact with the layer 34. However, since the trenches 27 have no electrical function, the formation of defects on the layer 34 does not modify the absorption of the stress generated by the capacitor 12.

[0060] Figures 2A to 2C represent steps, preferably successive, of a manufacturing process for the device 10 of Figures IA and IB.

[0061] Fig. 2A represents a step in a manufacturing process for the device shown in Figures 1A and 1B.

[0062] During this step, layer 14 is formed. Layer 14 is formed, for example, on a substrate or support not shown. Layer 14 is, for example, a planar layer. The upper and lower faces of layer 14 are then parallel.

[0063] The step in [Fig.2A] then includes the formation of cavities 16 in region 17, and the formation of cavity 28 in region 26. The formation of cavities 16 and 28 is preferably carried out simultaneously, by the same etching step.

[0064] The formation of cavities 16 and 28 includes, for example, the formation of a mask (not shown) on the upper surface of layer 14. This mask (not shown) comprises openings opposite the locations of cavities 16 and 18, these openings having dimensions substantially equal to the dimensions of the openings of cavities 16 and 18. The formation of the cavities then includes etching layer 14 through the openings of the mask. The difference between the dimensions of the opening of trenches 16 and the dimensions of the opening of trench 28 results in the difference in height of the cavities formed during the etching.

[0065] Fig. 2B represents another step in a manufacturing process for the device of Figures IA and IB.

[0066] During this step, a stack of layers 40, 42, 44 is formed conformally on at least regions 17, 24 and 26, preferably on the whole of layer 14.

[0067] Layer 40 is made of the same material as layers 18 and 30. Layer 40 has a thickness substantially equal to the thickness of layers 18 and 30. Layer 42 is made of the same material as layers 20 and 32. Layer 42 has a thickness substantially equal to the thickness of layers 20 and 32. Layer 44 is made of the same material as layers 22 and 34. Layer 44 has a thickness substantially equal to the thickness of layers 22 and 34.

[0068] Layer 40 conforms to the regions 17, 24, 28. Preferably, layer 40 conforms to the entire layer 14. Thus, layer 40 covers the lateral walls and the bottom of the cavities 16 and 28. Layer 40 also covers the upper face of the regions 17, 24, 26 of layer 14.

[0069] Layer 42 conforms to the layer 40. Preferably, the layer 42 completely covers layer 40. In particular, layer 42 covers the portions of layer 40 located in cavities 16 and 28 and on the upper faces of regions 17, 24, 26.

[0070] Similarly, layer 44 conformally covers layer 42. Preferably, layer 44 completely covers layer 42. In particular, layer 44 covers the portions of layer 42 located in cavities 16 and 28 and on the upper faces of regions 17, 24, 26. Layer 44 has a thickness such that, after the formation of layer 44, the cavities 16 are filled by the stacking of layers 40, 42, 44. The thicknesses of layers 40, 42, 44 are such that cavity 28 is not filled by layers 40, 42, 44. The dimensions of cavity 28 and of layers 40, 42, 44 are such that, over at least half the height of cavity 28, the portions of layer 44 extending over opposite lateral walls of cavity 28 are not in contact.

[0071] Fig. 2C represents another step in a manufacturing process for the device of Figures IA and IB.

[0072] During this step, a non-conforming layer 46 is formed on the structure resulting from the step in [Fig. 2B]. The layer 46 is made of the same material as the layers 36 and 38. The layer 46 is formed so as to close the cavity 28, while retaining the gas pocket 37 in the cavity 28. The layer 46 is formed, for example, by a physical vapor deposition (PVD) process, the layer 46 being, for example, made of metal, or by a plasma-enhanced chemical vapor deposition (PECVD) process, the layer 46 being, for example, made of a dielectric, for example, silicon oxide.

[0073] The process further comprises, after the step in [Fig.2C], a step of etching the portions of layers 40, 42, 44, 46 located on region 24. Layers 18, 20, 22, 30, 32, 34 are thus formed.

[0074] The process further includes the formation of the connection elements not shown allowing the connection of electrodes 18 and 22.

[0075] Figure 3 shows two views, 3A and 3B, illustrating two arrangements of the capacitors in Figures IA and IB. Each arrangement comprises four capacitors 12. The device may, however, comprise any number of capacitors 12, for example, at least two. Capacitors 12 are used, for example, in filters.

[0076] In [Fig.3], the regions 26, including the trenches 27, are represented by simple lines, the regions 17 including the capacitors 12 are represented by hatched rectangles and the regions 24 separating the regions 26 and 17 are represented by the white bands separating the rectangles and the simple lines.

[0077] According to the embodiment of view 3A, illustrating a first example In the arrangement, the trenches 27 form a grid, delimiting the regions 24. In the embodiment of view 3A, the trenches 27 form columns and rows of a mesh and delimit a matrix of locations each comprising a region 17 and a region 24, preferably a single region 17 and a single region 24. All the trenches 27 are thus connected to each other.

[0078] Two neighboring capacitors are separated by a single trench 27. Two neighboring capacitors are therefore separated by a portion of region 24, a trench 27 and a portion of another region 24.

[0079] According to the embodiment of view 3B, illustrating a second example of arrangement, the device comprises an assembly matrix including a region 17, a region 24, and a region 26, the different assemblies being separated from each other by a portion 50 of the substrate 14. The trenches 27 are thus independent of each other. In other words, the trenches 27 are separated from each other by the portions 50.

[0080] Two neighboring capacitors are separated by two trenches 27. Two neighboring capacitors are therefore separated by a portion of region 24, a trench 27, a portion 50, a trench 27 and a portion of another region 24.

[0081] Although, in [Fig.3], the capacitors 12 are aligned in rows and columns, the capacitors may, for example, be aligned in rows and have offset columns.

[0082] Furthermore, the device comprising capacitors 12 may include portions in which the capacitors are arranged according to the first arrangement and portions in which the capacitors are arranged according to the second arrangement.

[0083] One advantage of the described embodiments is that it is possible to form plates having a high density of three-dimensional capacitors without causing deformation.

[0084] Another advantage of the described embodiments is that, since the trenches 27 are not electrically active, the presence of the gas pocket does not cause damage and does not impact the efficiency of the capacitors.

[0085] Another advantage of the described embodiments is that the simultaneous formation of the trenches 27 and the capacitors 12 avoids deformation of the plate and avoids the addition of a forming step.

[0086] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0087] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given herein. above.

Claims

Claims

1. Electronic device (10) comprising at least two three-dimensional capacitors (12), each capacitor (12) being surrounded by a trench (27) comprising a gas pocket (37).

2. A method of manufacturing an electronic device (10) comprising forming at least two three-dimensional capacitors (12), each capacitor (12) being surrounded by a trench (27) comprising a gas pocket (37).

3. A device according to claim 1 or a method according to claim 2, wherein the capacitors (12) and trenches (27) are in a first insulating layer (14).

4. The device or method of claim 3, wherein each capacitor (12) is located in a first region (17) of the first layer (14), each trench (27) being located in a second region (26) of the first layer (14) separated from the first region (17) by a third region (24) of the first layer (14).

5. The device or method of claim 4, wherein each third region (24) is not covered with conductive material.

6. A device or method according to claim 4 or 5, wherein each capacitor (12) comprises a first stack (18, 20, 22) of two conductive layers separated by an insulating layer, the first stack conformally extending over the first region of the first layer, the first region comprising at least two first cavities (16), the first stack filling the first cavities (16).

7. A device or method according to claim 6, wherein each trench (27) comprises a second stack (30, 32, 34) of layers identical to the first stack (18, 20, 22), extending conformably into a second cavity (28), the gas pocket (37) being located in the second cavity (28), partially delimited by the second stack (30, 32, 34).

8. Device or method according to claim 7, wherein the device (10) comprises a second layer (36) closing each second cavity (28), and partially delimiting the gas pocket (37) located in the second cavity.

9. A device or method according to claim 8, wherein each first region (17) is covered with a third layer (38) in the second layer material (36).

10. A device or method according to claim 8 or 9, wherein the second layer (36) extends, in the second cavity (28), over less than 20% of the height of the second cavity.

11. A device or method according to any one of claims 6 to 10, wherein each gas pocket (37) extends over at least half the height of the first cavities (16).

12. A device according to any one of claims 1, 3 to 11 or a method according to any one of claims 2 to 11, wherein the trenches (27) surrounding at least two neighboring capacitors (12) comprise common portions.

13. A device according to any one of claims 1, 3 to 11 or a method according to any one of claims 2 to 11, wherein the trenches (27) surrounding at least two neighboring capacitors (12) are separated from each other by portions (50) of the first layer.

14. A device according to any one of claims 1, 3 to 13, wherein the device comprises a filter, the capacitors forming part of the filter.

15. A method according to any one of claims 7 to 10, the method comprising: forming in the first layer the first and second cavities; forming a third stack of two conductive layers separated by an insulating layer in a conformal manner, the first cavities being filled, the second cavities not being filled, forming a fourth non-conformal layer closing the second cavities; etching the third stack and the fourth layer in the third regions so as to form the first and second stack and the second and third layers.

16. The method of claim 15, wherein the formation of the fourth layer is carried out by a physical vapor deposition method or a plasma-activated chemical vapor deposition method.

Images