Display screen comprising display pixels including light sources

Abstract

Display screen comprising display pixels including light sources. This description relates to a display pixel (Pix2) comprising a light source, a light source control circuit (45) for driving said light source, first and second electrically conductive solder pads (P_Row, P_Col) connected to the control circuit, a first transmission circuit (50, 52), and third and fourth conductive pads connected to the first transmission circuit. When the third conductive pad (P_STD_IN, P_DATA_IN) is electrically connected outside the display pixel, the first transmission circuit sends a first signal (STD, DATA), received at the third conductive pad, to the fourth conductive pad (P_STD_OUT, P_DATA_OUT), and sends a second signal (Comi, Dataj) to the control circuit and to one of the first and second conductive pads. Figure for the abbreviation: Fig. 10

Description

Title of the invention: Display screen comprising display pixels comprising luminescent sources Technical field

[0001] The present description relates to a display screen having display pixels comprising light-emitting sources, for example light-emitting diodes. Prior art

[0002] A pixel of an image corresponds to the unit element of the image displayed by a display screen. For the display of color images, the display screen generally comprises, for the display of each pixel of the image, at least three components, also called display sub-pixels, which each emit light radiation, called image pixel color component substantially in a single color (for example, red, green and blue). The superposition of the image pixel color components emitted by the three display sub-pixels provides the observer with the colored sensation corresponding to the pixel of the displayed image. In this case, the assembly formed by the three display sub-pixels used for the display of a pixel of an image is called a display pixel of the display screen. Each display sub-pixel may comprise a light-emitting source, in particular a light-emitting diode.

[0003] The display pixels may be distributed in a matrix, with each display pixel located at the intersection of a row (also referred to as a line) and a column of the matrix. Row electrodes are provided along the rows for connecting each display pixel to a row drive circuit, and column electrodes are provided along the columns for connecting each display pixel to a column drive circuit. Generally, each row of display pixels is successively selected by a signal transmitted along the row electrodes, and the display pixels in the selected row are programmed to display the desired image pixels by signals transmitted along the column electrodes.

[0004] An active matrix is ​​a screen control architecture that allows all rows of display pixels to be kept active for the entire duration of an image, unlike so-called passive matrices, where each row is active only for a time T = Tframe / M (where Tframe is the display time of the entire image and M is the number of rows on the screen). This allows the brightness of the display screen to be increased. In addition, it is possible to send low voltage levels or current on the matrix control lines, allowing larger data streams to be displayed.

[0005] The row driver circuit and the column driver circuit of the display screen are generally located on two sides of the display pixel matrix. A disadvantage is that, given the space occupied by the row driver circuit and the column driver circuit, it may be difficult to produce a frameless display. Furthermore, for certain applications, it is desirable to be able to manufacture a display screen by assembling several elementary display screens, or panels.However, a display screen including a row drive circuit and a column drive circuit located on two sides of the display pixel array cannot be used as an elementary display screen because, at the time of assembling a plurality of such elementary display screens, the row drive circuits and the column drive circuits of the elementary display screens are located among the display pixels. Summary of the invention

[0006] An object of an embodiment is to provide a display screen comprising display pixels overcoming all or part of the drawbacks of existing display screens comprising such display pixels.

[0007] Another object is that the display screen may be a frameless screen.

[0008] Another object is that the display screen can be used as a display screen elementary for the manufacture of a display screen by assembling several elementary display screens.

[0009] One embodiment provides a display screen comprising a matrix of display pixels arranged in rows and columns. Each display pixel comprises at least one light-emitting source and a light-emitting source control circuit for driving said light-emitting source. The display pixels comprise first display pixels and second display pixels, at least some of the second display pixels being connected in series in a first succession. Each second display pixel of the first succession further comprises a first transmission circuit configured to: - sending first display data to the display pixels of the column of said second display pixel and to transmit second display data to the next second display pixel of the first succession; or - sending a first selection signal to the display pixels of the line of said second display pixel and to transmit a second selection signal to the next second display pixel of the first succession.

[0010] The second display pixels can advantageously be used, in a display screen, as a column drive circuit for a column of the display screen or as a row drive circuit for a row of the display screen. A display screen comprising such second display pixels does not comprise a separate row drive circuit and / or a separate column drive circuit. Therefore, a frameless display can be manufactured because there is no need for a reserved space for the row drive circuit and the column drive circuit. Furthermore, the display screen comprising such second display pixels can be used to manufacture a display screen having a tiled structure comprising multiple copies of the display screen comprising such second display pixels.

[0011] According to one embodiment, each display pixel comprises first and second electrically conductive solder pads connected to said light-emitting source control circuit. Each second display pixel further comprises third and fourth electrically conductive solder pads connected to said first transmission circuit.Said first transmission circuit is configured, when the third electrically conductive solder pad is electrically connected outside the display pixel, to send a first signal, received on the third electrically conductive solder pad, to the fourth electrically conductive solder pad, and to send a second signal to the light-emitting source control circuit and to one of the first and second electrically conductive solder pads, wherein the first signal corresponds to a first selection signal and wherein the second signal corresponds to a second selection signal; or wherein the first signal corresponds to the first display data and wherein the second signal corresponds to the second display data.

[0012] The number of conductive pads of each first display pixel is advantageously kept as low as possible. Furthermore, the structure of the first display pixels and the second display pixels may be partially the same.

[0013] According to one embodiment, for each first display pixel, the first electrically conductive solder pad is intended to receive the second selection signal and the second electrically conductive solder pad is intended to receive the second data signal.

[0014] According to one embodiment, the display screen comprises, for each row, a first electrically conductive track connecting the first electrically conductive solder pads of the first and second display pixels of said row, and, for each column, a second electrically conductive track connecting the second electrically conductive solder pads of the first and second display pixels of said column.

[0015] According to one embodiment, in the first succession, the fourth electrically conductive solder pad of a second display pixel of the first succession is connected to the third electrically conductive solder pad of the next second display pixel of the first succession. There is no need for additional conductive tracks extending over the entire row or column to connect the second display pixels.

[0016] According to one embodiment, for each second display pixel of the first succession, the light-emitting source control circuit of the second display pixel is configured to receive the second signal sent by the first transmission circuit of the second display pixel to drive the light-emitting source and, for each second display pixel which is not in the first succession, the third electrically conductive solder pad of the second display pixel is not electrically connected to the outside of the second display pixel and the light-emitting source control circuit of the second display pixel is configured to receive the second signal, received on the first electrically conductive solder pad, to drive the light-emitting source.Connecting the second display pixel in the display screen advantageously automatically controls which signals are used by the control circuit of the light-emitting source of the second display pixel.

[0017] According to one embodiment, each second display pixel further comprises a second transmission circuit, and fifth and sixth electrically conductive solder pads connected to said second transmission circuit. Said second transmission circuit is configured, when the fifth electrically conductive solder pad is electrically connected to the outside of the display pixel, to send a third signal, received on the fifth electrically conductive solder pad, to the sixth electrically conductive solder pad, and to send a fourth signal to the light-emitting source control circuit and to the other of the first and second electrically conductive solder pads.The first signal corresponds to the first selection signal, the second signal corresponds to the second selection signal, the third signal corresponds to the first display data, and the fourth signal corresponds to the second display data. The first transmission circuit of each second display pixel of the first succession is configured to send the second selection signal to the display pixels of the row of said second display pixel and to transmit the first selection signal to the next second display pixel of the first succession. At least some of the second display pixels are connected in series in a second succession, and wherein the second transmission circuit of each second display pixel of the second succession is . configured to send the second display data to the display pixels of the column of said second display pixel and to transmit the first display data to the next second display pixel of the second succession.

[0018] The display screen may advantageously comprise only two types of display pixels, namely first display pixels and second display pixels. The second display pixel may advantageously be used, in a display screen, as a column drive circuit for a column of the display screen or as a row drive circuit for a row of the display screen.

[0019] According to one embodiment, in the second succession, the sixth electrically conductive solder pad of a second display pixel of the second succession is connected to the fifth electrically conductive solder pad of the next second display pixel of the second succession. There is no need for additional conductive tracks extending over the entire row or column to connect the second display pixels.

[0020] According to one embodiment, for each second display pixel of the second succession, the light-emitting source control circuit of the second display pixel is configured to receive the fourth signal sent by the second transmission circuit of the second display pixel to drive the light-emitting source and, for each second display pixel which is not in the second succession, the fifth electrically conductive solder pad of the second display pixel is not electrically connected to the outside of the second display pixel and the light-emitting source control circuit of the second display pixel is configured to receive the fourth signal, received on the first electrically conductive solder pad, to drive the light-emitting source.Connecting the second display pixel in the display screen advantageously automatically controls which signals are used by the control circuit of the light-emitting source of the second display pixel.

[0021] According to one embodiment, the display screen comprises a row and a column of the second display pixels, the other display pixels of the display screen being the first display pixels.

[0022] According to one embodiment, the first transmission circuit of each second display pixel comprises an electronic control circuit and a demultiplexer. Said electronic control circuit is configured to receive the first data signal and the first selection signal and configured to send the second data signal or the second selection signal to the demultiplexer. Said demultiplexer is configured to transmit the second data signal to the second electrically conductive pad or the second selection signal to the first electrical pad. trically conductive according to a control signal. It is the value of the multiplexer control signal that controls the operation of the second display pixel as a row driver or column driver.

[0023] According to one embodiment, the display screen comprises a row and a column of the second display pixels with the exception of a single display pixel which is one of the first display pixels, the other display pixels of the display screen being the other first display pixels.

[0024] According to one embodiment, the first transmission circuit of each second display pixel of the first succession is configured to send the second data signal to the display pixels of the column of said second display pixel and to transmit the first data signal to the next second display pixel of the first succession. The display pixels comprise third display pixels different from the second display pixels. The third display pixels are connected in series in a second succession. Each third display pixel comprises a third transmission circuit configured to send the second selection signal to the display pixels of the row of said third display pixel and to transmit the first selection signal to the next third display pixel of the second succession.Since the third display pixel may be different from the second display pixel, the structure of each third display pixel and each second display pixel may advantageously be simplified.

[0025] According to one embodiment, the display screen comprises a row of second display pixels and a column of third display pixels with the exception of the display pixel at the intersection of said row and said column which is one of the first display pixels, the other display pixels of the display screen being the other first display pixels.

[0026] According to one embodiment, the display screen comprises a row of second display pixels and a column of third display pixels except for the display pixel of said row, or comprising a column of third display pixels and a row of second display pixels except for the display pixel of said column, the other display pixels of the display screen being the first display pixels.

[0027] According to one embodiment, the display screen comprises a row of second display pixels except for one display pixel of said row which is a third display pixel and a column of third display pixels except for one display pixel of said column which is a second display pixel, the other display pixels of the display screen being the first pixels display except for a display pixel that is a second display pixel or a third display pixel.

[0028] According to one embodiment, each light-emitting source control circuit comprises a storage circuit for storing at least one digital signal, the light-emitting source control circuit being configured to drive said light-emitting source on the basis of the stored digital signal, and to update said stored digital signal from the first data signal upon detection of a pattern of the first selection signal.

[0029] According to one embodiment, said light-emitting source control circuit is configured not to update said stored digital signal from the first data signal when the pattern of the first selection signal is not detected.

[0030] According to one embodiment, each display pixel comprises a stack of a first electronic circuit comprising the light-emitting source control circuit and a second electronic circuit comprising the light-emitting source.

[0031] One embodiment provides a display pixel comprising: - at least one electroluminescent source; - a light-emitting source control circuit for driving said light-emitting source; - first and second electrically conductive solder pads connected to said light-emitting source control circuit; - a first transmission circuit; and - third and fourth electrically conductive solder pads connected to said first transmission circuit, said first transmission circuit being configured, when the third electrically conductive solder pad is electrically connected to the outside of the display pixel, to send a first signal, received on the third electrically conductive solder pad, to the fourth electrically conductive solder pad, and to send a second signal to the light-emitting source control circuit and to one of the first and second electrically conductive solder pads.

[0032] Such a display pixel may advantageously be used, in a display screen, as a column drive circuit for a column of the display screen or as a row drive circuit for a row of the display screen. A display screen comprising such modified display pixels does not comprise a separate row drive circuit and / or a separate column drive circuit. Therefore, a frameless display can be manufactured since there is no need for a reserved space for the row drive circuit and the row drive circuit. column. Furthermore, the display screen comprising such modified display pixels can be used to manufacture a display screen having a mosaic structure comprising multiple copies of the display screen comprising such modified display pixels.

[0033] According to one embodiment, the light-emitting source control circuit is configured to receive the second signal received on said one of the first and second electrically conductive solder pads when the third electrically conductive solder pad is not electrically connected to the outside of the display pixel.

[0034] According to one embodiment, the display pixel further comprises: - a second transmission circuit; and - fifth and sixth electrically conductive solder pads connected to said second transmission circuit, said second transmission circuit being configured, when the fifth electrically conductive solder pad is electrically connected to the outside of the display pixel, to send a third signal, received on the fifth electrically conductive solder pad, to the sixth electrically conductive solder pad, and to send a fourth signal to the light-emitting source control circuit and to the other of the first and second electrically conductive solder pads.

[0035] The same display pixel may advantageously be used, in a display screen, as a column driver for a column of the display screen or as a row driver for a row of the display screen.

[0036] According to one embodiment, the light emitting source control circuit is configured to receive the fourth signal received on said other of the first and second electrically conductive solder pads when the fifth electrically conductive solder pad is not electrically connected to the outside of the display pixel. Brief description of the drawings

[0037] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0038] [Fig.l] partially and schematically represents an example of a display screen;

[0039] [Fig.2] partially and schematically represents another example of a display screen;

[0040] [Fig.3] schematically represents the locations occupied by the circuits of control of the display screen of [Fig.l];

[0041] [Fig.4] is a schematic view of a display screen produced by assembling several copies of the display screen of [Fig.l] representing the locations occupied by the control circuits of the display screen;

[0042] [Fig.5] partially and schematically represents an embodiment of a display screen;

[0043] [Fig.6] is a highly simplified cross-sectional view of a display pixel of a first type of the display screen of [Fig.5];

[0044] [Fig.7] represents a block diagram of an embodiment of the display pixel of the first type;

[0045] [Fig.8] is a bottom view of the display pixel of [Fig.7];

[0046] [Fig.9] is a very simplified cross-sectional view of a display pixel of a second type of the display screen of [Fig.5];

[0047] [Fig. 10] represents a block diagram of an embodiment of the display pixel of the second type;

[0048] [Fig. 11] is a bottom view of the display pixel of [Fig. 10];

[0049] [Fig. 12] is a schematic view of the display screen of [Fig.5] representing the connection of electrodes and display pixels;

[0050] [Fig. 13] partially and schematically represents another embodiment of a display screen;

[0051] [Fig. 14] represents a block diagram of an embodiment of a display pixel of a third type of the display screen of [Fig. 13];

[0052] [Fig. 15] is a bottom view of the display pixel of [Fig. 14];

[0053] [Fig. 16] is a schematic view of the display screen of [Fig. 13] showing the connection of electrodes and display pixels;

[0054] [Fig. 17] partially and schematically represents another embodiment of a display screen;

[0055] [Fig. 18] represents a block diagram of an embodiment of a display pixel of a fourth type of the display screen of [Fig. 17];

[0056] [Fig. 19] is a bottom view of the display pixel of [Fig. 18];

[0057] [Fig.20] represents a block diagram of an embodiment of a display pixel of a fifth type of the display screen of [Fig.17];

[0058] [Fig.21] is a bottom view of the display pixel of [Fig.20];

[0059] [Fig.22] is a schematic view of the display screen of [Fig. 17] showing the connection of the electrodes and the display pixels;

[0060] [Fig.23] partially and schematically represents another embodiment of a display screen;

[0061] [Fig.24] is a schematic view of the display screen of [Fig.23] showing the connection of electrodes and display pixels;

[0062] [Fig.25] partially and schematically represents another embodiment of a display screen;

[0063] [Fig.26] is a schematic view of the display screen of [Fig.25] showing the connection of the electrodes and the display pixels;

[0064] [Fig.27] partially and schematically represents another embodiment of a display screen;

[0065] [Fig.28] is a schematic view of the display screen of [Fig.27] showing the connection of the electrodes and the display pixels; and

[0066] [Fig.29] partially and schematically represents another embodiment of a display screen. Description of the embodiments

[0067] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed.

[0068] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be linked by means of one or more other elements. In addition, a signal which alternates between a first constant state, for example a low state, denoted "0", and a second constant state, for example, a high state, denoted "1", is called a "binary signal". The high and low states of different binary signals of the same electronic circuit can be different. In practice, binary signals can correspond to voltages or currents which may not be perfectly constant in the high or low state.

[0069] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean within 10%, preferably within 5%. In addition, the expression "substantially constant" means that it varies by less than 10% over time relative to a reference value.

[0070] In the following description, embodiments are described for display pixels comprising light-emitting diodes. However, these embodiments may be implemented for display pixels comprising light-emitting sources other than light-emitting diodes, for example organic light-emitting diodes, light-emitting components field-induced polymers, or laser diodes.

[0071] In the following description, embodiments are described for a color display screen comprising color display pixels, each display pixel comprising light-emitting diodes adapted to emit radiation of different colors. However, these embodiments also apply to a monochrome display screen comprising monochrome display pixels, each monochrome display pixel comprising a light-emitting diode or only light-emitting diodes adapted to emit radiation of a single color.

[0072] [Fig. 1] partially and schematically represents an example of a display screen 10. The display screen 10 comprises a matrix 12 of display pixels Pixlij, for example, arranged in M ​​rows and N columns, M being an integer varying from 1 to 8,000 and N being an integer varying from 1 to 16,000, i being an integer varying from 1 to M, and j being an integer varying from 1 to N. By way of example, in [Fig.l], M and N are equal to 3.

[0073] For each row, the display pixels Pixlij of the row are connected to at least one row electrode E_Row;. For each column, the display pixels Pixlij of the column are connected to at least one column electrode E_Colj. The display screen 10 comprises a row control circuit 14 connected to the row electrodes E_Row; and adapted to deliver a selection and synchronization signal Com; on each row electrode E_Row;. The display screen 10 comprises a column control circuit 16 connected to the column electrodes E_Colj and adapted to deliver a data signal Dataj on each column electrode E_Colj. The row control circuit 14 and the column control circuit 16 are controlled by a circuit 18, comprising for example a microprocessor, hereinafter called a synchronization controller.According to one embodiment, the selection and synchronization signal Com; is a binary signal and the data signal Dataj is a binary signal.

[0074] Furthermore, each display pixel Pixl^ is connected to a source of low reference potential Gnd, for example, ground, via an electrode not shown in [Fig.l], and to a source of high reference potential Vcc, via an electrode not shown in [Fig.l]. The supply voltage of the display screen corresponds to the voltage between the high reference potential Vcc and the low reference potential Gnd. The supply voltage depends in particular on the arrangement of the light-emitting diodes and the technology according to which the light-emitting diodes are manufactured. For example, the supply voltage may be of the order of 3.5 V to 5.5 V.

[0075] Generally, each row of display pixels is selected in succession, and the display pixels of the selected row are programmed to display the pixels desired image. In a known method of selecting display pixels, the row driver 14 is adapted to provide the selection and synchronization signals Com; on the row electrodes E_Row; to successively select each row of display pixels Pi x 1, and the column driver 16 is adapted to provide data signals Dataj on each column electrode E_Colj representative of color digital data which are stored in the selected display pixels Pixiij.

[0076] In [Fig.l], the row driver 14 is a multi-channel driver and the column driver 16 is a multi-channel driver.

[0077] [Fig.2] partially and schematically represents a variant of the display screen 10 in which the row control circuit 14 comprises several single-channel row control circuits 14i to 143 and the column control circuit 16 comprises several single-channel column control circuits 16i to 163.

[0078] [Fig. 3] schematically represents, for the display screen 10 of [Fig. 1] or 2, the areas occupied by the matrix 12 of display pixels, the row driver 14 and the column driver 16. As can be seen in [Fig. 3], the row driver 14 and the column driver 16 are generally located on two sides of the matrix 12 of display pixels. A disadvantage is that, given the space occupied by the row driver 14 and the column driver 16, it may be difficult to provide a frameless screen.

[0079] [Fig. 4] is a schematic view of a display screen 20 having a mosaic structure, meaning that it comprises an assembly of several copies of the display screen 10. As shown in [Fig. 4], some of the row driver circuits 14 and column driver circuits 16 are located among the display pixel matrices 12. Therefore, the display screen 10 is not suitable for manufacturing a display screen having a mosaic structure.

[0080] The present invention involves modifying certain display pixels of the display screen so that they also collectively perform, in addition to displaying image pixels, the function usually performed by the row drive circuit and the column drive circuit. A display screen including such modified display pixels does not include a row drive circuit or a column drive circuit. Therefore, a frameless display can be manufactured because there is no need for a space reserved for the row drive circuit or the column drive circuit. Furthermore, the display screen including such modified display pixels can be used to manufacture a display screen having a tiled structure including multiple copies of the display screen including such modified display pixels.

[0081] Furthermore, according to the present invention, the number of conductive tracks connecting the synchronization controller 18 to the display pixel matrix is ​​reduced, preferably at most equal to six conductive tracks. This advantageously makes it possible to reduce the number of solder pads for connecting the display pixel matrix. Furthermore, according to the present invention, the display screen does not comprise a row control circuit or a column control circuit. This advantageously makes it possible to reduce the number of chips connected to the display pixel matrix.

[0082] [Fig.5] partially and schematically represents an embodiment of a display screen 30. The display screen 30 comprises a matrix 32 of display pixels, for example arranged in M ​​rows and N columns, i being an integer varying from 1 to M, and j being an integer varying from 1 to N. In the present embodiment, the display screen 30 comprises display pixels Pixl of a first type (Pixel) and display pixels Pix2 of a second type (Pixel & Driver). The first column of the matrix 32 comprises display pixels of the second type Pix2; i, i varying from 1 to M, and the first row of the matrix 32 comprises display pixels of the second type Pix2ij, j varying from 1 to N. The other display pixels of the matrix 32 are of the first type. Therefore, the matrix 32 comprises a sub-matrix of display pixels of the first type Pixhj, i being an integer varying from 2 to M, and j being an integer varying from 2 to N.The synchronization controller 18 is connected to the display pixel Pix2i at the first row and at the first column. The synchronization controller 18 is configured to send four signals CLK_COL, DATA, CLK_ROW, STD to the display pixel Pix2i. According to one embodiment, each signal CLK_COL, DATA, CLK_ROW, STD is a binary signal.

[0083] In the present embodiment, each display pixel Pixl of the first type only fulfills the function of displaying an image pixel. In the present embodiment, each display pixel Pix2 of the second type, in addition to fulfilling the function of displaying an image pixel, comprises a single row / column driver circuit which can operate as a single row driver circuit providing the selection and synchronization signal Com; to the row to which it belongs and / or as a single column driver circuit providing the data signal Dataj to the column to which it belongs depending on the connection of the display pixel. According to one embodiment, the selection and synchronization signal Com; is a binary signal and the data signal Dataj is a binary signal.

[0084] [Fig.6] is a highly simplified cross-sectional view of the display pixel Pixl of the first type. The display pixel Pixl comprises a driver circuit 34 covered by a display circuit 36. The driver circuit 34 comprises a lower surface 38 and an upper surface 40 opposite the lower surface 38, the surfaces 38 and 40 preferably being planar and parallel. The display circuit 36 comprises a lower surface 42 and an upper surface 44 opposite the lower surface 42, the surfaces 42 and 44 preferably being planar and parallel. The surface 38 corresponds to the lower surface of the display pixels Pixl and Pix2 and the surface 44 corresponds to the upper surface of the display pixels Pixl and Pix2. The upper surface 40 of the driver circuit 34 is attached to the lower surface 42 of the display circuit 36.

[0085] The display circuit 36 ​​comprises at least one light-emitting diode, preferably at least three light-emitting diodes LED_R, LED_G, LED_B. The control circuit 34 may correspond to an integrated circuit comprising electronic components, in particular insulated gate field effect transistors, also called MOS transistors, or thin-film transistors, also called TFTs. Preferably, the display circuit 36 ​​comprises only light-emitting diodes LED_R, LED_G, LED_B and the conductive elements of these light-emitting diodes LED_R, LED_G, LED_B, and the control circuit 34 comprises all the electronic components necessary for controlling the light-emitting diodes LED_R, LED_G, LED_B of the display circuit 36. According to a variant, the display circuit 36 ​​may also comprise other electronic components in addition to the light-emitting diodes LED_R, LED_G, LED_B.The LED_R, LED_G, LED_B light-emitting diodes can be 2D light-emitting diodes, also called planar light-emitting diodes, comprising a stack of planar layers, or 3D light-emitting diodes each comprising a three-dimensional semiconductor element covered with an active area.

[0086] According to one embodiment, the display pixel Pixl comprises at least three light-emitting diodes LED_R, LED_G, LED_B emitting light at first, second and third wavelengths. According to one embodiment, the first wavelength corresponds to blue light and is in the range from 430 nm to 490 nm. According to one embodiment, the second wavelength corresponds to green light and is in the range from 510 nm to 570 nm. According to one embodiment, the third wavelength corresponds to red light and is in the range from 600 nm to 720 nm. Alternatively, the display pixels Pixl and Pix2 may include a single light-emitting diode emitting light at the first, second, or third wavelength, or only two light-emitting diodes emitting light at two of the first, second, and third wavelengths.

[0087] In [Fig.6], the light-emitting diodes LED_R, LED_G, LED_B are shown as being connected to a common anode. The control circuit 34 comprises, visible on the upper surface 40, a conductive pad R connected to the cathode of the light-emitting diode LED_R, a conductive pad G connected to the cathode of the light-emitting diode LED_G, a conductive pad B connected to the cathode of the light-emitting diode LED_B and a conductive pad A connected to the anodes of the light-emitting diodes LED_R, LED_G, LED_B. However, it may be desirable to arrange the light-emitting diodes LED_R, LED_G, LED_B in another configuration. For example, the light-emitting diodes can be connected with a common cathode, or be connected independently of each other.

[0088] The control circuit 34 further comprises at least conductive solder pads P_Gnd, P_Vcc, P_Col, P_Row on the lower surface 38 in order to electrically connect the display pixel Pixl with the outside. Each conductive solder pad P_Gnd, P_Vcc, P_Col, P_Row is intended to be connected to an electrode. The first conductive pad P_Gnd is connected to the low reference potential source Gnd. The second conductive pad P_Vcc is connected to the high reference potential source Vcc. The third conductive pad P_Row is connected to the row electrode E_Row; and receives the selection and synchronization signal Com;. The fourth conductive pad P_Col is connected to the column electrode E_Colj and receives the data signal Dataj.

[0089] [Fig.7] shows a block diagram of an embodiment of the control circuit 34 of the display pixel Pixl. The control circuit 34 of the display pixel Pixl comprises an electronic circuit 45 comprising a light-emitting diode control circuit 46 which controls light-emitting diodes by means of the conductive pads R, G, B and comprising a control and memory circuit 48 for controlling the light-emitting diode control circuit 46. The control and memory circuit 48 receives the selection and synchronization signal Com;, received at the conductive pad P_Row, and the data signal Dataj, received at the conductive pad P_Col. The control circuit 34 is powered by the high reference potential Vcc, received at the conductive pad P_Vcc and the low reference potential Gnd, received at the conductive pad P_Gnd.

[0090] The light-emitting diode control circuit 46 may comprise three controllable current sources, each connected to one of the conductive pads R, G and B. Each controllable current source may comprise a MOS transistor. In the present example, for each light-emitting diode, the anode of the light-emitting diode receives the high reference potential Vcc by means of the conductive pad A and the cathode of each light-emitting diode is for example connected to the terminal of the respective controllable current source by means of the conductive pads R, G and B, the other terminal of the controllable current source receiving the low reference potential Gnd.

[0091] The control and memory circuit 48 may in particular comprise electronic components such as MOS transistors. According to one embodiment, the control and memory circuit 48 comprises a storage circuit configured to store digital color signals based on the received digital data. The digital color signals each comprise a number NB of bits and are representative of the color components of the image pixel to be displayed. The control and memory circuit 48 is configured to control the light-emitting diode control circuit 46 with signals obtained from digital color signals. According to one embodiment, the light-emitting diodes are controlled by pulse width modulation, also called PWM (acronym for "Pulse Width Modulation").According to another embodiment, the light-emitting diodes are controlled by pulse amplitude modulation, also called PAM (acronym for "Pulse Amplitude Modulation").

[0092] [Fig.8] is a bottom view of the control circuit 34 of the display pixel Pixl. On the lower surface 38, the display pixel Pixl comprises only four conductive pads P_Vcc, P_Gnd, P_Row and P_Col. The number of conductive pads of the display pixel Pixl is advantageously kept as low as possible.

[0093] [Fig.9] is a very simplified cross-sectional view of the Pix2 display pixel of the second type. The Pix2 display includes all the elements of the Pixl display pixel and further includes additional solder conductive pads P_CLK_ROW_IN, P_STD_IN, P_CLK_COL_IN, P_DATA_IN, P_CLK_ROW_OUT, P_STD_OUT, P_CLK_COL_OUT, P_DATA_OUT and P_Vdd in order to electrically connect the Pix2 display pixel with the outside. Depending on the position of the Pix2 display pixel in the display pixel matrix, the conductive pad P_Row can transmit or receive the selection and synchronization signal Com;. Depending on the position of the Pix2 display pixel in the display pixel matrix, the conductive pad P_Col can transmit or receive the data signal Dataj.

[0094] [Fig. 10] shows a block diagram of an embodiment of the control circuit 34 of the display pixel Pix2. The control circuit 34 of the display pixel Pix2 comprises the electronic circuit 45 of the control circuit 34 of the display pixel Pixl, which is shown in dotted lines in [Fig. 10]. The control circuit 34 of the display pixel Pix2 further comprises a first transmission circuit 50, also called row control circuit 50 hereinafter, and a second transmission circuit 52, also called column control circuit 52 hereinafter. The control circuit 34 of the display pixel Pix2 comprises, in addition to the conductive pads P_Vcc, P_Gnd, P_Row and P_Col, conductive pads additional P_CLK_ROW_IN, P_STD_IN, P_CLK_COL_IN, P_DATA_IN, P_CLK_ROW_OUT, P_STD_OUT, P_CLK_COL_OUT, P_DATA_OUT and P_Vdd.

[0095] The control circuit 34 receives, from the conductive pad P_Vdd, a supply voltage Vdd lower than the supply voltage Vcc. The row control circuit 50 receives the signal CLK_R0W, received at the pad P_CLK_ROW_IN, and receives the signal STD, received at the pad P_STD_IN. The row control circuit 50 provides the signal CLK_R0W at the pad P_CLK_ROW_OUT and provides the signal STD at the pad P_STD_OUT. The row control circuit 50 provides the selection and synchronization signal Com; at the pad P_Row and also to the electronic circuit 45 by means of the conductive path internal to the control circuit 34. The column control circuit 52 receives the signal CLK_COL, received at the pad P_CLK_COL_IN, and receives the signal DATA, received at the pad P_DATA_IN. The column driver circuit 52 provides the CLK_COL signal at the P_CLK_COL_OUT pad and provides the DATA signal at the P_DATA_OUT pad.The column control circuit 52 provides the data signal Dataj at the P_Col pad and also to the electronic circuit 45 by means of the internal conductive path to the control circuit 34.

[0096] [Fig. 11] is a bottom view of the control circuit 34 of the display pixel Pix2. On the bottom surface 38, the display pixel Pix2 comprises thirteen conductive pads P_Vcc, P_Gnd, P_Row, P_Col, P_CLK_ROW_IN, P_STD_IN, P_CLK_COL_IN, P_DATA_IN, P_CLK_ROW_OUT, P_STD_OUT, P_CLK_COL_OUT, P_DATA_OUT and P_Vdd.

[0097] [Fig. 12] is a schematic view of the display screen 30 of [Fig. 5] showing the connection of the electrodes and the display pixels.

[0098] For the pixel Pix2i i of the first row and the first column, the pads P_CLK_ROW_IN, P_STD_IN, P_CLK_COL_IN and P_DATA_IN are connected to the synchronization controller 18, not shown in [Fig. 12]. The pad P_CLK_ROW_IN of the display pixel Pix2i i receives the signal CLK_R0W from the synchronization controller 18. The pad P_STD_IN of the display pixel Pix2i i receives the signal STD from the synchronization controller 18. The pad P_CLK_COL_IN of the display pixel Pix2i i receives the signal CLK_COL from the synchronization controller 18. The pad P_DATA_IN of the display pixel Pix2i i receives the signal DATA from the synchronization controller 18.

[0099] For the display pixels Pix2; i of the first column, i varying from 2 to M, the pads P_CLK_ROW_IN and P_STD_IN of the display pixel Pix2; i are connected to the pixel Pix2i ii . The pad P_CLK_ROW_IN of the display pixel Pix2; i is connected, preferably connected, to the pad P_CLK_ROW_OUT of the display pixel Pix2; ii. The pad P_STD_IN of the display pixel Pix2u is connected, preferably connected, to the P_STD_OUT pad of the display pixel Pix2;4 b The P_COL_ROW_IN, P_DATA_IN, P_COL_ROW_OUT and P_DATA_OUT pads of the display pixel Pix2;i are left floating or tied to a fixed level such as the low reference potential Gnd. Furthermore, the P_Col pad of Pix2u is connected to the P_Col pad of Pix2i i by the column electrode E-Colj.

[0100] For the display pixels Pix2ij of the first row, j varying from 2 to N, pads P_CLK_COL_IN and P_DATA_IN of the display pixel Pix2ij are connected to the display pixel Pix2ij.i. The pad P_CLK_COL_IN of the display pixel Pix2ij is connected, preferably connected, to the pad P_CLK_COL_OUT of the display pixel Pix2ij b. The pad P_DATA_IN of the display pixel Pix2Lj is connected, preferably connected, to the pad P_DATA_OUT of the display pixel Pix2lj_1. The pads P_CLK_ROW_IN, P_STD_IN, P_CLK_R0W_0UT and P_STD_OUT of the display pixel Pix2ij are left floating or tied to a fixed level such as the low reference potential Gnd. Furthermore, the P_Row pad of Pix2i j is connected to the P_Row pad of Pix2i i by the row electrode E_Rowi.

[0101] For all display pixels Pixlij, i varying from 2 to M and j varying from 2 to N, the pad P_Col of the display pixel Pixlij is connected, preferably connected, to the pad P_Col of the display pixel Pix2ij by the column electrode E_Colj, and the pad P_Row of the display pixel Pixlij is connected, preferably connected, to the pad P_Row of the display pixel Pix2i by the row electrode E_Row;.

[0102] An embodiment of the operation of the display screen 30 will now be described. As an example, the display pixels on the row of rank i are selected when the signal Com; on the electrode E_Row; comprises a row selection pattern. A row selection pattern may correspond to a signal Com; which is set to logic level "1" for a given duration or to a signal Com; which comprises serial pulses. By default, each display pixel Pix2u of the first column provides the signal Com; without the row selection pattern, for example by setting the signal Com; to logic value "0" or without serial pulses. In order to select the display pixels of the row of rank i, the synchronization controller 18 provides the signal STD having the row selection pattern to the display pixel Pix2i i.When the display pixel Pix2i i receives the STD signal having the row selection pattern, it sets the Comi signal on the P_Row pad having the row selection pattern to select the display pixels on the first row. Then, the STD signal having the row selection pattern is sent to the display pixel Pix22>i. The time difference between the display pixel Pix2i.i and the display pixel Pix22>i is one row time, i.e., equal to the ratio of the frame time to the number of rows. The STD signal having the row selection pattern is then transmitted from the display pixel Pix2;i to the display pixel Pix2i+i i. When the . display pixel Pix2ii receives the STD signal having the row selection pattern, it sets the Com signal; on the P_Row pad having the row selection pattern to select the display pixels on the row of rank i. The selected display pixel at the row of rank i and the column of rank j can therefore store display data Dataj provided by the display pixel Pix2ij. The CLK_ROW signal is also transmitted from the display pixel Pix2u to the display pixel Pix2i+ii and can be sent to the P_Row pad by each display pixel Pix2u of an unselected row to be used as a synchronization signal for driving the LEDs by the display pixels.

[0103] For displaying image pixels on the row of rank i, the display data is serially supplied by the synchronization controller 18 to the display pixel Pix2i i, clocked by the signal CLK_COL, starting from the display data relating to the display pixel DataN at the last column to the display data Datai relating to the display pixel at the first column. The display data DATA is serially transmitted from the display pixel Pix2i j to the display pixel Pix2ij+i, clocked by the signal CLK_COL which is also transmitted from the display pixel Pix2ij to the display pixel Pix2ij+i, until the display data DataN relating to the display pixel at the last column reaches the display pixel Pix2ijN. At this stage, each display pixel Pix2ij, j varying from 1 to N, has received and stored display data Dataj concerning the column of rank j.Each display pixel Pix2ij provides display data Dataj to the plot P_Col. .

[0104] [Fig. 13] partially and schematically represents another embodiment of a display screen 60. The display screen 60 comprises a matrix 62 of display pixels, for example arranged in M ​​rows and N columns, i being an integer varying from 1 to M, and j being an integer varying from 1 to N. In the present embodiment, the display screen 60 comprises display pixels Pixl of the first type (Pixel) and display pixels Pix3 of a third type (Pixel & Driver). The display pixels Pix3 of the third type may have the general structure shown in [Fig.9] with a reduced number of conductive pads. The display pixel Pixli i of the first column and of the first row is a display pixel of the first type. The remainder of the first column of the matrix 62 comprises display pixels Pix3; i of the third type, i varying from 2 to M.The remainder of the first row of the matrix 62 comprises display pixels Pix3ij of the third type, j varying from 2 to N. The other display pixels of the matrix 62 are of the first type. Therefore, the matrix 62 comprises a sub-matrix of display pixels of the first type Pixlij, i being an integer varying from 2 to M, and j being an integer varying from 2 to N. The synchronization controller 18 is configured to send six signals CLK_COL, DATA, CLK_R0W, . STD, Datai and Comi to the 62 display pixel matrix. According to one embodiment, each CLK_COL, DATA, CLK_ROW, STD, Datai and Comi signal is a binary signal.

[0105] In the present embodiment, each display pixel Pix3 of the third type, in addition to fulfilling the function of displaying an image pixel, comprises a control circuit which can operate as a row control circuit providing the selection and synchronization signal Com; or as a column control circuit providing the data signal Dataj according to the programming of the display pixel.

[0106] [Fig. 14] shows a block diagram of an embodiment of the control circuit 34 of the display pixel Pix3. The control circuit 34 of the display pixel Pix3 comprises the electronic circuit 45 of the control circuit 34 of the display pixel Pixl, which is shown in dotted lines in [Fig. 14]. The control circuit 34 of the display pixel Pix3 comprises, in addition to the conductive solder pads P_Vcc, P_Gnd, P_Row and P_Col, additional conductive solder pads P_CLK_IN, P_DATA_STD_IN, P_CLK_OUT, P_DATA_STD_OUT, and P_Vdd in order to electrically connect the display pixel Pix3 with the outside. The control circuit 34 receives the supply voltage Vdd from the conductive pad P_Vdd.

[0107] The control circuit 34 of the display pixel Pix3 further comprises a row / column control circuit 64 connected to the pads P_CLK_IN, P_DATA_STD_IN, P_CLK_OUT and P_DATA_STD_OUT. The row / column control circuit 64 receives signals from the pads P_CLK_IN and P_DATA_STD_IN and provides signals at the pads P_CLK_OUT and P_DATA_STD_OUT. The control circuit 34 of the display pixel Pix3 further comprises a demultiplexer 66 controlled by a signal provided by a CTL node. The demultiplexer 66 receives a signal from the row / column control circuit 64 and provides this signal either to the pad P_Row or to the pad P_Col depending on the voltage value of the CTL node. The CTL node is connected to either the I_Vdd node or the I_Gnd node. The I_Vdd node is connected to the P_Vdd pad and the I_Gnd node is connected to the P_Gnd pad.The connection of the CTL node to either the I_Vdd node or the I_Gnd node is performed during a programming phase, during an assembly phase, or during wafer-level production. In one embodiment, the CTL node is initially connected to the I_Vdd node by a first fusible track and to the I_Gnd node by a second fusible track, and the first fusible track or the second fusible track is interrupted during the programming phase, for example by a laser, so that the CTL node remains connected only to either the I_Vdd node or the I_Gnd node. In another embodiment, the control circuit 34 of the display pixel Pix3. further comprises a register which can be programmed during the programming phase and which controls the voltage level of the CTL node. In another embodiment, during the assembly phase of the display circuit 36 ​​and the control circuit 34, the CTL node is connected either to a metal pad of the display circuit 36 ​​receiving the supply voltage Vdd, or to a metal pad of the display circuit 36 ​​receiving the low reference voltage Gnd.

[0108] [Fig. 15] is a bottom view of the control circuit 34 of the display pixel Pix3. On the bottom surface 38, the display pixel Pix3 includes nine conductive solder pads P_Vcc, P_Gnd, P_Row, P_Col, P_CLK_IN, P_DATA_STD_IN, P_CLK_OUT, P_DATA_STD_OUT and P_Vdd in order to electrically connect the display pixel Pix3 with the outside.

[0109] [Fig. 16] is a schematic view of the display screen 60 of [Fig. 13] showing the connection of the electrodes and the display pixels.

[0110] The display pixels PixSij of the first column, i varying from 2 to M, are programmed so that the demultiplexer 66 provides the signal sent by the circuit 64 to the pad P_Row. The display pixels Pix3ij of the first row, j varying from 2 to N, are programmed so that the demultiplexer 66 provides the signal sent by the circuit 64 to the pad P_Col.

[0111] The row electrode E_Rowi receives the signal Comi from the synchronization controller 18. The column electrode E_Coli receives the signal Datai from the synchronization controller 18. For the display pixel Pix32>i of the second row and the first column, the pads P_CLK_IN, P_DATA_STD_IN are connected to the synchronization controller 18. The pad P_CLK_IN of the display pixel Pix32>i receives the signal CLK_R0W from the synchronization controller 18. The pad P_DATA_STD_IN of the display pixel Pix32ji receives the signal STD from the synchronization controller 18. For the display pixel Pix3i>2 of the first row and the second column, the pads P_CLK_IN, P_DATA_STD_IN are connected to the synchronization controller 18. The pad P_CLK_IN of the display pixel Pix3i>2 receives the CLK_COL signal from the synchronization controller 18.The P_DATA_STD_IN pin of the Pix3i>2 display pixel receives the DATA signal from the synchronization controller 18. .

[0112] For the display pixels Pix3; i of the first column, i varying from 3 to M, pads P_CLK_IN and P_DATA_STD_IN of the display pixel Pix3; i are connected to the display pixel Pix3i-i,i. The pad P_CLK_IN of the display pixel Pix3,. । is connected, preferably connected, to the pad P_CLK_OUT of the display pixel Pix3i-i,i. The pad P_DATA_STD_IN of the display pixel Pix3,. । is connected, preferably connected, to the pad P_DATA_STD_OUT of the display pixel Pix3i-i,i. For the display pixels Pix3ij of the first row, j varying from 3 to N, the pads P_CLK_IN and P_DATA_STD_IN of the display pixel Pix3ij are connected to display pixel Pix3ij i. The P_CLK_IN pad of display pixel Pix3ij is connected, preferably connected, to the P_CLK_OUT pad of display pixel Pix3ij i. The P_DATA_STD_IN pad of display pixel Pix3|d is connected, preferably connected, to the P_DATA_STD_OUT pad of display pixel Pix3, , i. For all display pixels Pixljj, i varying from 2 to M and j varying from 2 to N, the P_Col pad of display pixel Pix ILJ is connected, preferably connected, to the P_Col pad of display pixel Pix3ij by the column electrode E_Colj, and the P_Row pad of display pixel Pix ILJ is connected, preferably connected, to the P_Row pad of display pixel Pix2u by the row electrode E_Row;. For the display pixel Pixli i of the first row and the first column, the pad P_Row is connected, preferably connected, to the row electrode E_Rowi, and the pad P_Col is connected, preferably connected, to the column electrode E_Coli.

[0113] An embodiment of the operation of the display screen 60 will now be described. By default, each display pixel PixSij of the first column provides the signal Com; without the row selection pattern. In order to select the display pixels of the first row, the timing controller 18 provides the signal Comi having the row selection pattern to the row electrode E_Rowi. In order to select the display pixels of the row of row i, i varying from 2 to M, the timing controller 18 provides the signal STD having the row selection pattern to the display pixel Pix32,i. When the display pixel Pix32,i receives the signal STD having the row selection pattern, it establishes the signal Com2 on the pad P_Row having the row selection pattern in order to select the display pixels on the second row. Then, the signal STD having the row selection pattern is sent to the display pixel Pix33ji.The STD signal having the row selection pattern is then transmitted from the display pixel Pix3; i to the display pixel Pix3i+i i. When the display pixel Pix3; i receives the STD signal having the row selection pattern, it sets the Com; signal on the P_Row pad having the row selection pattern to select the display pixels on the row of row i. The selected display pixel at the row of row i and the column of row j can therefore store display data Dataj provided by the display pixel Pix2Lj or Pixli i for the first column. The CLK_R0W signal is also transmitted from the display pixel Pix3; i to the display pixel Pix3i+ii and can be sent to the P_Row pad by each display pixel Pix3; i of an unselected row to be used as a synchronization signal for driving the LEDs by the display pixels.For the first line, the Comi signal can be used as a synchronization signal.

[0114] For displaying image pixels on row i, display data Data i is sent to column electrode E_Coli and display data DATA is supplied serially by the synchronization controller 18 to the display pixel Pix3i>2, clocked by the signal CLK_COL, starting from the display data relating to the display pixel DataN at the last column to the display data Data2 relating to the display pixel at the second column. The display data DATA is transmitted serially from the display pixel Pix3ij to the display pixel Pix3ij+i, clocked by the signal CLK_COL which is also transmitted from the display pixel Pix3ij to the display pixel Pix3ij+i, until the display data DataN relating to the display pixel at the last column reaches the display pixel Pix3ijN. At this point, each display pixel Pix3ij, j varying from 2 to N, has received and stored display data Dataj relating to the column of rank j. Each display pixel Pix3ij, j varying from 2 to N, provides display data Dataj to plot P_Col.

[0115] [Fig. 17] partially and schematically represents another embodiment of a display screen 70. The display screen 70 comprises a matrix 72 of display pixels, for example, arranged in M ​​rows and N columns, i being an integer varying from 1 to M, and j being an integer varying from 1 to N. In the present embodiment, the display screen 70 comprises the display pixels Pixl of the first type (Pixel), display pixels Pix4 of a fourth type (Pixel and Column), and display pixels Pix5 of a fifth type (Pixel and Row). The display pixels Pix4 of the fourth type and the display pixels of the fifth type may have the general structure shown in [Fig.9]. The display pixel Pixlii of the first column and the first row is a display pixel of the first type. The remainder of the first row of matrix 72 comprises display pixels Pix4ij of the fourth type, j varying from 2 to N.The remainder of the first column of the matrix 72 comprises display pixels Pix5;i of the fifth type, i varying from 2 to M. The other display pixels of the matrix 72 are of the first type. Therefore, the matrix 72 comprises a sub-matrix of the display pixel PixCj, i being an integer varying from 2 to M, and j being an integer varying from 2 to N. The synchronization controller 18 is configured to send six signals CLK_COL, DATA, CLK_ROW, STD, Datai and Comi to the matrix 72 of display pixels. According to one embodiment, each signal CLK_COL, DATA, CLK_ROW, STD, Datai and Comi is a binary signal.

[0116] In the present embodiment, each display pixel Pix4 of the fourth type, in addition to performing the function of displaying an image pixel, comprises a control circuit which can operate as a column control circuit providing the data signal Dataj. Furthermore, each display pixel Pix5 of the fifth type, in addition to performing the function of displaying an image pixel, comprises a control circuit which can operate as a row control circuit providing the selection and synchronization signal Com;.

[0117] [Fig. 18] shows a block diagram of one embodiment of the drive circuit 34 of the display pixel Pix4. The drive circuit 34 of the display pixel Pix4 includes all the elements of the drive circuit 34 of the display pixel Pix2 shown in [Fig.2], except that the row drive circuit 50 is not present. Therefore, the drive circuit 34 of the display pixel Pix4 includes a column drive circuit 52 receiving the signal CLK_COL, received at the pad P_CLK_COL_IN, receiving the signal DATA, received at the pad P_DATA_IN, providing the signal CLK_COL at the pad P_CLK_COL_OUT and providing the signal DATA at the pad P_DATA_OUT.

[0118] [Fig. 19] is a bottom view of the drive circuit 34 of the display pixel Pix4. On the bottom surface 38, the display pixel Pix4 includes nine conductive solder pads P_Vcc, P_Gnd, P_Row, P_Col, P_CLK_COL_IN, P_DATA_IN, P_CLK_COL_OUT, P_DATA_OUT and P_Vdd in order to electrically connect the display pixel Pix4 with the outside.

[0119] [Fig.20] shows a block diagram of an embodiment of the drive circuit 34 of the display pixel Pix5. The drive circuit 34 of the display pixel Pix5 includes all the elements of the drive circuit 34 of the display pixel Pix2 shown in [Fig.2], except that the column drive circuit 52 is not present. Therefore, the drive circuit 34 of the display pixel Pix5 includes a row drive circuit 50 receiving the signal CLK_ROW, received at the pad P_CLK_ROW_IN, receiving the signal STD, received at the pad P_STD_IN, providing the signal CLK_ROW at the pad P_CLK_ROW_OUT and providing the signal STD at the pad P_STD_OUT.

[0120] [Fig.21] is a bottom view of the control circuit 34 of the display pixel Pix5. On the bottom surface 38, the display pixel Pix5 includes nine conductive solder pads P_Vcc, P_Gnd, P_Row, P_Col, P_CLK_ROW_IN, P_STD_IN, P_CLK_ROW_OUT, P_STD_OUT and P_Vdd in order to electrically connect the display pixel Pix5 with the outside.

[0121] [Fig. 22] is a schematic view of the display screen 70 of [Fig. 17] showing the connection of the electrodes and the display pixels.

[0122] The row electrode E_Rowi receives the signal Comi from the synchronization controller 18. The column electrode E_Coli receives the signal Datai from the synchronization controller 18. For the display pixel Pix41>2 of the first row and the second column, the pads P_CLK_COL_IN, P_DATA_IN are connected to the synchronization controller 18. The pad P_CLK_COL_IN of the display pixel Pix4[j2 receives the signal CLK_COL from the synchronization controller 18. The pad P_DATA_IN of the display pixel Pix2i>2 receives the signal DATA from the synchronization controller 18. For the display pixel Pix52j[ of the second row and of the first column, the pads P_CLK_ROW_IN, P_STD_IN are connected to the synchronization controller 18. The pad P_CLK_ROW_IN of the display pixel Pix5 2,1 receives the CLK_ROW signal from the synchronization controller 18. The pad P_STD_IN of the display pixel Pix52,i receives the STD signal from the synchronization controller 18. For the display pixels Pix4ij of the first row, j varying from 3 to N, the pads P_CLK_COL__IN and P_DATA_IN of the display pixel Pix4Lj are connected to the display pixel Pix41>j_1. The pad P_CLK_COL_IN of the display pixel Pix4i,j is connected, preferably connected, to the pad P_CLK_COL_OUT of the display pixel Pix4 i j_i. The P_DATA_IN pin of the display pixel Pix4i,j is connected, preferably connected, to the P_DATA_OUT pin of the display pixel Pix4ij_i. For the display pixels Pix5i,i of the first column, i varying from 3 to M, the P_CLK_ROW_IN and P_STD_IN pins of the display pixel Pix5i,i are connected to the display pixel Pix5i i,i.The P_CLK_ROW_IN pad of the display pixel Pix5i,i is connected, preferably connected, to the P_CLK_ROW_OUT pad of the display pixel Pix5i i,i. The P_STD_IN pad of the display pixel Pix5;,i is connected, preferably connected, to the P_STD_OUT pad of the display pixel Pix5i-i,i. For all display pixels Pixhj, i varying from 2 to M and j varying from 2 to N, the P_Col pad of the display pixel Pi x L; is connected, preferably connected, to the P_Col pad of the display pixel Pix4ij by the column electrode E_Colj, and the P_Row pad of the display pixel Pi x L; is connected, preferably connected to the P_Row pad of the display pixel Pix5;,i by the row electrode E_Row;. For the display pixel Pixli i of the first row and the first column, the pad P_Row is connected, preferably connected, to the row electrode E_Rowi, and the pad P_Col is connected, preferably connected, to the column electrode E_Coli.

[0123] An embodiment of the operation of the display screen 70 will now be described. By default, each display pixel Pix5i,i of the first column provides the signal Com; without the row selection pattern. In order to select the display pixels of the first row, the timing controller 18 provides the signal Comi having the row selection pattern to the row electrode E_Rowi. In order to select the display pixels of the row of row i, i varying from 2 to M, the timing controller 18 provides the signal STD having the row selection pattern to the display pixel Pix52,i. When the display pixel Pix52,i receives the signal STD having the row selection pattern, it establishes the signal Com2 on the pad P_Row having the row selection pattern in order to select the display pixels on the second row. Then, the signal STD having the row selection pattern is sent to the display pixel Pix53,i.The STD signal having the row selection pattern is then transmitted from the display pixel Pix5;,i to the display pixel Pix5i+i,i. When the display pixel Pix5;,i receives the STD signal having the row selection pattern, it sets the Com; signal on the P_Row pad having the row selection pattern to select . the display pixels on row of rank i. The selected display pixel at row of rank i and column of rank j can therefore store display data Dataj provided by display pixel Pi x4,, or Pixli i for the first column. The signal CLK_ROW is also transmitted from display pixel Pix5; i to display pixel Pix5i+ii and can be sent to pad P_Row by each display pixel Pix5; i of an unselected row to be used as a synchronization signal for controlling the LEDs by the display pixels. For the first row, the signal Comi can be used as a synchronization signal.

[0124] For displaying the image pixels on the row of rank i, the display data Data i is sent to the column electrode E_Coli and the display data DATA is serially supplied by the timing controller 18 to the display pixel Pix4i>2, clocked by the signal CLK_COL, starting from the display data relating to the display pixel DataN at the last column to the display data Data2 relating to the display pixel at the second column. The display data DATA is serially transmitted from the display pixel Pix4ij to the display pixel Pix4ij+i, clocked by the signal CLK_COL which is also transmitted from the display pixel Pix4i j to the display pixel Pix4ij+i, until the display data DataN relating to the display pixel at the last column reaches the display pixel Pix4ijN.At this point, each display pixel Pix4ij, j varying from 2 to N, has received and stored display data Dataj concerning the column of rank j. Each display pixel Pix4i j, j varying from 2 to N, provides display data Dataj to the plot P_Col. .

[0125] [Fig.23] partially and schematically represents another embodiment of a display screen 80. The display screen 80 comprises a matrix 82 of display pixels, for example, arranged in M ​​rows and N columns, i being an integer varying from 1 to M, and j being an integer varying from 1 to N. In the present embodiment, the display screen 80 comprises the display pixels Pixl of the first type (Pixel and Column), the display pixels Pix4 of the fourth type (Pixel), and the display pixels Pix5 of the fifth type (Pixel and Row). The first row of the matrix 82 comprises the display pixels Pix4ij of the fourth type, j varying from 1 to N. The remainder of the first column of the matrix 82 comprises the display pixels Pix5; i of the fifth type, i varying from 2 to M. The other display pixels of the matrix 82 are of the first type.Therefore, the matrix 82 comprises a sub-matrix of display pixels Pixlij, i being an integer varying from 2 to M, and j being an integer varying from 2 to N. The synchronization controller 18 is configured to send five signals CLK_COL, DATA, CLK_ROW, STD and Comi to the matrix 82 of display pixels. According to one embodiment, each signal CLK_COL, DATA, CLK_ROW, STD and . Comi is a binary signal.

[0126] [Fig.24] is a schematic view of the display screen 80 of [Fig.23] showing the connection of the electrodes and the display pixels.

[0127] For the display pixel Pix4i i of the first row and the first column, the P_CLK_COL_IN and P_DATA_IN pads are connected to the synchronization controller 18, not shown in [Fig.24]. The P_CLK_COL_IN pad of the Pix4 display pixel 11 receives the CLK_COL signal from the synchronization controller 18. The P_DATA_IN pad of the Pix4i display pixel i receives the DATA signal from the synchronization controller 18. For the Pix4ij display pixels of the first row, j varying from 2 to N, the P_CLK_COL_IN and P_DATA_IN pads of the Pix4ij display pixel are connected to the Pix4ij_i display pixel. The P_CLK_COL_IN pin of the Pix4ij display pixel is connected, preferably wired, to the P_CLK_COL_OUT pin of the Pix4ij_i display pixel. The P_DATA_IN pin of the Pix4ij display pixel is connected, preferably wired, to the P_DATA_OUT pin of the Pix4ij i display pixel.

[0128] For the display pixel Pix52,i of the second row and the first column, the pads P_CLK_ROW_IN and P_STD_IN are connected to the synchronization controller 18. The pad P_CLK_ROW_IN of the display pixel Pix52,i receives the signal CLK_R0W from the synchronization controller 18. The pad P_STD_IN of the display pixel Pix52ji receives the signal STD from the synchronization controller 18. For the display pixels Pixôij of the first column, i varying from 3 to M, the pads P_CLK_ROW_IN and P_STD_IN of the display pixel Pix5;i are connected to the display pixels Pix5i i i. The pad P_CLK_ROW_IN of the display pixel Pix5;i receives the signal CLK_R0W from the synchronization controller 18. i is connected, preferably connected, to the P_CLK_R0W_0UT pad of the display pixel PixSuj. The P_STD_IN pad of the display pixel Pix5; i is connected, preferably connected, to the P_STD_OUT pad of the display pixel Pix5i i i.

[0129] For all display pixels Pixljj, i varying from 2 to M and j varying from 2 to N, the pad P_Col of the display pixel Pix ILJ is connected, preferably connected, to the pad P_Col of the display pixel Pix4ij by the column electrode E_Colj, and the pad P_Row of the display pixel Pix ILJ is connected, preferably connected, to the pad P_Row of the display pixel Pix5i i by the row electrode E_Row;.

[0130] An embodiment of the operation of the display screen 80 will now be described. By default, each display pixel Pix5; i of the first column provides the signal Com; without the row selection pattern. In order to select the display pixels of the first row, the timing controller 18 provides the signal Comi having the row selection pattern to the row electrode E_Rowi. In order to select the display pixels of the row of row i, i varying from 2 to M, the timing controller 18 provides the signal STD having the row selection pattern to the display pixel Pix52>i. When the display pixel Pix52j[ receives the signal STD having the row selection pattern, it sets the Com2 signal on the P_Row pad having the row selection pattern to select the display pixels on the second row. Then, the STD signal having the row selection pattern is sent to the display pixel Pix53ji. The STD signal having the row selection pattern is then transmitted from the display pixel Pix5; i to the display pixel Pix5i+i i. When the display pixel Pix5; i receives the STD signal having the row selection pattern, it sets the Com; signal on the P_Row pad having the row selection pattern to select the display pixels on the row of rank i. The display pixel selected at the row of rank i and the column of rank j can therefore store display data Dataj provided by the display pixel Pix4ij.The CLK_ROW signal is also transmitted from display pixel Pix5;i to display pixel Pix5i+ii and can be sent to the P_Row pad by each display pixel Pix5;i of an unselected row to be used as a synchronization signal for driving the LEDs by the display pixels. For the first row, the Comi signal can be used as a synchronization signal.

[0131] For displaying the image pixels on the row of rank i, the display data DATA are supplied serially by the synchronization controller 18 to the display pixel Pix4i i, clocked by the signal CLK_COL, starting from the display data relating to the display pixel DataN at the last column to the display data Datai relating to the display pixel at the first column. The display data DATA are transmitted serially from the display pixel Pix4ljj to the display pixel Pix4ljj+1, clocked by the signal CLK_COL which is also transmitted from the display pixel Pix4ljj to the display pixel Pix4ljj+1, until the display data DataN relating to the display pixel at the last column reaches the display pixel Pix41>N. At this stage, each display pixel Pix4ljj, j varying from 1 to N, has received and stored display data Dataj concerning the column of rank j.Each display pixel Pix4ij, j varying from 1 to N, provides display data Dataj to plot P_Col. .

[0132] [Fig.25] partially and schematically represents another embodiment of a display screen 90. The display screen 90 comprises a matrix 92 of display pixels, for example, arranged in M ​​rows and N columns, i being an integer varying from 1 to M, and j being an integer varying from 1 to N. In the present embodiment, the display screen 90 comprises the display pixels Pixl of the first type (Pixel), the display pixels Pix4 of the fourth type (Pixel and Column), and the display pixels Pix5 of the fifth type (Pixel and Row). The first column of the matrix 92 comprises the display pixels Pixôij of the fifth type, i varying from 1 to M. The remainder of the first row of the matrix 92 comprises the display pixels Pix4ij of the fourth type, j varying from 2 to N. The other display pixels of the matrix 92 are of the first type. Therefore, the matrix 92 comprises a sub-matrix of display pixels Pi x 1 ir i being an integer varying from 2 to M, and j being an integer varying from 2 to N. The synchronization controller 18 is configured to send five signals CLK_COL, DATA, CLK_ROW, STD and Datai to the matrix 92 of display pixels. According to one embodiment, each signal CLK_COL, DATA, CLK_ROW, STD and Datai is a binary signal.

[0133] [Fig.26] is a schematic view of the display screen 90 of [Fig.25] showing the connection of the electrodes and the display pixels.

[0134] For the display pixel Pix5i i of the first row and the first column, the pads P_CLK_ROW_IN and P_STD_IN are connected to the synchronization controller 18, not shown in [Fig.26]. The pad P_CLK_ROW_IN of the display pixel Pix5i i receives the signal CLK_R0W from the synchronization controller 18. The pad P_STD_IN of the display pixel Pix5ii receives the signal STD from the synchronization controller 18. For the display pixels Pi x5 K| of the first column, i varying from 2 to M, the pads P_CLK_ROW_IN and P_STD_IN of the display pixel Pix5,. । are connected to the display pixels Pix5i-i,i. The pad P_CLK_ROW_IN of the pixel Pi x5 K| is connected, preferably connected, to the P_CLK_ROW_OUT pad of the display pixel Pix5i-i,i . The P_STD_IN pad of the display pixel Pi x5,. । is connected, preferably connected, to the P_STD_OUT pad of the display pixel PixÔMj.

[0135] For the display pixel Pix4[j2 of the first row and the second column, the P_CLK_COL_IN and P_DATA_IN pads are connected to the synchronization controller 18. The P_CLK_COL_IN pad of the display pixel Pix4i 2 receives the CLK_COL signal from the synchronization controller 18. The P_DATA_IN pad of the display pixel Pix4i>2 receives the DATA signal from the synchronization controller 18. For the display pixels Pix4ij of the first row, j varying from 3 to N, the P_CLK_COL_IN and P_DATA_IN pads of the display pixel Pix4ij are connected to the display pixel Pix4ij_i. The P_CLK_COL_IN pad of the display pixel Pix4ij is connected, preferably connected, to the P_CLK_COL_OUT pad of the display pixel Pix4ij i. The P_DATA_IN pin of the Pix4 display pixel, , is connected, preferably to the P_DATA_OUT pin of the Pix4i display pixel j i.

[0136] For all display pixels Pixljj, i varying from 2 to M and j varying from 2 to N, the pad P_Col of the display pixel Pix ILJ is connected, preferably connected, to the pad P_Col of the display pixel Pix4ij by the column electrode EColj, and the pad P_Row of the display pixel Pixhj is connected, preferably connected to the pad P_Row of the display pixel Pix5,.i by the row electrode E_Row;.

[0137] An embodiment of the operation of the display screen 90 will now be described. By default, each display pixel Pixôij of the first column provides the signal Com; without the row selection pattern. In order to select the pixels display pixel of row i, i varying from 1 to M, the synchronization controller 18 provides the STD signal having the row selection pattern to the display pixel Pix5ii. When the display pixel Pix5ii receives the STD signal having the row selection pattern, it establishes the Comi signal on the P_Row pad having the row selection pattern in order to select the display pixels on the first row. Then, the STD signal having the row selection pattern is sent to the display pixel Pix52>i. The STD signal having the row selection pattern is then transmitted from the display pixel Pix5 ii to the display pixel Pix5i+i i. When the display pixel Pix5; i receives the STD signal having the row selection pattern, it establishes the Com; signal on the P_Row pad having the row selection pattern in order to select the display pixels on the row of row i.The selected display pixel at row i and column j can therefore store display data Dataj provided on column electrode E_Colj. The signal CLK_R0W is also transmitted from display pixel Pixôij to display pixel Pix5i+i,i and can be sent to pad P_Row by each display pixel Pixôij of an unselected row to be used as a synchronization signal for driving the LEDs by the display pixels. For the first row, the signal Comi can be used as a synchronization signal.

[0138] For displaying the image pixels on the row of rank i, the display data Data i is sent to the column electrode E_Coli and the display data DATA is serially supplied by the timing controller 18 to the display pixel Pix4i>2, clocked by the signal CLK_COL, starting from the display data relating to the display pixel DataN at the last column to the display data Data2 relating to the display pixel at the second column. The display data DATA is serially transmitted from the display pixel Pix4ij to the display pixel Pix4ij+b clocked by the signal CLK_COL which is also transmitted from the display pixel Pix4ij to the display pixel Pix4ij+i, until the display data DataN relating to the display pixel at the last column reaches the display pixel Pix4i>N.At this point, each display pixel Pix4ij, j varying from 2 to N, has received and stored display data Dataj concerning the column of rank j. Each display pixel Pix4ij, j varying from 2 to N, provides display data Dataj to the plot P_Col. .

[0139] [Fig.27] partially and schematically represents another embodiment of a display screen 100. The display screen 100 comprises a matrix 102 of display pixels, for example, arranged in M ​​rows and N columns, i being an integer varying from 1 to M, and j being an integer varying from 1 to N. In the present embodiment, the display screen 100 comprises the display pixels Pixl of the first type (Pixel), the display pixels Pix4 of the fourth type (Pixel and Column), and the display pixels Pix5 of the fifth type (Pixel and Row). The display pixel Pix4i i at the first row and the first column is of the fourth type. The remainder of the first column of the matrix 102 comprises the display pixels Pix5; i of the fifth type, i varying from 2 to M. The display pixel Pix5i>2 at the first row and the second column is of the fifth type. The remainder of the first row of the matrix 102 comprises the display pixels Pix4ij of the fourth type, j varying from 3 to N. The display pixel Pix42>2 at the second row and the second column is of the fourth type. The other display pixels of the matrix 102 are of the first type. The timing controller 18 is configured to send four signals CLK_COL, DATA, CLK_ROW and STD to the matrix 102 of display pixels. According to one embodiment, each CLK_COL, DATA, CLK_ROW and STD signal is a binary signal.

[0140] [Fig.28] is a schematic view of the display screen 100 of [Fig.27] re showing the connection of the electrodes and the display pixels.

[0141] For the display pixel Pix4i i of the first row and the first column, the P_CLK_COL_IN and P_DATA_IN pads are connected to the synchronization controller 18, not shown in [Fig.28]. The P_CLK_COL_IN pad of the display pixel Pix4 ii receives the CLK_COL signal from the synchronization controller 18. The P_DATA_IN pad of the display pixel Pix4i i receives the DATA signal from the synchronization controller 18. For the display pixel Pix42>2 of the second row and the second column, the P_CLK_COL_IN and P_DATA_IN pads are connected to the display pixel Pix4i i. The P_CLK_COL_IN pin of the display pixel Pix42>2 is connected, preferably connected, to the P_CLK_COL_OUT pin of the display pixel Pix4i b. The P_DATA_IN pin of the display pixel Pix42>2 is connected, preferably connected, to the P_DATA_OUT pin of the display pixel Pix4i i.For the display pixel Pix4i>3 of the first row and the third column, the P_CLK_COL_IN and P_DATA_IN pads are connected to the display pixel Pix42 2. The P_CLK_COL_IN pad of the display pixel Pix4i 3 is connected, preferably connected, to the P_CLK_COL_OUT pad of the display pixel Pix42>2. The P_DATA_IN pad of the display pixel Pix4i>3 is connected, preferably connected, to the P_DATA_OUT pad of the display pixel Pix42 2. For the display pixels Pix4ij of the first row, j varying from 4 to N, the P_CLK_COL_IN and P_DATA_IN pads of the display pixel Pix4ij are connected to the display pixel Pix4ij_i. The P_CLK_COL_IN pad of the display pixel Pix4ij is connected, preferably connected, to the P_CLK_COL_OUT pad of the display pixel Pix4i j i. The P_DATA_IN pad of the display pixel Pix4id is connected, preferably connected, to the P_DATA_OUT pad of the display pixel Pix4ij i.

[0142] For the display pixel Pix5i>2 of the first row and the second column, the pads P_CLK_ROW_IN and P_STD_IN are connected to the synchronization controller 18. The P_CLK_ROW_IN pad of the display pixel Pix5i>2 receives the CLK_ROW signal from the synchronization controller 18. The P_STD_IN pad of the display pixel Pix5i>2 receives the STD signal from the synchronization controller 18. For the display pixel Pix52ji of the second row and the first column, the P_CLK_ROW_IN and P_STD_IN pads are connected to the display pixel Pix5i>2. The P_CLK_ROW_IN pad of the display pixel Pix52ji is connected, preferably connected, to the P_CLK_ROW_OUT pad of the display pixel Pix5i>2. The P_STD_IN pad of the display pixel Pix52ji is connected, preferably connected, to the P_STD_OUT pad of the display pixel Pix5i>2. For the display pixels Pix5; i of the first column, i varying from 3 to M, the P_CLK_ROW_IN and P_STD_IN pads of the display pixel Pix5; i are connected to the display pixel PixSuj. The P_CLK_ROW_IN pad of the display pixel Pix5 ü is connected, preferably connected, to the P_CLK_ROW_OUT pad of the display pixel Pixôi i i.The P_STD_IN pin of the display pixel Pix5;i is connected, preferably connected, to the P_STD_OUT pin of the display pixel Pix5i-i,i.

[0143] For all display pixels Pixhj, i varying from 2 to M and j varying from 3 to N, the pad P_Col of the display pixel Pix ILJ is connected, preferably connected, to the pad P_Col of the display pixel Pix4ij by the column electrode E_Colj. For all display pixels of the second column Pixli>2, i varying from 3 to M, the pad P_Col of the display pixel Pixli>2 is connected, preferably connected, to the pad P_Col of the display pixel Pix52>2 by the column electrode E_Col2. For all display pixels Pixlij, i varying from 2 to M and j varying from 2 to N, i and j not being simultaneously equal to 2, the pad P_Row of the display pixel Pixlij is connected, preferably connected, to the pad P_Row of the display pixel Pix5; i by the row electrode E_Row;.

[0144] An embodiment of the operation of the display screen 100 will now be described. By default, the display pixel Pix5i>2 and each display pixel Pix5; i of the first column provides the signal Com; without the row selection pattern. In order to select the display pixels of the row of rank i, i varying from 1 to M, the synchronization controller 18 provides the signal STD having the row selection pattern to the display pixel Pix5i>2. When the display pixel Pix5i>2 receives the signal STD having the row selection pattern, it establishes the signal Comi on the pad P_Row having the row selection pattern in order to select the display pixels on the first row. Then, the signal STD having the row selection pattern is sent to the display pixel Pix52ji. The STD signal having the line selection pattern is then transmitted from the display pixel PixSij to the display pixel Pix5i+i,i.When the display pixel PixSij receives the STD signal having the row selection pattern, it sets the Com signal; on the P_Row pad having the row selection pattern to select the display pixels on the row of rank i. The display pixel selected at the row of rank i and the column of rank j can therefore store data. display data provided on column electrode E_Colj. The CLK_ROW signal is also transmitted from display pixel Pix5;i to display pixel Pix5i+ii and can be sent to pad P_Row by each display pixel Pix5;i of an unselected row to be used as a synchronization signal for driving the LEDs by the display pixels. For the first row, the Comi signal can be used as a synchronization signal.

[0145] For the display of the image pixels on the row of rank i, the display data DATA are supplied in series by the synchronization controller 18 to the display pixel Pix4ki, clocked by the signal CLK_COL, starting from the display data concerning the display pixel DataN at the last column to the display data Datai concerning the display pixel at the first column. The display data DATA are transmitted in series from the display pixel Pix41>1 to the display pixel Pix4k2, and from the display pixel Pix42>2 to the display pixel Pix4k3, clocked by the signal CLK_COL which is also transmitted from the display pixel Pix4i i to the display pixel Pix4k2, and from the display pixel Pix42>2 to the display pixel Pix4k3.The display data DATA is transmitted serially from the display pixel Pix4ij to the display pixel Pix4ij+i, clocked by the signal CLK_COL which is also transmitted from the display pixel Pix4ij to the display pixel Pix4ij+i, until the display data DataN concerning the display pixel at the last column reaches the display pixel Pix4kN. At this point, each display pixel Pix4ki, Pix4k2 and Pix4ij, j varying from 3 to N, has received and stored display data Dataj concerning the column of rank j and provides the data Dataj to the plot P_Col.

[0146] [Fig.29] partially and schematically represents another embodiment of a display screen 110. The display screen 110 shown in [Fig.29] comprises all the elements of the display screen 30 shown in [Fig.5] with the difference that the display pixels of the second type Pix2 (Pixel & Driver) are not located on the first row and the first column but are located on the row of rank i and the column of rank j. Consequently, the column of rank j of the matrix 32 comprises display pixels of the second type Pix2k>j, k varying from 1 to M, and the row of rank i of the matrix 32 comprises display pixels of the second type Pix2 ijk, k varying from 1 to N. The other display pixels of the matrix 32 are of the first type Pixl (Pixel). The synchronization controller 18 is connected to the display pixel Pix2ij at the level of the row of rank i and the column of rank j.The timing controller 18 is configured to send the four signals CLK_COL, DATA, CLK_ROW, STD to the display pixel Pix2ij. This embodiment is particularly interesting for manufacturing frameless displays or frameless display panels to be assembled.

[0147] In the embodiments described above, the dimensions of the conductive pads and the arrangement of the conductive pads on the lower surface 38 of the control circuit 34 of the display pixel Pixl, Pix2, Pix3, Pix4 and Pix5 are particularly imposed by the design rules of the display pixel and by the method of assembling the display pixels in the display screen.

[0148] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these embodiments can be combined and other variants will readily appear to those skilled in the art. In the embodiment described above, each display pixel Pix2, Pix3, Pix4 and Pix5 comprises a pad P_Vdd which receives a lower supply voltage Vdd. Alternatively, a lower supply voltage Vdd can be generated within the control circuit 34 of the display pixels Pix2, Pix3, Pix4 and Pix5, for example from the supply voltage Vcc. In this case, the pad P_Vdd is not present.

[0149] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A display screen (30; 60; 70; 80; 90; 100) comprising a matrix of display pixels arranged in rows and columns, each display pixel comprising at least one light-emitting source (LED_R, LED_G, LED_B), and a light-emitting source control circuit (45) for driving said light-emitting source, the display pixels comprising first display pixels (Pixl) and second display pixels (Pix2; Pix3; Pix4; Pix5), at least some of the second display pixels being connected in series in a first succession, each second display pixel of the first succession further comprising a first transmission circuit (50, 52; 64, 66) configured to: - send first display data (Dataj) to the display pixels of the column of said second display pixel and transmit second display data (DATA) to the second next display pixel of the first succession;or - sending a first selection signal (Com;) to the display pixels of the line of said second display pixel and transmitting a second selection signal (STD) to the next second display pixel of the first succession.;

2. The display screen of claim 1, wherein each display pixel (Pixl, Pix2; Pix3; Pix4; Pix5) comprises first and second electrically conductive solder pads (P_Row, P_Col) connected to said light-emitting source control circuit (45), each second display pixel (Pix2; Pix3; Pix4; Pix5) further comprising third and fourth electrically conductive solder pads (P_STD_IN, P_DATA_IN, P_DATA_STD_IN, P_STD_OUT, P_DATA_OUT, P_DATA_STD_OUT) connected to said first transmission circuit (50, 52; 64, 66), said first transmission circuit (50, 52;64, 66) being configured, when the third electrically conductive solder pad (P_STD_IN, P_DATA_IN, P_DATA_STD_IN) is electrically connected to the outside of the display pixel, to send a first signal (STD, DATA), received on the third electrically conductive solder pad (P_STD_IN, P_DATA_IN, P_DATA_STD_IN), to the fourth electrically conductive solder pad (P_STD_OUT, P_DATA_OUT, P_DATA_STD_OUT), and to send a second signal (Com;, Data; j) to the light-emitting source control circuit (45) and to one of the first and second electrically conductive solder pads (P_Row, P_Col), wherein the first signal corresponds to a first selection signal (STD) and wherein the second signal corresponds to a second selection signal (Com;); or wherein the first signal corresponds to first display data (DATA) and wherein the second signal corresponds to second display data (Dataj).

3. A display screen according to claim 2, wherein for each first display pixel (Pixl), the first electrically conductive solder pad (P_Row) is intended to receive the second selection signal (Com;) and the second electrically conductive solder pad (P_Col) is intended to receive the second data signal (Dataj).

4. A display screen according to claim 3, comprising, for each row, a first electrically conductive track (E_Row;) connecting the first electrically conductive solder pads (P_Row) of the first and second display pixels (Pixl, Pix2, Pix3, Pix4, Pix5) of said row, and, for each column, a second electrically conductive track (E_Colj) connecting the second electrically conductive solder pads (P_Col) of the first and second display pixels (Pixl, Pix2, Pix3, Pix4, Pix5) of said column.

5. A display screen according to claim 4, wherein, in the first succession, the fourth electrically conductive solder pad (P_STD_OUT, P_DATA_OUT) of a second display pixel (Pix2; Pix3; Pix4; Pix5) of the first succession is connected to the third electrically conductive solder pad (P_STD_IN, P_DATA_IN) of the next second display pixel (Pix2; Pix3; Pix4; Pix5) of the first succession.

6. A display screen according to claim 5, wherein, for each second display pixel (Pix2; Pix3; Pix4; Pix5) of the first succession, the light-emitting source control circuit (45) of the second display pixel is configured to receive the second signal (Com;, Dataj) sent by the first transmission circuit (50, 52) of the second display pixel to drive the light-emitting source (LED_R, LED_G, LED_B) and, for each second display pixel (Pix2; Pix3; Pix4; Pix5) which is not in the first

7. succession, the third electrically conductive solder pad (P_STD_IN, P_DATA_IN) of the second display pixel is not electrically connected to the outside of the second display pixel and the light-emitting source control circuit (45) of the second display pixel is configured to receive the second signal (Com;, Dataj), received on the first electrically conductive solder pad (P_Row), to drive the light-emitting source (LED_R, LED_G, LED_B). A display screen according to any one of claims 2 to 6, wherein each second display pixel (Pix2) further comprises a second transmission circuit (52), and fifth and sixth electrically conductive solder pads (P_DATA_IN, P_DATA_OUT) connected to said second transmission circuit (52), said second transmission circuit (52) being configured, when the fifth electrically conductive solder pad (P_DATA_IN) is electrically connected to the outside of the display pixel, to send a third signal (DATA), received on the fifth electrically conductive solder pad (P_DATA_IN), to the sixth electrically conductive solder pad (P_DATA_OUT), and to send a fourth signal (Dataj) to the light-emitting source control circuit (45) and to the other of the first and second electrically conductive solder pads (P_Row, P_Col), wherein the first signal corresponds to the first selection signal (STD),wherein the second signal corresponds to the second selection signal (Com;), wherein the third signal corresponds to the first display data (DATA), wherein the fourth signal corresponds to the second display data (Dataj), wherein the first transmission circuit (50) of each second display pixel of the first succession is configured to send the second selection signal (Com;) to the display pixels of the row of said second display pixel and to transmit the first selection signal (STD) to the next second display pixel of the first succession, wherein at least some of the second display pixels (Pix2; Pix3) are connected in series in a second succession,and wherein the second transmission circuit (52) of each second display pixel (Pix2) of the second succession is configured to send the second display data (Dataj) to the display pixels of the column of said second display pixel and to transmit the first data, display (DATA) to the second next display pixel in the second succession.

8. A display screen according to claim 7, wherein, in the second succession, the sixth electrically conductive solder pad (P_DATA_OUT) of a second display pixel (Pix2) of the second succession is connected to the fifth electrically conductive solder pad (P_DATA_IN) of the next second display pixel (Pix2) of the second succession.

9. The display screen of claim 8, wherein, for each second display pixel (Pix2) of the second succession, the light-emitting source control circuit (45) of the second display pixel is configured to receive the fourth signal (Dataj) sent by the second transmission circuit (52) of the second display pixel to drive the light-emitting source (LED_R, LED_G, LED_B) and, for each second display pixel (Pix2) that is not in the second succession, the fifth electrically conductive solder pad (P_DATA_IN) of the second display pixel is not electrically connected to the outside of the second display pixel and the light-emitting source control circuit (45) of the second display pixel is configured to receive the fourth signal (Dataj), received on the first electrically conductive solder pad (P_Col), to drive the light-emitting source (LED_R, LED_G, LED_B).

10. A display screen according to any one of claims 7 to 9, comprising a row and a column of second display pixels (Pix2), the other display pixels of the display screen being the first display pixels (Pixl).

11. A display screen according to any one of claims 2 to 6, wherein the first transmission circuit of each second display pixel (Pix3) comprises an electronic control circuit (64) and a demultiplexer (11), said electronic control circuit (64) being configured to receive the first data signal (DATA) and the first selection signal (STD) and configured to send the second data signal (Dataj) or the second selection signal (Com;) to the demultiplexer (66), said demultiplexer (66) being configured to transmit the second data signal (Dataj) to the second electrically conductive pad (P_Col) or the second selection signal (Com;) to the first electrically conductive pad (P_Row) in function of a control signal.

12. A display screen according to claim 11, comprising a row and a column of the second display pixels (Pix3) except for a single display pixel which is one of the first display pixels (Pixl), the other display pixels of the display screen being the other first display pixels (Pixl).

13. A display screen according to any one of claims 2 to 6, wherein the first transmission circuit (52) of each second display pixel (Pix4) of the first succession is configured to send the second data signal (Data,) to the display pixels of the column of said second display pixel and to transmit the first data signal (DATA) to the next second display pixel of the first succession, wherein the display pixels comprise third display pixels (Pix5) different from the second display pixels (Pix4), wherein the third display pixels are connected in series in a second succession, and wherein each third display pixel comprises a third transmission circuit (50) configured to send the second selection signal (Coin,) to the display pixels of the row of said third display pixel and to transmit the first selection signal (STD) to the next third display pixel of the second succession.,

14. A display screen according to claim 13, comprising a row of second display pixels (Pix4) and a column of third display pixels (Pix5) except for the display pixel at the intersection of said row and said column which is one of the first display pixels (Pixl), the other display pixels of the display screen being the other first display pixels (Pixl).

15. A display screen according to claim 13, comprising a row of second display pixels (Pix4) and a column of third display pixels (Pix5) except for the display pixel of said row, or comprising a column of third display pixels (Pix5) and a row of second display pixels (Pix4) except for the display pixel of said column, the other display pixels of the display screen being the first display pixels (Pixl).

16. A display screen according to claim 13, comprising a row of second display pixels (Pix4) except for one display pixel of said row which is a third display pixel (Pix5) and a column of third display pixels (Pix5) except for one pixel display pixel of said column which is a second display pixel (Pix4), the other display pixels of the display screen being the first display pixels (Pixl) with the exception of a display pixel which is a second display pixel (Pix4) or a third display pixel (Pix5).

17. A display screen according to any one of claims 1 to 16, wherein each light-emitting source control circuit (45) comprises a storage circuit for storing at least one digital signal, the light-emitting source control circuit being configured to drive said light-emitting source (LED_R, LED_G, LED_B) based on the stored digital signal, and to update said stored digital signal from the first data signal (Dataj) upon detection of a pattern of the first selection signal (Com;).

18. A display screen according to claim 17, wherein said light emitting source control circuit (45) is configured not to update said stored digital signal from the first data signal (Dataj) when the pattern of the first selection signal (Com;) is not detected.

19. A display screen according to any one of claims 1 to 18, wherein each display pixel comprises a stack of a first electronic circuit (34) comprising the light-emitting source control circuit (45) and a second electronic circuit (36) comprising the light-emitting source (LED_R, LED_G, LED_B).

Images