Electronic circuit

Abstract

Electronic Circuit This description relates to an electronic circuit (100) comprising a reference clock signal generator block (106) and functional blocks (102, 104, 240); the circuit being configured to reset only said generator block (106) when a fault on a signal (OscClk) from a reference frequency generator (202) of the generator block is detected. Figure for the abbreviation: Fig. 2

Claims

Claims

1. Electronic circuit (100) comprising a reference clock signal generator block (106) and functional blocks (102, 104, 240); the circuit being configured to reset only said generator block (106) when a fault on a signal (OscClk) from a reference frequency generator (202) of the generator block is detected.

2. Method for controlling an electronic circuit (100) comprising a reference clock signal generator block (106) and functional blocks (102, 104, 240), the method comprising a step where only the reference clock signal generator block (106) is reset when a fault on a signal (OscClk) from a reference frequency generator (202) of the generator block is detected.

3. Circuit according to claim 1, further comprising a control circuit (104, 270) configured to generate, when a fault on said signal (OscClk) from the reference frequency generator (202) is detected, a signal for resetting the reference frequency generator (ClkReArm), different from a reset signal (resetn) common to said functional blocks (102, 104, 240) and to said generator block (106).

4. Circuit according to claim 3, wherein the reference clock signal generator block (106) comprises a detection circuit (204) configured to: detect whether said signal from the reference frequency generator (OscClk) has a fault, and generate, at the output of the detection circuit, a fault status signal (ClkFail) depending on the result of the detection.

5. Circuit according to claim 4, in which the reference clock signal generator block (106) comprises a flip-flop (210) of which: a clock input (210b) is connected to the output of the detection circuit (204) and a reset input (210a) connected to a first logic block (214) configured to perform an AND type logic function between the inverse of the reset signal of the reference frequency generator (ClkReArm) and the reset signal (resetn) common to said functional blocks (102, 104, 240) and to said reference clock generator block (106).

6. A circuit according to claim 5, wherein said generator block reference clock (106) comprises a control element (224) of which a reset input (224a) is connected to a second logic block (222) configured to perform an AND type logic function between a signal present on an inverse output (210d) of said flip-flop (210) and said reset signal (resetn) common to said functional blocks and to said reference clock generator block.

7. The circuit of claim 6, wherein said control element (224) comprises an oscillator output (224c) configured to provide a control signal for the reference frequency generator (202).

8. The circuit of claim 7, wherein the control signal of the reference frequency generator (202) is configured to stop the reference frequency generator (202) when the reset input (224a) of the control element (224) is activated.

9. A circuit according to any one of claims 6 to 8, wherein said control element (224) comprises: - a clock output (250) configured to provide a reference clock signal (ClkOut) having the reference frequency; and - a clock input (224b) configured to receive said signal from the reference frequency generator (OscClk); the control element (224) being configured so that the clock output (224b) provides the reference clock signal (ClkOut) from the signal from the reference frequency generator (OscClk) after a given number of periods have been verified.

10. Circuit according to any one of claims 5 to 9, in which the flip-flop (210) is connected to the output of the detection circuit (204) via a third logic block (212) configured to perform an AND type logic function between the fault status signal (ClkFail) and an activation signal (ClkDetEn) of the detection circuit (204).

11. A circuit according to any one of claims 5 to 10, wherein the flip-flop (210) comprises a data input (210c) set to one.

12. A circuit according to any one of claims 5 to 11, wherein the flip-flop (210) is a D-type flip-flop.

13. A circuit according to any one of claims 6 to 12, wherein the inverse output (210d) of the flip-flop (210) is configured to be reset when the reset input (210a) is activated.

14. A circuit according to any one of claims 6 to 13, wherein the reset input (210a) of the flip-flop (210) is enabled when it receives a signal at 0.

15. A circuit according to any one of claims 8 or 9 to 14 as dependent on claim 8, wherein the reset input (224a) of the control element (224) is activated when it receives a 0 signal.

Images