Non-volatile memory device and corresponding manufacturing process

Abstract

The non-volatile memory device comprises memory cells (CEL1, CEL2) having a control gate (CG) vertically embedded in a semiconductor substrate (SUB) doped with a first type of dopant, and a dielectric interface (ITFD) capable of trapping electrical charges covering flanks (FL1, FL2) of the control gate (CG) facing the semiconductor substrate. The device further comprises a vertically implanted region (AdVt) of a second type of dopant, opposite to the first type, located along said flanks of the control gate (FL1, FL2) in the semiconductor substrate (SUB). Figure for the abstract: Fig 13

Description

Title of the invention: Non-volatile memory device and corresponding manufacturing method

[0001] Embodiments and implementations relate to integrated circuits, in particular integrated circuits comprising a non-volatile memory device such as a so-called charge trap memory.

[0002] Conventional non-volatile memories are typically based on the use of transistors comprising a floating gate conductive region, to store an electrical charge in a non-volatile manner in order to encode stored data.

[0003] In charge trapping memories, the electrical charges are stored in "charge traps" of a dielectric interface. For example, the charge trapping dielectric interface may comprise a layer of silicon nitride which may be framed ("sandwiched") on either side by layers of silicon oxide, in which case we can speak of "SONOS" type technology (for "Silicon Oxide Nitride Oxide Silicon"). Other charge trapping technologies exist, such as silicon-rich dielectrics (usually "Si-Rich" in English), or so-called silicon "nanocrystal" technologies.

[0004] Typically, conventional charge trapping memories comprise a conventional planar transistor structure in which the gate dielectric layer is composed of the charge trapping dielectric interface. As a result, conventional charge trapping memory technologies do not have a large footprint advantage over floating gate transistor technology.

[0005] On the other hand, conventional charge-trapping memories can allow programming (arbitrarily, writing a "0" or resp. a "1") with a granularity of one bit, but typically impose erasures (arbitrarily, writing a "1" or resp. a "0") with a larger granularity, for example a granularity of a page, i.e. the hardware-defined size of a row of memory cells.

[0006] Indeed, conventional erasure operations are implemented by the Fowler-Nordheim effect controlled by a high voltage between the control gate and the semiconductor substrate, usually with a negative potential in the control gate and a positive or zero potential in the substrate. Consequently, conventional erasure potentials are only selective on the group of memory cells that share the same control gate (typically a row).

[0007] Thus, there is a need to benefit from more compact charge-trapping memories, with an advantageous granularity for both programming and erasing write operations, for example a granularity of one bit, while limiting the number of manufacturing steps in order to reduce production costs.

[0008] According to one aspect, there is proposed in these respects a device, for example produced in an integrated manner in an integrated circuit, of non-volatile memory comprising memory cells comprising a control gate vertically buried in a semiconductor substrate doped with a first type of dopant, for example the P type, and a dielectric interface capable of trapping electric charges covering flanks of the control gate opposite the semiconductor substrate. Each memory cell further comprises a vertical implanted region of a second type of dopant opposite the first type, for example the N type, located along said flanks of the control gate in the semiconductor substrate.

[0009] On the one hand, the vertical arrangement and buried in the substrate of the structure of the control gate and the dielectric interface, makes it possible to greatly reduce the surface area of ​​the substrate occupied by each memory cell.

[0010] On the other hand, the vertically implanted region in the semiconductor substrate along said flanks of the control gate, being doped with the opposite type to the type of the substrate, makes it possible to provide a source of minority charge carriers in the substrate, without creating an inversion channel in the substrate. Consequently, the same selectivity can be obtained for erasure as for programming, advantageously obtained by forming an inversion channel, while erasure does not generate an inversion channel.

[0011] According to one embodiment, each memory cell comprises a first conduction region doped with the second type of dopants, located in the substrate at an upper surface and on one side of the control gate, and a second conduction region doped with the second type of dopants, located in the substrate at depth at the bottom of a trench containing the control gate.

[0012] The first conduction region, for example the drain region, allows in particular selective access to the memory cell individually via a track usually called a bit line (or "bit line" in English); while the second conduction region, for example the source region, is advantageously shared for the memory cells belonging to the same group, for example a row, or even all or a portion of a memory plane.

[0013] Furthermore, it will be noted that the first conduction region is located on only one side of the control gate, so that the same control gate structure can be common to two memory cells (each having its drain region on one side respective of the control grid), usually distinguished by the terms "even" and "odd". This is again advantageous in terms of surface footprint.

[0014] According to one embodiment, the device further comprises writing means configured to generate erasure conditions adapted to an injection of hot charge carriers of a first sign, for example the positive sign, into the dielectric interface, from said vertically implanted region as a source of charge carriers of the first sign.

[0015] Thus, in the case where the first type of dopants (i.e. the substrate type) is the P type, and the vertical implanted regions located along said flanks of the control gate are of the N type, this corresponds to erasure conditions implementing an injection of hot carriers of positive charge, i.e. an injection of hot “holes” (the first sign being the positive sign). And, unlike erasure by global extraction of the trapped charges by Fowler-Nordheim effect implemented between the control gate and the substrate; erasure by injection of hot holes corresponds to a recombination of a negative charge (electrons) contained in a trap with a positive charge (holes) injected into the same trap and coming from said source of positive charge carriers. Thus, erasure by injection of hot holes is not global and can be selective by individual memory cells.

[0016] According to one embodiment, the writing means are configured to generate the erasure conditions comprising a polarization of the control gate to a potential of a second sign, for example the negative sign, and a polarization of the vertical implanted region to a potential of the first sign, for example the positive sign.

[0017] This corresponds to an example of conditions for erasure by injection of hot holes, selective for each memory cell, mentioned above.

[0018] According to one embodiment, the writing means are configured to generate the polarization of the vertical implanted region with a potential of the first non-zero sign in the first conduction region and a zero reference potential in the second conduction region, or with a potential of the first non-zero sign in the second conduction region and a zero reference potential in the first conduction region.

[0019] Indeed, depending on the orientation of the voltage between the conduction regions, for example from the source to the drain (or respectively from the drain to the source), the electric field will be greatest at the PN junction between the drain and the substrate (or respectively at the PN junction between the source and the substrate).

[0020] However, impact ionizations, that is to say the generation of hot carriers, will occur where the electric field is greatest, that is to say at the level of one or other of said PN junctions.

[0021] Thus, two distinct impact ionization regions can be provided in the same memory cell, and therefore two locations of the dielectric interface to trap charges by injecting hot carriers. This advantageously makes it possible to independently store two bits per memory cell.

[0022] Furthermore, when the same control grid structure is common to two memory cells, a single control grid structure thus allows access to four bits, each of these four bits being selectively and individually accessible for erasing, programming, as well as reading.

[0023] According to one embodiment, the writing means are further configured to generate programming conditions suitable for an injection of hot charge carriers of the second sign, for example the negative sign, into the dielectric interface, from a channel region formed along said flanks of the control gate in the semiconductor substrate as a source of charge carrier of the second sign.

[0024] According to one embodiment, the writing means are further configured to generate the programming conditions comprising a polarization of the control grid at a potential of the first sign.

[0025] According to one embodiment, the vertical implanted region is doped with a concentration of dopants of the second type of between 5*1015 at / cm3 and 1018 at / cm3, the semiconductor substrate being doped with a concentration of dopants of the first type of less than 5*1015 at / cm3.

[0026] And for example, the first conduction region can be doped with a concentration of dopants of the second type between 1018 at / cm3 and 1020 at / cm3; the second conduction region can be doped with a concentration of dopants of the second type between 5*1015 at / cm3 and 1018 at / cm3.

[0027] According to one embodiment, said buried control grid belongs to a trench extending vertically in the substrate and is superimposed on a selection grid in said trench.

[0028] According to another aspect, there is also provided a method of manufacturing a non-volatile memory device comprising memory cells, the manufacturing of each memory cell comprising: - a formation of a control gate vertically buried in a semiconductor substrate doped with a first type of dopants; - formation of a dielectric interface capable of trapping electrical charges covering the sides of the control gate facing the semiconductor substrate; and furthermore - a formation of a vertical implanted region of a second type of dopants opposite to the first type located along said flanks of the control gate in the semiconductor substrate.

[0029] According to one embodiment, said manufacturing of each memory cell comprises: - a formation of a first conduction region doped with the second type of dopants, located in the substrate at an upper surface and on one side of the control gate, and - a formation of a second conduction region doped with the second type of dopants, located in the substrate deep at the bottom of a trench containing the control gate.

[0030] According to an embodiment, further comprising write operations comprising a generation of erasure conditions producing an injection of hot charge carriers of a first sign, for example the positive sign, into the dielectric interface, from said vertical implanted region as a source of charge carriers of the first sign.

[0031] According to one embodiment, the write operations comprise a generation of erasure conditions comprising a polarization of the control gate to a potential of a second sign, for example the negative sign, and a polarization of the vertical implanted region to a potential of the first sign.

[0032] According to one embodiment, the write operations comprise a generation of the polarization of the vertical implanted region with a non-zero first sign potential in the first conduction region and a zero reference potential in the second conduction region, or with a non-zero first sign potential in the second conduction region and a zero reference potential in the first conduction region.

[0033] According to one embodiment, the write operations further comprise a generation of programming conditions producing an injection of hot charge carriers of the second sign, for example the negative sign, into the dielectric interface, from a channel region formed along said flanks of the control gate in the semiconductor substrate as a source of charge carrier of the second sign.

[0034] According to one embodiment, the write operations further comprise a generation of the programming conditions comprising a polarization of the control grid to a potential of the second sign.

[0035] According to one mode of implementation: - said formation of the control gate and said formation of the dielectric interface comprise an etching of a trench sinking vertically into the semiconductor substrate; and - said formation of the vertical implanted region of the second type of dopants includes, prior to the formation of the respective materials of the dielectric interface and the control grid in the trench: — formation of a sacrificial body doped with the second type of dopants filling the trench; — diffusion of dopants from the sacrificial body into the semiconductor substrate along the sides of the trench; — a removal of the sacrificial body from the trench.

[0036] According to one embodiment, the vertical implanted region is doped with a concentration of dopants of the second type of between 5*1015 at / cm3 and 1018 at / cm3, the semiconductor substrate being doped with a concentration of dopants of the first type of less than 5*1015 at / cm3.

[0037] And for example, the first conduction region can be doped with a concentration of dopants of the second type between 1018 at / cm3 and 1020 at / cm3; the second conduction region can be doped with a concentration of dopants of the second type between 5*1015 at / cm3 and 1018 at / cm3.

[0038] According to one embodiment, the manufacture of each memory cell further comprises: - a formation of a selection gate in a trench extending vertically in the semiconductor substrate; said formation of the control grid being made in said trench over the selection grid.

[0039] Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments and implementations, which are in no way limiting, and the appended drawings, in which the figures:

[0040] [Fig.l];

[0041] [Fig.2];

[0042] [Fig.3];

[0043] [Fig.4];

[0044] [Fig.5];

[0045] [Fig.6A];

[0046] [Fig.6B];

[0047] [Fig.6C];

[0048] [Fig.6D];

[0049] [Fig.7];

[0050] [Fig. 8];

[0051] [Fig.9];

[0052] [Fig. 10];

[0053] [Fig.11];

[0054] [Fig. 12];

[0055] [Fig. 13];

[0056] [Fig. 14];

[0057] [Fig. 15 A];

[0058] [Fig.l5B];

[0059] [Fig.l5C];

[0060] [Fig.lôA];

[0061] [Fig.lôB];

[0062] [Fig.lôC];

[0063] [Fig.l6D];

[0064] [Fig.l7A];

[0065] [Fig.l7B];

[0066] [Fig.l7C];

[0067] [Fig.l7D];

[0068] [Fig. 18] illustrent des modes de réalisation et de mise en œuvre de l’invention.

[0069] Figures 1 to 12 illustrate results of steps in a manufacturing process of “SONOS” charge trapping type memory cells (acronym for the common terms “silicon oxide nitride silicon oxide” well known to those skilled in the art) as represented by figures 13 and 14.

[0070] In this regard, reference is made to [Fig. 13].

[0071] [Fig. 13] illustrates an exemplary embodiment of a non-volatile memory device comprising memory cells CEL1, CEL2 of the “SONOS” type.

[0072] A control gate CG is vertically buried in a semiconductor substrate SUB doped with a first type of dopant, for example the P type.

[0073] The control grid CG is in this respect advantageously formed in an opening, called a trench, etched vertically in depth in the substrate SUB, from a front face FA of the substrate.

[0074] The control grid CG can advantageously be common to two memory cells CEL1, CEL2, usually designated respectively “odd cell” CEL1 and “even cell” CEL2. The two memory cells CEL1, CEL2 are located on either side (horizontally) of the vertical control grid CG.

[0075] A dielectric interface ITFD capable of trapping electric charges covers the sides of the control gate CG facing the semiconductor substrate SUB.

[0076] A dielectric interface ITFD is in this respect advantageously formed in said trench containing the control gate CG, before the formation of the control gate CG so as to envelop the control gate CG on the flanks FL1, FL2 and the bottom of the control gate CG.

[0077] For example, the ITFD dielectric interface comprises a succession of layers of silicon oxide O, silicon nitride N, and silicon oxide O. Briefly, the silicon nitride N layer is capable of storing electrical charges in "charge traps" while the oxide O layers have an electrical insulation functionality of the gate oxide type.

[0078] Each memory cell CEL1, CEL2 further comprises a vertical implanted region AdVt of a second type of dopants opposite to the first type, i.e. the N type in this example, located in the semiconductor substrate SUB, along the sides FL1, FL2 of the control gate CG and thus along the dielectric interface ITFD.

[0079] In absolute terms, given that each of the two memory cells CEL1, CEL2 is located on the side of a respective flank of the control gate CG, the vertical implanted region AdVt of the respective memory cells CEL1, CEL2 is located in the substrate SUB along the respective flank FL1, FL2, and along the respective dielectric interface ITFD.

[0080] Furthermore, the memory cells CEL1, CEL2 each comprise a first conduction region D1, D2 doped with the second type of dopant (the N type in this example), for example the drain region, located in the substrate SUB at the level of an upper surface of the substrate, i.e. the front face FA, and on the respective side of the control gate CG.

[0081] The front face FA of the substrate SUB corresponds to the surface on which CNT metal contacts are coupled, connecting elements of the semiconductor substrate (D1, CG, D2), with metal tracks of an interconnection network (not shown, conventional and known per se).

[0082] On the other hand, the memory cells CEL1, CEL2 comprise a second S-NISO conduction region doped with the second type of dopants (the N type in this example), for example the source region, located in the substrate SUB in depth at the level of the bottom FD of the trench containing the control gate CG.

[0083] For example, the second S-NISO conduction region belongs to a “source plane”, that is to say a region implanted deep in the substrate, of the isolation box type (“NISO”) of a triple-box type structure.

[0084] Furthermore, in this example, the memory cells CEL1, CEL2 comprise a selection gate SG, also in the trench containing the control gate CG, between the control gate CG and the bottom FD of the trench.

[0085] The selection gate SG is electrically isolated from the substrate SUB and the source region S-NISO by a gate dielectric shell Dsg. The selection gate SG is also isolated from the control gate by a dielectric layer.

[0086] For example, in practice: - the semiconductor substrate SUB, typically silicon, can be doped with boron at a concentration between 1014 and 5*1015 at / cm3; - the first conduction regions Dl, D2 can be doped with arsenic at a concentration between 1018 and 1020 at / cm3; - the second S-NISO conduction region can be doped with phosphorus at a concentration between 5*1015 and 1018 at / cm3 - the vertical implanted regions AdVt can be doped with phosphorus (or arsenic) at a concentration between 5*1015 and 1018 at / cm3.

[0087] [Fig. 14] illustrates an exemplary embodiment of a non-volatile memory device comprising memory cells CEL1, CEL2 of the “SONOS” type, as an alternative to that described in relation to [Fig. 13].

[0088] In this alternative, the memory cells CEL1, CEL2 do not include the selection gate SG, nor the corresponding gate dielectric envelope Dsg.

[0089] The other elements of the device and of the memory cells CEL1, CEL2 bear the same references, and all the rest of the description given in relation to [Fig.13] applies to the alternative of [Fig.14].

[0090] We now refer to Figures 1 to 12.

[0091] [Fig.l] illustrates the result of a step 100 of etching the trench TR in the semiconductor substrate SUB, doped with the first type of dopant, i.e. for example the P type, and comprising the S-NISO region doped with the N type implanted deep in the substrate SUB.

[0092] [Fig.2] illustrates the result of a step 200 of forming a layer of “sacrificial” oxide SACOX, on the sides and the bottom of the trench TR. The layer of sacrificial oxide SACOX will nevertheless form the gate oxide Dsg ([Fig. 13]) of the future selection gate SG ([Fig.3] and following). For example, the layer of sacrificial oxide SACOX can have a thickness of between 5 nm and 10 nm.

[0093] [Fig. 3] illustrates the result of a step 300 of forming a first conductive gate material PO, for example made of doped polycrystalline silicon. The first gate material PO is deposited in excess so as to fill the trench and also overflow above the front face FA.

[0094] [Fig.4] illustrates the result of an etching step 400 removing the first gate material PO over a height less than the depth of the trench TR, for example a height between 50% and 90% of the depth of the trench. For example, the etching 400 is implemented for a duration configured in this regard as a function of the etching speed. Furthermore, the etching 400 is configured to be selective with respect to the silicon oxide, so as not to etch or to etch very little of the sacrificial oxide layer SACOX in order to protect the substrate SUB against this etching 400.

[0095] [Fig.5] illustrates the result of a first example of a training step 500 of a vertical implanted region AdVt of the second type of dopants, i.e. the N type, in the semiconductor substrate SUB, and located along the flanks FLTrl, FLTr2 of the trench TR.

[0096] In this first example, this vertical orientation of the implanted region AdVt can be obtained by implementing a first inclined implantation TLTIMP1 so as to obliquely expose a first flank of the trench FLTrl, and a second inclined implantation TLTIMP2 so as to obliquely expose a second flank of the trench FLTr2.

[0097] Figures 6A to 6D illustrate a second, preferred example of formation of a vertical implanted region AdVt of the second type of dopants, i.e. the N type, in the semiconductor substrate SUB, along the flanks FLTrl, FLTr2 of the trench TR.

[0098] Indeed, it can be difficult to achieve uniform channel implantation, vertically along the side walls of the trench, particularly depending on the form factor using inclined implantation techniques. The second example described advantageously makes it possible to form the uniform vertical implanted region AdVt around the vertical trenches.

[0099] [Fig.6A] illustrates the result of a step 610 of forming a thin layer of sacrificial oxide SACOX_Thn, on the flanks FLTr, FLTr and the bottom of a trench TRd already formed.

[0100] In particular, the thin layer of sacrificial oxide SACOX_Thn is thinner than the SACOX sacrificial oxide layer previously described in relation to [Fig.2]. For example, the thin layer of sacrificial oxide SACOX_Thn has a thickness of less than 5 nm. In particular, the thin layer of sacrificial oxide SACOX_Thn is not intended to form a gate dielectric region, and does not have the constraint of a minimum thickness in this regard.

[0101] In an embodiment corresponding to the example of [Fig.13], the already formed trench TRd may correspond to the trench TR of [Fig.4], in which the sacrificial oxide layer SACOX is removed wherever it is not covered by the first gate material PO.

[0102] In an embodiment corresponding to the example of [Fig.14], the trench TRd already formed can correspond to the trench TR of [Fig.l].

[0103] [Fig.6B] illustrates the result of a step 620 of forming a heavily doped sacrificial body of the second type of dopants SACPOLYN+, i.e. the N type, in the already formed trench TRd. For example, the sacrificial body SACPOLYN+ is formed with a gate conductive material, such as polycrystalline silicon, and for example in the manner previously described in relation to [Fig.3].

[0104] [Fig.6C] illustrates the result of a step 630 of diffusion of N-type dopants, of the sacrificial body SACPOLYN+ to the semiconductor substrate SUB through the thin layer of sacrificial oxide SACOX_Thn.

[0105] At the end of diffusion 630, the profile of the N-type doping, i.e. the spatial variation of the concentration of the dopants in the substrate SUB, can have a “drop” shape caused by the sharp shape of the trench.

[0106] [Fig.6D] illustrates the result of a step 640 in which annealing and stabilization of the dopants have been implemented, so that the profile of the N-type doping obtained by the diffusion of step 630 is uniformized along the FLTr flanks of the TRd trench.

[0107] Furthermore, step 640 comprises a removal of the sacrificial body, for example according to the same type of etching as described previously in relation to [Fig.4].

[0108] [Fig.7] illustrates the result of a step 700, after the formation 500, 610-640 of the vertical implanted region AdVt of the N type located in the semiconductor substrate SUB, along the flanks FLTrl, FLTr2 of the trench TR, i.e. along the flanks of the future control gate CG and along the future charge trapping dielectric interface ITFD.

[0109] Step 700 corresponds to the removal of the sacrificial oxide layer SACOX wherever it is not covered by the first gate material PO, in an implementation mode corresponding to the example of [Fig. 13] (after the formation 500 described in relation to [Fig. 5]); or to the removal of the thin sacrificial oxide layer SACOX_Thn, optionally in an implementation mode corresponding to the example of [Fig. 14] (after the formation 610-640 described in relation to FIGS. 6A to 6D).

[0110] [Fig.8] illustrates the result of a step 800 of forming a first layer of silicon oxide O, for example by means of a conformal deposition, that is to say a deposition of a uniform and constant thickness of the layer O, whatever the orientation (vertical or horizontal) of the deposition surface.

[0111] [Fig.9] illustrates the result of a step 900 of forming a nitride layer of silicon N, conformally on the first oxide layer O.

[0112] [Fig. 10] illustrates the result of a step 1000 of forming a second layer of silicon oxide 0, conformally on the layer of nitride N.

[0113] For example, each of the oxide and nitride layers of the ONO stack may have a thickness of between 5 nm and 10 nm.

[0114] At the end of steps 800, 900, 1000 described in relation to FIGS. 8, 9 and 10, a dielectric interface ITFD capable of trapping electrical charges has been formed, in particular in “charge traps” of the silicon nitride layer N. The dielectric interface is intended to cover the sides of the future control gate CG facing the semiconductor substrate SUB.

[0115] [Fig. 11] illustrates the result of a step 1100 of forming a second gate conductive material P2, for example made of doped polycrystalline silicon.

[0116] The second gate material P2 is deposited in excess so as to fill the trench TR, i.e. the volume remaining inside the trench TR between the sides and the bottom of the stack of ONO dielectric layers of the ITFD interface, and to overflow onto the stack of ONO dielectric layers, above the front face FA.

[0117] [Fig. 12] illustrates the result of a “planarization” step 1200 (common anglicism from the English term “planarization”) in which all the layers located above the front face FA of the substrate SUB have been removed.

[0118] This type of removal 1200 is for example implemented by a chemo-mechanical planarization technique “CMP” (acronyms for the usual English terms “chemical-mechanical planarization”).

[0119] Thus, with the second gate material P2, the vertical control gate structure CG buried in the substrate SUB was formed, as described previously in relation to FIGS. 13 or 14; and, with the first gate material PO, the selection gate structure SG was formed, as described previously in relation to [Fig. 13].

[0120] Thus, after steps 1300 of implantation of the drain regions D1, D2, of formation of the CNT metal contacts and of the rest of the integrated circuit manufacturing chain, the memory device described previously in relation to [Fig. 13] in the case of the presence of the selection gate SG, or with [Fig. 14] in the case of the absence of the selection gate SG has been obtained.

[0121] Furthermore, it will be noted that each selection grid SG can be common to a group of even and odd memory cells CEL1, CEL2, usually called a “page”, typically a line of the physical organization of a memory plane containing all the memory cells, and comprising subsets called “words”. The words can for example comprise one or more bytes, and have a command grid CG common to the even and odd memory cells CEL1, CEL2 belonging to the same word.

[0122] Figures 15A, 15B and 15C illustrate the principles of the write operations, typically comprising programming and / or erasure, in the example of the memory cell CEL1 described previously in relation to [Fig.13].

[0123] In the remainder of this description, it is conventionally considered that programming a memory cell corresponds to writing the data item “0” (according to an example of arbitrary convention), while erasing a memory cell corresponds to writing the data item “1” (according to the same example). It is also conventionally considered that programming is obtained by charge trapping having the negative sign, that is to say electrons; and that the erasure is obtained by expulsion of the trapped negative charges, or advantageously by an injection of charges of positive sign, that is to say holes, recombining with trapped negative charges.

[0124] Also by convention, and in consistency with the example given previously in relation to figures 1 to 14 according to which the first type of dopants is the P type while the second type of dopants is the N type, it is considered that the positive sign of the charges and the potentials (in volts) is the “first sign”, while the negative sign of the charges and the potentials (in volts) is the “second sign”.

[0125] [Fig.15A] illustrates PRHT programming conditions producing an injection of negatively charged hot carriers, i.e. HTe- "hot electrons", into charge traps of the ITFD dielectric interface.

[0126] The PRHT programming conditions include biasing the control gate CG to a high voltage positive potential, for example substantially +9 V (volts), so that the hot electrons HTe- can originate from a CNL channel region formed along the flanks of the control gate CG in the semiconductor substrate. The CNL channel region thus forms the source of the hot negative charge carriers.

[0127] Furthermore, the programming conditions PRHT may comprise a biasing of the drain DI of the selected memory cell CEL1 to a moderate positive potential, for example substantially +4.5V; an application of an activation potential in the selection gate SG capable of generating the continuity of the channel region CNL along the selection gate SG to the source S-NISO, for example substantially 1.5V; a biasing of the source S-NISO and the substrate SUB to a zero reference voltage 0V; as well as leaving floating the potential in the drains D2 of all the other memory cells CEL2, as well as a blocking potential, for example 0V, in the non-selected selection gates.

[0128] [Fig.15B] illustrates ERFD “global” erasure conditions producing an extraction of the charges stored in the charge traps of the ITFD dielectric interface by Fowler-Nordheim effect.

[0129] These global erasure ERFD conditions comprise a polarization of the control gate CG at a negative potential of high voltage called shared, for example substantially -10 V, and a polarization of the substrate SUB at a moderate positive voltage also shared, for example substantially +5 V, so that the trapped electrons are expelled from the traps of the N nitride layer towards the substrate SUB.

[0130] Furthermore, the conditions for global erasure by Fowler-Nordheim effect ERFD may further comprise a polarization of the drains D1, D2, of the selection gate SG and of the source S-NISO of all the memory cells of the row erased (selected) at the shared positive potential of approximately 5 V.

[0131] The conditions of the Fowler-Nordheim effect being obtained between the control gate CG and the substrate SUB, all the even and odd memory cells CEL1, CEL2 belonging to the same row are erased by these ERFD conditions. This is disadvantageous in itself.

[0132] [Fig.15C] illustrates preferential ERHT erasure conditions advantageously producing an injection of hot carriers of positive charge, i.e. HTh+ "hot holes", into the charge traps of the ITFD dielectric interface, recombining with negative charges trapped in said traps.

[0133] The preferential erasure conditions ERHT have the advantage of being bit-selective, i.e. each bit of each memory cell CEL1 can be selectively erased relative to the other bits of the memory cells CEL2 of the same row or of the same memory word.

[0134] Indeed, the preferential conditions for ERHT erasure include biasing the control gate CG to a high voltage negative potential, for example substantially -9 V (volts). This high negative potential of the control gate CG blocks the formation of a channel region CNL in the substrate SUB. However, despite the absence of the channel region CNL (and therefore of the source of charge carriers such as for PRHT programming), a high current can flow in the vertical implanted regions AdVt, provided that there is a sufficiently high drain potential DI. The high positive drain potential DI causes the creation of hot holes HTh+ by impact ionization. The current flowing in the vertical implanted region AdVt of the odd cell CEL1 thus forms the source of the hot carriers of positive charge HTh+.

[0135] Furthermore, the preferential erasure conditions ERHT are bit-selective because they include biasing the drain DI of the selected memory cell CEL1 to a moderately high positive potential, for example substantially +4.5V.

[0136] On the other hand, the preferential conditions for selective erasure by bit ERHT comprise an application of an activation potential in the selection gate SG, capable of generating a channel region making an electrical continuity between the vertical implanted region AdVt and the source S-NISO, along the selection gate SG, for example of substantially 2.5 V; a polarization of the source S-NISO and the substrate SUB to a zero reference voltage 0 V; as well as leaving the potential floating in the drains D2 of all the other memory cells CEL2. The non-selected selection gates can be brought to a blocking potential, for example 0 V.

[0137] Figures 16A, 16B, 16C and 16D illustrate the preferential ERHT erasure conditions, selective by bit, in the case of the realization of the memory cells without the selection gate SG, as described previously in relation to [Fig. 14],

[0138] Figures 16A to 16D further illustrate another advantageous feature of the preferential erasure conditions ERHT, allowing storage of two independent bits in the same odd memory cell CEL1 or even memory cell CEL2.

[0139] Indeed, in this regard, we can generate: - first erasure conditions ERHT_l_up for the odd memory cell CEL1 ([Fig.lôA]), - first erasure conditions ERHT_2_up for the even memory cell CEL2 ([Fig.l6C]), - second erasure conditions ERHT_l_dwn for the odd memory cell CEL1 ([Fig.lôB]), - second erasure conditions ERHT_2_dwn for the even memory cell CEL2 ([Fig. 16D]).

[0140] [Fig.16A] illustrates the first erasure conditions ERHT_1_up for the odd memory cell CEL1, polarizing the vertical implanted region AdVt with the non-zero positive potential, for example 4.5 V, in the first conduction region DI and the zero reference potential, 0 V, in the second conduction region S-NISO.

[0141] Further, the negative high voltage, for example -9 V, is applied in the control gate CG, and the first conduction region D2 of the even memory cell CEL2 sharing the same control gate CG is left at a floating potential at high impedance Hz.

[0142] [Fig.16B] illustrates the second erasure conditions ERHT_1_dwn for the odd memory cell CEL1, polarizing the vertical implanted region AdVt with the zero reference potential, 0 V, in the first conduction region DI and the non-zero positive potential, for example 4.5 V, in the second conduction region S-NISO.

[0143] Further, the negative high voltage, for example -9 V, is applied in the control gate CG, and the first conduction region D2 of the even memory cell CEL2 sharing the same control gate CG is left at a floating potential at high impedance Hz.

[0144] [Fig.16C] illustrates the first erasure conditions ERHT_2_up for the even memory cell CEL2, polarizing the vertical implanted region AdVt with the non-zero positive potential, for example 4.5 V, in the first conduction region D2 and the zero reference potential, 0 V, in the second conduction region S-NISO.

[0145] Further, the negative high voltage, for example -9 V, is applied in the control gate CG, and the first conduction region D1 of the odd memory cell CEL1 sharing the same control gate CG is left at a floating potential with high impedance Hz.

[0146] [Fig.16D] illustrates the second erasure conditions ERHT_2_dwn for the even memory cell CEL2, biasing the vertical implanted region AdVt with the zero reference potential, 0 V, in the first conduction region D2 and the non-zero positive potential, for example 4.5 V, in the second conduction region S-NISO.

[0147] Further, the negative high voltage, for example -9 V, is applied in the control gate CG, and the first conduction region D1 of the odd memory cell CEL1 sharing the same control gate CG is left at a floating potential with high impedance Hz.

[0148] Indeed, depending on the orientation of the voltage between the conduction regions, for example from the source to the drain in the case of the first erasure conditions ERHT_l_up, ERHT_2_up, the electric field will be the largest at the PN junction between the drain Dl, D2 and the substrate SUB.

[0149] And, respectively in the orientation of the voltage between the drain-to-source conduction regions, in the case of the second erasure conditions ERHT_l_dwn, ERHT_2_dwn, the electric field will be the largest at the PN junction between the S-NISO source and the SUB substrate.

[0150] However, the ionizations by impacts IMPCT_l_up, IMPCT_l_dwn, IMPCT_2_up, IMPCT_2_dwn, that is to say the generations of hot carriers, will occur where the electric field is the greatest, that is to say at the level of one or other of said PN junctions.

[0151] Thus, two distinct impact ionization regions IMPCT_l_up, IMPCT_l_dwn can be provided in the same odd memory cell CEL1; and respectively two distinct impact ionization regions IMPCT_2_up, IMPCT_2_dwn in the same even memory cell CEL2.

[0152] Each odd memory cell CEL1 or even CEL2 therefore has two locations of the ITFD dielectric interface to trap charges by injecting hot holes. This advantageously makes it possible to independently store two bits per memory cell.

[0153] Figures 17A, 17B, 17C and 17D illustrate the bit-selective PRHT programming conditions in the case of the memory cell embodiments without the SG selection gate, as previously described in relation to [Fig. 14].

[0154] The programming conditions present the same advantageous faculty of storing two independent bits in the same odd memory cell CEL1 or even CEL2.

[0155] In this regard, reference will be made to:

[0156] [Fig.l7A] which illustrates the first programming conditions PRHT_l_up for the odd memory cell CEL1, which may for example be identical to the first erase conditions ERHT_l_up for the odd memory cell CEL1 but with a bias of the control gate CG with the positive high voltage potential, for example +10 V;

[0157] [Fig.l7B] which illustrates second programming conditions PRHT_l_dwn for the odd memory cell CEL1, which may for example be identical to the second erasure conditions ERHT_l_dwn for the odd memory cell CEL1 but with a polarization of the control gate CG with the positive high voltage potential, for example +10 V;

[0158] [Fig.l7C] which illustrates first programming conditions PRHT_2_up for the even memory cell CEL2, which may for example be identical to the first erasure conditions ERHT_2_up for the even memory cell CEL2 but with a polarization of the control gate CG with the positive high voltage potential, for example +10 V;

[0159] [Fig.l7D] which illustrates second programming conditions PRHT_2_dwn for the even memory cell CEL2, which may for example be identical to the second erasure conditions ERHT_2_dwn for the even memory cell CEL2 but with a polarization of the control gate CG with the positive high voltage potential, for example +10 V.

[0160] The selectivity and location mechanisms IMPCT_l_up, IMPCT_l_dwn, IMPCT_2_up, IMPCT_2_dwn, of the two bits per odd cell CEL1 and even cell CEL2 are the same in programming PRHT_l_up, PRHT_l_dwn, PRHT_2_up, PRHT_2_dwn, as described previously in relation to figures 16A-16D for erasure ERHT_l_up, ERHT_l_dwn, ERHT_2_up, ERHT_2_dwn.

[0161] [Fig. 18] illustrates on the one hand in an RD_l_up table, the conditions allowing selective read access to the first bit (IMPCT_l_up) of the odd memory cell CEL1, and on the other hand in an RD_l_dwn table, the conditions allowing selective read access to the second bit (IMPCT_l_dwn) of the odd memory cell CELL

[0162] The read access conditions of the two bits of the even memory cell CEL2 are obtained by inverting the polarizations between the drain regions DI and D2 of the tables RD_l_up and RD_l_dwn.

[0163] Furthermore, writing means ME of conventional design and not shown are provided to implement the writing operations ERHT, ERFD, PRTH, ERHT_l_up, ERHT_l_dwn, ERHT_2_up, ERHT-2-dwn, PRTH_l_up, PRTH_l_dwn, PRTH-2-up, PRTH_2_up, and reading operations RD_l_dwn, RD_l_up as described above in relation to FIGS. 15A to 18, and may for example comprise a high voltage generator of the charge pump type, a logic for transmitting the high voltages to the memory cells, and a logic of the type state machine to time and control write and read operations.

[0164] In summary, a non-volatile memory of the charge trapping type has been described, in which a single vertical control gate structure CG, possibly superimposed on a selection gate SG in a trench, therefore having a very small surface footprint at the level of the front face FA of the substrate SUB, allows access to 4 bits, each of these four bits being selectively and individually accessible for erasure, programming, as well as reading.

Claims

Claims

1. Non-volatile memory device comprising memory cells (CEL1, CEL2) comprising a control gate (CG) vertically buried in a semiconductor substrate (SUB) doped with a first type of dopants, and a dielectric interface (ITFD) capable of trapping electric charges covering flanks (FL1, FL2) of the control gate (CG) facing the semiconductor substrate, further comprising a vertical implanted region (AdVt) of a second type of dopants opposite the first type located along said flanks of the control gate (FL1, FL2) in the semiconductor substrate (SUB).

2. Device according to claim 1, in which each memory cell (CEL1, CEL2) comprises a first conduction region (Dl, D2) doped with the second type of dopants, located in the substrate (SUB) at an upper surface (FA) and on one side of the control gate (CG), and a second conduction region (S-NISO) doped with the second type of dopants, located in the substrate (SUB) in depth at the bottom of a trench (FD) containing the control gate (CG).

3. Device according to one of claims 1 or 2, further comprising writing means (ME) configured to generate erasure conditions (ERHT) adapted to an injection of hot charge carriers of a first sign, into the dielectric interface (ITFD), from said vertical implanted region (AdVt) as a source of charge carriers of the first sign.

4. Device according to claim 3, in which the writing means (ME) are configured to generate the erasure conditions (ERHT) comprising a polarization of the control gate (CG) at a potential of a second sign, and a polarization of the vertical implanted region (AdVt) at a potential of the first sign.

5. Device according to claim 4 taken in combination with claim 2, wherein the writing means (ME) are configured to generate the polarization of the vertical implanted region (AdVt) with a potential of the first non-zero sign in the first conduction region (Dl) and a zero reference potential in the second conduction region (S-NISO), or with a potential of the first non-zero sign in the second conduction region (S-NISO) and a zero reference potential in the first conduction region (Dl).

6. Device according to one of claims 3 to 5, in which the writing means (ME) are further configured to generate programming conditions (PRHT) adapted to an injection of hot charge carriers of the second sign, into the dielectric interface (ITFD), from a channel region (CNL) formed along said flanks of the control gate (CG) in the semiconductor substrate (SUB) as a source of charge carrier of the second sign.

7. Device according to claim 6, in which the writing means (ME) are further configured to generate the programming conditions (PRHT) comprising a polarization of the control gate (CG) at a potential of the second sign.

8. Device according to one of claims 1 to 7, in which the vertical implanted region (AdVt) is doped with a concentration of dopants of the second type between 5*1015 at / cm3 and 1018 at / cm3, the semiconductor substrate (SUB) being doped with a concentration of dopants of the first type less than 5*1015 at / cm3.

9. Device according to one of claims 1 to 8, wherein said buried control grid (CG) belongs to a trench (TR) extending vertically in the substrate (SUB) and is superimposed on a selection grid (SG) in said trench (TR).

10. Method for manufacturing a non-volatile memory device comprising memory cells (CEL1, CEL2), the manufacturing of each memory cell (CEL1, CEL2) comprising: - a formation (1100, 1200) of a control gate (CG) vertically buried in a semiconductor substrate (SUB) doped with a first type of dopants; - a formation (800, 900 1000) of a dielectric interface (ITFD) capable of trapping electrical charges covering flanks of the control gate (CG) facing the semiconductor substrate (SUB); and further - a formation (500; 610, 620, 630, 640) of a vertical implanted region (AdVt) of a second type of dopants opposite to the first type located along said flanks of the control gate (CG) in the semiconductor substrate (SUB).

11. Method according to claim 10, wherein said fabrication of each memory cell comprises: - a formation (1300) of a first conduction region (Dl) doped with the second type of dopants, located in the substrate at a upper surface (FA) and on one side of the control gate (CG), and - a formation (100) of a second conduction region (S-NISO) doped with the second type of dopants, located in the substrate in depth at the bottom (FD) of a trench (TR) containing the control gate (CG).

12. Method according to one of claims 10 or 11, further comprising writing operations comprising a generation of erasure conditions (ERTH) producing an injection of hot charge carriers of a first sign, into the dielectric interface (ITFD), from said vertical implanted region (AdVt) as a source of charge carriers of the first sign.

13. The method of claim 12, wherein the write operations comprise generating erase conditions (ERHT) comprising biasing the control gate (CG) to a potential of a second sign, and biasing the vertical implanted region (AdVt) to a potential of the first sign.

14. A method according to claim 13 taken in combination with claim 10, wherein the writing operations comprise generating the polarization of the vertical implanted region (AdVt) with a potential of the first non-zero sign in the first conduction region (Dl) and a zero reference potential in the second conduction region (S-NISO), or with a potential of the first non-zero sign in the second conduction region (S-NISO) and a zero reference potential in the first conduction region (Dl).

15. Method according to one of claims 12 to 14, wherein the writing operations further comprise a generation of programming conditions (PRHT) producing an injection of hot charge carriers of the second sign, in the dielectric interface (ITFD), from a channel region (CNL) formed along said flanks of the control gate (CG) in the semiconductor substrate (SUB) as a source of charge carrier of the second sign.

16. The method of claim 15, wherein the write operations further comprise generating the programming conditions (PRHT) comprising biasing the control gate (CG) to a potential of the second sign.

17. Method according to one of claims 10 to 16, wherein: - said formation of the control gate and said formation of the dielectric interface comprise an etching (100) of a trench sinking vertically into the semiconductor substrate; and - said formation of the vertical implanted region of the second type of dopants comprises, before the formations (800, 900, 1000, 1100) of the respective materials of the dielectric interface and of the control gate in the trench: — a formation (620) of a sacrificial body doped with the second type of dopants filling the trench; — a diffusion (630) of the dopants of the sacrificial body in the semiconductor substrate along the sides of the trench; — a withdrawal (640) of the sacrificial body from the trench.

18. Method according to one of claims 10 to 17, in which the vertical implanted region (AdVt) is doped with a concentration of dopants of the second type between 5*1015 at / cm3 and 1018 at / cm3, the semiconductor substrate (SUB) being doped with a concentration of dopants of the first type less than 5*1015 at / cm3.

19. Method according to one of claims 10 to 18, in which the manufacturing of each memory cell (CEL1, CEL2) further comprises: - a formation (200, 300, 400) of a selection gate (SG) in a trench (TR) extending vertically in the semiconductor substrate (SUB); said formations (1100, 1200) of the control grid (CG) being made in said trench (TR) over the selection grid (SG).

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