Improved High Mobility Field-Effect Transistor

Abstract

The invention relates to a high-mobility field-effect transistor comprising: a z-axis stack (10) deposited on a substrate (11) and comprising: a buffer layer (12), a barrier layer (13), a heterojunction (15) between said buffer layer (12) and said barrier layer (13), and a two-dimensional electron gas (9), a drain (D), a source (S), and a gate (G), a first passivation layer (PLhi) having a first dielectric constant (εhi) greater than or equal to 15, a second passivation layer (PLlow) having a second dielectric constant (εlow) less than or equal to 10 and extending over at least the second zone (Z2). Figure to be published: Figure 3

Description

Title of invention: Improved high mobility field effect transistor FIELD OF THE INVENTION

[0001] The present invention lies in the field of high electron mobility field effect transistors called HEMT transistors (acronym for the English expression “High Electron Mobility Transistor”) in GaN technology and for microwave applications, typically at frequencies up to 40 GHz, or even 80 GHz in the near future.

[0002] More particularly, the invention relates to the passivation of transistors in the vicinity of the gate. STATE OF THE ART

[0003] [Fig.l] schematically represents a section of the structure of a conventional elementary HEMT transistor system, in an Oxz plane, produced on a substrate 11. Conventionally, an insulating or semiconducting substrate 11 is used, for example comprising silicon (Si), Silicon Carbide (SiC) or Sapphire (A12O3), on which a stack is produced along the z axis of at least two semiconductor layers which extend in the Oxy plane.

[0004] A first layer 12, called a buffer layer, or “buffer” (term used in the English literature), has a wide forbidden band (semiconductor material known as a large gap) for example comprising a binary nitrogen compound material, such as GaN or a material based on a ternary compound of element III nitride, called IILN, such as AlGaN, or more precisely AlxGai_xN.

[0005] A second layer, called barrier layer 13, has a greater band gap than that of buffer layer 12. This layer comprises a material based on a quaternary, ternary or binary compound of III element nitride, called IILN, based on Al, Ga, In or B.

[0006] For example, with a GaN buffer layer, the barrier layer comprises Alx GabxN or Ini xAlxN, or an Ini xAlxN / AlN or AlxGabxN / AlN sequence. The thickness of the barrier layer 13 is typically between 5 nm and 40 nm, the thickness of the buffer layer 12 is typically between 0.2 pm and 3 pm. The buffer layer 12 and the barrier layer 13 are conventionally produced by epitaxy by MOCVD or by MBE. As an example, mention may be made of a GaN-based buffer layer with a barrier layer based on AlGaN or InAlN, and more precisely based on AlxGai xN or InzAli_zN, with x typically between 15% and 35% and z typically between 15% and 25%.

[0007] Additional layers may be present either on the surface or between the buffer layer and the barrier layer.

[0008] The junction between the buffer layer and the barrier layer constitutes a heterojunction 15 which also extends in the Oxy plane. The origin O of the Oxyz reference frame is chosen in this plane.

[0009] A HEMT transistor conventionally comprises a source S, a drain D and a gate G deposited on the upper face 14 of the barrier layer 13. The gate G is deposited between the source S and the drain D and makes it possible to control the transistor. Typically the gate-source distance dGS is between 0.4 and 1 pm and the gate-drain distance dGD is between 0.6 and 2 pm. Preferably the gate G has a T or T shape, and is made up of a trunk 16 surmounted by at least one cap 17 (there may be several of them one on top of the other). The two branches of the cap are not necessarily symmetrical, and the drain-side branch may even be non-existent (so-called T-shaped gate). The base of the trunk 16 in contact with the barrier layer 13 is commonly called the grid foot, the reference 18s corresponding to the grid foot on the source side and the reference 18d corresponding to the grid foot on the drain side in [Fig.l].

[0010] The conductance between the source S and the drain D is modulated by the electrostatic action of the gate G, classically of the Schottky type or of the MIS type for (metal / insulator / semiconductor), and the voltage VGS applied between the gate and the source controls the transistor.

[0011] A two-dimensional electron gas 9 (called 2DEG for “two-Dimensional Electron Gas”) is located in the vicinity of the heterojunction 15. These electrons are mobile in the Oxy plane and have a high electronic mobility pe, typically greater than 1000cm2 / Vs. In normal operation of the transistor these electrons cannot circulate in the z direction because they are confined in the potential well forming in the Oxy plane in the vicinity of the heterojunction 15. The electron gas 9, confined in what is called the channel of the transistor, is therefore capable of carrying a current IDS circulating between the drain and the source. Conventionally, a potential difference VDS is applied between the source S and the drain D, with typically a source S at ground, and the value of the current IDS is a function of the applied voltage VGS between the gate G and the source S.

[0012] The transistor effect is based on the modulation of the conductance gm between the contacts S and D by the electrostatic action of the control electrode G. The variation of this conductance is proportional to the number of free carriers in the channel, and therefore to the current between source and drain. It is the transistor amplification effect which makes it possible to transform a weak signal applied to the gate into a stronger signal recovered on the drain.

[0013] In order for GaN technology components to operate at frequencies millimeter wave (> 20 GHz) with sufficient performance, it is necessary to modify a number of parameters defining the transistor. Among these modifications, those having a primary importance are:

[0014] The reduction in the thickness of the barrier 13 which, by bringing the gate closer to the electron channel, makes it possible to improve the gain of the transistor.

[0015] Increasing the number of carriers in structures to reduce access resistances.

[0016] Reducing the gate length of the transistors which makes it possible to reduce the transit time of the electrons under the gate. This latter option may require optimization of the buffer layer 12 in order to maintain good confinement of the electrons in the channel.

[0017] However, some of its modifications, in particular the increase in the carrier density in the ns channel and the reduction in the thickness of the barrier 13, contribute to increasing the value of the electric field in the structure when the transistor is in operation. This increase in the electric field is particularly pronounced for InAl(Ga)N / GaN or AIN transistor dies for which the electron density in the ns channel is in the range 1.2xl013 / cm2 to 2xl013 / cm2. This results in a reduced robustness of this die.

[0018] The particularly intense electric field in these materials can locally reach an intensity greater than 10 MV / cm. The maximum electric field is located at the foot of the gate, typically in the gate-drain space.

[0019] Due to the absence of large GaN substrates (greater than 3”), it is necessary to grow the semiconductor materials on host substrates such as Al2O3, SiC or silicon. However, the latter have a different lattice parameter than GaN, which generates a high density of defects oriented perpendicular to the current flowing in the channel.

[0020] These defects cross the entire structure and the typical density of emerging surface defects is of the order of some 108 to some 109 / cm2. [Fig.2] illustrates one of these dislocations 20 located at the foot of the gate in an xz section plane. These defects constitute points of weakness of the transistor which, under the action of a high electric field and stresses induced by the inverse piezoelectric effect, will be at the origin of a degradation of the performances (increase of the gate current in particular) or even of a failure of the components. This zone of intense electric field has been identified in the literature as impacting the reliability of the devices (see for example the publication “Correlation between Physical Defects and Performance in AlGaN / GaN High Electron Mobility Transistor Devices”, DOI: 10.4313 / TEEM.2010.11.2.049).

[0021] The electric field in the structure being proportional to the voltages applied to the transistor, one solution would be to reduce these, in particular the drain voltage Vds. This would however be to the detriment of the added power efficiency (PAE) and the power available at the transistor output.

[0022] Furthermore, according to the state of the art, the face 14 is covered with a dielectric layer, called a passivation layer, because the upper face 14 of the barrier layer 13 must be protected from contact with the outside to protect the surface from external aggressions (humidity, impurities) and to stabilize / neutralize the surface states present on the surface of the semiconductor. Conventionally, the dielectric materials used are: A12O3, Si3N4, SiO2, SiOxNy or AIN. They have dielectric constants between 3.7 (SiO2) and 10 (A12O3).

[0023] Document US9099433 describes a HEMT transistor with a T-gate comprising two passivation layers. A first passivation layer is deposited on surface 14 between the gate and the source and between the gate and the drain, and has a conventional passivation function. A second passivation layer coats the gate and covers the first layer.

[0024] Patent US9099433 proposes a solution for optimizing RF performance by reducing the Cgd and Cgs capacitances without degrading leakage currents and electrical performance in pulsed mode (drain lag and gate lag) which are linked to the electric field.

[0025] To reduce the capacitances Cgd and Cgs, the branches of the T of the gate are moved away from the surface of the component. In doing so, the electric field within the transistor increases, which leads to an increase in leakage currents and a degradation of electrical performance in pulsed mode.

[0026] To maintain the effect on the electric field of the Cgd and Cgs capacitances while not degrading (or at least minimally) the RF performances, a dielectric material is deposited locally, as close as possible to the gate foot, where the electric field is the most intense. MIS capacitances are thus added locally that are sufficiently small compared to Cgd and Cgs. This approach makes it possible to maintain the reduction effect on the electric field while limiting the impact on the Cgd and Cgs capacitances and therefore on the RF performances. This second layer is made of a standard dielectric material as listed above.

[0027] This second layer makes it possible to partially resolve the problem of high electric field but is of limited effectiveness by the choice of dielectric materials with dielectric constants which must not be too high (<= 10), because they are present throughout the transistor, so as not to degrade RF performance.

[0028] The invention aims to overcome at least one of the aforementioned drawbacks by proposing a HEMT transistor having two passivation layers configured so as to reduce the value of the electric field at the gate foot. DESCRIPTION OF THE INVENTION

[0029] The present invention relates to a high mobility field effect transistor comprising: • a stack along a z axis deposited on a substrate and comprising: • a buffer layer comprising a first semiconductor material comprising a binary or ternary or quaternary nitride compound and having a first band gap, • a barrier layer comprising a second semiconductor material comprising a binary or ternary or quaternary nitride compound and having a second band gap, the second band gap being greater than the first band gap, • a heterojunction between said buffer layer and said barrier layer and, • a two-dimensional gas of electrons located in an xy plane perpendicular to the z axis and in the vicinity of the heterojunction, • a drain, a source, and a grid arranged on an upper face of said barrier layer between the source and the drain, • the grid having a shape comprising a trunk topped by at least one cap, a base of the trunk in contact with said barrier layer being called the grid base, • the upper face of the barrier layer between the source and the drain having a first zone located from the gate foot and extending over a distance of at most 100 nm on either side of the gate, and a second zone located on the remaining part of the upper face, • a first passivation layer having a first dielectric constant greater than or equal to 15 and extending over at least the first zone, the first passivation layer being in direct contact with the barrier layer only over the first zone, • a second passivation layer having a second dielectric constant less than or equal to 10 and extending over at least the second zone, the second passivation layer being in direct contact with the barrier layer only over the second zone.

[0030] According to one embodiment, the second passivation layer is configured to at least partially cover the first passivation layer.

[0031] According to one embodiment, the first passivation layer is configured to at least partially cover the second passivation layer.

[0032] According to one embodiment, the first passivation layer is further configured to cover the trunk of the grid.

[0033] According to one embodiment, the first passivation layer is furthermore configured to coat the grid.

[0034] According to one embodiment, the first passivation layer is delimited by the projection along Z of said cap.

[0035] According to one embodiment, the first passivation layer extends at most over half of a distance between the gate and the source and over half of a distance between the gate and the drain.

[0036] According to one embodiment, the first passivation layer comprises a material chosen from: Y2O3, ZrO2, HfO2, La2O5, TiO2, Pr2O3, La2O3, SrTiO3, BaTiO3.

[0037] Another aspect of the invention relates to a method of producing a high mobility field effect transistor comprising: • a step of producing a stack along a z axis deposited on a substrate, the stack comprising: • a buffer layer comprising a first semiconductor material comprising a binary or ternary or quaternary nitride compound and having a first band gap, • a barrier layer comprising a second semiconductor material comprising a binary or ternary or quaternary nitride compound and having a second band gap, the second band gap being greater than the first band gap, • a heterojunction between said buffer layer and said layer barrier and, • a two-dimensional gas of electrons located in an xy plane perpendicular to the z axis and in the vicinity of the heterojunction, then a step of producing a drain, a source, and a grid arranged on an upper face of said barrier layer between the source and the drain, and such that the grid has a shape comprising a trunk overhung by at least one cap, a base of the trunk in contact with said barrier layer being called a grid foot, the upper face of the barrier layer between the source and the drain having a first zone located from the gate foot and on either side of the gate over a distance of at most 100 nm, and a second zone located on the remaining part of the upper face, a step of depositing a first passivation layer having a dielectric constant greater than or equal to 15, said deposition being carried out so that the first passivation layer extends over at least the first zone, the first passivation layer being in direct contact with the barrier layer only over the first zone, • a step of depositing a second passivation layer having a dielectric constant less than or equal to 10, said deposition being carried out so that the second passivation layer extends over at least the second zone, the second passivation layer being in direct contact with the barrier layer only over the second zone.

[0038] According to one embodiment, the step of depositing the first passivation layer takes place before the step of depositing the second passivation layer, said second passivation layer then at least partially covering the first passivation layer.

[0039] According to one embodiment, the step of depositing the second passivation layer takes place before the step of depositing the first passivation layer, said first passivation layer then partially covering the second passivation layer.

[0040] According to one embodiment, the step of depositing the first passivation layer comprises a sub-step of etching through said gate cap, the first passivation layer then being delimited by the projection along Z of said cap.

[0041] The following description presents several exemplary embodiments of the device of the invention. These examples are not limiting of the scope of the invention. These exemplary embodiments present both the essential characteristics of the invention as well as additional characteristics linked to the embodiments considered.

[0042] The invention will be better understood and other characteristics, aims and advantages thereof will appear during the detailed description which follows and with reference to the appended drawings given as non-limiting examples and in which:

[0043] The [Fig. 1] already cited illustrates a high mobility field effect transistor according to the state of the art.

[0044] The [Fig.2] already cited illustrates a dislocation located at the foot of the grid.

[0045] [Fig.3] illustrates the first variant of a HEMT transistor according to the invention in which the first passivation layer is deposited first.

[0046] [Fig.4] illustrates the second variant of a HEMT transistor according to the invention in which the second passivation layer is deposited first.

[0047] [Fig.5] illustrates an embodiment of a HEMT transistor according to the invention for which the first passivation layer coats the entire gate.

[0048] [Fig.6] illustrates an embodiment of the first variant of a HEMT transistor according to the invention for which the first passivation layer is delimited by the projection along Z of the gate cap.

[0049] [Fig.7] illustrates an embodiment of the second variant of a HEMT transistor according to the invention for which the first passivation layer is delimited by the projection along Z of the gate cap.

[0050] [Fig.8a] illustrates the first variant of a transistor according to the invention with the option of a first passivation layer which coats the entire gate and which is deposited using the gate cap as a mask.

[0051] [Fig.8b] illustrates the second variant of a transistor according to the invention with the option of a first passivation layer which coats the entire gate and which is deposited using the gate cap as a mask.

[0052] [Fig.9] illustrates the value of the electric field Fz(B) as a function of x for three different values ​​7, 15 and 30 of the dielectric constant of the first passivation layer.

[0053] [Fig. 10] illustrates the value of the electric field Fx(ch) as a function of x for three different values ​​7, 15 and 30 of the dielectric constant of the first passivation layer.

[0054] [Fig. 11] illustrates the value of the electric field modulus IF(D)I as a function of x for three different values ​​7, 15 and 30 of the dielectric constant of the first passivation layer.

[0055] [Fig. 12] illustrates the gain of a transistor according to the invention as a function of the frequency of use for a deposition of the first passivation layer located over the entire surface, at 100 nm on either side of the gate or at 25 nm on either side of the gate. DETAILED DESCRIPTION OF THE INVENTION

[0056] The invention relates to a HEMT transistor 10 having a stack, a gate, a source and a drain as described [Fig.l].

[0057] An example of sizing the gate for a high frequency application (frequency of use greater than 10 GHz, typically between 10 and 80 GHz) is a trunk 16 with a width between 40 and 250 nm, a drain-side branch with a dimension Bd between 0 and 150 nm, and a source-side branch with a dimension Bs between 0 and 300 nm.

[0058] We call dGs the distance between the gate and the source and dGD the distance between the gate and the drain. For a high frequency application, dGS is typically between 0.5 and 2 pm and dGD is typically between 1 and 4 pm.

[0059] The specificity of the HEMT 10 according to the invention is that it has a particular arrangement of two passivation layers PLhi and PLlow as illustrated in figures 3 and 4, the passivation layer PLhi having a specific characteristic as explained later.

[0060] For high frequency applications (typically > 20 GHz), the barrier layer 13 comprises a material chosen from: InAIN, AlGaN, InAlGaN, AIN. These different materials are currently conventionally used for the production of components GaN at high frequencies.

[0061] The upper surface 14 of the barrier layer 13 between the source S and the drain D is decomposed into a first zone ZI located from the gate foot 18s, 18d, and on either side of the gate G over a distance of at most 100 nm on each side of the gate foot, and a second zone Z2 located on the remaining part of the upper face 14 between the gate and the source and between the gate and the drain.

[0062] The transistor 10 according to the invention comprises a first passivation layer PLhi which has a dielectric constant ehi greater than or equal to 15. This high value of the dielectric constant is counter-intuitive as explained later. The part of PLhi in direct contact with the upper face extends only over the zone ZI. The zone ZI on the source side is not necessarily of the same dimension as the zone ZI on the drain side.

[0063] The transistor 10 also comprises a second passivation layer PLlow having a dielectric constant eiow less than or equal to 10. The part of PLlow in direct contact with the barrier layer extends only over the second zone Z2. This second passivation layer has a standard thickness (typically 10-50 nm), and a dielectric constant less than 10 corresponds to the case of a usual passivation layer in this type of transistor.

[0064] The barrier layer 13 is thus in direct contact with a PLhi passivation layer with a high dielectric constant at the foot of the gate (over at most 100 nm) and in direct contact with a PLlow passivation layer with a low dielectric constant on the rest of its surface.

[0065] The manufacturing technology allows two arrangements constituting two variants of the transistor 10.

[0066] [Fig. 3] illustrates the first variant in which the PLhi layer is deposited first. The portion of the PLhi layer in contact with face 14 (zone Z1) then constitutes the entirety of the PLhi layer extending along the xy plane. The PLlow layer deposited after the PLhi layer has a portion in contact with face 14 extending over region Z2 and a portion which at least partially covers the first PLhi passivation layer. Whether the PLlow layer extends to the gate foot (over PLhi) or not depends on the manufacturing technology. Typically the gate cap creates shadowing during deposition, and the PLlow layer decreases in thickness from the projection along z of the cap, as illustrated in Figures 3 and 4. The distance between the gate and the source is called dGS and the distance between the gate and the drain is called dGD.

[0067] [Fig.4] illustrates the second variant in which the PLlow layer is deposited first. The PLlow layer is deposited so as to leave an area Z1 without a layer. The part of the PLlow layer in contact with the face 14 (area Z2) then constitutes the entirety of the PLlow layer extending along the xy plane. The PLhi layer, deposited after PLlow, has a part in contact with the face 14 which extends along ZI and another part which at least partially covers the PLlow layer.

[0068] Depending on the deposition technology of the PLhi layer, the first passivation layer can, according to a first option, cover the trunk 16 of the grid G, or according to a second option, coat the entire grid, as illustrated [Fig. 5]. These options are of course compatible with all the aforementioned variants and embodiments.

[0069] According to an embodiment which presents ease of technological implementation, the extent of the first passivation layer PLhi is delimited by the projection along Z of the grid cap 17, as illustrated [Fig.6] for the first variant and [Fig.7] for the second variant.

[0070] Using numerous simulations and experiments, the inventors have demonstrated that the use of a PLhi passivation layer with a high dielectric constant compared to the use of a layer with a lower dielectric constant, for example 7 for a Si3N4 layer, makes it possible to significantly reduce the electric field in the vicinity of the gate foot (see below). The reduction effect is particularly notable when ehi is greater than or equal to 15. Typically ehi is in the range 15-200. The reduction of the electric field at the gate foot makes it possible to relax the mechanical stresses induced by the inverse piezoelectric effect to acceptable values ​​for the target operating voltages. An example of these voltages is: Vds_max = 40 V and Vgs_max = -9V

[0071] In order not to degrade the power gain of the transistor, the PLhi layer is located in the vicinity of the gate foot when it is in direct contact with the barrier layer 13 (zone ZI extending over a maximum of 100 nm). The second passivation layer PLlow covers the remainder of the face 14 (zone Z2) in order to passivate the entire face 14.

[0072] Thus, locating the first passivation makes it possible to use materials with higher relative permittivity (so-called High-K materials) and to considerably improve voltage resistance without degrading RF performance (optimally, up to 30-40% reduction in the electric field is obtained compared to at best 10% for patent US9099433).

[0073] Typically the first passivation layer is made of a material chosen from: Y2 O3, ZrO2, HfO2, Ta2O5, TiO2, La2O3, Pr2O3, SrTiO3, BaTiO3.

[0074] These materials with high dielectric constant are not conventionally used for the passivation of high-frequency HEMT transistors: the presence of a dielectric layer with high dielectric constant at the gate foot is counter-intuitive. Indeed, for high-frequency applications, we seek to reduce the Cgs and Cgd capacitances as much as possible, therefore using passivations with the lowest possible dielectric constants.

[0075] The choice of the PLhi dielectric material depends on the maximum voltages seen by the transistor and the electron density ns in the channel. Thus, the higher the operating voltages and the electron density in the channel, the higher the dielectric constant of the material must be to reduce the intensity of the electric field in the barrier and relax the stresses induced by the inverse piezoelectric effect, which is the cause of some of the degradation of the power components.

[0076] The thickness of the PLhi layer is delimited for its low value by obtaining an effect on the electric fields and for its high value by the degradations which appear on the RF performances of the transistor. For a localized PLhi layer, the critical high value for the RF performances is all the higher as the extension of the zone ZI is low.

[0077] [Fig.8a] illustrates the transistor 10 according to the invention of the first variant (PLhi layer deposited first) with the option of a PLhi layer which coats the entire gate and which is deposited using the gate cap as a mask.

[0078] [Fig.8b] illustrates the transistor 10 according to the invention of the second variant (PLlow layer deposited first) with the option of a PLhi layer which coats the entire gate and which is deposited using the gate cap as a mask. The PLlow layer is only deposited on a zone Z2 and leaves a zone Z1 free so that PLhi deposited after is in direct contact with the barrier layer 13.

[0079] In [Fig.8b] are also illustrated the different electric fields of interest in the vicinity of the gate foot: the field Fz(B) is the projection along z of the electric field in the barrier layer close to the surface 14; the term | F(D) | is the modulus of the electric field in the part of the PLhi layer in contact with the barrier layer; the field Fx(ch) is the projection along x of the electric field in the channel 9 located in the buffer layer 12 close to the interface 15.

[0080] Preferably as illustrated in figures 8b the space between the Source and the Drain is filled with a BCB type material to avoid any contact with air.

[0081] Figures 9, 10 and 11 illustrate the values ​​of the electric fields Fz(B), Fx(ch) and IF(D)I (modulus of the electric field) respectively as a function of x (drain side), the value of x corresponding to the gate foot (18s source side, 18d drain side) being indicated in the figures. It is on the drain side that the electric field at the gate foot is the largest, the field on the source side is lower than the field on the drain side. In Figures 9 and 10 the origin of the x is the source S, and in [Fig. 11] the origin of the x is the gate foot 18d and the electric field is plotted between 4 angstroms and 100 m from this origin.

[0082] The curves in solid lines 91, 101, 111 correspond to a value of the dielectric constant of the first passivation layer PLhi equal to 7 (classical case of Si3N 4), the curves in long dotted lines 92, 102, 112 to a value of ehi of 15 and the curves dotted 93, 103 and 113 at a value of 30 (e.g. TiO2 or Ta2O5).

[0083] The simulations of a GaN HEMT according to the invention for an InAlGaN / AlN / GaN type structure of figures 9 to 11 were carried out using the Silvaco software, with:

[0084] - a configuration of type [Fig.8a] PLhi extends along ZI and around the grid

[0085] - dGS = 0.8 pm; dGD = 1.6 pm;

[0086] -Grid: trunk width 16: 150 nm; branch dimension: 150 nm on each side,

[0087] - an electron density in the channel ns = 1.6.1013 / cm2, a voltage Vds = 40V; a voltage Vgs = -9V (most stressful conditions for the transistor);

[0088] - extension of ZI of 100 nm on each side of the gate foot; a thickness of the PLhi layer ehi = 30 nm;

[0089] -Eiow = 7 eiow = 30 nm;

[0090] These three figures show a very significant decrease in the values ​​of the three electric fields in the vicinity of the gate foot 18d when the value of the dielectric constant of PLhi increases. The field Fz(B) decreases from a value of almost 21 MV / cm for ehi=7 to a value of 15 MV / cm for ehi=15. Similarly, Fx(ch) decreases from a value of 5 MV / cm for ehi=7 to a value of 3.8 MV / cm for ehi=15. The modulus of F(D) decreases from almost 21 MV / cm for ehi=7 to a value of 12 MV / cm for ehi=15. These lower values ​​of the electric fields of 30 to 40% make the transistor much less sensitive to local dislocations and relax the stresses induced by the inverse piezoelectric effect.

[0091] [Fig. 12] illustrates the Gain or MAG (“Max Available Gain”) of the transistor according to the invention as a function of the frequency of use, for the following configuration:

[0092] - a configuration of type [Fig.8a] PLhi extends along ZI and around the grid

[0093] - dGS = 0.8 pm; dGD = 1.6 pm;

[0094] -Grid: trunk width 16: 100 nm; branch dimension: 150 nm on each side.

[0095] -ns = 1.6 1013 / cm2; Vds=20V; Ids = 150 mA / mm (corresponds to a class AB operating situation).

[0096] ehi = 30 and ehi = 30 nm

[0097] eiow = 7 and eiow = 30 nm

[0098] Curve 6 illustrates the case for which PLhi extends over the entire surface (does not correspond to the invention), curve 7 illustrates the case of a PLhi deposition with ZI extending 100 nm on either side of the gate, and layer 8 illustrates the case of a PLhi deposition located over 25 nm on either side of the gate.

[0099] We see with curve 6 (extension of PLhi over the entire surface) that the gain of the transistor is degraded: the extension of the zone ZI is limited by maintaining a gain of the acceptable transistor, and too large a ZI area is not desirable.

[0100] For 25 nm of extension (curve 8) the performances are better than for 100 nm (curve 7), and we consider that 100 nm is therefore an upper limit for the extension of Zl. Beyond this, the losses on the gain are considered too important. Thus the maximum value of the extension of Zl is given by the acceptable reduction in performances on the gain of the transistor.

[0101] The minimum value of the extension of Zl at the foot of the grid is that which allows obtaining a significant effect on the reduction of the electric field evaluated by simulation at 1 nm.

[0102] According to another aspect, the invention relates to a method for producing a high mobility field effect transistor comprising a step of producing a stack 10 along a z axis deposited on a substrate, the stack comprising a buffer layer 12, a barrier layer 13, a heterojunction 15 between said buffer layer 12 and said barrier layer 13 and a two-dimensional electron gas 9 as described previously.

[0103] The method also comprises a step of producing a drain D, a source S, and a gate G arranged on the upper face 14 of the barrier layer 13 between the source and the drain, and such that the gate G has a shape comprising a trunk 16 overhung by at least one cap 17, the base of the trunk in contact with the barrier layer being called the gate foot, with 18s corresponding to the gate foot on the source side and 18d corresponding to the gate foot on the drain side. The upper face 14 of the barrier layer between the source and the drain has a first zone Zl located from the gate foot and on either side of the gate over a distance of at most 100 nm, and a second zone Z2 located on the remaining part of the upper face.

[0104] The method also comprises a step of depositing a first passivation layer PLhi having a first dielectric constant greater than or equal to 15, the deposition being carried out so that the first passivation layer extends over at least the first zone Zl, the first passivation layer PLhi being in direct contact with the barrier layer 13 only on the first zone ZL

[0105] The method also comprises a step of depositing a second passivation layer PLlow having a dielectric constant eiow less than or equal to 10, the deposition being carried out so that the second passivation layer extends over at least the second zone Z2, the second passivation layer being in direct contact with the barrier layer 13 only over the second zone Z2.

[0106] According to a first variant, the step of depositing the first passivation layer takes place before the step of depositing the second passivation layer, the second passivation layer then at least partially covering the first passivation layer.

[0107] According to a second variant, the step of depositing the second passivation layer takes place before the step of depositing the first passivation layer, the first passivation layer then partially covering the second passivation layer.

[0108] According to an embodiment compatible with the two variants, the step of depositing the first passivation layer comprises a sub-step of etching through said gate cap, the first passivation layer (PLhi) then being delimited by the projection along Z of said cap.

[0109] According to one embodiment, the step of depositing the first PLhi passivation layer is carried out by plasma atomic deposition called PE-ALD for “Plasma Enhanced-Atomic Layer Deposition” in English.

[0110] ALD deposition is a technique that allows the deposit of ultra-thin films of a few nm thickness in a controlled manner. This technique offers excellent control over the thickness and uniformity of the deposited layer and also allows conformal deposition on 3D structures with high aspect ratios. Plasma allows these depositions to be carried out at lower temperatures.

[0111] This first layer can also be produced by PECVD (Plasma Enhanced Chemical Vapor Deposition), PVD (Plasma Vapor Deposition), ALD (Atomic Layer Deposition), HWCVD (Hot Wire Chemical Vapor Deposition), CAT-CVD (catalytic Chemical Vapor Deposition), ECR-CVD (Electron-Cyclotron Resonance Chemical Vapor Deposition), ICP-CVD (Inductively Coupled Plasma Chemical Vapor Deposition), by evaporation, sputtering or any other known deposition technique.

[0112] According to one embodiment, the step of depositing the second PLlow passivation layer is carried out by ICP CVD (for “Inductively Coupled Plasma Chemical Vapor Deposition” in English).

[0113] This deposition technique makes it possible to produce dielectric films (typically SiO2, Si3N4, SiON) of very good quality, at low temperature (from 5°C) without damaging the surface on which these films are deposited.

[0114] This second layer can also be produced by LPCVD (Low-Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PVD (Plasma Vapor Deposition), ALD (Atomic Layer Deposition), PEALD (Plasma Enhanced Atomic Layer Deposition), ICP-CVD (Inductively Coupled Plasma Chemical Vapor Deposition), by evaporation, sputtering or any other known deposition technique.

Claims

Claims

1. A high mobility field effect transistor comprising: - a stack (10) along a z axis deposited on a substrate (11) and comprising: • a buffer layer (12) comprising a first semiconductor material comprising a binary or ternary or quaternary nitride compound and having a first forbidden band, • a barrier layer (13) comprising a second semiconductor material comprising a binary or ternary or quaternary nitride compound and having a second forbidden band, the second forbidden band being greater than the first forbidden band, • a heterojunction (15) between said buffer layer (12) and said barrier layer (13) and, • a two-dimensional electron gas (9) located in an xy plane perpendicular to the z axis and in the vicinity of the heterojunction (15), - a drain (D), a source (S), and a gate (G) arranged on an upper face (14) of said barrier layer (13) between the source and the drain, the grid (G) having a shape comprising a trunk (16) overhung by at least one cap (17), a base of the trunk in contact with said barrier layer being called the gate foot (18s, 18g), the upper face (14) of the barrier layer between the source and the drain having a first zone (Zl) located from the gate foot and extending over a distance of at most 100 nm on either side of the grid, and a second zone (Z2) located on the remaining part of the upper face, a first passivation layer (PLhi) having a first dielectric constant (ehi) greater than or equal to 15 and extending over at least the first zone (Zl), the first passivation layer (PLhi) being in direct contact with the barrier layer (13) only on the first zone (Zl), - a second passivation layer (PLlow) having a second dielectric constant (eiow) less than or equal to 10 and extending over at least the second zone (Z2), the second passivation layer being in direct contact with the barrier layer (13) only on the second zone (Z2).

2. Transistor according to the preceding claim in which the second passivation layer (PLlow) is configured to at least partially cover the first passivation layer (PLhi).

3. Transistor according to claim 1 wherein the first passivation layer (PLhi) is configured to at least partially cover the second passivation layer (PLlow).

4. Transistor according to one of the preceding claims wherein the first passivation layer is further configured to cover the trunk of the gate.

5. Transistor according to one of the preceding claims wherein the first passivation layer is further configured to coat the gate.

6. Transistor according to one of the preceding claims in which the first passivation layer (PLhi) is delimited by the projection along Z of said cap.

7. Transistor according to one of the preceding claims in which the first passivation layer extends at most over half of a distance between the gate and the source (dGs) and over half of a distance between the gate and the drain (dGD).

8. Transistor according to one of the preceding claims in which the first passivation layer comprises a material chosen from: Y2 O3, ZrO2, HfO2, La2O5, TiO2, Pr2O3, La2O3, SrTiO3, BaTiO3.

9. Method for producing a high mobility field effect transistor comprising: - a step of producing a stack (10) along a z axis deposited on a substrate (11), the stack comprising: a buffer layer (12) comprising a first material semiconductor comprising a binary or ternary or quaternary nitride compound and having a first forbidden band, • a barrier layer (13) comprising a second semiconductor material comprising a binary or ternary or quaternary nitride compound and having a second forbidden band, the second forbidden band being greater than the first forbidden band, • a heterojunction (15) between said buffer layer (12) and said barrier layer (13) and, • a two-dimensional gas of electrons (9) located in an xy plane perpendicular to the z axis and in the vicinity of the heterojunction (15), then - a step of producing a drain (D), a source (S), and a grid (G) arranged on an upper face (14) of said barrier layer (13) between the source and the drain, and so that the grid (G) has a shape comprising a trunk (16) overhung by at least one cap (17), a base of the trunk in contact with said barrier layer being called a grid foot (18s, 18d), the upper face (14) of the barrier layer between the source and the drain having a first zone (Zl) located from the gate foot and on either side of the gate over a distance of at most 100 nm, and a second zone (Z2) located on the remaining part of the upper face, - a step of depositing a first passivation layer (PLhi) having a dielectric constant (ehi) greater than or equal to 15, said deposition being carried out so that the first passivation layer extends over at least the first zone (Zl), the first passivation layer (PLhi) being in direct contact with the barrier layer (13) only over the first zone (Zl), - a step of depositing a second passivation layer (PLlow) having a dielectric constant (Eiow) less than or equal to 10, said deposit being carried out so that the second passivation layer extends over at least the second zone (Z2), the second passivation layer being in direct contact with the barrier layer (13) only over the second zone (Z2).

10. Method according to the preceding claim in which the step of depositing the first passivation layer takes place before the step of depositing the second passivation layer, said second passivation layer then at least partially covering the first passivation layer.

11. Method according to claim 9 in which the step of depositing the second passivation layer takes place before the step of depositing the first passivation layer, said first passivation layer then partially covering the second passivation layer.

12. Method according to one of claims 9 to 11 in which the step of depositing the first passivation layer comprises a sub-step of etching through said gate cap, the first passivation layer (PLhi) then being delimited by the projection along Z of said cap.

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