Electronic device

Abstract

Electronic Device This description relates to a device (30) adapted to transmit and receive signals by means of a single antenna (12), comprising first (36), second (42), and third (48) windings, the first (36) and second (42) windings being coupled so as to transmit the signals to be emitted by the antenna (12), the first (36) and third (48) windings being coupled so as to transmit the signals received by the antenna (12), the device comprising first (32) and second (34) chips, the first chip (32) comprising the antenna (12) and the first winding (36), and the second chip (34) comprising one winding from the second (42) and third (48) windings, the first (32) and second (34) chips being attached to each other by molecular bonding. Figure for the abstract: Fig. 2

Description

Title of the invention: Electronic device technical field

[0001] This description relates generally to electronic devices and more specifically to transmitting / receiving devices. Previous technique

[0002] In the field of wireless communication, there are several modes of operation allowing reciprocal communication between two elements capable of transmitting and receiving signals.

[0003] Duplex or "Full Duplex" mode is an operating mode in which both circuits can send signals simultaneously. Thus, it is possible to transmit and receive signals at the same time.

[0004] Time division duplex mode is an operating mode in which the transmission and reception of data take place on the same frequency band, with the signals being transmitted successively.

[0005] Frequency division duplex mode is an operating mode in which data transmission and reception occur simultaneously on two different frequency bands. In other words, the signal carrier frequency differs depending on the direction of transmission.

[0006] The different operating modes face various problems. One problem is the isolation between the receiving and transmitting parts. Summary of the invention

[0007] One embodiment overcomes all or part of the drawbacks of known electronic transmitting / receiving devices.

[0008] An embodiment provides a device adapted to transmit and receive signals by the same antenna, comprising first, second and third windings, the first and second windings being coupled so as to transmit the signals to be transmitted by the antenna, the first and third windings being coupled so as to transmit the signals received by the antenna, the device comprising first and second chips, the first chip comprising the antenna and the first winding, and the second chip comprising a winding among the second and third windings, the first and second chips being fixed to each other by molecular bonding.

[0009] According to one embodiment, the first winding is connected between the antenna and a node for applying a reference voltage, the second winding is connected between two terminals of a first circuit configured to generate a signal to be transmitted, the third winding being connected between two terminals of a second circuit configured to process a received signal.

[0010] According to one embodiment, each first or second chip comprises a semiconductor substrate and an interconnection network comprising a stack of insulating layers including conductive tracks and conductive vias, each interconnection network comprising a first layer, the first layer of each interconnection network being furthest from the substrate of said chip, the first and second chips being fixed to each other by the first layers of each interconnection network.

[0011] According to one embodiment, the first winding comprises a first conductive track in a second layer of the intersection network of the first chip, the first track being separated from the second chip only by insulating material.

[0012] According to one embodiment, the second winding comprises a second conductive track in a third layer of the intersection network of the second chip, the second track being separated from the first chip only by insulating material.

[0013] According to one embodiment, the third winding comprises a third conductive track in a fourth layer of the intersection network of the first chip, the third track being separated from the first track by insulating material, the third track being located between the first track and the substrate of the first chip.

[0014] According to one embodiment, the third winding comprises a third conductive track in a fifth layer of the intersection network of the second chip, the third track being separated from the first chip by insulating material.

[0015] According to one embodiment, the third winding comprises a second conductive track in a third layer of the intersection network of the second chip, the second track being separated from the first chip only by insulating material.

[0016] According to one embodiment, the second winding includes a third conductive track in a fourth layer of the intersection network of the first chip, the third track being separated from the first track by insulating material, the third track being located between the first track and the substrate of the first chip.

[0017] According to one embodiment, the second winding includes a third conductive track in a fifth layer of the intersection network of the second chip, the third track being separated from the first chip by insulating material.

[0018] According to one embodiment, the second and third tracks are located in the same third layer of the interconnection network of the second chip.

[0019] According to one embodiment, the device is configured to operate in time-division duplex mode or frequency-division duplex mode.

[0020] According to one embodiment, molecular bonding is a metal-to-metal bond or a oxide / oxide bonding.

[0021] Another embodiment provides for a method of manufacturing a device adapted to transmit and receive signals by the same antenna, the device comprising first, second and third windings, the first and second windings being coupled so as to transmit the signals to be transmitted by the antenna, the first and third windings being coupled so as to transmit the signals received by the antenna, the method comprising the formation of first and second chips, the first chip comprising the antenna and the first winding, and the second chip comprising a winding from among the second and third windings, the method further comprising the fixing of the first and second chips to each other by molecular bonding.

[0022] According to one embodiment, the manufacturing process described above is applied to the manufacture of a device as described above. Brief description of the drawings

[0023] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0024] [Fig.1] represents an example of a transmission / reception device;

[0025] [Fig.2] schematically represents an embodiment of a transmission and reception device;

[0026] [Fig.3] schematically represents the implementation of the embodiment of [Fig.2];

[0027] Figure 4 schematically represents another embodiment of a transmitting and receiving device; and

[0028] Figure 5 schematically represents the implementation of the embodiment of Figure 4. Description of embodiments

[0029] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0030] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular,...

[0031] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without any intermediate elements other than conductors, and when referring to two coupled elements, this means that these two elements can be connected or linked by through one or more other elements.

[0032] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0033] Unless otherwise specified, the expressions "approximately", "about", "meaning" "Suitably" and "of the order of" mean to within 10%, preferably to within 5%.

[0034] Fig. 1 represents an example of a transmitting / receiving device 10. The device 10 is configured, for example, to operate in frequency division duplex mode or in time division duplex mode.

[0035] Device 10 is, for example, part of a transmit / receive system. This system comprises device 10 and another transmit / receive device (not shown). The other device is configured to transmit and receive signals. The other device is configured to operate in the same mode as device 10. Device 10 and the other device are configured to be able to communicate wirelessly with each other.

[0036] The device 10 includes an antenna 12, for example a single antenna 12. The antenna 12 is configured to transmit and receive signals.

[0037] The device 10 includes, for example, a switching circuit 14. The circuit 14 includes, for example, a main terminal 16 and two secondary terminals 18, 20. The circuit 14 is configured to connect the terminal 16 to either of the terminals 18, 20. The circuit 14 is controlled by a CTRL control signal, for example, a binary signal. The CTRL signal determines whether terminal 16 is connected to terminal 18 or to terminal 14. The CTRL signal determines whether device 10 is in a transmit mode, that is, a mode in which a signal is supplied to the antenna to be transmitted, or in a receive mode, in which a signal is received by the antenna and supplied by the antenna to the rest of device 10. Thus, the CTRL signal can take a first value indicating that the device is in transmit mode and that circuit 14 connects terminals 16 and 18, or a second value indicating that the device is in receive mode and that circuit 14 connects terminals 16 and 20.

[0038] The switching circuit 14, and more specifically terminal 16, is connected, preferably connected, to the antenna 12. The switching circuit 14, and more specifically terminal 18, is connected, preferably connected, to a node 22, on which a TX signal to be transmitted is provided, by a balun 24. The switching circuit 14, and more specifically terminal 20, is connected, preferably connected, to a node 26, on which an RX signal received by the antenna 12 is obtained, by a balun 28.

[0039] The balun 24 comprises two windings, or coils, a first winding 24a and a second winding 24b. One end of winding 24a is connected, preferably connected, to terminal 18. One end of winding 24b is connected, preferably connected, to node 22. Windings 24a and 24b are magnetically coupled to allow transmission between antenna 12 and the rest of device 10. Similarly, balun 28 comprises two windings, a first winding 28a and a second winding 28b. One end of winding 28a is connected, preferably connected, to terminal 20. One end of winding 28b is connected, preferably connected, to node 26. Windings 28a and 28b are magnetically coupled to allow transmission between antenna 12 and the rest of device 10.

[0040] There is a need to ensure separation between the transmitting branch, including terminal 18, circuit, or balun, 24 and node 22, and the receiving branch, including terminal 20, circuit, or balun, 28 and node 26, so as to avoid power leaks which could increase consumption and disrupt transmissions.

[0041] Figure 2 schematically represents an embodiment of a transmitting / receiving device 30. The device 30 is configured to operate in frequency-division duplex mode or time-division duplex mode. The device 30 comprises elements of the device 10 of Figure 1.

[0042] The device 30 comprises a first chip 32 and a second chip 34. The chip 32 preferably comprises a transmitting branch of the device 30 in its entirety. The chip 34 comprises at least part of a receiving branch of the device 30.

[0043] The chip 32 includes the antenna 12. The chip 32 further includes a winding 36. The winding 36 includes one end connected, preferably connected, to the antenna 12 and another end connected, preferably connected, to a reference node 38, for example ground.

[0044] The chip 32 includes a transmission circuit 40. The circuit 40 is configured to generate the signals to be emitted by the antenna 12.

[0045] The chip 32 further includes a winding 42. The winding is connected between two terminals 40a, 40b of the circuit 40. Thus, the winding 40 includes a first end connected, preferably connected, to a terminal 40a of the circuit 40 and a second end connected, preferably connected, to another terminal 40b of the circuit 40.

[0046] Windings 36 and 42 are magnetically coupled to form balun 24. Winding 36 then corresponds to winding 24a and winding 42 corresponds to winding 24b. Windings 36 and 42 are configured to be coupled with each other to allow the transmission of signals in a first range of frequencies, corresponding to the transmission frequencies.

[0047] Terminals 40a and 40b of circuit 40 are, for example, each connected to node 38 by a switch, for example a transistor. Thus, terminal 40a is, for example, connected, preferably connected, to one conduction terminal of a transistor 44, the other conduction terminal of transistor 44 being connected, preferably connected, to node 38. Terminal 40a is, for example, connected, preferably connected, to one conduction terminal of a transistor 46, the other conduction terminal of transistor 46 being connected, preferably connected, to node 38. Transistors 44 and 46 are, for example, controlled by a control circuit of device 30, for example located in chip 32.

[0048] The chip 34 includes a receiving circuit 46. The circuit 40 is configured to process the signals received by the antenna 12.

[0049] The chip 34 further includes a winding 48. The winding 48 is connected between two terminals 46a, 46b of the circuit 46. Thus, the winding 48 includes a first end connected, preferably connected, to a terminal 46a of the circuit 46 and a second end connected, preferably connected, to another terminal 46b of the circuit 46.

[0050] Windings 36 and 48 are magnetically coupled to form balun 28. Winding 36 then corresponds to winding 28a and winding 48 corresponds to winding 28b. Windings 36 and 48 are configured to be coupled with each other to allow the transmission of signals in a second frequency range, corresponding to the reception frequencies.

[0051] Terminals 46a and 46b of circuit 40 are, for example, each connected to node 38 by a switch, for example, a transistor. Thus, terminal 46a is, for example, connected, preferably connected, to one conduction terminal of a transistor 50, the other conduction terminal of transistor 50 being connected, preferably connected, to node 38. Terminal 46a is, for example, connected, preferably connected, to one conduction terminal of a transistor 52, the other conduction terminal of transistor 52 being connected, preferably connected, to node 38. Transistors 50 and 52 are, for example, controlled by a control circuit of the device 30, for example, located in the chip 34.

[0052] Switches 44, 46, 50, 52 are configured, for example, to allow device 30 to operate in time-division duplex mode.

[0053] Figure 3 schematically represents the implementation of the embodiment of Figure 2.

[0054] The device 30 comprises, in [Fig. 3], the chip 32 and the chip 34. Each chip 32, 34 comprises a substrate, for example a semiconductor substrate, in which electronic components, forming, for example, the circuits 40 and 46, can be formed. The chip 32 comprises a substrate 54 and the chip 34 comprises a substrate 56. In other words, the substrate 54 can comprise the electronic components of the circuit 40, preferably all the electronic components of circuit 40. The substrate 56 may include the electronic components of circuit 46, preferably all the electronic components of circuit 46.

[0055] In addition, each chip 32, 34 includes an interconnection network covering its substrate 54 or 56.

[0056] Thus, the chip 32 includes an interconnection network 58. The network 58 comprises a stack of a plurality of insulating layers 60. More precisely, the network 58 comprises an alternation of layers 60 comprising metallic tracks, or metallizations, 68 and layers 60 comprising conductive vias connecting the metallic tracks. The network 58 rests on a face 54a of the substrate 54, for example, on the entire face 54a of the substrate 54.

[0057] Similarly, the chip 34 includes an interconnection network 62. The network 62 comprises a stack of a plurality of insulating layers 60. More specifically, the network 62 comprises an alternation of layers 60 comprising metallic tracks, or metallizations, 78 and layers 60 comprising conductive vias connecting the metallic tracks. The network 62 rests on a face 56a of the substrate 56, for example, on the entire face 56a of the substrate 56.

[0058] The network 58 comprises a layer 66. The layer 66 is an insulating layer corresponding to a layer 60 of the network 58, comprising a metallization 68. The layer 66 is preferably separated from the substrate 54 by at least one layer 60.

[0059] A metallic track 68 is located in layer 66. The track 68 extends from an upper face of layer 66, i.e., the face in contact with the upper layer 60 in the lattice 58, to a lower face of layer 66, i.e., the face in contact with the lower layer 60 in the lattice 58. The metallic track 68 constitutes the winding 42 of [Fig. 2]. Thus, the length of the track 68 and its arrangement allow the winding 42 to be formed. For example, the track 68 forms a spiral in layer 66, with one end of the track 68 located outside the spiral and the other end of the track 68 located inside the spiral.

[0060] The network 58 comprises a layer 70. The layer 70 is an insulating layer corresponding to a layer 60 of the network 58, comprising a metallization 78.

[0061] A metallic track 72 is located in layer 70. The track 72 extends from an upper face of layer 70, i.e., the face in contact with the upper layer 60 in the lattice 58, to a lower face of layer 70, i.e., the face in contact with the lower layer 60 in the lattice 58. The metallic track 72 constitutes the winding 36 of [Fig. 2]. Thus, the length of the track 72 and its arrangement allow the winding 36 to be formed. For example, the track 72 forms a spiral in layer 70, with one end of the track 72 located outside the spiral and the other end of the track 72 located inside the spiral.

[0062] Track 72 is located at least partially opposite track 68. Layers 66 and 70, and more specifically tracks 68 and 72, are separated from each other by at least one layer 60. Preferably, the at least one layer 60 separating layers 66 and 70 does not include metallic tracks or conductive vias between tracks 68 and 72 or between the portions of layers 66 and 70 located between the portions of tracks 68 and 72.

[0063] The number and height of the layers 60 separating layers 66 and 70 are chosen so as to ensure that the tracks 68 and 72, forming the windings 36 and 42, are magnetically coupled and form a balun having the desired operating frequency range. For example, layers 66 and 70 are separated by a single layer 74 and a single layer 80. For example, layer 74 has a thickness between 1 nm and 1 mm and layer 80 has a thickness between 1 nm and 1 mm.

[0064] The network 58 comprises a layer 74. Layer 74 is an insulating layer covering layer 70. Layer 74 corresponds to the layer 60 furthest from the substrate 54 of the network 58. Layer 74 covers at least track 72, and preferably completely covers layer 70. Layer 74 corresponds, for example, to a single layer of the interconnecting network or to a single layer made of an insulating material different from the material of the layers 60. Alternatively, layer 74 comprises a plurality of insulating layers, including, for example, one or more layers 60 and / or one or more insulating layers made of one or more insulating materials different from the material of the layers 60.

[0065] Layer 74 is separated from layer 66 by layer 70. Layer 66 is located between layer 70 and substrate 54. Thus, the network 58 preferably comprises, in this order from face 54a of substrate 54, one or more layers 60 separating layer 66 from substrate 54, layer 66, one or more layers 60 separating layers 66 and 70, layer 70 and layer 74.

[0066] The layer or layers 60 separating layer 66 from substrate 54 include, for example, conductive tracks and conductive vias not shown so as to electrically connect track 68 and substrate 54. More specifically, the layer or layers 60 separating layer 66 from substrate 54 include, for example, conductive tracks and conductive vias not shown so as to electrically connect track 68 and circuit 40.

[0067] The lattice 62 of the chip 34 includes a layer 76. The layer 76 is an insulating layer corresponding to a layer 60 of the lattice 62. The layer 76 is preferably separated from the substrate 56 by at least one layer 60.

[0068] A metallic track 78 is located in layer 76. The track 78 extends from an upper face of layer 76, i.e., the face in contact with the upper layer 60 in the lattice 62, to a lower face of layer 76, i.e., the face in contact with the lower layer 60 in the lattice 62. The metallic track 78 constitutes the winding 48 of [Fig.2]. Thus, the length of the track 78 and its arrangement allow the winding 48 to be formed. For example, the track 78 forms a spiral in the layer 76, with one end of the track 78 located outside the spiral and another end of the track 78 located inside the spiral.

[0069] The network 62 comprises a layer 80. Layer 80 is an insulating layer covering layer 76. Layer 80 corresponds to the layer 60 furthest from the substrate 56 of the network 62. Layer 80 covers at least track 78, and preferably completely covers layer 76. Layer 80 corresponds, for example, to a single layer of the interconnecting network or to a single layer made of an insulating material different from the material of the layers 60. Alternatively, layer 80 comprises a plurality of insulating layers, including, for example, one or more layers 60 and / or one or more insulating layers made of one or more insulating materials different from the material of the layers 60.

[0070] The track 78 is for example separated from the substrate 56 by at least one layer 60. The layer 80 is separated from the substrate 56 by the layer 76. Thus, the network 62 comprises, preferably, in this order from the face 56a of the substrate 56, one or more layers 60 separating the layer 76 from the substrate 56, the layer 76, and the layer 80.

[0071] Track 78 is located at least partially opposite track 72. Layers 74 and 80 preferably do not include conductive elements between tracks 72 and 78 and between the portions of layers 70 and 76 located in the spiral formed by track 72 or 78.

[0072] Tracks 78 and 72 are arranged to be magnetically coupled and form a balun with the desired operating frequency range. Thus, layers 74 and 80, and more specifically their thickness, are chosen to ensure that tracks 72 and 78 are magnetically coupled and form the balun. For example, layer 74 has a thickness between 1 nm and 1 mm and layer 80 has a thickness between 1 nm and 1 mm.

[0073] The layer or layers 60 separating the layer 78 from the substrate 56 include, for example, conductive tracks and conductive vias not shown so as to electrically connect the track 78 and the substrate 56. More specifically, the layer or layers 60 separating the layer 78 from the substrate 56 include, for example, conductive tracks and conductive vias not shown so as to electrically connect the track 78 and the circuit 46.

[0074] Chips 32 and 34 are attached to each other by molecular bonding, preferably of the hybrid type. More specifically, layers 74 and 80 are attached to each other by molecular bonding. Thus, the face of layer 74 furthest from substrate 54 is in contact with the face of layer 80 furthest from substrate 56.

[0075] Layers 74 and 80 include, for example, conductive tracks not shown in contact with each other so as to allow the electrical connection of chips 32 and 34. Said tracks not shown are not located between tracks 72 and 78.

[0076] Fig. 4 schematically represents another embodiment of a transmission and reception device 100.

[0077] Device 100 comprises the elements, preferably all the elements, of device 30, arranged differently.

[0078] Thus, a chip 320 comprises, like the chip 32 of [Fig.2], the antenna 12 and the winding 36. As in [Fig.2], one end of the winding 36 is connected, preferably connected, to the antenna 12 and the other end of the winding 36 is connected, preferably connected, to the node 38.

[0079] A chip 340 comprises, like the chip 34 of [Fig.2], the winding 48, the circuit 46 and the transistors 50, 52. As in [Fig.2], the winding 48 is connected, preferably connected, between the terminals 46a and 46b of the circuit 46 and the transistors 50, 52 are connected as in [Fig.2].

[0080] Unlike the embodiment of [Fig.2], the chip 340 also includes the circuit 40, the winding 42 and the transistors 44, 46. As in [Fig.2], the winding 42 is connected, preferably connected, between the terminals 40a and 40b of the circuit 40 and the transistors 44, 46 are connected as in [Fig.2].

[0081] Windings 36, 42, and 48 are arranged such that windings 36 and 42 are coupled, such that windings 36 and 48 are coupled, and such that windings 42 and 48 are neither coupled nor in contact. Windings 36 and 42 are coupled so as to transmit only the operating frequency range for transmission. Windings 36 and 48 are coupled so as to transmit only the operating frequency range for reception.

[0082] Figure 5 schematically represents the implementation of the embodiment of Figure 4.

[0083] The device 100 comprises, in [Fig. 5], the chip 320 and the chip 340. Each chip 320, 340 comprises a substrate, for example a semiconductor substrate, in which electronic components can be formed. More specifically, the chip 320, like the chip 32 of [Fig. 3], comprises the substrate 54, and the chip 340 comprises the substrate 36. Unlike the embodiment of [Fig. 3], the substrate 56 comprises the electronic components of circuits 40 and 46, preferably all the components of circuits 40 and 46. The substrate 54 preferably does not comprise any electronic components of circuits 40 and 46.

[0084] In addition, each chip 320, 340 includes the interconnection network covering its substrate 54 or 56.

[0085] Thus, like the chip 32 of [Fig. 3], the chip 320 includes the interconnect network 58. The network 58 comprises a stack of a plurality of insulating layers 60. More precisely, the network 58 comprises an alternation of layers 60 comprising metallic tracks, or metallizations, and layers 60 comprising conductive vias connecting the metallic tracks. The network 58 rests on the face 54a of the substrate 54, for example, on the entire face 54a of the substrate 54.

[0086] Similarly, the chip 340 includes an interconnect network 62. The network 62 comprises a stack of a plurality of insulating layers 60. More specifically, the network 62 comprises an alternation of layers 60 comprising metallic tracks, or metallizations, and layers 60 comprising conductive vias connecting the metallic tracks. The network 62 rests on face 56a of the substrate 56, for example, on the entire face 56a of the substrate 56.

[0087] The network 58 includes the layer 70. The layer 70 is, as in [Fig.3], an insulating layer corresponding to a layer 60 of the network 58.

[0088] The metallic track 72 is located in layer 70. The track 72 extends, as in [Fig. 3], from an upper face of layer 70, i.e., the face in contact with the upper layer 60 in the lattice 58, to a lower face of layer 70, i.e., the face in contact with the lower layer 60 in the lattice 58. The metallic track 72 constitutes the winding 36 of [Fig. 4]. Thus, the length of the track 72 and its arrangement allow the winding 36 to be formed. For example, the track 72 forms a spiral in layer 70, with one end of the track 72 located outside the spiral and the other end of the track 72 located inside the spiral.

[0089] Unlike device 30 in [Fig.3], chip 320 does not include layer 66 and does not include track 68.

[0090] The network 58 comprises layer 74, as in [Fig. 3], corresponding to a layer 60. Layer 74 is an insulating layer covering layer 70. Layer 74 corresponds to the layer 60 furthest from the substrate 54 of the network 58. Layer 74 covers at least track 72, and preferably completely covers layer 70.

[0091] The network 58 preferably comprises, in this order from the face 54a of the substrate 54, one or more layers 60 separating the layer 70 of the substrate 54, the layer 70 and the layer 74.

[0092] The layer or layers 60 separating layer 70 from substrate 54 include, for example, conductive tracks and conductive vias not shown so as to electrically connect track 72 and substrate 54.

[0093] Unlike the embodiment of [Fig. 3], the network 62 of the chip 340 does not include layer 76. The network 62 of the chip 340 includes a layer 102. The layer 102 is an insulating layer corresponding to a layer 60 of the network 62. Layer 102 is preferably separated from the substrate 56 by at least one layer 60.

[0094] A metallic track 104 is located in layer 102. The track 104 extends from an upper face of layer 100, i.e., the face in contact with the upper layer 60 in the lattice 62, to a lower face of layer 102, i.e., the face in contact with the lower layer 60 in the lattice 62. The metallic track 104 constitutes the winding 42 of [Fig. 4]. Thus, the length of the track 104 and its arrangement allow the winding 42 to be formed. For example, the track 104 forms a spiral in layer 102, with one end of the track 104 located outside the spiral and the other end of the track 104 located inside the spiral.

[0095] Another metallic track 106 is located in layer 102. The track 106 extends from an upper face of layer 100, i.e., the face in contact with the upper layer 60 in the lattice 62, to a lower face of layer 102, i.e., the face in contact with the lower layer 60 in the lattice 62. The metallic track 106 constitutes the winding 48 of [Fig. 4]. Thus, the length of the track 106 and its arrangement allow the winding 48 to be formed. For example, the track 106 forms a spiral in layer 102, with one end of the track 106 located outside the spiral and the other end of the track 106 located inside the spiral.

[0096] Tracks 102 and 104 are not in contact. Thus, tracks 102 and 104 are separated by a portion 108 of layer 102.

[0097] Alternatively, tracks 104 and 106 can be located in separate layers of the network 62. Tracks 104 and 106 are arranged so that they are not directly opposite each other, even partially. Each track 104, 106 is separated from the chip 320, and more specifically from track 72, only by electrically insulating materials, for example by layers 60, 80, 74.

[0098] The network 62 includes a layer 80, corresponding to a layer 60. The layer 80 is an insulating layer covering the layer 102. The layer 80 corresponds to the layer 60 furthest from the substrate 56 of the network 62. The layer 80 covers at least the tracks 104 and 106, and preferably completely covers the layer 102.

[0099] Tracks 104 and 106 are, for example, separated from substrate 56 by at least one layer 60. Layer 80 is separated from substrate 56 by layer 102. Thus, the network 62 comprises, preferably, in this order from face 56a of substrate 56, one or more layers 60 separating layer 102 from substrate 56, layer 102, and layer 80.

[0100] Runways 104 and 106 are located at least partially adjacent to runway 72. More specifically, runway 104 is located at least partially adjacent to runway 72. and runway 106 is located at least partially opposite runway 72. Layers 74 and 80 preferably do not include conductive elements between runways 104 and 72, between runways 106 and 72 and between the portions of layers 70 and 102 located in the spirals formed by runway 72, 104 or 106.

[0101] Tracks 104 and 72 are arranged so as to be magnetically coupled and form a balun having the range of operating frequencies required to allow transmission by antenna 12. Thus, layers 74 and 80, and more particularly the thickness of layers 74 and 80, are chosen so as to ensure that tracks 72 and 104 are magnetically coupled and form the balun.

[0102] Tracks 106 and 72 are arranged so as to be magnetically coupled and form a balun having the range of operating frequencies required to enable reception by antenna 12. Thus, layers 74 and 80, and more particularly the thickness of layers 74 and 80, are chosen so as to ensure that tracks 72 and 106 are magnetically coupled and form the balun.

[0103] The layer(s) 60 separating layer 102 from substrate 56 include, for example, conductive tracks and conductive vias not shown so as to electrically connect track 104 and substrate 56 and include, for example, conductive tracks and conductive vias not shown so as to electrically connect track 103 and substrate 56. Tracks 104 and 106 are preferably not electrically connected by vias or conductive tracks located in the layers 60 of the network 62.

[0104] As in [Fig. 3], the chips 320 and 340 are attached to each other by molecular bonding, preferably of the hybrid type. More specifically, layers 74 and 80 are attached to each other by molecular bonding. Thus, the face of layer 74 furthest from substrate 54 is in contact with the face of layer 80 furthest from substrate 56.

[0105] Layers 74 and 80 include, for example, conductive tracks not shown in contact with each other so as to allow the electrical connection of chips 320 and 340. Said tracks not shown are not located between tracks 72 and 104 or between tracks 72 and 106.

[0106] One advantage of the described embodiments is the reduction of power leakage between the transmission and reception paths. Indeed, in the described embodiments, the windings 42 and 48 are not electrically connected by conductive elements, for example vias.

[0107] Another advantage of the described embodiments is that the absence of physical connection between circuits 40 and 46 makes it possible to form protection against electrostatic discharges.

[0108] Various embodiments and variations have been described. The person skilled in the art It will be understood that certain features of these various embodiments and variants could be combined, and other variants will become apparent to a person skilled in the art. In particular, in the embodiment of Figures 2 and 3, the assembly comprising circuit 40, winding 42, and transistors 44, 46 and the assembly comprising circuit 46, winding 48, and transistors 50, 52 can be interchanged.

[0109] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A device (30, 100) adapted to transmit and receive signals by the same antenna (12), comprising first (36), second (42) and third (48) windings, the first (36) and second (42) windings being coupled so as to transmit the signals to be transmitted by the antenna (12), the first (36) and third (48) windings being coupled so as to transmit the signals received by the antenna (12), the device comprising first (32, 320) and second (34, 340) chips, the first chip (32, 320) comprising the antenna (12) and the first winding (36), and the second chip (34, 340) comprising a winding from among the second (42) and third (48) windings, the first (32, 320) and second (34, 340) chips being fixed to each other by molecular bonding.

2. Device according to claim 1, wherein the first winding (36) is connected between the antenna (12) and a node (38) for applying a reference voltage, the second winding (42) is connected between two terminals of a first circuit (40) configured to generate a signal to be transmitted, the third winding (48) being connected between two terminals of a second circuit (46) configured to process a received signal.

3. Device according to claim 1 or 2, wherein each first (32, 320) or second (34, 340) chip comprises a semiconductor substrate (54, 56) and an interconnect network (58, 62) comprising a stack of insulating layers (60) comprising conductive tracks and conductive vias, each interconnect network (58, 62) comprising a first layer (74, 80), the first layer (74, 80) of each interconnect network being furthest from the substrate of said chip (32, 320, 34, 340), the first (32, 320) and second (34, 340) chips being fixed to each other by the first layers (74, 80) of each interconnect network.

4. Device according to claim 3, wherein the first winding (36) comprises a first conductive track (72) in a second layer (70) of the interconnection network (58) of the first chip (32, 320), the first track (72) being separated from the second chip (36) only by insulating material.

5. Device according to claim 4, wherein the second winding (42) comprises a second conductive track (78, 104) in a third layer (76, 102) of the interconnection network (62) of the second chip (34, 340), the second track (78, 104) being separated from the first chip (32, 320) only by insulating material.

6. Device according to claim 5, wherein the third winding (48) comprises a third conductive track (68) in a fourth layer (66) of the interconnect network (58) of the first chip (32), the third track (68) being separated from the first track (72) by insulating material, the third track (68) being located between the first track (72) and the substrate (54) of the first chip (32).

7. Device according to claim 5, wherein the third winding (48) comprises a third conductive track (106) in a fifth layer (102) of the interconnection network (62) of the second chip (340), the third track (106) being separated from the first chip (320) by insulating material.

8. Device according to claim 4, wherein the third winding (48) comprises a second conductive track (78, 104) in a third layer (76, 102) of the interconnection network (62) of the second chip (34, 340), the second track (78, 104) being separated from the first chip (32, 320) only by insulating material.

9. Device according to claim 8, wherein the second winding (42) comprises a third conductive track (68) in a fourth layer (66) of the interconnect network (58) of the first chip (32), the third track (68) being separated from the first track (72) by insulating material, the third track (68) being located between the first track (72) and the substrate (54) of the first chip (32).

10. Device according to claim 8, wherein the second winding (42) comprises a third conductive track (106) in a fifth layer (102) of the interconnection network (62) of the second chip (340), the third track (106) being separated from the first chip (320) by insulating material.

11. Device according to claim 7 or 10, wherein the second (104) and third (106) tracks are located in the same third layer (102) of the interconnect network (62) of the second chip (34, 340).

12. Device according to any one of claims 1 to 11, wherein the device is configured to operate in time-division duplex mode or frequency-division duplex mode.

13. A device according to any one of claims 1 to 12, wherein the molecular bonding is a metal / metal bond or an oxide / oxide.

14. A method for manufacturing a device (30, 100) adapted to transmit and receive signals by the same antenna (12), the device comprising first (36), second (42) and third (48) windings, the first (36) and second (42) windings being coupled so as to transmit the signals to be transmitted by the antenna (12), the first (36) and third (48) windings being coupled so as to transmit the signals received by the antenna (12), the method comprising the formation of first (32, 320) and second (34, 340) chips, the first chip (32, 320) comprising the antenna (12) and the first winding (36), and the second chip (34, 340) comprising a winding from among the second (42) and third (48) windings, the method further comprising the fixing of the first (32, 320) and second (34, 340) chips to each other by molecular bonding.

15. A manufacturing method according to claim 14 applied to the manufacture of a device according to any one of claims 1 to 13.

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