HEMT transistor

Abstract

HEMT Transistor This description relates to a HEMT transistor comprising: - a first semiconductor layer (13); - a gate (15) disposed on a first surface of the first semiconductor layer (13); - a first passivation layer (17) comprising at least one sublayer of a first dielectric material on the sides of the gate, the first passivation layer further extending over a first part of said surface of the first semiconductor layer; and - a second passivation layer (19), distinct from the first passivation layer (19), comprising at least one sublayer of the same first dielectric material on a second part of said surface of the first semiconductor layer adjacent to the first passivation layer. Abstract Figure: Fig. 1

Description

Title of the invention: HEMT Transistor technical field

[0001] This description relates generally to the field of transistors and more particularly to the field of high electronic mobility transistors also called HEMTs. Previous technique

[0002] HEMT transistors are based on a heterojunction on the surface of which a two-dimensional electron gas, also called 2DEG, is formed.

[0003] It is necessary to improve HEMT transistors and their manufacturing processes. Summary of the invention

[0004] To achieve this, one embodiment provides:

[0005] A HEMT transistor comprising: - a first semiconductor layer; - a grid arranged on a first surface of the first semiconductor layer; - a first passivation layer comprising at least one sublayer consisting of a first dielectric material on the sides of the grid, the first passivation layer further extending over a first part of said surface of the first semiconductor layer; and - a second passivation layer, distinct from the first passivation layer, comprising at least one sublayer made of the same first dielectric material on a second part of said surface of the first semiconducting layer next to the first passivation layer.

[0006] According to one embodiment, the first dielectric material is aluminum nitride.

[0007] According to one embodiment, the first semiconductor layer is gallium nitride based, for example made of aluminum-gallium nitride.

[0008] According to one embodiment, the transistor comprises a source contact metallization and a drain contact metallization, respectively arranged on either side of the gate.

[0009] According to one embodiment, the first passivation layer extends laterally from the grid to the contact metallization of the drain, over only a part of the surface between the grid and the contact metallization of the drain, the first passivation layer also extending laterally from the grid to the contact metallization of the source.

[0010] According to one embodiment, the second passivation layer extends laterally from an edge of the first passivation layer located between the grid and the contact metallization of the drain, to the contact metallization of the drain.

[0011] According to one embodiment, the first passivation layer is covered with an insulating layer, the second passivation layer covering the side of the insulating layer located between the grid and the drain contact metallization and extending over a part of the insulating layer towards the grid.

[0012] According to one embodiment, the first passivation layer comprises a first sub-layer and a second sub-layer, the first sub-layer being made of the first dielectric material, the second sub-layer being made of a second dielectric material different from the first dielectric material and the second sub-layer covering the upper face of the first sub-layer.

[0013] According to one embodiment, the second dielectric material is alumina.

[0014] According to one embodiment, the first dielectric material of the first layer The first passivation layer and the first dielectric material of the second passivation layer have different physical properties.

[0015] Another embodiment provides a method for manufacturing a HEMT transistor, comprising the following successive steps: a) the formation of a first semiconductor layer; b) the formation of a grid on a first surface of the first semiconductor layer; c) Training: of a first passivation layer comprising at least one sublayer consisting of a first dielectric material on the sides of the grid, the first passivation layer further extending over a first part of said surface of the first semiconductor layer, and a second passivation layer, distinct from the first passivation layer, comprising at least one sublayer made of the same first dielectric material on a second part of said surface of the first semiconducting layer near the first passivation layer.

[0016] According to one embodiment, during step c), the first passivation layer is formed before the second passivation layer, step c) comprising: - a step of depositing the first passivation layer; - a step of depositing an insulating layer; - a partial etching step of the first passivation layer and the insulating layer; and - a step of depositing the second passivation layer on the top face of the first semiconductor layer and the insulating layer.

[0017] According to one embodiment, The first passivation layer comprises a first sublayer and a second sublayer, the first sublayer being made of the first dielectric material, the second sublayer being made of a second dielectric material different from the first dielectric material, and the second sublayer covering the upper face of the first sublayer, and step c) comprises: - a step of depositing the first undercoat; - a step of depositing the second underlayer; - a step of depositing an insulating layer; - a partial etching step of the first passivation layer and the insulating layer; and - a step of depositing the second passivation layer on the top face of the first semiconductor layer and the insulating layer.

[0018] According to one embodiment, during step c), the first and second passivation layers are coated during a deposition step, step c) being preceded by a local heat treatment step.

[0019] According to one embodiment, step c) successively comprises a step of depositing the first passivation layer and a step of depositing the second passivation layer, the second passivation layer being deposited by a different deposition process than the deposition process of the first passivation layer. Brief description of the drawings

[0020] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0021] Fig. 1 is a simplified partial cross-sectional view of an example of a HEMT transistor according to a first embodiment;

[0022] Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 21 and 2J are cross-sectional views illustrating steps in an example of a manufacturing process for the HEMT transistor shown in [Fig.1];

[0023] The [Fig.3] is a simplified partial cross-sectional view of an example of a HEMT transistor according to a second embodiment;

[0024] Figure 4 is a simplified partial cross-sectional view of an example of a HEMT transistor according to a third embodiment; and

[0025] Figures 5A, 5B and 5C are cross-sectional views illustrating steps in an example of a manufacturing process for the HEMT transistor shown in [Fig.4]. Description of the implementation methods

[0026] The same elements have been designated by the same references in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0027] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the applications that the described HEMT transistors can have are not detailed, as the embodiments are compatible with common applications of HEMT transistors. The range of HEMT transistors capable of withstanding relatively high voltages in the off state, for example, voltages on the order of 100 to 650 volts, is considered more specifically here.

[0028] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0029] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0030] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0031] For the purposes of the present invention, the expression "same materials" means that two materials have a respective chemical composition (or stoichiometry) containing essentially the same principal chemical elements (or components). The expression "principal chemical element" means that the element has a weight percentage greater than 40% in the chemical composition. Typically, the weight percentage of each principal chemical element in the two materials may be (nominally) different. For example, the actual weight percentage of a principal chemical element may vary in a range of +3% / -3%, preferably +2% / -2%, relative to the nominal value (for example, in AIN, the nominal weight percentage of Al and N is 50%, whereas the actual weight percentage may vary in a range of 47%-53%).Furthermore, two identical materials may contain different traces of impurities (such as carbon, hydrogen, and oxygen). For the purposes of the present invention, "impurity" means an element present in the chemical composition with a weight percentage less than or equal to 2%, preferably less than or equal to 1%. Generally, the overall weight percentage of impurities in the material is less than or equal to 5%. preference less than or equal to 3%.

[0032] Fig. 1 is a simplified partial cross-sectional view of an example of a HEMT 110 transistor according to one embodiment.

[0033] The HEMT 110 transistor comprises a first semiconductor layer 13, arranged on a second conductive layer 23. The semiconductor layer 13 is, for example, in contact, by its lower surface, with the upper surface of the conductive layer 23. By way of example, the stack comprising the semiconductor layer 13 and the semiconductor layer 23 rests on a substrate 21. The semiconductor layer 23 is, for example, in contact, by its lower surface, with the upper surface of the substrate 21. The interface between the first semiconductor layer 13 and the second semiconductor layer 23 defines a heterojunction on the surface of which a two-dimensional electron gas 2DEG, also called an electron channel, is formed.

[0034] The semiconductor layers 13 and 23 are, for example, made of IILV type semiconductor materials, for example gallium nitride (GaN) based. The semiconductor layer 13 is, for example, made of gallium aluminum nitride (AlGaN). The semiconductor layer 23 is, for example, made of gallium nitride.

[0035] By way of example, the substrate 21 comprises a semiconductor material. The substrate 21 is, for example, made of silicon or silicon carbide. Alternatively, the substrate 21 is made of aluminum nitride. The substrate 21 includes, for example, on its upper surface, a buffer layer, not detailed in the drawings, for example, made of gallium nitride. The buffer layer is, for example, in contact, via its upper surface, with the lower surface of the semiconductor layer 23. The substrate 21 may be a complex composition of different semiconductor and insulating materials to ensure good quality of the layer 23. The substrate 21 may be silicon or a different substrate (sapphire or SiC) plus a suitable sequence of AIN, AlGaN, and GaN layers to obtain a suitable layer 23 in terms of defects, stresses, and insulation from the semiconductor wafer.

[0036] The HEMT 110 transistor includes a gate 15 on the upper surface of the semiconductor layer 13. The gate 15 is, for example, in contact, by its lower surface, with the upper surface of the semiconductor layer 13.

[0037] The grid 15 is for example made of a semiconductor material, for example of a type IILV semiconductor material, for example gallium nitride, for example P-type doped.

[0038] By way of example, the HEMT 110 transistor further comprises a source contact metallization 29 and a drain contact metallization 31. The contact metallizations 29 and 31 are, for example, based on titanium, titanium nitride and / or an alloy of aluminum and copper. The source and drain contact metallizations 29 and 31 each define, for example, an ohmic contact with the semiconductor layer 23 or with the semiconductor layer 13. The contact metallizations 29 and 31 are, for example, located on top and in contact with the semiconductor layer 23, on either side of the gate 15. Alternatively, the contact metallizations 29 and 31 are, for example, located on top and in contact with the semiconductor layer 13, on either side of the gate 15.

[0039] The HEMT transistor 110 further comprises a first passivation layer 17 made of a first dielectric material, for example aluminum nitride, covering the sides of the gate 15 and extending over a portion of the upper surface of the first semiconductor layer 13. In the example of [Fig. 1], the passivation layer 17 also partially covers the upper surface of the gate 15, in a peripheral part of the gate 15 (near the sides of the gate 15). For example, the passivation layer 17 is in contact, by its lower surface, with the upper surface of the semiconductor layer 13. In the embodiment of [Fig. 1], the passivation layer 17 covers only a portion of the upper surface of the semiconductor layer 13, located next to the gate 15, for example, at the periphery of the gate 15.More specifically, in this example, the passivation layer 17 extends laterally from the grid 15 towards the drain contact metallization 31, but only over a portion of the surface between the grid 15 and the drain contact metallization 31. In other words, the passivation layer 17 does not extend all the way to the drain contact metallization 31. In this example, the passivation layer 17 extends laterally from the grid 15 towards the source contact metallization 29, but only over a portion of the surface between the grid 15 and the source contact metallization 29. In other words, the passivation layer 17 does not extend all the way to the source contact metallization 29. Alternatively (not shown), the passivation layer 17 extends laterally from the grid 15 to the contact metallization of source 29. .

[0040] The HEMT 110 transistor further comprises a second passivation layer 19, distinct from the first passivation layer 17, made for example of the same first dielectric material as the first passivation layer 17, for example aluminium nitride.

[0041] According to one embodiment, the first and second passivation layers may also be made of another nitride or oxide material. In another embodiment not shown, the first and second passivation layers may be made of alumina, hafnium oxide, and / or nitrogen-based alumina.

[0042] For example, the aluminum nitride of the first passivation layer 17 and the second passivation layer 19 have a chemical composition comprising a percentage by weight of aluminium equal to 50% and a percentage by weight of nitrogen equal to 50%.

[0043] Alternatively, the aluminum nitride of the first passivation layer and the aluminum nitride of the second passivation layer may have a chemical composition comprising a weight percentage of aluminum between 47% and 53% and a complementary weight percentage of nitrogen. For example, the chemical composition of the aluminum nitride of the first passivation layer is 47% aluminum and 53% nitride, and the chemical composition of the aluminum nitride of the second passivation layer is 51% aluminum and 49% nitride.

[0044] In one embodiment (not illustrated), the chemical composition of one or both of the aluminium nitrides of the first and second passivation layers may contain a weight percentage of an impurity element (for example, hydrogen), for example equal to 1%.

[0045] The second passivation layer 19 is disposed on another part of the upper surface of the semiconductor layer 13. By way of example, the passivation layer 19 is in contact with the upper surface of the first semiconductor layer 13. More precisely, the passivation layer 19 is formed near the passivation layer 17 and covers a portion of the semiconductor layer 13 that is not covered by the passivation layer 17. The passivation layers 17 and 19 are, for example, in contact along their sides. In the illustrated example, the passivation layer 19 extends laterally from the edge of the passivation layer 17 located between the gate 15 and the drain contact metallization 31, to the drain contact metallization 31.In the illustrated example, the passivation layer 19 also extends laterally from the edge of the passivation layer 17 located between the grid 15 and the source contact metallization 29, to the source contact metallization 29, on top and in contact with the layer 13.

[0046] The passivation layers 17 and 19 each have, for example, a thickness between 2 nm and 20 nm, or for example, between 5 nm and 10 nm. The passivation layers 17 and 19 have, for example, approximately the same thickness. The passivation layers 17 and 19 may also have different thicknesses depending on the application requirements.

[0047] In an embodiment not shown, the grid is surmounted by an optional intermediate conductive layer made of a metallic material, for example, titanium nitride-based. The intermediate metallic layer is, for example, in contact with the grid. The intermediate metallic layer extends, for example, only over a central part of the upper surface of the grid, so that a peripheral part of the upper surface of the grid is not covered by a metallic layer. The passivation layer 17 extends, for example, laterally to the Intermediate metallic layer. Alternatively, the intermediate metallic layer completely covers the upper surface of the grid.

[0048] The grid 15 is, for example, surmounted by a grid contact metallization 27 and is, for example, in direct contact with it. By way of example, the grid contact metallization 27 is based on titanium nitride and / or an aluminum-copper alloy. In the presence of an intermediate metal layer (not shown), the grid contact metallization is, for example, in direct contact with the intermediate metal layer.

[0049] The HEMT 110 transistor comprises, for example, several levels of insulating layers with metallizations formed inside and above them.

[0050] By way of example, the HEMT 110 transistor comprises a first insulating layer 33 on the upper surface of the passivation layer 17 and in contact with it. For example, the insulating layer 33 covers the entire surface of the passivation layer 17 and does not cover the passivation layer 19. The insulating layer 33 is, for example, self-aligned with the passivation layer 17. The insulating layer 33 is, for example, open opposite a central portion of the gate 15 to allow passage through the gate contact metallization 27. The insulating layer 33 is, for example, made of a dielectric material, for example an oxide, for example silicon dioxide (SiO2).

[0051] By way of example, the passivation layer 19 covers the side of the insulating layer 33 located between the grid 15 and the drain contact metallization 31, and then extends over a portion of the insulating layer 33 towards the grid 15. Thus, starting from the drain contact metallization 31, the passivation layer 19 covers the portion of the upper surface of the semiconductor layer 13 located between the drain contact metallization 31 and the passivation layer 17, and then extends over the insulating layer 33, so that a portion of the passivation layer 19 lies in front of the passivation layer 17 and is separated from it by the insulating layer 33. In the illustrated example, the passivation layer 19 also covers the side of the insulating layer 33 located between the grid 15 and the contact metallization from source 29, and then extends over part of the insulating layer 33 towards the grid 15.Thus, from the source contact metallization 29, the passivation layer 19 covers the part of the upper surface of the semiconducting layer 13 located between the source contact metallization 29 and the passivation layer 17, and then extends onto the insulating layer 33, so that a part of the passivation layer 19 is in front of the passivation layer 17 and is separated from it by the insulating layer 33. As an example, the insulating layer 19 is deposited and shaped so as to be aligned with the insulating layer 35 (described below).

[0052] By way of example, the HEMT 110 transistor comprises a second insulating layer 35 on the upper surface of the passivation layer 19 and in contact with it. For example, the insulating layer 35 has one face in contact with the drain contact metallization 31 and extends towards the source contact metallization 29. For example, the insulating layer 35 covers, for instance, exclusively, the entire surface of the passivation layer 19. The insulating layer 35 therefore extends, for example, over the part of the upper surface of the semiconductor layer 13 that is not covered by the insulating layer 33 and over the peripheral part of the insulating layer 33. The insulating layer 35 is, for example, made of a dielectric material, for example silicon nitride (SiN) or an oxide, for example silicon dioxide (SiO2).

[0053] For example, the HEMT 110 transistor includes a third insulating layer 39 covering the second insulating layer 35 and the source and drain contact metallizations 29 and 31.The third insulating layer 39, for example, is made of the same material as the insulating layers 33 and / or 35.

[0054] By way of example, the HEMT 110 transistor includes a metallic region 37 that extends simultaneously over a portion of the surface of the first insulating layer 33 not covered by the second insulating layer 35, and over a portion of the surface of the third insulating layer 39. The metallic region 37 is thus arranged on two different levels of the insulating layer. By way of example, the metallic region 37 is based on titanium nitride and / or an aluminum-copper alloy. The metallic region 37 is, for example, made of the same material as the gate contact metallization 27.

[0055] The metallic region 37, for example, has the function of modifying the electric field distribution profile of the drain-side grid edge (the right edge of the grid in [Fig. 1]) and reducing the critical electric field peak, thereby increasing the avalanche voltage. For example, the metallic region 37 is called the field plate.

[0056] In the transistor of [Fig. 1], the 2DEG channel is, for example, normally off, that is, it is interrupted below the gate 15, which prevents current from flowing between the source and the drain of the transistor. The transistor is then said to be in the blocked state. The channel can be restored (that is, made conductive) by biasing the gate 15. In this case, current can flow between the source and the drain of the transistor. The transistor is then said to be in the conducting state. The embodiments described can also be applied to normally conducting transistors.

[0057] The presence of the passivation layers 17 and 19 protects the upper surface of the semiconductor layer 13, on which dangling bonds and Ga-0 bonds may be present, introducing negative charges that can lead to a degradation of the 2 DEG mobility, generating leakage currents and / or a decrease in the transistor breakdown voltage. The passivation layers 17 and 19 fill these bonds to make the surface of the semiconductor layer 13 electrically inactive.

[0058] The passivation layers 17 and 19 also make it possible to protect the semiconducting layer 13 against oxidation and to improve its condition, to which the 2DEG channel is sensitive.

[0059] The passivation layers 17 and 19 can reduce the density of the interface state and increase the density of 2DEG carriers and drift mobility by suppressing the trapping effect.

[0060] The first passivation layer 17, and more particularly the portion of the passivation layer 17 located on the sides of the grid 15, increases the resistivity of the 2DEG channel under and around the grid. This results in a decrease in the electric field formed at the corner of the grid 15, and therefore a reduction in leakage currents. Furthermore, the passivation effect of the portion of the layer 17 located on the side wall of the grid is also significant, again with the aim of reducing leakage current (reduction of conduction by trapping mechanism at the side of the grid 15).

[0061] The second passivation layer 19 allows positive charges to be introduced at the interface between the passivation layer and the first semiconductor layer 13, which locally increases the electron density in the 2DEG channel, and therefore locally decreases the resistivity of the 2DEG channel and improves the value of R0N on the device.

[0062] The use of double passivation makes it possible to find a compromise between the reduction of leakage current and the reduction of the resistivity of the 2DEG channel.

[0063] In this embodiment, the passivation layers 17 and 19 are both made of aluminum nitride but can be deposited under different deposition conditions to obtain the respective desired effects of local increase in the resistivity of the 2DEG channel under and around the grid (passivation layer 17), and local increase in the electron density in the 2DEG channel (passivation layer 19). Alternatively, or in addition, before the deposition of the passivation layers 17 and 19, the surface of the semiconductor layer 13 can be subjected to different treatments with respect to the deposition zone of the passivation layer 17 and the deposition zone of the passivation layer 19 respectively, in order to obtain the respective desired effects of local increase in the resistivity of the 2DEG channel (passivation layer 17), and local increase in the electron density in the 2DEG channel (passivation layer 19).

[0064] The first passivation layer 17 and the second passivation layer 19 may have different physical structures. For example, the first passivation layer 17 and the second passivation layer 19 have different crystallographic properties. For example, the first passivation layer 17 and the second passivation layer 19 have different properties at the interface with the semiconductor layer 13.

[0065] By way of example, the use of a more similar AIN material to layer 13 (AlGaN) makes it possible to restore the original characteristics of the AlGaN layer by restoring the low intrinsic 2DEG resistivity damaged by the processes necessary to draw and remove the grid layer 15. In general, independently, it is possible to deposit the same material (layers 17 and 19) with different deposition conditions to modulate the effect on the grid leakage and the 2DEG resistivity by modulating the impurities inside the film such as carbon, hydrogen and oxygen or by changing the film density to obtain a layer with a different permeability to H. This will, for example, protect the electrical performance of the layer 15 used inside the grid.

[0066] Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 21 and 2J are cross-sectional views illustrating the successive stages of an example of a manufacturing process for the HEMT transistor illustrated in [Fig.1].

[0067] [Fig.2A] illustrates an initial structure comprising, in order, from the lower surface of the structure, the substrate 21, the second semiconductor layer and the first semiconductor layer 13. The initial structure further comprises a gate layer 15. In the initial structure illustrated in [Fig.2A], the layers 23, 13 and 15 extend continuously and with a substantially uniform thickness over the entire upper surface of the substrate 21.

[0068] Fig. 2B illustrates a structure obtained after a local etching step of the gate layer 15 to retain only a part of each layer forming the gate stack of the transistor of Fig. 1.

[0069] During this step, the grid 15 is etched, for example by a plasma etching process, for example by a chlorine-based plasma etching process, for example by a boron trichloride (BC13) and oxygen (O2) plasma etching process.

[0070] This etching step is, for example, followed by a cleaning step of the upper surface of the structure to remove, for example, residues from the etching mask(s) and impurities resulting from the etching of the grid 15. The cleaning of the structure includes, for example, a plasma etching step using oxygen and nitrogen (N2). The cleaning of the structure may also include a step of removing organic residues using a solvent.

[0071] Fig. 2C illustrates a structure obtained after a step of forming the passivation layer 17 and the insulating layer 33 on the upper surface of the structure illustrated in Fig. 2B.

[0072] During this step, the passivation layer 17 is first manufactured continuously, so as to cover the entire upper surface of the structure illustrated in [Fig.2B].

[0073] The passivation layer 17 is for example in contact with the upper surface of the semiconductor layer 13, as well as with the sides and the upper surface of the grid 15.

[0074] The passivation layer 17 is formed, for example, by a thin-film deposition process, for example an atomic layer deposition process, also called an ALD process, for example by thermal or plasma means using a suitable Al source precursor. For example, the deposition process for the passivation layer 17 is a plasma-enhanced ALD process or a heat-enhanced ALD process. At the end of this step, the passivation layer 17 has a thickness, for example, in the range of 1 nm to 15 nm, for example in the range of 3 nm to 10 nm, for example on the order of 6 nm.

[0075] Next, the insulating layer 33 is, in this example, formed continuously so that it covers the entire upper surface of the passivation layer 17. The insulating layer 33 is formed, for example, in contact with the passivation layer 17. The insulating layer 33 is formed, for example, by plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or another chemical vapor deposition technique. At the end of this step, the insulating layer 33 has a thickness, for example, in the range of 10 nm to 200 nm, for example, in the range of 30 nm to 150 nm, for example, on the order of 70 nm.

[0076] By way of example, the steps of depositing the passivation layer 17 and the insulating layer 33 are preceded by one or more surface preparation steps for the structure illustrated in [Fig. 2B]. Surface preparation of the structure illustrated in [Fig. 2B] may include cleaning, for example, by chemical cleaning with an acid, such as hydrogen chloride (HCl) or hydrogen fluoride (HF), or with basic solutions, such as ammonia (NH3). Surface preparation of the structure illustrated in [Fig. 2B] may further include cleaning, for example, by surface oxidation. The passivation layer 17 will thus be formed in contact with an oxide film, itself formed in contact with the upper surface of the layer 13.

[0077] Fig. 2D illustrates a structure obtained after an etching step of the passivation layer 17 and the insulating layer 33.

[0078] More particularly, during this step, the passivation layer 17 and the insulating layer 33 are removed opposite a portion of the semiconducting layer 13. By way of example, the layers 17 and 33 are held next to the grid 15, and removed outside the periphery of the grid 15, here in a portion located to the right and left of the grid 15.

[0079] By way of example, the removal of layers 17 and 33 is carried out by plasma etching, for example fluorine-based, for example carbon tetrafluoride-based (CF4).

[0080] The etching of layers 17 and 33 is, for example, selective and does not attack the semiconductor layer 13. The etching of layers 17 and 33 then stops with the exposure of the upper surface of layer 13.

[0081] These engraving steps are followed, for example, by a cleaning step of the upper surface of the structure, for example in a manner similar to that described in relation to [Fig.2B].

[0082] Fig. 2E illustrates a structure obtained after a step of forming the passivation layer 19 and the insulating layer 35 on the upper surface of the structure illustrated in Fig. 2D.

[0083] During this step, the passivation layer 19 is first formed continuously, so that it covers the entire upper surface of the structure illustrated in [Fig.2D],

[0084] The passivation layer 19 is for example formed in contact with the upper surface of the insulating layer 33 and the part of the semiconducting layer 13 which is not covered by the passivation layer 17. For example, the passivation layer 19 also covers the etched face of the layers 17 and 33.

[0085] The passivation layer 19 is formed, for example, by a thin-film deposition process, for example, an atomic layer deposition (ALD) process. For example, the deposition process for the passivation layer 19 is a plasma-enhanced ALD process or a thermal ALD process. After this step, the passivation layer 19 has a thickness, for example, between 1 nm and 10 nm, for example between 2 nm and 8 nm, for example on the order of 5 nm.

[0086] Next, the insulating layer 35 is, in this example, formed continuously so that it covers the entire upper surface of the passivation layer 19. The insulating layer 35 is formed, for example, in contact with the passivation layer 19. The insulating layer 35 is formed, for example, by a process similar to one of the possible processes for forming the layer 33 described in relation to [Fig. 2C]. At the end of this step, the insulating layer 35 has a thickness, for example, in the range of 50 nm to 200 nm, for example, on the order of 80 or 100 nm.

[0087] By way of example, the steps of depositing the passivation layer 19 and the insulating layer 35 are preceded by one or more steps of preparing the surface of the structure illustrated in [Fig.2D] in a manner similar to that which has been described in relation to [Fig.2C].

[0088] Fig. 2F illustrates a structure obtained at the end of a step of forming openings intended to receive the ohmic contacts and more particularly the source and drain contact metallizations 29 and 31.

[0089] Figure 2G illustrates a structure obtained at the end of a formation step of ohmic contacts and more particularly metallizations of the source and drain contacts 29 and 31.

[0090] Openings for receiving the source and drain contact metallizations 29 and 31 are first created in layers 35 and 19 ([Fig. 2F]). The openings are formed, for example, by a plasma etching process, for example, fluorine-based or carbon tetrafluoride (CF4)-based. In this example, the etching extends through the semiconductor layer 13 and opens onto or into the semiconductor layer 23. The step of forming the openings for receiving the contact metallizations 29 and 31 is, for example, followed by a step of cleaning the upper surface of the structure, for example, in a manner similar to that described in relation to [Fig. 2B].

[0091] By way of example, a step of preparing the surface of the upper face of the layer 23 in the openings may be provided. This step includes, for example, chemical cleaning by means of an acid, for example hydrogen chloride (HCl).

[0092] Next ([Fig. 2G]), the source and drain contact metallizations 29 and 31 are, for example, formed in the previously formed openings. The metallizations 29, 31 are, for example, formed by depositing one or more layers of a metallic material followed by an etching step.

[0093] In the illustrated example, the source and drain metallizations extend to the bottom and sides of the openings, and also extend over the top of the passivation layer 35 near the sides of the openings.

[0094] Fig. 2H illustrates a structure obtained after a step of forming the insulating layer 39 on the upper surface of the structure illustrated in Fig. 2G, followed by a step of forming an opening in the layers 39, 35 and 19 in a central part of the structure.

[0095] The insulating layer 39 is, for example, first formed continuously so as to cover the entire upper surface of the structure illustrated in [Fig. 2G]. The insulating layer 39 is, for example, formed according to a process identical to the process for forming layer 33 described in relation to [Fig. 2C]. At the end of this step, the insulating layer 39 has a thickness, for example, in the range of 150 nm to 400 nm, for example, in the range of 200 nm to 350 nm, for example, on the order of 300 nm.

[0096] An opening is then formed in a central part of the structure, the opening vertically passing through layers 39, 35 and 19 and opening onto the upper surface of layer 33. The opening extends in front of the grid 15 and extends in front of a part of the area located between the grid 15 and the drain contact metallization 31.

[0097] Figure 21 illustrates a structure obtained at the end of a step in the formation of the me- tallisation 37 on the upper surface of the structure illustrated in [Fig.2H].

[0098] By way of example, during this step, region 37 is formed on a portion of the surface of the first insulating layer 33, and extends over one side of the opening formed in step [Fig. 2H], and over the top of the insulating layer 39 next to the side of the opening. Region 37 is formed, for example, by the deposition of one or more layers of a metallic material followed by an etching step.

[0099] Fig. 2J illustrates a structure obtained after an opening step of layers 33 and 17 opposite the grid 15 of the structure illustrated in Fig. 2I, and a subsequent step of forming the grid metallization 27 in the opening.

[0100] More specifically, during this step, layers 33 and 17 are removed opposite a central part of the upper surface of the grid 15.

[0101] By way of example, the removal of layers 33 and 17 is carried out by plasma etching, for example based on fluorine, for example based on carbon tetrafluoride (CF4) or an equivalent chemistry capable of attacking the dielectric made of silicon dioxide or silicon nitride.

[0102] The presence of layers 17 and 19 under layers 33 and 35 is also useful from an integration point of view because it is possible to have etching steps capable of stopping on layers 17 and 19 before reaching layers 15 and 13 respectively. In this way, the impact on the thickness and surface quality of layers 13 and 15 is preserved in order to maintain their electrical performance, the removal of layers 17 and 19 can be carried out smoothly using wet etching processes or soft dry etching processes capable of preserving the characteristics of layers 17 and 19 (thickness, surface quality).

[0103] The etching step of [Fig. 2J] is, for example, selective or partially selective on layer 17, which can then be removed by a wet process or by gentle dry etching. The partial removal of layers 33 and 17 is, for example, followed by a cleaning step of the upper surface of the structure, for example in a manner similar to that described in relation to [Fig. 2B].

[0104] The grid contact metallization 27 is formed in the opening formed in the layers 33 and 17 opposite the central part of the grid 15. For example, the grid contact metallization 27 is formed above and in contact with the grid layer 15 or with an intermediate metallic layer (not shown) covering the grid layer. The grid contact metallization 27 is formed, for example, by depositing one or more layers of a metallic material, followed by an etching step.

[0105] By way of example, the step of forming the contact metallization of grid 27 is preceded by a step of preparing the surface of the structure, consisting for example of chemical cleaning with an acid, for example chloride of hydrogen (HCl).

[0106] Fig. 3 is a simplified partial cross-sectional view of an example of a HEMT 114 transistor according to a third embodiment.

[0107] Figure 3 illustrates a transistor 114 similar to the transistor 110 shown in relation to Figure 1, except that the passivation layer 17 consists of a stack of a first sub-layer 171 made of a first dielectric material, preferably aluminum nitride, and a second sub-layer 173 made of a second dielectric material different from the first material, preferably alumina (Al₂O₃). The second passivation layer 19 is made of either the first or second dielectric material. Preferably, the second passivation layer 19 is made of aluminum nitride.

[0108] In this embodiment, the first sub-layer 171 and the second sub-layer 173 are in contact with each other, the second sub-layer 173 covering the upper face of the first sub-layer 171.

[0109] The manufacturing process of transistor 114 is, for example, similar to that described for transistor 110 in relation to Figures 2A to 2J. The first 171 and second 173 sublayers are continuously fabricated so that they cover the upper surface of the semiconductor layer 13, as well as the sides and upper surface of the gate 15. Then, the insulating layer 33 is, for example, continuously formed so that it covers the entire upper surface of the passivation layer 17. Then, the passivation layer 17 (formed by the two sublayers) and the insulating layer 33 are removed as explained above with reference to [Fig. 2D].

[0110] Alternatively (not shown), the second passivation layer corresponds to a portion of the first sublayer above which the second sublayer has been removed. In this case, the second passivation layer does not cover the first insulating layer. The manufacturing process for such a transistor is, for example, similar to that described for transistor 110 with reference to Figures 2A to 2J, except that the etching step in [Fig. 2D] stops at the upper surface of the first sublayer. The first sublayer is therefore not removed and continues continuously until the drain contact metallization. In other words, the second passivation layer is formed by the first sublayer. In this embodiment, the step of depositing the second passivation layer as described with reference to [Fig. 2E] is not performed.

[0111] For example, the second sublayer 173 is made of alumina (Al2O3).

[0112] Alternatively, the sub-layer 171 is made of alumina (Al2O3) and the sub-layer 173 is made of AIN with different deposition conditions.

[0113] Adding sublayer 173 to passivation layer 17 modifies further- significantly improves the passivation properties of passivation layer 17 relative to the passivation properties of passivation layer 19, further increasing the resistivity of the 2DEG channel under and around the grid, while maintaining the low resistivity of the rest of the 2DEG channel.

[0114] Fig. 4 is a simplified partial cross-sectional view of an example of a HEMT 116 transistor according to a fourth embodiment.

[0115] [Fig. 4] illustrates a transistor 116 similar to the transistor 110 illustrated in relation to [Fig. 1], except that the passivation layer 19 does not extend over the sides and part of the top face of the layer 33. In other words, the second passivation layer 19 is formed by a part of the first passivation layer which extends (continuously) to the drain contact metallization 31. In this embodiment, the first passivation layer 17 and the second passivation layer 19 are in one piece (the separation line between the passivation layers 17 and 19 in Figures 4 and 5C is for illustrative purposes only).

[0116] For example, the passivation layer 17 is made of alumina and the passivation layer 19 is made of AlN.

[0117] Figures 5A, 5B and 5C are cross-sectional views illustrating the steps of an example manufacturing process for the HEMT 116 transistor shown in [Fig.4].

[0118] The manufacturing process for transistor 116 illustrated in [Fig. 4] includes, for example, steps similar to those illustrated in Figures 2A to 2C, with the difference that the passivation layer 17 is made of alumina. Starting from the formation of layers 17 and 33, as illustrated in relation to [Fig. 2C] and reproduced in [Fig. 5A], in this embodiment, a portion of the alumina layer 17 is transformed by chemical reaction into an aluminum nitride layer forming the passivation layer 19.

[0119] [Fig. 5B] illustrates a structure obtained after an etching step of the insulating layer 33 of the structure illustrated in [Fig. 5A]. Unlike the step illustrated in [Fig. 2D] for the fabrication of transistor 110, in [Fig. 5B] the etching of layer 33 is stopped on the upper surface of layer 17, so as to leave layer 17 even outside the vertical alignment of layer 33.

[0120] Fig. 5C illustrates a transformation step of the part of the alumina passivation layer 17 not covered by the aluminum nitride layer 33 to form the passivation layer 19.

[0121] For example, the transformation step is carried out by annealing the structure illustrated in [Fig. 5B] under ammonia. During this step, oxygen is degassed from layer 19 and replaced by nitrogen.

[0122] Alternatively, the transformation step is carried out by depositing a nitride layer on the upper face of the structure at the end of the step illustrated in relation to [Fig. 5B], so as to cover the upper face of the passivation layer 17 and of the insulating layer 33, before a heating treatment applied to the entire structure.

[0123] At the end of this step, the manufacturing process of transistor 116 is, for example, identical to that described in relation to Figures 2E to 2J, except that a passivation layer 19 is not deposited during the step illustrated in [Fig.2E].

[0124] In the embodiment of [Fig.4] and Figures 5A to 5C, the use of two passivation layers 17 and 19 of different chemical nature between the gate and the drain of the transistor advantageously improves the trade-off between the resistance in the on-state and the leakage currents in the off-state of the transistor, with a single deposit of passivation material.

[0125] To this end, an embodiment provides a method for manufacturing a HEMT transistor, comprising the following successive steps: a) the formation of a first semiconductor layer 13; b) the formation of a grid 15 on a first surface of the first semiconductor layer 13; c) the deposition of a first dielectric material on the sides of the grid 15 and on said surface of the first semiconducting layer 13; d) the formation of an insulating layer 33 on a first part of said first dielectric material, located on the sides of the grid 15 and near the grid; e) the processing of the first dielectric material, in a second part next to the first part, to transform the first dielectric material into a second dielectric material.

[0126] According to one embodiment, the first dielectric material is alumina.

[0127] According to one embodiment, the second dielectric material is nitride aluminum.

[0128] According to one embodiment, the first semiconductor layer 13 is based on gallium nitride, for example on aluminum-gallium nitride.

[0129] According to one embodiment, the first semiconductor layer 13 is in contact, by a second surface opposite to the first surface, with a second semiconductor layer 23.

[0130] According to one embodiment, the second semiconductor layer 23 is made of gallium nitride.

[0131] According to one embodiment, the process includes the formation of a source contact metallization 29 and a drain contact metallization 31.

[0132] According to one embodiment, step e) includes annealing under ammonia.

[0133] According to one embodiment, step e) includes a step of forming a nitride layer on the insulating layer, followed by a heat treatment step.

[0134] Various embodiments and variations have been described. The person skilled in the art It will be understood that certain features of these various embodiments and variants could be combined, and other variants will become apparent to a person skilled in the art. In particular, it may be foreseen that ohmic contact metallizations, for example source and drain contact metallizations, are formed before the formation of the gate contact metallization.

[0135] Furthermore, although the first embodiment was described with an aluminum nitride passivation layer 17, the passivation layer 17 may consist of a first aluminum nitride sublayer and a second sublayer, for example, of alumina, the first and second sublayers being in contact with each other and the first aluminum nitride sublayer covering the upper surface of the second sublayer. In this variant, the etching step illustrated in [Fig. 2D] includes etching the layer 33 and etching the stack of the first and second sublayers in order to expose a portion of the upper surface of the semiconductor layer 13 for the subsequent deposition of the passivation layer 19 and the insulating layer 33.

[0136] Furthermore, although an example embodiment in which the gate of the transistor 15 is in contact with the upper surface of the upper semiconductor layer 13 has been described above, alternatively, the gate 15 can be separated from the semiconductor layer 13 by a gate insulator layer.

[0137] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Claims

1. HEMT transistor comprising - a first semiconductor layer (13); - a gate (15) arranged on a first surface of the first semiconductor layer (13); - a first passivation layer (17) comprising at least one sub-layer made of a first dielectric material on the sides of the gate, the first passivation layer further extending over a first portion of said surface of the first semiconductor layer; and - a second passivation layer (19), distinct from the first passivation layer (17), comprising at least one sub-layer made of the same first dielectric material on a second portion of said surface of the first semiconductor layer next to the first passivation layer.

2. The transistor of claim 1, wherein the first dielectric material is aluminum nitride.

3. Transistor according to claim 1 or 2, in which the first semiconductor layer (13) is based on gallium nitride, for example aluminum-gallium nitride.

4. Transistor according to any one of claims 1 to 3, comprising a source contact metallization (29) and a drain contact metallization (31), respectively arranged on either side of the gate (15).

5. A transistor according to claim 4, wherein the first passivation layer (17) extends laterally from the gate (15) to the drain contact metallization (31), over only a portion of the surface between the gate (15) and the drain contact metallization (31), the first passivation layer (17) further extending laterally from the gate (15) to the source contact metallization (29).

6. A transistor according to any one of claims 4 or 5, wherein the second passivation layer (19) extends laterally from an edge of the first passivation layer (17) located between the gate (15) and the drain contact metallization (31), to the drain contact metallization (31).

7. A transistor according to any one of claims 1 to 6, wherein the first passivation layer (17) is covered with a layer insulating layer (33), the second passivation layer (19) covering the side of the insulating layer (33) located between the gate (15) and the drain contact metallization (31) and extending over a portion of the insulating layer (33) towards the gate (15).

8. A transistor according to any one of claims 1 to 7, wherein the first passivation layer (17) comprises a first sub-layer (171) and a second sub-layer (173), the first sub-layer (171) being made of the first dielectric material, the second sub-layer (173) being made of a second dielectric material different from the first dielectric material and the second sub-layer (173) covering the upper face of the first sub-layer (171).

9. The transistor of claim 8, wherein the second dielectric material is alumina.

10. A method of manufacturing a HEMT transistor, comprising the following successive steps: a) forming a first semiconductor layer (13); b) forming a gate (15) on a first surface of the first semiconductor layer (13); c) forming: a first passivation layer (17) comprising at least one sub-layer made of a first dielectric material on the sides of the gate, the first passivation layer further extending over a first portion of said surface of the first semiconductor layer (13), and a second passivation layer (19), distinct from the first passivation layer (19), comprising at least one sub-layer made of the same first dielectric material on a second portion of said surface of the first semiconductor layer next to the first passivation layer.

11. The method of claim 10, wherein during step c), the first passivation layer (17) is formed before the second passivation layer (19), step c) comprising: - a step of depositing the first passivation layer (17); - a step of depositing an insulating layer (33); - a step of partially etching the first passivation layer (17) and the insulating layer (33); and - a step of depositing the second passivation layer (19) on the upper face of the first semiconductor layer (13) and of the insulating layer (33).

12. The method of claim 10, wherein: the first passivation layer (17) comprises a first sub-layer (171) and a second sub-layer (173), the first sub-layer (171) being made of the first dielectric material, the second sub-layer (173) being made of a second dielectric material different from the first dielectric material and the second sub-layer (173) covering the upper face of the first sub-layer (171), and step c) comprises: - a step of depositing the first sub-layer (171); - a step of depositing the second sub-layer (173); - a step of depositing an insulating layer (33); - a step of partially etching the first passivation layer (17) and the insulating layer (33); and - a step of depositing the second passivation layer (19) on the upper face of the first semiconductor layer (13) and the insulating layer (33).

13. Method according to claim 10, wherein during step c), the first (17) and the second (19) passivation layers are coated during a deposition step, step c) being preceded by a local heat treatment step.

14. Method according to claim 10, in which step c) successively comprises a step of depositing the first passivation layer (17) and a step of depositing the second passivation layer (19), the second passivation layer (19) being deposited by a deposition method different from the method of depositing the first passivation layer (17).

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