Power electronic module with thermal delay element during a short circuit

Abstract

Power electronic module (10) comprising a substrate (11) comprising at least one power circuit (11c), said module (10) comprising at least one main interconnection joint (13) secured to the power circuit (11c) and at least one semiconductor (12) comprising a metallized upper surface (12b) and a lower surface (12a) assembled to the power circuit (11c) via the main interconnection joint (13). The module comprises at least one secondary interconnection joint (17) secured to the metallized upper surface (12b) of the semiconductor (12) and at least one projection (20) provided with a thermal retardation capacity and secured to said metallized upper surface (12b) via the secondary interconnection joint (17). Figure for abstract: [Fig 1]

Description

Title of the invention: Power electronic module with thermal delay element during a short circuit Technical field of the invention

[0001] The present invention relates to so-called power modules, i.e. modules used in the field of power electronics.

[0002] The invention finds a particular application in the field of aeronautics.

[0003] Power electronics modules are integrated into converters required for the electrification of propulsion and non-propulsion systems on board aircraft. They enable the conversion of electrical energy from the main network (115V AC, 230V AV, 540V DC, etc.) into several forms (AC / DC, DC / AC, AC / AC and DC / DC). State of the prior art

[0004] In a known manner, a power module comprises semiconductors controlled by external electronics. Such components mainly adopt two stationary states (a passing state, allowing the conduction of a current or a blocked state, preventing any conduction of current) as well as a transient state, through which the component passes to go from the passing state to the blocked state, or vice versa.

[0005] A fault external to the power module may occur, significantly increasing the value of the current seen by the semiconductors in conduction, in particular under the effect of the power supplied by an external voltage source.

[0006] We know the semiconductor component called MOSFET, acronym for “metal-oxide-semiconductor field-effect transistor” in Anglo-Saxon terms.

[0007] Such a semiconductor can be made using Silicon, such as silicon carbide, a chemical compound of formula SiC.

[0008] The increase in the current value will induce the short-circuiting of the semiconductor, in particular in the case of a MOSFET-SiC, after thermal runaway. This “short-circuit” state is not always desired, because the user then no longer has control over the control of the semiconductor concerned.

[0009] It is therefore impossible to control the semiconductor(s) in the open state.

[0010] Furthermore, the energy dissipated in the power module then becomes very significant and can lead to the destruction of all or part of the electronic power module. The failure of the electronic power module results in the loss of availability of the equipment and constrains the entire electrical chain both upstream and downstream.

[0011] The power modules currently designed are primarily defined to meet needs such as: maximum size, mounting type and compliance with functional, performance, environmental, efficiency or even lifetime and / or reliability requirements. However, they do not always aim to meet a requirement aimed at obtaining an open circuit type failure mode, in the aforementioned fault cases.

[0012] Improvement of known power modules is a necessity. Statement of the invention

[0013] The present invention therefore aims to overcome the aforementioned drawbacks.

[0014] The aim of the invention is therefore to avoid the degradation of the semiconductors of a power module in the event of overheating linked to a short circuit.

[0015] More particularly, the present invention aims to meet a requirement aimed at obtaining an open circuit type failure mode, in the cases of faults described above.

[0016] The subject of the invention is an electronic power module comprising a substrate comprising at least one power circuit, said module comprising at least one main interconnection joint secured to the power circuit and at least one semiconductor or semiconductor component extending along an extension plane, for example horizontal, and comprising a metallized upper surface and a lower surface assembled to the power circuit via the main interconnection joint.

[0017] The power electronic module comprises at least one secondary interconnection joint secured to the metallized upper surface of the semiconductor and at least one element or projection provided with a thermal retardation capacity and secured to said metallized upper surface via the secondary interconnection joint.

[0018] It is of interest for a user to be able to have an electronic power module which, subjected to short-circuit conditions, due to an internal and / or external fault, is able to adopt an open circuit, without being subject to violent degradation, such as an explosion for example.

[0019] The thermal connection between the thermal retardation projection and the semiconductor via the additional connection joint makes it possible to limit the increase in temperature of the outer surface of the semiconductor. By doing so, an open-circuit failure mode of the semiconductor is achieved.

[0020] The thermal delay projection is an additional element to an electrical connection, which may be of the “wire bonding” type.

[0021] It is preferable that the contact surface between the thermal retardation projection and the metallized upper surface of the semiconductor is maximum, with the constraint that this contact surface will be limited by the surface occupied by the electrical connections such as, for example, wire bonding type connections.

[0022] The thermal retardation projection makes it possible to provide thermal inertia on the metallized outer surface, called metallization, of the semiconductor which is highly stressed during an open circuit operating mode of the semiconductor, which makes it possible to avoid degradation of said semiconductor.

[0023] Indeed, in the case of a short circuit, the current flowing through the semiconductor is greater than the current for which said semiconductor is designed. The temperature of the areas of the semiconductor carrying the main current increases significantly, despite the short duration of the short circuit. Generally, this is the surface metallization area, i.e. the metallized upper surface of the semiconductor, poorly thermally connected to the substrate, which is a cold source.

[0024] Under the stress of a significant quantity of energy concentrated at the level of the surface metallization zone of the semiconductor, the metallization can change state and pass from a solid state to a liquid state, then gaseous for a part of the constituents of the metallization and finally again to a solid state having surface asperities.

[0025] The dynamics of this transformation are directly linked to the temperature rise rate of the metallization. It therefore depends on the energy to be dissipated but also on the nature of the thermal exchanges between the metallization and its environment. The greater the transformation dynamics, the greater the risk of obtaining a semiconductor in an uncontrollable short-circuit state. On the other hand, the lower the dynamics, the lower this risk and it is possible to obtain a semiconductor forced into an open state, without suffering uncontrollable degradation.

[0026] The thermal retardation projection makes it possible to establish efficient thermal contact with the metallization of the semiconductor acting as a thermal retarder. The capacity of the thermal retardation projection to play this role of thermal retarder is determined by the thermal conduction performance as well as the excess thermal inertia provided by the assembly of the semiconductor with the thermal retardation projection.

[0027] The production of such an assembly makes it possible to force the transition of the semiconductor from the short-circuit state to the open-circuit state, ensuring that a “clean” degradation is obtained within the power electronic module, i.e. not damaging other components of the power electronic module.

[0028] For example, the thermal retardation protrusion extends in a direction perpendicular to the extension plane of the semiconductor.

[0029] For example, the thermal retardation projection has a cylinder shape.

[0030] Alternatively, any other shape could be provided for said thermal retardation projection, for example semi-spherical, hollow cylindrical, parallelepiped.

[0031] It could also be provided that the thermal retardation projection is in the form of a metal strip.

[0032] The thermal retardation projection is, for example, made of conductive material, for example metallic, for example copper.

[0033] According to one embodiment, the power electronic module comprises a plurality of thermal retardation protrusions distributed on the metallized upper surface of the semiconductor.

[0034] The semiconductor may comprise a drain disposed on the lower face and a gate and a source disposed on the upper face, the semiconductor further comprising a metallization of the drain, the gate and the source.

[0035] For example, the thermal retardation protrusions are distributed around the semiconductor source.

[0036] For example, the drain of the semiconductor is connected to the substrate by a main interconnect joint or solder and thus has a good thermal connection with the substrate.

[0037] For example, the source of the semiconductor is connected to the substrate by the wiring wires, for example by a welding process technique which makes it possible to make a wire bond, or "wire bonding" in English terms, ensuring an electrical connection between the source of the semiconductor and the substrate. This connection does not always allow for a good thermal connection.

[0038] According to one embodiment, the main interconnection joint is in the form of a paste, for example a solder, and the secondary interconnection joint is in the form of a paste, for example a solder, the paste forming the main interconnection joint having a liquidus greater than the liquidus of the paste forming the secondary interconnection joint. This allows the semiconductors to remain in position during the step of assembling the thermal retardation protrusions.

[0039] For example, the main interconnection joint is connected to the substrate, in particular to the upper conductive layer, by soldering.

[0040] By way of non-limiting example, the substrate successively comprises a lower conductive layer, an electrically insulating layer and an upper conductive layer.

[0041] The conductive lower layer and upper layer are, for example, made of metallic material.

[0042] The electrically insulating layer is, for example, made of ceramic material.

[0043] For example, said electrically insulating layer is arranged between the conductive lower layer and upper layer.

[0044] The conductive lower layer and upper layer can be assembled to the electrically insulating layer by one of the various known techniques, such as for example by brazing, or "active metal brazing", acronym AMB in English terms, or by direct bonded copper, acronym DBD in English terms, or by direct bonded aluminum, acronym DBA in English terms.

[0045] Alternatively, other layers forming the substrate could be provided.

[0046] The conductive upper layer forms a power circuit on which power semiconductor components are assembled.

[0047] For example, the electronic power module may further comprise connectors making it possible to connect the electronic power module to external electrical elements.

[0048] According to one embodiment, the electronic power module further comprises at least one connector secured to the power circuit and at least one wiring wire electrically connecting the connector and the semiconductor, in particular the source of the semiconductor.

[0049] For example, and in a non-limiting manner, the electronic power module comprises a housing, for example made of plastic material such as polymer surrounding the semiconductor components and secured to the substrate, in particular by bonding using an adhesive.

[0050] For example, the housing may be filled with an encapsulant, for example a gel or an epoxy resin to provide mechanical and electrical protection of the power components and wiring wires.

[0051] For example, the semiconductor is an electronic chip known as MOSFET, an acronym for “metal-oxide-semiconductor field-effect transistor” in English terms, and may comprise a silicon carbide, a chemical compound with the formula SiC.

[0052] Alternatively, it could be provided that the semiconductors comprise other materials.

[0053] According to a second aspect, the invention relates to a method of manufacturing an electronic power module comprising a substrate comprising at least one power circuit, in which: - the substrate is prepared; - at least one main interconnection joint or solder is deposited on the power circuit of the substrate; and - at least one semiconductor is assembled to the power circuit of the substrate via the main interconnection joint, for example by soldering or sintering techniques.

[0054] According to the method: - at least one secondary interconnection joint or solder is deposited on a metallized upper surface of the semiconductor; and - at least one thermal retardation projection is assembled on said metallized upper surface via the secondary interconnection joint.

[0055] For example, the thermal retardation protrusion extends in a direction perpendicular to the extension plane of the semiconductor.

[0056] For example, the method further comprises a step of electrically connecting the semiconductor, and in particular the source, by wiring wires, for example by a welding process technique which makes it possible to make a wire bonding. This makes it possible to ensure an electrical connection between the source of the semiconductor and the substrate.

[0057] In a non-limiting manner, the method could also provide for subsequent steps, such as assembling the cover, injecting an encapsulant, etc. Brief description of the drawings

[0058] Other aims, characteristics and advantages of the invention will appear on reading the following description, given solely by way of non-limiting example, and made with reference to the indexed drawings in which:

[0059] [Fig.l], is a schematic sectional view of an electronic power module according to the invention;

[0060] [Fig.2], is a perspective view of the power electronic module of [Fig.l];

[0061] [Fig.3] illustrates the steps of a flowchart of a manufacturing process of the power electronic module of [Fig.l]; and

[0062] [Fig.4], [Fig.5], [Fig.6], [Fig.7] and [Fig.8] represent the power electronic module of [Fig.l] during the different stages of the manufacturing process of [Fig.3], the module has been represented here without a cover.

[0063] Detailed description of at least one embodiment

[0064] As illustrated in [Fig.l], a power electronic module 10 comprises a substrate 11.

[0065] By way of non-limiting example, the substrate 11 successively comprises a lower conductive layer 11a, an electrically insulating intermediate layer 11b and an upper conductive layer 11e.

[0066] The lower and upper conductive layers 11a, 11e are, for example, made of metallic material.

[0067] The electrically insulating intermediate layer 11b is, for example, made of ceramic material.

[0068] Said electrically insulating intermediate layer 11b is arranged between the conductive lower layer 11a and upper layer 11c.

[0069] The lower layer 11a and the upper layer 11c are assembled to the electrically insulating intermediate layer 11b by one of the various known techniques, such as for example by brazing, or "active metal brazing", acronym AMB in English terms, or by direct bonded copper, acronym DBD in English terms or by direct bonded aluminum, acronym DBA in English terms.

[0070] Alternatively, other layers forming the substrate 11 could be provided.

[0071] The upper conductive layer 1 forms a power circuit on which power semiconductor components 12 are assembled. Here, a number of six semiconductors 12 are assembled on the upper conductive layer 11c. Alternatively, a number of semiconductors greater than or equal to one could be provided.

[0072] As illustrated, the power electronic module 10 further comprises main interconnect joints 13 via which the semiconductor components 12 are assembled to the power circuit 11c.

[0073] The main interconnecting joints 13 may be in the form of a paste, for example a solder or a solder preform.

[0074] The main interconnection joints 13 can be connected to the substrate 11, in particular to the upper conductive layer 1, by soldering.

[0075] The assembly of the main interconnection joints 13 with the substrate 11 is known and will not be described further.

[0076] The electronic power module 10 may further comprise connectors (not shown) making it possible to connect the electronic power module 10 to external electrical elements (not shown).

[0077] As illustrated, and in a non-limiting manner, the electronic power module 10 further comprises connectors 14 and electrical connections 15, for example in the form of wiring wires, electrically connecting the connectors 14 and the semiconductors 12.

[0078] As illustrated in [Fig.l], and in a non-limiting manner, the electronic power module 10 comprises a housing 16, for example made of plastic material such as polymer surrounding the semiconductor components 12 and secured to the substrate 11, in particular by bonding using an adhesive (not shown).

[0079] The housing 16 may be filled with an encapsulant, for example a gel or an epoxy resin to provide mechanical and electrical protection of the components of power 12, 14 and 15 wiring wires.

[0080] The semiconductors 12 comprise, for example, an electronic chip known as MOSFET, an acronym for “metal-oxide-semiconductor field-effect transistor” in English terms, and may comprise a silicon carbide, a chemical compound with the formula SiC.

[0081] Alternatively, it could be provided that the semiconductors 12 comprise other materials.

[0082] Generally, each semiconductor 12 extends along a horizontal plane and comprises a lower face 12a, on the substrate 11 side, and a metallized upper face 12b.

[0083] By “metallized upper face” is meant that the upper face or surface 12b of the semiconductor 12 is provided with a surface metallization.

[0084] Each semiconductor 12 comprises a drain (not visible in the figures) arranged on the lower face 12a and a gate 12c and a source 12d arranged on the metallized upper face 12b. Each semiconductor 12 has a drain metallization, the gate 12c and the source 12d.

[0085] The drain of the semiconductor 12 is connected to the substrate 11 by a main interconnection joint 13 or solder and thus has a good thermal connection with the substrate 11.

[0086] The source of the semiconductor 12 is connected to the substrate 11 by the wiring wires 15, for example by a welding process technique which makes it possible to make a wire connection, or "wire bonding" in English terms, ensuring an electrical connection between the source of the semiconductor 12 and the substrate 11, but does not allow, via this connection, to have a good thermal connection.

[0087] As illustrated, the power electronic module 10 further comprises a plurality of projections 20 each provided with a thermal retardation capacity and secured to each semiconductor 12 using a secondary interconnection joint 17.

[0088] Each projection 20 having a thermal retardation capability is called a thermal retardation projection.

[0089] In other words, the so-called thermal retardation projections 20 are assembled on the metallized upper surface 12b of the semiconductors 12 via the secondary interconnection joints 17.

[0090] The secondary interconnecting joints 17 may be in the form of a paste, for example a solder.

[0091] The paste forming the main interconnection joints 13 has a liquidus greater than the liquidus of the paste forming the secondary interconnection joints 17 so that the semiconductors 12 do not move during the step of assembling the projections. thermal retardation.

[0092] In a phase diagram, the curve that separates a liquid single-phase domain from a two-phase domain comprises a liquid and a solid solution.

[0093] The thermal retardation projections 20 extend, here, in a direction perpendicular to the extension plane of the semiconductors 12.

[0094] As illustrated, the thermal retardation projections 20 each have a cylindrical shape. Alternatively, any other shape could be provided for said thermal retardation projections 20, for example semi-spherical, hollow cylindrical, parallelepiped or in the form of a metal strip.

[0095] The thermal retardation projections 20 are made of metallic material, for example copper.

[0096] As illustrated, each semiconductor 12 includes three secondary interconnection joints 17 and three thermal retardation projections 20, each integral with a secondary interconnection joint 17.

[0097] Alternatively, it could be provided that each semiconductor 12 comprises at least one secondary interconnection joint 17 and at least one thermal retardation projection 20, each integral with a secondary interconnection joint 17.

[0098] It could also be provided that several thermal retardation projections 20 are assembled on a single secondary interconnection joint 17.

[0099] The thermal retardation projections 20 are here distributed on the metallized upper surface 12b of each semiconductor 12 around the source 12d.

[0100] [Fig.3] illustrates the steps of a method 100 for manufacturing the electronic power module 10 of FIGS. 1 and 2.

[0101] The method 100 for manufacturing the electronic power module 10 comprises a first step 101, visible in [Fig.4], of preparing the substrate and the connectors 14, a second step 102, visible in [Fig.5], of depositing a main interconnection joint 13 or solder on the substrate 11 for the assembly, in step 103, of the semiconductors 12.

[0102] During step 103, visible in [Fig.6], the semiconductors 12 are assembled to the substrate 11 by soldering or sintering techniques.

[0103] The method 100 further comprises a step 104, visible in [Fig.7], of electrically connecting the semiconductors 12, and in particular the source 12d, by the wiring wires 15, for example by a welding process technique which makes it possible to make a wire bonding, ensuring an electrical connection between the source of the semiconductor 12 and the substrate 11.

[0104] Steps 101, 102, 103 and 104 are known and will not be described further.

[0105] As illustrated, the method 100 further comprises a step 105 of depositing one or more secondary interconnection joints 17 or secondary solders on the surface upper 12b metallized of each semiconductor 12, as visible in [Fig.8].

[0106] The secondary interconnection joints 17 allow the assembly, at step 106, of thermal retardation projections 20 on the semiconductors 12, as visible in [Fig.2]. This assembly can be done by sintering technique or by reflow of the interconnection joint 17.

[0107] It is also conceivable that step 105 consists of depositing a metal paste, for example by a technique known as “dispensing” in English terms, on the metallized upper surface 12b of the semiconductor 12, after wiring the electrical connections or wiring wires 15. The implementation of rapid reflow may prove necessary to guarantee the best thermal contact with the surface metallization of the semiconductor chip.

[0108] In a non-limiting manner, the method 100 could also provide subsequent steps (not shown), of assembling the cover 16, of injecting an encapsulant, etc.

[0109] The thermal retardation projection(s) 20 make it possible to establish efficient thermal contact with the metallized upper surface 12b of the corresponding semiconductor 12 acting as a thermal retarder. The assembly of the semiconductor 12 with the thermal retardation projection(s) makes it possible to force the transition of the semiconductor 12 from the short-circuit state to the open-circuit state, ensuring that a “clean” degradation is obtained within the power electronic module, i.e. not damaging other components of the power electronic module.

Claims

Claims

1. Power electronic module (10) comprising a substrate (11) comprising at least one power circuit (11c), said module (10) comprising at least one main interconnection joint (13) secured to the power circuit (11c) and at least one semiconductor (12) extending along an extension plane, and comprising a metallized upper surface (12b) and a lower surface (12a) assembled to the power circuit (11c) via the main interconnection joint (13), characterized in that it comprises at least one secondary interconnection joint (17) secured to the metallized upper surface (12b) of the semiconductor (12) and at least one projection (20) provided with a thermal retardation capacity and secured to said metallized upper surface (12b) via the secondary interconnection joint (17).

2. Power electronic module (10) according to claim 1, in which the thermal retardation projection (20) has a shape of a cylinder or a metal strip.

3. Power electronic module (10) according to any one of the preceding claims, in which the thermal retardation projection (20) is made of conductive material, preferably metallic.

4. Power electronic module (10) according to any one of the preceding claims, comprising a plurality of thermal retardation projections (20) distributed on the metallized upper surface (12b) of the semiconductor (12).

5. Power electronic module (10) according to any one of the preceding claims, in which the semiconductor (12) comprises a drain arranged on the lower face (12a) and a gate (12c) and a source (12d) arranged on the metallized upper face (12b), the semiconductor (12) further comprising a metallization of the drain, the gate and the source.

6. Power electronic module (10) according to claims 4 and 5, wherein the thermal retardation projections (20) are distributed around the source (12d) of the semiconductor (12).

7. A power electronic module (10) according to any one of the preceding claims, wherein the primary interconnection joint (13) is in the form of a paste and the secondary interconnection joint (17) is in the form of a paste, the paste forming the joint. main interconnection joint (13) has a liquidus greater than the liquidus of the secondary interconnection joint paste (17).

8. Power electronic module (10) according to any one of the preceding claims, further comprising at least one connector (14) integral with the power circuit (11e) and at least one wiring wire (15) electrically connecting the connector (14) and the semiconductor (12).

9. Method (100) for manufacturing a power electronic module (10) comprising a substrate (11) comprising at least one power circuit (11c), in which: - the substrate (11) is prepared; - at least one main interconnection joint (13) is deposited on the power circuit (11c) of the substrate (11); and - at least one semiconductor (12) is assembled to the power circuit (11c) of the substrate (11) via the main interconnection joint (13); characterized in that according to the method: - at least one secondary interconnection joint (17) is deposited on a metallized upper surface (12b) of the semiconductor (12); and - at least one thermal retardation projection (20) is assembled on said metallized upper surface (12b) via the secondary interconnection joint (17).

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