Power factor correction device for an automotive vehicle charger

Abstract

One method comprises receiving a sinusoidal setpoint current in phase with a sinusoidal supply voltage; generating a regulated current corresponding to the current drawn by the electrical load; generating a measured current from the regulated current; generating an error signal by comparing the sinusoidal setpoint current with the measured current; and generating the regulated current, including: generating a gain factor based on the error signal; applying the gain factor to the error signal to generate a weighted error signal; and applying a regulation function to the weighted error signal to generate the regulated current. Figure for the abstract: Fig. 6

Description

Title of the invention: Power factor correction device for an automotive vehicle charger. Technical field

[0001] This description relates to a power factor correction device and an on-board automotive charger incorporating such a charger. Technical background

[0002] On-board car chargers can be connected to a wide variety of power supply networks. One of their characteristics is line impedance (primarily line inductance), which depends essentially on the distance from the vehicle to the power transformer and the quality of the electrical cable(s) through which the charger is connected to the power supply network. A good approximation is to consider that the equivalent line inductance increases from 1pH to 1.6pH per linear meter of electrical cable.

[0003] This line inductance adds to the power inductance and affects the stability and performance of the power factor correction module integrated into the on-board charger. Therefore, there is a need to improve the situation. Summary

[0004] A first aspect relates to a power factor correction device for an on-board electric charger of a motor vehicle battery.

[0005] According to a first aspect, a power factor correction device for an on-board electric charger of a motor vehicle battery is described.The power factor correction device includes a current regulation loop; the regulation loop comprising a forward chain generating a regulated current corresponding to the current drawn by the electric charger and a feedback chain generating a measured current from the regulated current; the regulation loop being configured to receive as input a sinusoidal setpoint current in phase with a sinusoidal supply voltage and to generate an error signal by comparing the sinusoidal setpoint current with the measured current supplied by the feedback chain; the forward chain comprising a controller of the regulation loop, a gain adapter configured to generate a gain factor, an amplifier configured to apply the gain factor to the input signal of the controller, the gain factor being generated on the basis of the error signal.

[0006] In one or more embodiments, the gain adapter is configured to generate the gain factor based on a tracking error of the control loop determined from the error signal.

[0007] In one or more embodiments, the tracking error is determined as the effective value of the error signal.

[0008] In one or more embodiments, the tracking error is determined as the average, over a period of the supply voltage, of the error signal.

[0009] In one or more embodiments, the gain adapter is configured to generate the gain factor based on a weighting coefficient of the open-loop transfer function gain.

[0010] In one or more embodiments, the gain adapter is configured to determine an error rate from the error signal and to normalize the error rate between 0 and 1 based on the sinusoidal setpoint current or the measured current so as to generate a normalized error rate.

[0011] In one or more embodiments, the gain adapter is configured to compare the normalized error rate with a setpoint error rate.

[0012] According to another aspect, an electric battery charger intended for installation in a motor vehicle is described. The electric charger includes a power factor correction device according to the first aspect.

[0013] A second aspect relates to a power factor correction method for an on-board electric charger of a motor vehicle battery.

[0014] The method comprises: receiving a sinusoidal setpoint current in phase with a sinusoidal supply voltage; generating a regulated current corresponding to the current drawn by the electric charger; generating a measured current from the regulated current; generating an error signal by comparing the sinusoidal setpoint current with the measured current; generating the regulated current comprising: generating a gain factor based on the error signal; applying the gain factor to the error signal to generate a weighted error signal; applying a regulation function to the weighted error signal to generate the regulated current.

[0015] A third aspect relates to a computer program comprising instructions adapted to cause the execution of the steps of a power factor correction process according to the second aspect. These instructions are intended to be stored in a device's memory, loaded, and then executed by a processor of that device.

[0016] In general, the device according to the first aspect may include means for carrying out one or more or all of the steps of a power factor correction process according to any of the embodiments described in this document.

[0017] These means may include software and / or hardware means. These means may include, for example, one or more configured circuits to perform one or more or all of the steps of a power factor correction process according to the second aspect or according to any of the embodiments described in this document. These means may include, for example, at least one processor and at least one memory comprising instructions, the memory and instructions being configured to, together with the processor, cause a device to perform one or more or all of the steps of a power factor correction process according to any of the embodiments disclosed in this document.

[0018] The term "circuit" may refer to one or more analog and / or digital circuits, whether or not combined with software and / or firmware, to perform one or more functions described in this document. These circuits may include one or more memories and / or one or more hardware processors (e.g., a microprocessor or microcontroller) that cooperate to enable a host device including this circuit to implement one or more functions described in this document. These hardware processors may or may not require software (e.g., firmware) to implement the corresponding function(s). Brief description of the Figures

[0019] Other features and advantages will become apparent upon reading the detailed description that follows, for which reference should be made to the attached drawings, including:

[0020] [Fig-1] - [Fig.1] schematically represents a charger embedded in a motor vehicle according to an example of implementation.

[0021] [Fig.2] - [Fig.2] shows curves illustrating the effect on the current of a power factor correction device according to an example embodiment.

[0022] [Fig.3] - [Fig.3] schematically represents a system comprising an electrical supply network and a charger including a power factor correction device according to an example embodiment in the case where the network includes line inductances.

[0023] [Fig.4] - [Fig.4] schematically represents a system comprising an electrical supply network and a charger including a power factor correction device according to an example embodiment in the case where the line inductances are reduced to the power inductances to constitute an equivalent inductance

[0024] [Fig.5] - [Fig.5] shows the open-loop transfer function of a power factor correction device with different types of controller according to embodiment examples and for two line inductance values.

[0025] [Fig.6] - [Fig.6] schematically represents a correction device of power factor incorporating an adapter of the open-loop transfer function gain according to an example embodiment.

[0026] [Fig.7] - [Fig.7] schematically represents an adaptation device for the open-loop transfer function gain for a power factor correction device according to an example embodiment.

[0027] [Fig.8] - [Fig.8] is a flowchart of a method for activating a device gain adaptation for a power factor correction device according to an example implementation.

[0028] [Fig.9] - Fig.9 shows curves illustrating the operation of a device power factor correction in the absence of gain matching according to an example implementation.

[0029] [Fig. 10] - the [Fig. 10] shows curves illustrating the operation of a power factor correction device with gain matching according to an example embodiment. Detailed description

[0030] In the description that follows, identical, similar or analogous elements will be designated by the same reference numerals.

[0031] This description relates to a vehicle charger (also called an on-board charger) installed in a motor vehicle and a power factor correction device for such a charger. Such a charger is called a "High Voltage On-board Charger" in Anglo-Saxon terminology.

[0032] Fig. 1 schematically represents such a charger 100.

[0033] During vehicle charging, it is this charger 100 inside the vehicle that receives the voltage VGrid supplied by the electrical power grid and optimizes the charging of the battery 190. The voltage supplied by the electrical grid, referred to here as the supply voltage VGR1D, is an alternating, sinusoidal voltage with a frequency considered to be fixed (in practice, this frequency varies around a reference value, for example 50 Hz, depending on the different loads / power sources connected to the grid). This voltage can be supplied via a single-phase or three-phase electrical power source. For the sake of simplicity, only the single-phase case will be described in detail. However, the invention is also applicable to a three-phase source, with the gain matching being applied to each phase.

[0034] The charger contains a power factor correction device 110 (also referred to here as PFC for "Power Factor Corrector" according to Anglo-Saxon terminology) whose purpose is to draw a current Io from the electrical network so that the current drawn Io is as sinusoidal as possible and as in phase as possible with the voltage VGR1D of the The power supply network is designed to optimize the power factor. Power factor is related to instantaneous power, which is the product of voltage and current. Therefore, the power factor is maximized when current and voltage are in phase (and have the same sign). This reduces power losses.

[0035] Figure 2 shows the effect of PFC 120 on the current Io drawn by the charger. The shape The current drawn by the charger, passively without corrective action from the PFC, depends on the battery and the PFC 110 and is not necessarily sinusoidal, nor in phase with the sinusoidal supply voltage, as illustrated in [Fig. 2]. According to the example in sub-figure 2A, the current drawn Io, before correction by the PFC, is neither sinusoidal nor in phase with the AC voltage VGR1D of the electrical grid. Power losses are schematically represented in sub-figure 2A and depend, in particular, on the phase shift between the voltage and the current. In sub-figure 2B, we see that the corrected current Io drawn by the charger, as corrected by the PFC, is sinusoidal and in phase with the AC voltage VGrid of the electrical grid.

[0036] The PFC 110 receives the alternating voltage VGR1D from the electrical network as input and supplies a current L to a DC bus 120. The DC bus 120 is also called the "DC link" in Anglo-Saxon terminology. The DC link 120 may include one or more capacitors. In the schematic example in [Fig. 1], only one capacitor Cl is shown.

[0037] The PFC 110 thus ensures power transfer between an alternating input voltage VGR1D and an output voltage, which is a constant direct current voltage, namely the voltage VDc across the DC Link. This voltage can be set to a value, for example, 400 Volts or 800 Volts.

[0038] The output of the DC link 120 is connected to a power transfer device 130 (called "high voltage DC-DC" in Anglo-Saxon terminology) which receives the VDC voltage across the terminals of the DC link 120, performs a power transfer between the DC link with a fixed voltage and the input voltage VBat of the battery 190. The input voltage of the battery VBat is also a DC voltage, but variable: this input voltage VBat of the battery 190 depends on the charge level of the battery 190. The voltage across the terminals of the battery 190 drops as the battery 190 discharges and increases during the charging of the battery 190. The nominal voltage across the terminals of the battery 190, in the fully charged state, can, for example, be 400 Volts or 800 Volts.

[0039] Figures 3 and 4 schematically represent a system comprising a power supply network and a charger including a power factor correction device according to an exemplary embodiment. Compared to [Fig. 3], [Fig. 4] shows the effect of line inductances on the PFC through an additional inductance. applied to power inductances, the sum of which constitutes the equivalent inductance.

[0040] According to what is shown in [Fig. 3] and for this embodiment of the PFC, on each arm in the case of a three-phase power supply, in the charger 300, there is a power inductance denoted LBoost- on each arm. A switching cell 350 includes, for each phase of the supply signal, 2 switches: an upper switch 351 and a lower switch 352. Power transfer occurs between the power supply network and the DC link by an activation and deactivation sequence of these switches so that the power inductance is charged and then discharged in the DC link via the PFC 330. In a known manner, the control signals of these switches are produced by a control device 360 ​​of the PFC 330, from signals produced in the current regulation loop 340 of the PFC. The LBoost power inductance has a nominal value on the order of several hundred qH (micro Henri), for example between 2 and 300 qH.

[0041] According to the electrical supply network 310, the distance from the vehicle to the last power transformer can vary. Therefore, additional inductances, called line inductances Ll1ne, are added to the power inductances. The value of these line inductances depends primarily on the distance between the vehicle being charged and the last power transformer isolating the electrical supply network. This increase in inductance is on the order of 1 qH per meter. For example, for 2 km from the last transformer, the cumulative line inductance on one phase is 2000 qH, or 2 mH.

[0042] A small-signal analysis makes it possible to characterize the effect of line inductances and shows that the value of the cumulative line inductance adds to the power inductance of the phase concerned, so that, as shown in [Fig. 4], for each phase, the equivalent inductance LEQ is the sum of the power inductance LBoost and the line inductance Ll1ne, with LEQ much greater than LBOost-

[0043] For example, with a power inductance of 200 μH, the equivalent inductance, taking into account line inductances, will be 2.2 mH, representing a factor of 10 on the power inductance value. Consequently, the charger's response is significantly altered, particularly the current regulation function implemented by the PFC 330 control device 360, which aims to generate a sinusoidal current as close as possible to the supply voltage.

[0044] The PFC 330 receives the sinusoidal supply voltage as input. If the input current drawn by the PFC 110 is not controlled, the load, i.e., in this case the battery, will dictate the waveform of the current drawn by the charger. The function of the PFC 330 is to ensure that the load draws a sinusoidal current at the input of the DC link.

[0045] The current regulation function is performed by the PFC by means of the current regulation loop 340, which receives as input a sinusoidal setpoint current Iset (or "set point" in Anglo-Saxon terminology) in phase with the sinusoidal supply voltage. The regulation loop thus regulates the current Io drawn by the charger. The amplitude of the sinusoidal setpoint current is adjusted over time: the amplitude at any given instant is that which provides the DC link terminals with sufficient power to meet the battery charging current requirements.

[0046] The PFC current regulation loop can be a digital loop. The current regulation loop comprises a forward path and a feedback path. The forward path includes a current regulation loop controller. This controller can be a digital controller.

[0047] This controller can be, for example, a 1-pole, 1-zero controller (Ip / lz controller) or a PI (proportional-integral) controller.

[0048] PI controllers (numerical expression of HPi(z) = Kp + Ki / z) are a common implementation of current regulation loop controllers because these controllers require a limited number of computational steps and provide high gain at low frequencies. More specifically, as the line impedance increases, the cutoff frequency of the open-loop transfer function decreases, the phase margin (which corresponds to the difference between the phase of the open-loop transfer function and -180° at the frequency corresponding to the zero gain of this same open-loop transfer function) of the current loop decreases, falls below the stability threshold (often considered to be 40 to 45°, stability being more generally determined by the combination of the gain and phase margins), and the system begins to oscillate.

[0049] This is why other types of controllers, such as 1 zero / 1 pole (denoted "Iz / lp"), also called phase-delay controllers, can be used. These controllers are characterized by a lower gain at the fundamental frequency. High line impedance shifts the open-loop transfer function towards a lower gain, resulting in an excessively low gain at the fundamental frequency. Consequently, the ability of the current regulation loop to follow the sinusoidal setpoint signal is reduced, and a permanent error appears.

[0050] The profile (in particular the phase) of the current setpoint signal ISET over time is determined based on the phase detection of the supply voltage by a phase-locked loop (PLL). The amplitude of the current setpoint signal is that which allows the DC link to generate sufficient power to meet the battery charging requirements. To meet the battery's needs, the PFC must therefore draw power from the power supply network. sufficient, which translates into a corresponding amplitude of the current Io drawn at the input of the PFC.

[0051] The total harmonic distortion (THD), which determines the extent to which the drawn current Io contains harmonics of the fundamental frequency, is also considered for the current generation itself. In particular, when the value of the equivalent inductance (sum of the power inductance and the line inductance) increases, this can increase the THD. The control loop can then become so unstable that regulation fails. As the line inductances increase, the phase margin decreases, and the control loop becomes more unstable.

[0052] The current regulation loop controller must be robust in the face of high line impedances. However, the variations in equivalent line inductance from one network outlet to another are so significant that it is not possible to calibrate a PI controller that will guarantee the stability requirements for all inductance values ​​(particularly in terms of gain margin and phase margin).

[0053] In addition, the controller is intended to control the high-frequency switching in such a way as to ensure correct tracking of the sinusoidal waveform of the input voltage, which results in a displacement factor as close as possible to the setpoint signal (factor 1 if the PFC 110 does not manage reactive power control).

[0054] An unintentional mismatch between the current drawn at the input of the PFC 110 and the network voltage can have various effects such as:

[0055] - To produce unexpected reactive power, i.e., power losses which must be dispelled;

[0056] - disrupt the power supply network because the expected power factor is not Respected.

[0057] - increase the apparent power demanded from the power supply network (and (possibly an oversizing of the power supply network).

[0058] Figure 5 shows the open-loop transfer function of a power factor correction (PFC) device with different types of controller according to embodiment examples.

[0059] The curves in subfigures 5A-5B show the delay (phase shift) and attenuation (gain) between the setpoint signal of the current ISET and the current IMES measured for different types of controller, with and without line inductance, according to the frequency of the current.

[0060] More specifically, the Bode plots of subfigures 5A-5B, curves 51, 52 represent the open-loop transfer function (gain in subfigure 5A and phase in subfigure 5B) of a PFC 110 controlled by a PI controller, with a line inductance of 2200pH (curve 52) and without line inductance (curve 51). curves 53 and 54 represent the open-loop transfer function (gain and phase) of a PFC 110 controlled by an Iz / lp controller, with a line inductance of 2200pH (curve 54) and without line inductance (curve 53).

[0061] For both types of controller, the phase of the open-loop transfer function does not depend on the line impedance: for an Iz / lp controller, the phase has a local minimum, whereas the phase tends to decrease to -180 with a PI controller. Consequently, the Iz / lp controller can be made robust to any inductance. This is also applicable to a PI controller.

[0062] However, the Izlp controller has a local minimum and is therefore robust to any line inductance. Indeed, if the line inductance increases, it reduces the gain. The gain will pass through zero at lower frequencies: thus, the phase margin will be obtained at lower frequencies. As the phase increases again from the phase minimum when moving towards increasingly lower frequencies, the phase margin would be even greater, and therefore the system is more stable.

[0063] One disadvantage of an Iz / lp controller compared to a PI controller is a significantly lower open-loop transfer function gain at the fundamental frequency (supply network frequency, typically 50 or 60 Hz): nearly 20 dB, as shown in the curves of subfigure 5A. A low gain at the fundamental frequency leads to a tracking error between the current drawn at the input of the PFC 110 and the setpoint signal ISET.

[0064] On the other hand, an Iz / lp controller cannot be set to provide sufficient gain at the maximum expected value of the line impedance, because this would lead to an open-loop transfer function with no gain margin (which is the difference between the gain in dB of the open-loop transfer function and OdB, at the frequency corresponding to a phase of that same transfer function equal to -180°) when the line impedance is low or non-existent. An Iz / lp controller is less powerful than a PI controller and generates a lower fundamental gain.

[0065] The solution proposed here consists of a real-time adaptation of the open-loop transfer function gain of the current regulation loop. This regulation is implemented by means of a dedicated device, also called an "open-loop transfer function gain adaptation device," or "gain adapter," or, simply, "adapter." This gain adaptation is performed in such a way as to compensate for the effects on the open-loop transfer function gain of the equivalent inductance of the power supply line. The gain adapter can be implemented using an integrating controller.

[0066] This regulation can be implemented by means of a computer program implemented by a 360 PFC control device. The gain adapter can thus being a digital device, forming part of the PFC's 360 control system.

[0067] The gain adapter makes it possible in particular to compensate for the variations produced on the open-loop transfer function by the equivalent inductance due to power inductances and line inductances.

[0068] The gain adapter is designed to minimize the tracking error of the current regulation loop (for example, to minimize the RMS value of the tracking error determined from the error signal) and determines a gain factor F to be applied to the error signal e of the current regulation loop. The gain adapter performs an adaptation (or modulation) of the gain of the open-loop transfer function of the current regulation loop by applying a gain factor determined based on the error signal e. This adaptation (or modulation) can be applied based on the RMS value, normalized with respect to the current itself, of the error signal e.

[0069] Advantageously, the gain adapter is designed to ensure the adaptation of the regulation of the normalized RMS value of the error signal e around a calibratable setpoint which is not fixed at 0% but close to zero (for example, 1%) in order to prevent the strategy from overcompensating the line inductance effect and reducing the gain margin.

[0070] Figure 6 schematically represents a power factor correction device incorporating a gain adapter according to an example embodiment.

[0071] The power factor correction device 600 includes a current regulation loop. The regulation loop includes a forward chain generating a regulated current Io corresponding to the current drawn by the electric charger and a feedback chain acquiring this current (for example, by acquisition in block 630) IMes from the regulated current Io.

[0072] The direct chain of the regulation loop receives at input a sinusoidal setpoint current ISET in phase with a sinusoidal supply voltage and generates an error signal e by comparing the sinusoidal setpoint current with the measured current supplied by the feedback chain.

[0073] The direct chain, comprising a 620 regulator loop controller, a 610 gain adapter configured to generate a gain factor F, and an amplifier 615 to apply the gain factor F in the direct chain to the error signal and generate a weighted error signal, provides input m to the 620 (PI or IzlP) current regulator loop controller. The 620 controller applies a regulation function to the weighted error signal.

[0074] The gain factor is generated on the basis of the error signal.

[0075] According to [Fig.6], the direct chain of the control loop further comprising an integrator block 640 corresponding to the modeling (for example, according to a small signal model) according to the Laplace formalism (using the parameter s) of the inductive effect of the equivalent inductance LEQ.

[0076] Figure 7 schematically represents a gain matching device 700 (or adapter) for a power factor correction device according to an example embodiment of the gain adapter 610 of Figure 6. The gain adapter receives the error signal and generates the gain factor F based on the error signal.

[0077] The gain factor F is generated from the error signal e obtained by comparing (for example, by calculating the difference) the sinusoidal setpoint current ISEt with the measured current IMES, this measured current being supplied (see [Fig. 6]) by the feedback chain of the control loop: e = ISET - Imes -

[0078] The gain factor F can be determined on the basis of a tracking error rate obtained from the error signal.

[0079] A tracking error R(e) is calculated on the basis of the error signal e.

[0080] This tracking error R(e) can be calculated as the root mean square (RMS) value of the error signal: R(e) = RMS(e). This RMS value can be calculated over one period of the supply voltage (for example, using the zero-crossing information provided by the PLL). This RMS value is usually calculated as the square root of the mean square of the error signal, the mean being calculated over one period of the supply voltage. This mean can be calculated by integrating the error signal or by a discrete sum of sampled values.

[0081] The tracking error R(e) can also be calculated as the average of the error signal over a period of the supply voltage. This variant reduces the processor load by eliminating the square root operation.

[0082] The error rate T(e) is determined based on this tracking error R(e). The determination may include normalization (block 710), weighting (block 720), and / or integration (block 730) including a clipping function (saturation block 731). The error rate can thus be a normalized error rate, then weighted and / or integrated.

[0083] The normalization (block 710) of the tracking error can be performed on the basis of the sinusoidal setpoint current or the measured current. The normalization can be performed by calculating a normalization coefficient N and dividing the tracking error R(e) by the normalization coefficient to determine a relative tracking error R(e) / N. The normalization coefficient N can be the RMS value (or respectively the average value) R(ISEt) of the sinusoidal setpoint current or respectively that R(IMES) of the measured current.

[0084] Optionally, a setpoint error rate RC (either zero or non-zero and between 0 and 1) can also be chosen for the relative RMS value R(e) / N: this setpoint error rate RC serves to define an optimal value to be achieved. The normalized error rate can thus be determined as TN(e) = RC - R(e) / N.

[0085] The dynamics of the adaptation can be adjusted by means of a weighting coefficient K applied (block 720) to the normalized error rate so as to determine a weighted error rate: TP(e)= K*TN(e).

[0086] The value of K can be calibrated to find a compromise between the need for rapid adaptation (the system must be stabilized quickly enough to prevent any oscillation from disabling the PFC 110) and learning that is slow enough to be uncorrelated with the current control dynamics.

[0087] The integration is performed by an integral controller 730 including a clipping function 731, and applied to the weighted error rate TP(e) so as to obtain an integrated error rate TI(e) at the output. The integral controller has a discrete transfer function of the form K / z, with block 720 applying the adjustment coefficient K. The function of the saturation block 731 is to limit the value of the integrated error rate TI(e).

[0088] The gain factor F is then calculated based on the error rate (normalized, weighted or integrated). The gain factor is calculated based on the error rate (normalized, weighted or integrated) such that the gain factor F (F = 1 - TI(e) in the example of [Fig. 7], the reference value being equal to 1) is an increasing function of the tracking error.

[0089] Indeed, the higher the normalized error rate R(e) / R(ISET), the lower RC-R(e) / R(ISET) becomes (towards negative values). The more negative this error is, the more the integration drifts towards negative values. And the higher the value of F=l-TI(e).

[0090] In the case where an Iz / lp controller is used in the control loop and calibrated to provide a minimum phase margin satisfying the stability requirements.

[0091] The gain regulation strategy F aims to improve the open-loop transfer function gain, i.e. to compensate for the potential gain drop associated with line inductances, which, if not compensated, would result in poorer tracking of the sinusoidal current setpoint, i.e. a lower harmonic distortion rate.

[0092] The PFC is thus robust to any value of line impedance.

[0093] The on-board charger thus configured resists a wide range of parasitic inductances, i.e. to many configurations of the power supply network, including in the case of a supply by static inverters.

[0094] Fig. 8 illustrates an example of an implementation of a method for activating the calculation of the gain factor.

[0095] The initial value of the gain factor can be reset and set to 1 (step 880) after a preload period (step 810) during which the gain adaptation device is not activated.

[0096] Then, according to some embodiments, the phase-locked loop (PLL) is allowed to synchronize (step 815) so that zero crossings of the supply voltage can be detected. A first value of the measured current IMES can then be obtained (step 820).

[0097] Furthermore, the gain adaptation device is deactivated (step 830) when no load is in progress, so that the gain factor is frozen (step 870) at its current value.

[0098] In addition, the gain adaptation device can be deactivated (so that the gain factor is in this case also frozen at its current value, step 870) when the RMS value (or the average value) of the setpoint current ISEt is low (for example if R(ISET) is less than a threshold, according to the test in step 840) for several reasons:

[0099] - The calculation of the RMS value is less precise when the setpoint current ISET is low (below a threshold);

[0100] - For topologies comprising diodes characterized by a conduction mode discontinuous, the open-loop gain in DCM mode (discontinuous conduction mode) is significantly different from that in CCM mode (continuous conduction mode), which would require a dedicated controller for each mode.

[0101] The gain factor calculation is performed in step 850, when the gain adaptation device is not deactivated following the cumulative tests of steps 830 and 840. The gain factor calculation is performed for example according to what is described in [Fig.7].

[0102] After activation, during the implementation of the gain factor calculation process in step 850, the error e is measured and the cumulative sums are calculated to obtain R(e) and the normalization coefficient N during the switching period. The gain factor F is calculated, based on these cumulative sums over one period, at each zero crossing of the supply voltage, in order to save the load on the central processing unit of the gain matching device that performs the calculation of the gain factor to be applied.

[0103] Then, following the calculation of the gain factor and a zero crossing of the supply voltage (step 860), step 820 of measuring the current IMES is carried out again (according to what has been described in this document for example by reference to [Fig.6]). Following step 820, steps 830 and 840 are repeated again according to the logic described above.

[0104] Figures 9 and 10 show the behavior of the charger with an Izlp controller for a value of 2.27mH as line inductance, when gain matching is enabled ([Fig. 10]) or disabled ([Fig. 9]).

[0105] With this high line inductance, the error signal e oscillates between -0.6 A and +0.6 A (cosine wave at the network frequency, since sin(wt+q>)-sin(wt) = 2*cos(wt +<p / 2)*sin(q> / 2) ~ q>* cos(wt+ q> / 2)) in the absence of gain adaptation (subfigure 9A).

[0106] When the gain factor is kept constant, equal to 1 (subfigure 9D): the effective value of the error signal e converges to 0.4A (subfigure 9B), i.e. a relative effective RMS(e) / RMS(ISEt) value of nearly 3% (subfigure 9C) of the effective RMS(Iset) value of the sinusoidal setpoint current ISET.

[0107] When gain matching F is activated: - the amplitude of the error signal e is reduced to + / -0.16A: it is therefore divided by a factor of 4 (subfigure 10A); - the RMS effective value(e) of the error signal e is maintained below 0.1 A (subfigure 10B) - the relative RMS(e) / RMS(Iset) value is limited to approximately 0.7% (the setpoint error rate chosen for this simulation) (subfigure 10C); ; and - the gain factor F converges towards 4, within a delay of about 1 second (subfigure 10D).

[0108] In the description of the various signal processing functions and processes, although the steps are described sequentially, a person skilled in the art will understand that some steps may be omitted, combined, carried out in a different order and / or in parallel.

[0109] One or more or all of the functions, steps and processes described in this document can be implemented by software (for example, via software on one or more processors, for execution on a general purpose or specific purpose computer) and / or by hardware (for example, one or more electronic circuits, programmable or not, specific or not and / or any other hardware component).

[0110] The devices described in this document include means for implementing the functions described for these devices. These means may include software means (for example, instructions from one or more components of a program) and / or hardware means (for example, data memory, processor(s), communication bus, hardware interface(s), electronic circuits, etc.).

[0111] These means may, for example, include one or more electronic circuits configured to perform one or more or all of the functions described for these devices. These means may, for example, include at least one processor and at least one memory comprising program instructions configured to, when executed by the processor, cause the device in question to perform one or more or all of the functions described for the device in question.

[0112] This description relates to a software or computer program capable of being executed by a host device (such as, for example, a power factor correction device or gain matching arrangement) by means of one or more data processors. This software / program comprises instructions to cause the host device to execute all or part of the process steps and / or functions described in this document for that host device. These instructions are intended to be stored in a memory of the host device, loaded, and then executed by one or more processors of that host device so as to cause the host device to execute the process.

[0113] This software / program may be coded using any programming language, and may be in the form of source code, object code, or code intermediate between source code and object code, such as in a partially compiled form, or in any other desirable form.

Claims

Demands

1. Power factor correction device (600) for an on-board electric charger of an automotive battery, the power factor correction device comprising a current regulation loop; the regulation loop comprising a forward chain generating a regulated current (10) corresponding to the current drawn by the electric charger and a feedback chain generating a measured current from the regulated current; the regulation loop being configured to receive as input a sinusoidal setpoint current (ISEt) in phase with a sinusoidal supply voltage and to generate an error signal by comparing the sinusoidal setpoint current with the measured current supplied by the feedback chain;the direct chain comprising a control loop controller (620), a gain adapter (610) configured to generate a gain factor, an amplifier (615) configured to apply the gain factor to the controller input signal, the gain factor being generated on the basis of the error signal, said device being characterized in that the gain adapter is configured to generate the gain factor on the basis of a weighting coefficient (K) of the open-loop transfer function gain.

2. Power factor correction device according to claim 1, wherein the gain adapter (610) is configured to generate the gain factor based on a tracking error of the control loop determined from the error signal.

3. Power factor correction device according to claim 2, wherein the tracking error is determined as the RMS value of the error signal.

4. Power factor correction device according to claim 2, wherein the tracking error is determined as the average, over a period of the supply voltage, of the error signal.

5. A power factor correction device according to any one of the preceding claims, wherein the gain adapter (610) is configured to determine an error rate from the error signal and to normalize the error rate between 0 and 1. the basis of the sinusoidal setpoint current or the measured current so as to generate a normalized error rate.

6. Power factor correction device according to any one of the preceding claims, wherein the gain adapter is configured to compare the normalized error rate with a setpoint error rate.

7. Electric battery charger for use in a motor vehicle, the electric charger comprising a power factor correction device according to any one of the preceding claims.

8. A method (600) for power factor correction for an on-board electric charger of an automotive battery, the method comprising: - receiving a sinusoidal setpoint current (ISEt) in phase with a sinusoidal supply voltage; - generating a regulated current (10) corresponding to the current drawn by the electric charger; - generating a measured current (IMES) from the regulated current; - generating an error signal by comparing the sinusoidal setpoint current with the measured current; the generation of the regulated current comprising: - generating a gain factor based on the error signal; - applying the gain factor to the error signal to generate a weighted error signal; - applying a regulation function to the weighted error signal to generate the regulated current (10).

9. A computer program comprising instructions adapted to, when the instructions are executed by at least one processor, cause the execution of the steps of the process according to claim 8.

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