COMPUTER SYSTEM CONFIGURED TO TIME OUT

Abstract

According to one aspect, there is provided a timing method implemented by a computer system (SYS) comprising: - a central processing unit (CPU), - an external clock circuit (EXT_CLK) comprising a counter, the counter (CNT) being configured to increment or decrement its value at each clock tick of the external clock circuit (EXT_CLK) over a range of values ​​corresponding to one millisecond, the timing method comprising: - a definition of a maximum number of transitions of a bit to be monitored of the value of the counter corresponding to a desired waiting time, - a monitoring of the transitions of the bit to be monitored of the value of the counter so as to carry out said timing until the number of transitions carried out of the bit to be monitored reaches the defined maximum number of transitions. Figure for abstract: Figure 1

Description

Title of the invention: COMPUTER SYSTEM CONFIGURED TO IMPLEMENT A WAITING TIME

[0001] Embodiments and implementations relate to computer systems, and more particularly to the timing of a duration of less than one millisecond by a central processing unit of such a computer system.

[0002] In certain applications, it is important to provide a solution allowing a central processing unit of a computer system to wait for a certain delay during the execution of a computer program.

[0003] In particular, a computer system may include peripherals that can be accessed by the central processing unit. For example, a peripheral of the computer system may be an analog-to-digital converter or an analog comparator or a voltage regulator.

[0004] These peripherals may have a stabilization time for intrinsic physical quantities (for example an electrical voltage). The stabilization time of a peripheral corresponds to a duration necessary for the peripheral to reach a stable state after a change in conditions or a disturbance, for example when starting the peripheral.

[0005] When the central processing unit wishes to access a peripheral of the computer system, it is important to provide a waiting time in order to allow access to the peripheral after the end of the stabilization time of this peripheral.

[0006] Generally, the stabilization time is less than one millisecond, in particular of the order of a few microseconds to a few tens of microseconds.

[0007] It is known to use software-only solutions to provide a waiting time in microseconds. In particular, a software loop can be used to make the central processing unit wait for a duration corresponding to the waiting time.

[0008] In particular, it is possible to provide an index which can be defined by the following formula:

[0009] — 22LL yl 1, where IDX is the index, DLY is the delay in microseconds — w 2x100000 and I_CLK is a global variable corresponding to the frequency of an internal clock of the central processing unit.

[0010] The software loop then includes a test at the start of the loop to determine whether the value of the index is different from 0.

[0011] If the value of the index is different from 0 then the software loop includes a decrement of the index.

[0012] When the index value reaches 0, then the loop start test allows you to exit the software loop.

[0013] Such a software loop then relies solely on a global variable corresponding to the frequency of the internal clock of the central processing unit.

[0014] The waiting time obtained by the implementation of such a software loop then has the disadvantage of depending on the compilation of the source code making it possible to obtain an assembler code of the software loop.

[0015] In particular, the number of instructions to perform the software loop may vary depending on the compilation performed. Thus, the waiting times that can be obtained from two different compilers may vary significantly.

[0016] Such a software-only solution is therefore not precise. It is then generally planned to provide a waiting margin to avoid the waiting time obtained being less than the desired waiting time. This results in a loss of time to access a device.

[0017] Furthermore, the computer system may comprise a specific clock circuit configured to manage durations that are multiples of a millisecond (the usual order of magnitude for computer system tasks). In particular, in the ARM Cortex-M architecture, such a clock circuit called a “Systick” is known. However, such a clock circuit is not suitable on its own for managing durations in microseconds that are less than a millisecond.

[0018] To manage microsecond delays of less than one millisecond, it is possible to use a dedicated clock circuit to count in microseconds. However, such a clock circuit has the disadvantage of monopolizing generic resources of the computer system for this specific task.

[0019] There is therefore a need to propose a timing solution making it possible to wait reliably for a duration in microseconds of less than 1 millisecond.

[0020] According to one aspect, there is provided a timing method implemented by a computer system comprising: - a central processing unit, - an external clock circuit comprising a counter, the counter being configured to increment or decrement its value at each clock tick of the external clock circuit over a range of values ​​corresponding to one millisecond, the timing method comprising: - a definition by the central processing unit of a maximum number of transitions of a bit to be monitored from the value of the counter, the maximum number of transitions corresponding to a desired waiting time, - monitoring by the central processing unit of the transitions of the bit to be monitored of the value of the counter so as to carry out said time delay until the number of transitions made of the bit to be monitored reaches the maximum number of transitions defined.

[0021] Such a method makes it possible to wait for a delay of less than one millisecond by monitoring a bit of a counter of an external clock circuit. The waiting time obtained is then independent of the compiler used to compile the source code.

[0022] Such a method thus makes it possible to improve the precision of the waiting time obtained.

[0023] Furthermore, the configuration of the clock circuit remains unchanged, therefore the microsecond wait solution is non-invasive in the computer system.

[0024] In an advantageous embodiment, the desired waiting time corresponds to a stabilization time of a peripheral of the computer system, said time delay being implemented during access by the central processing unit to this peripheral.

[0025] Preferably, monitoring the transitions of the bit to be monitored comprises defining a mask making it possible to isolate the bit to be monitored when the mask is applied to the value of the counter of the external clock circuit.

[0026] Advantageously, the maximum number of transitions of the bit to be monitored is calculated by the formula: IDX ~ ( ( DLY X > 1 Q + b °where IDX is the maximum number of transitions, DLY is the desired delay in microseconds, RLDV is the loading value of the CNT counter of the external clock circuit EXT_CLK corresponding to one millisecond and MSK is the mask value of the bit to be monitored.

[0027] In an advantageous embodiment, said maximum number of transitions is used to initialize an index making it possible to count the number of transitions made by the bit to be monitored of the counter of the external clock circuit.

[0028] Advantageously, the monitoring of the transitions of the bit to be monitored comprises an implementation of a main loop as long as the value of the index is different from 0, the main loop comprising: - a decrement of the index value, - a first secondary loop implemented as long as the value of the bit to be monitored is equal to 0, - a second secondary loop implemented as long as the value of the bit to be monitored is equal to 1.

[0029] According to another aspect, there is provided a computer system comprising: - a central processing unit, - an external clock circuit comprising a counter, the counter being configured to increment or decrement its value at each clock pulse of the circuit external clock over a range of values ​​corresponding to one millisecond, - a memory storing a computer program comprising instructions which, when executed by the central processing unit, cause it to: - define a maximum number of transitions of a bit to be monitored from the value of the counter, the maximum number of transitions corresponding to a desired waiting time, - monitoring transitions of the bit to be monitored from the value of the counter so as to carry out said time delay until the number of transitions carried out from the bit to be monitored reaches the maximum number of transitions defined.

[0030] In an advantageous embodiment, the computer system further comprises a peripheral having a stabilization time, the computer program comprising instructions which, when executed by the central processing unit, cause the latter to implement said time delay during access by the central processing unit to the peripheral, the desired waiting time of the time delay corresponding to the stabilization time of the peripheral.

[0031] Preferably, the computer program comprises instructions which, when executed by the central processing unit, cause the latter to define and apply a mask on the value of the counter of the external clock circuit to isolate the bit to be monitored in order to monitor the transitions of the bit to be monitored.

[0032] Advantageously, the computer program comprises instructions which, when executed by the central processing unit, cause the latter to calculate the maximum number of transitions of the bit to be monitored by the formula: IDX = ( ( DLY X > 11 ) + L where IDX is the maximum number of transitions, DLY is the desired delay in microseconds, RLDV is the loading value of the CNT counter of the external clock circuit EXT_CLK corresponding to one millisecond and MSK is the mask value of the bit to be monitored.

[0033] In an advantageous embodiment, the computer program comprises instructions which, when executed by the central processing unit, cause the latter to use said maximum number of transitions to initialize an index making it possible to count the number of transitions made by the bit to be monitored of the counter of the external clock circuit.

[0034] Advantageously, the computer program comprises instructions which, when executed by the central processing unit, cause the latter to monitor transitions of the bit to be monitored by implementing a main loop as long as the value of the index is different from 0, the main loop comprising: - a decrement of the index value, - a first secondary loop implemented as long as the value of the bit to be monitored is equal to 0, - a second secondary loop implemented as long as the value of the bit to be monitored is equal to 1.

[0035] According to another aspect, there is provided a computer program product comprising instructions which when implemented by a central processing unit of a computer system also comprising an external clock circuit comprising a counter, the counter being configured to increment or decrement its value at each clock tick of the external clock circuit over a range of values ​​corresponding to one millisecond, lead the central processing unit to: - define a maximum number of transitions of a bit to monitor from the counter value, the maximum number of transitions corresponding to a desired waiting time, - monitoring transitions of the bit to be monitored from the value of the counter so as to carry out said time delay until the number of transitions carried out from the bit to be monitored reaches the maximum number of transitions defined.

[0036] In an advantageous embodiment, the computer program product comprises instructions which, when executed by the central processing unit, cause the latter to implement said time delay during access by the central processing unit to a peripheral of the computer system, the desired waiting time of the time delay corresponding to a stabilization time of the peripheral.

[0037] Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments, which are in no way limiting, and the appended drawings in which:

[0038] [Fig.l]

[0039] [Fig.2]

[0040] [Fig.3] illustrate embodiments and implementations of the invention.

[0041] [Fig.l] illustrates a computer system SYS. The computer system SYS comprises a central processing unit CPU, an external clock circuit EXT_CLK, a program memory MEMP and at least one peripheral PRPH.

[0042] The PRPH peripheral is an electronic module that can be accessed by the central processing unit CPU. The PRPH peripheral can be an analog-digital circuit for example.

[0043] The PRPH device has a stabilization time. This stabilization time corresponds to the time required for the device to reach a stable state after a change in conditions or a disturbance. This stabilization time is generally indicated in a technical description document relating to this device.

[0044] The computer system SYS may have an ARM Cortex-M architecture. In this case, the external clock circuit EXT_CLK may correspond to the clock circuit called “Systick”.

[0045] The "Systick" clock circuit is usually used to manage time delays in milliseconds.

[0046] [Fig.2] illustrates an embodiment of an external clock circuit EXT_CLK. The external clock circuit EXT_CLK is configured to generate a clock signal E_CLK corresponding to a periodic square wave signal.

[0047] In particular, this clock signal E_CLK may have a frequency of between a few hundred kHz (kilohertz) and a few hundred MHz (megahertz), for example of the order of 100 MHz.

[0048] The external clock circuit EXT_CLK comprises a first register configured to store a load value RLDV.

[0049] The external clock circuit EXT_CLK also includes a counter CNT. The counter CNT is configured to decrement its current value CURV at each clock tick E_CLK.

[0050] The initial value of the CNT counter is initialized to the RLDV loading value. The RLDV loading value is chosen to correspond to the value that can be reached by the counter in one millisecond. In particular, the RLDV loading value can be determined by the following formula:

[0051] RLDV — F-ECLK , where RLDV is the load value and F_ECLK is the 2xF_CLK clock signal frequency and F_CLK is a clock frequency, typically equal to 1 kHz to obtain a period of 1 millisecond.

[0052] When the current value CURV of the CNT counter reaches zero, the CNT counter is configured to resume the loading value RLDV as the current value at the next clock tick E_CLK.

[0053] The external clock circuit EXT_CLK also includes a second register (notably the SYS_CVR register in the ARM Cortex-M architecture) configured to store the current value CURV of the CNT counter.

[0054] The central processing unit CPU is configured to execute instructions according to a frequency of an internal clock (not shown). The frequency of the internal clock may be between a few hundred kHz and a few hundred MHz, for example of the order of 100 MHz.

[0055] The central processing unit CPU is configured to be able to access the current value CURV of the counter of the external clock circuit EXT_CLK.

[0056] The central processing unit CPU is configured to execute a computer program PRG stored in the program memory MEMP.

[0057] The PRG computer program comprises instructions, which when executed by the central processing unit CPU, cause the latter to access a peripheral.

[0058] The computer program PRG also comprises instructions, which when executed by the central processing unit CPU, cause the latter to implement a timing method when accessing the peripheral, in particular to wait for a period corresponding to the stabilization time of this peripheral. [Fig. 3] illustrates a mode of implementation of such a timing method.

[0059] The computer program PRG also comprises instructions, which when executed by the central processing unit CPU, cause the latter to implement an initialization function (step 30 of the timing method).

[0060] This initialization function is configured to set the loading value of the external clock circuit EXT_CLK to the value reached by the counter in 1 millisecond.

[0061] The computer program PRG also comprises instructions, which when executed by the central processing unit CPU, cause the latter to implement a timeout function LL_uDLY making it possible to wait for a delay in microseconds less than one millisecond (step 31 of the timeout method).

[0062] This LL_uDLY function is notably implemented before accessing a PRPH peripheral, for example to wait for a stabilization time of the PRPH peripheral. A code in C programming language corresponding to an example of implementation of said LL_uDLY function is illustrated in Appendix 1.

[0063] Said LL_uDLY function is configured to receive as input a desired waiting time expressed in microseconds. This desired waiting time corresponds for example to the stabilization time associated with the peripheral accessed by the central processing unit.

[0064] Said function LL_uDLY is configured to use the external clock circuit EXT_CLK to measure said delay in microseconds.

[0065] In particular, said function LL_uDLY is configured to monitor a bit of the current value CURV of the counter CNT of the external clock circuit EXT_CLK in order to detect a number of transitions of this bit representative of the delay in microseconds.

[0066] The bit to be monitored is chosen according to the frequency of the transitions of this bit. In particular, it is important to choose a bit having transitions at a frequency sufficiently lower than the frequency of the internal clock of the central processing unit CPU so that the latter can detect these transitions.

[0067] It is also important to choose a bit having transitions according to a frequency sufficiently high compared to the desired waiting time. The bit to be monitored of the current CURV value of the CNT counter can for example be the fourth least significant bit.

[0068] In order to enable this monitoring, said LL_uDLY function is configured to define an MSK mask (step 31-1) making it possible to isolate the bit to be monitored when the MSK mask is applied to the current value CURV of the CNT counter.

[0069] Said function LL_uDLY is also configured to initialize an IDX index (step 31-2) making it possible to count the number of transitions made for the monitored bit. In particular, this IDX index is initialized to a value corresponding to the number of transitions representative of the desired waiting time in microseconds and is then decremented each time a transition is detected.

[0070] Thus, when the IDX index reaches 0 then the expected delay corresponds to the desired waiting time in microseconds.

[0071] This IDX index is stored in a volatile memory (not shown), in particular a random-access memory (RAM) of the central processing unit (CPU) during the implementation of said LL_uDLY function.

[0072] The calculation of the initial value of the IDX index is carried out by the central processing unit CPU during the implementation of said LL_uDLY function.

[0073] In particular, the initial value of the IDX index is calculated using the following formula:

[0074] / [)X = ( ( DLY x > 11 ) + L °where IDX is the index, DLY is the delay desired in microseconds, RLDV is the loading value of the CNT counter of the external clock circuit EXT_CLK corresponding to one millisecond and MSK is the mask value of the bit to be monitored.

[0075] The 11-bit shift to the right is equivalent to a division by 2048 which corresponds to an approximation of a division by 1000 multiplied by 2 (i.e. a division by 2000).

[0076] This shift makes it possible to convert a delay in milliseconds into microseconds, the transitions being carried out two by two (for the monitored bit, transition 1 to 0 then transition 0 to 1).

[0077] The RLDV loading value corresponding to the value reached by the CNT counter in one millisecond makes it easier to calculate the initial value of the IDX index corresponding to the desired waiting time.

[0078] The LL_uDLY function is then configured to wait for the desired timeout by performing a PLP main loop as long as the index value is different from 0.

[0079] This main PLP loop allows monitoring of bit transitions to monitor and an update of the index every two detected transitions. Monitoring of the transitions of the bit to be monitored is carried out in a loop by the central processing unit CPU.

[0080] In particular, the main PLP loop first comprises a 31-3 test of the value of the index in order to determine whether this value is equal to 0.

[0081] If the value of the IDX index is different from 0, then the PLP main loop implements operations to monitor the transitions of the bit to be monitored and to update the index.

[0082] In particular, the main PLP loop includes a 31-4 decrement of the IDX index.

[0083] The main loop PLP then comprises a first secondary loop SLP1 implemented as long as the value of the bit to be monitored is equal to 0. To do this, said first secondary loop SLP1 applies the mask MSK to the current value of the counter of the external clock circuit so as to isolate the value of the bit to be monitored and performs a test 31-5 to determine whether the value obtained by applying the mask MSK is equal to 0.

[0084] If the value obtained by applying the MSK mask is equal to 0, then the first secondary loop SLP1 continues to be executed. If the value obtained by applying the MSK mask is different from 0, then the first secondary loop SLP1 is stopped.

[0085] The first secondary loop SLP1 thus makes it possible to detect a transition of the monitored bit from 0 to 1.

[0086] The main loop PLP then comprises a second secondary loop SLP2 implemented as long as the value of the bit to be monitored is equal to 1. To do this, said second secondary loop SLP2 applies the mask MSK to the current value CURV of the counter of the external clock circuit EXT_CLK so as to isolate the value of the bit to be monitored and performs a test 31-6 to determine whether the value obtained by applying the mask MSK is other than 0.

[0087] If the value obtained by applying the MSK mask is different from 0, then the second secondary loop SLP2 continues to be executed. If the value obtained by applying the MSK mask is equal to 0, then the first secondary loop SLP1 is stopped.

[0088] The second secondary loop SLP2 thus makes it possible to detect a transition of the monitored bit from 1 to 0.

[0089] Then, the main PLP loop is iterated as long as the index value is different from 0.

[0090] The PLP main loop is stopped once the value of the IDX index reaches 0 during the PLP main loop start test (step 32).

[0091] The stopping of the main PLP loop marks the end of said LL_uDLY function, and therefore the end of the time delay.

[0092] Such a timing function is thus configured to execute a PLP main loop making it possible to time for a duration at least substantially close to the desired waiting time in microseconds.

[0093] This main PLP loop includes a one-bit monitoring of the counter of the external clock circuit EXT_CLK. In this way, the timed duration does not depend on the cycles of the central processing unit.

[0094] Thus, the timed duration does not depend on the compiler or the compilation options chosen but is based solely on the monitoring of a bit of the counter of the external clock circuit EXT_CLK.

[0095] Such a timing function also has the advantage of being precise, in particular when the frequency of the internal clock of the central processing unit CPU is greater than 4 MHz.

[0096] APPENDIX

[0097] Example 1 of a C language source code of the LL_uDLY timing function:

[0098] void LL_uDLY(uint32_t DLY)

[0099] {

[0100] uint32_tMSK = (lUL«4U);

[0101] uint32_t IDX = ((DLY * (SysTick->LOAD / MSK)) » 11U) + 1U;

[0102] while(IDX != 0)

[0103] {

[0104] IDX—;

[0105] while((SysTick->VAL & MSK) == 0UL)

[0106] {

[0107] }

[0108] while((SysTick->VAL & MSK) != 0UL)

[0109] {

[0110] } [YES]}

[0112] }

Claims

Claims

1. Timing method implemented by a computer system (SYS) comprising: - a central processing unit (CPU), - an external clock circuit (EXT_CLK) comprising a counter, the counter (CNT) being configured to increment or decrement its value at each clock tick of the external clock circuit (EXT_CLK) over a range of values ​​corresponding to one millisecond, the timing method comprising: - a definition by the central processing unit of a maximum number of transitions of a bit to be monitored of the value of the counter (CNT), the maximum number of transitions corresponding to a desired waiting time, - monitoring by the central processing unit of the transitions of the bit to be monitored of the value of the counter (CNT) so as to carry out said timing until the number of transitions carried out of the bit to be monitored reaches the defined maximum number of transitions.

2. Method according to claim 1, in which the desired waiting time corresponds to a stabilization time of a peripheral (PRPH) of the computer system (SYS), said time delay being implemented during access by the central processing unit (CPU) to this peripheral (PRPH).

3. Method according to any one of claims 1 or 2, in which the monitoring of the transitions of the bit to be monitored comprises a definition of a mask making it possible to isolate the bit to be monitored when the mask is applied to the value of the counter (CNT) of the external clock circuit (EXT_CLK).

4. Method according to claim 3 in which the maximum number of transitions of the bit to be monitored is calculated by the formula: IDX = ( ( DLY X ) > 11 ) + T °where IDX is the maximum number of transitions, DLY is the desired delay in microseconds, RLDV is the loading value of the CNT counter of the external clock circuit EXT_CLK corresponding to one millisecond and MSK is the value of the mask of the bit to be monitored.

5. Method according to one of claims 1 to 4 in which said maximum number of transitions is used to initialize an index making it possible to count the number of transitions carried out by the bit to be monitored of the external clock circuit counter.

6. Method according to claim 5, in which the monitoring of the transitions of the bit to be monitored comprises an implementation of a main loop (PLP) as long as the value of the index is different from 0, the main loop (PLP) comprising: - a decrement of the value of the index (IDX), - a first secondary loop (SLP1) implemented as long as the value of the bit to be monitored is equal to 0, - a second secondary loop (SLP2) implemented as long as the value of the bit to be monitored is equal to 1.

7. Computer system comprising: - a central processing unit (CPU), - an external clock circuit (EXT_CLK) comprising a counter (CNT), the counter (CNT) being configured to increment or decrement its value at each clock tick of the external clock circuit (EXT_CLK) over a range of values ​​corresponding to one millisecond, - a memory (MEM) storing a computer program (PRG) comprising instructions which, when executed by the central processing unit (CPU), cause the latter to: - define a maximum number of transitions of a bit to be monitored of the value of the counter (CNT), the maximum number of transitions corresponding to a desired waiting time, - monitor transitions of the bit to be monitored of the value of the counter (CNT) so as to carry out said time delay until the number of transitions made of the bit to be monitored reaches the defined maximum number of transitions.

8. A computer system according to claim 7, further comprising a peripheral (PRPH) having a settling time, the computer program (PRG) comprising instructions which, when executed by the central processing unit (CPU), cause the latter to implement said time delay during an access by the central processing unit (CPU) to the peripheral (PRPH), the desired waiting time of the time delay corresponding to the settling time of the peripheral (PRPH).

9. A computer system according to any one of claims 7 or 8, wherein the computer program (PRG) comprises instructions which, when executed by the central processing unit processing (CPU), lead the latter to define and apply a mask on the value of the counter (CNT) of the external clock circuit (EXT_CLK) to isolate the bit to be monitored in order to monitor the transitions of the bit to be monitored.

10. Computer system according to claim 9, in which the computer program (PRG) comprises instructions which, when executed by the central processing unit (CPU), cause the latter to calculate the maximum number of transitions of the bit to be monitored by the formula: IDX — ( (DLY X > 11 ) + 1' °where IDX is the maximum number of transitions, DLY is the desired delay in microseconds, RLDV is the loading value of the CNT counter of the external clock circuit EXT_CLK corresponding to one millisecond and MSK is the value of the mask of the bit to be monitored.

11. Computer system according to one of claims 7 to 10, in which the computer program (PRG) comprises instructions which, when executed by the central processing unit (CPU), cause the latter to use said maximum number of transitions to initialize an index making it possible to count the number of transitions carried out by the bit to be monitored of the counter (CNT) of the external clock circuit.

12. A computer system according to claim 11, wherein the computer program (PRG) comprises instructions which, when executed by the central processing unit (CPU), cause the latter to monitor transitions of the bit to be monitored by implementing a main loop (PLP) as long as the value of the index is different from 0, the main loop (PLP) comprising: - a decrement of the value of the index, - a first secondary loop (SLP1) implemented as long as the value of the bit to be monitored is equal to 0, - a second secondary loop (SLP2) implemented as long as the value of the bit to be monitored is equal to 1.

13. Computer program product comprising instructions which when implemented by a central processing unit of a computer system also comprising an external clock circuit (EXT_CLK) comprising a counter (CNT), the counter (CNT) being configured to increment or decrement its value to each clock tick of the external clock circuit (EXT_CLK) over a range of values ​​corresponding to one millisecond, lead the central processing unit to: - define a maximum number of transitions of a bit to be monitored of the value of the counter (CNT), the maximum number of transitions corresponding to a desired waiting time, - monitor transitions of the bit to be monitored of the value of the counter (CNT) so as to carry out said time delay until the number of transitions carried out of the bit to be monitored reaches the defined maximum number of transitions.

14. Computer program product according to claim 13, comprising instructions which, when executed by the central processing unit (CPU), cause the latter to implement said time delay during an access by the central processing unit (CPU) to a peripheral (PRPH) of the computer system (SYS), the desired waiting time of the time delay corresponding to a stabilization time of the peripheral (PRPH).

15. A computer program product according to any one of claims 13 or 14, comprising instructions which, when executed by the central processing unit (CPU), cause the latter to define and apply a mask to the value of the counter (CNT) of the external clock circuit (EXT_CLK) to isolate the bit to be monitored in order to monitor the transitions of the bit to be monitored.

16. Computer program product according to claim 15, comprising instructions which, when executed by the central processing unit (CPU), cause the latter to calculate the maximum number of transitions of the bit to be monitored by the formula: H)Y = ( ( DLY X 1 l) + 1, where IDX is the maximum number \ \ MSK > / of transitions, DLY is the desired delay in microseconds, RLDV is the loading value of the CNT counter of the external clock circuit EXT_CLK corresponding to one millisecond and MSK is the value of the mask of the bit to be monitored.

17. Computer program product according to one of claims 13 to 16, comprising instructions which, when executed by the central processing unit (CPU), cause the latter to use said maximum number of transitions to initialize an index making it possible to count the number of transitions made by the bit to be monitored of the counter (CNT) of the external clock circuit.

18. Computer program product according to claim 17, comprising instructions which, when executed by the central processing unit (CPU), cause the latter to monitor transitions of the bit to be monitored by implementing a main loop (PLP) as long as the value of the index is different from 0, the main loop (PLP) comprising: - a decrement of the value of the index, - a first secondary loop (SLP1) implemented as long as the value of the bit to be monitored is equal to 0, - a second secondary loop (SLP2) implemented as long as the value of the bit to be monitored is equal to 1.

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