Process for multi-layer integration of electronic circuits

Abstract

Method for multi-layer integration of electronic circuits The method for integrating electronic components and conductive tracks on a support comprising a substrate (2') equipped with a conductive track (4') and electronic components (5') makes it possible to design three-dimensional electronic circuits and thus increase the integration potential of the equipment.It comprises the following successive steps: step 1: depositing an insulating material (6) on the support so as to cover the entire support, including the substrate and the electronic circuit, with an external layer of insulating material, step 2: selective removal of a portion of the insulating material so as to form at least one hole (7) opening through the external layer of insulating material, step 3: integration of an electronic circuit (3) on the external layer of insulating material and in at least one hole, said electronic circuit comprising at least one electronic component (5) and / or a conductive track (4). Figure to be published with the abstract: Figure 5.

Description

Title of the invention: Method for multi-layer integration of electronic circuits TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of electronic circuits.

[0002] The present invention relates to a method for multi-layer integration of electronic components and conductive tracks on a support comprising an electronic circuit. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0003] Plastronics, also known by the English term Molded Interconnect Device, is a process combining plastics and electronics and which allows electronic circuits to be integrated directly onto thermoplastic parts, even when the surfaces on which the electronic circuits are integrated are not flat surfaces.

[0004] This technology makes it possible to increase the integration potential of equipment, but it usually remains limited to single-layer electronic circuits, i.e. electronic circuits in which the routing and arrangement of electronic components are two-dimensional.

[0005] In order to add even more electronics onto existing supports, however, there is a need for a technology that allows, in particular, the superposition of several electronic components and the generation of routing based on the superposition of several conductive tracks that may have different electrical potentials. This technology must also be adapted to the case where the surfaces on which the electronic circuits are integrated are not flat surfaces. Summary of the invention

[0006] The invention offers a solution to the problems mentioned above, by proposing a technology making it possible to integrate electronic circuits in a three-dimensional manner, in particular by making it possible to superimpose several successive layers of electronic components and conductive tracks for said electronic components.

[0007] One aspect of the invention relates to a method for integrating electronic components and conductive tracks on a support, said support comprising a substrate equipped with an electronic circuit, which method comprises the following successive steps: step 1: depositing an insulating material on the support so as to cover the entire support, including the substrate and the electronic circuit, with a outer layer of insulating material, • step 2: selective removal of a portion of the insulating material so as to form at least one hole opening through the outer layer of insulating material, • step 3: integration of an electronic circuit on the external layer of insulating material and / or in at least one hole.

[0008] This method advantageously makes it possible to superimpose electronic components and / or conductive tracks on an electronic circuit, which in particular makes it possible to superimpose several electronic components and several conductive tracks, for example with different electrical potentials.

[0009] According to one aspect of the invention, the deposition of the insulating material of step 1 is carried out by a vapor deposition process, which advantageously makes it possible to create a conformal and very thin insulating layer, which can be deposited on the entire external surface of the support, even in the most inaccessible corners and on surfaces which are not flat.

[0010] According to another aspect of the invention, the deposition method is a vapor deposition method without crosslinking of the insulating material.

[0011] Crosslinking is a chemical or physical process that involves forming covalent bonds or chemical bonds between the molecular chains of a deposited organic material. This can be done by heating, exposure to radiation, adding chemical reagents, etc. Crosslinking is a special case of polymerization that involves the formation of bonds between polymer chains, thus creating a three-dimensional network. Polymerization is a more general term that refers to the formation of a polymer from monomers, whether or not there is crosslinking. Parylene deposition is therefore not a crosslinking process.

[0012] Chemical Vapor Deposition (CVD) is a coating technique that involves vaporizing a material in gas form and then condensing it on the target surface to form a thin film. Vapor deposition allows for conformal and uniform coatings on complex substrates. The deposited film is typically very thin, making it ideal for applications requiring electrical insulation.

[0013] Vapor deposition has the following advantages: • Conformity with the surface allowing the production of thin (between 100 nm and 20 pm) and very homogeneous protections which can be easily engraved by laser or plasma to create a multitude of openings towards electrical contacts and this in an industrial manner. • The absence of solvent, catalyst and pollutants such as bromine, NaCl, etc. allows direct deposition on a silicon chip for example, which is more delicate with a material to be crosslinked which contains this type of material. • Excellent electrical insulation in the thicknesses mentioned, which particularly allows use in the power sector.

[0014] Furthermore, the CVD process is carried out at room temperature, thus preserving heat-sensitive materials, which is not the case with crosslinking and limits its use in the field particularly targeted by this invention.

[0015] According to a further aspect of the invention, the insulating material is parylene, namely a material chosen from polymers derived from paraxylene, because it is advantageously an excellent electrical insulator, capable of being deposited in the vapor phase and of being removed selectively by different technologies.

[0016] According to one aspect of the invention, the layer of insulating material obtained in step 1 has a thickness of between 0.1 μm and 200 μm, preferably between 0.5 μm and 75 μm and more preferably between 5 μm and 15 μm. These thicknesses are advantageously compatible with multilayer structures both in the field of electronics and in the field of microelectronics.

[0017] According to another aspect of the invention, the selective removal of step 2 is carried out using one of the following technologies or their combination: • excimer laser engraving, • femtosecond laser engraving, • oxygen plasma etching, • nitrogen plasma etching, • rare gas plasma etching.

[0018] These different techniques advantageously make it possible to selectively and locally remove the insulating material in order to create holes through which the elements located under the layer of insulating material become accessible, for example to electrically connect them to the elements which will be integrated on said layer of insulating material, these elements being for example electronic components or conductive tracks. They are also suitable when the surfaces on which the electronic circuits are integrated are not flat surfaces.

[0019] According to a further aspect of the invention, at least one through hole obtained in step 2 has a round, square or rectangular cross-section. These shapes are only examples of cross-sectional shapes which are advantageously easy to produce and which are suitable for connecting the elements located under the layer of insulating material to those located on it.

[0020] According to one aspect of the invention, the integrated electronic circuit in step 3 comprises at least one electronic component and / or a conductive track.

[0021] According to one aspect of the invention, step 3 comprises a step of selective metallization of at least a portion of the external layer of insulating material and / or at least one hole so as to deposit a conductive track therein. This step advantageously allows It is a good idea to create conductive tracks, not necessarily connected to each other, on the layer of insulating material and to deposit a conductive material in the holes in order to be able to electrically connect the elements located under the layer of insulating material to those located on it.

[0022] According to another aspect of the invention, the conductive track deposited during step 3 is a layer comprising mainly gold, palladium, copper, silver, carbon or a mixture thereof. These compositions are only examples of compositions which are advantageously excellent conductors and which are easy to deposit by the selective metallization techniques envisaged for the method of the invention.

[0023] According to an additional aspect of the invention, the deposition of the conductive track during step 3 is carried out using one of the following technologies or their combination: • aerosol printing (AJP), • inkjet printing, • chemically activated laser structuring (CALS).

[0024] These different techniques advantageously make it possible to create conductive tracks of very low thickness and with very high precision with respect to the thickness and other dimensions of the conductive tracks. They are also suitable when the surfaces on which the electronic circuits are integrated are not flat surfaces. Since the most precise techniques are generally more expensive, they are preferably reserved for cases where the method of the invention is applied to microelectronics.

[0025] According to one aspect of the invention, step 3 comprises a step of mounting at least one electronic component on the external layer of insulating material and in at least one hole. This step advantageously makes it possible to connect electronic components either with other elements of an electronic circuit located under said layer of insulating material, or with other elements of an electronic circuit located on the same layer as said electronic components, or with other elements which will be integrated into another upper layer of electronic circuit, located above the layer where the electronic components are integrated. In the latter case, the upper layer will be at least partially isolated from the electronic components integrated during step 3, this upper layer being obtained by repeating steps 1 to 3 of the method.

[0026] According to another aspect of the invention, at least one electronic component comprises electrical contacts and at least one electrical contact is mounted in a hole. This advantageously makes it possible to electrically connect an electronic component with an element of an electronic circuit located under said hole. As a reminder, such an element is for example an electronic component or a conductive track.

[0027] According to a further aspect of the invention, the method comprises a step of surface treatment of the external layer of insulating material provided before step 3 so as to improve its adhesion with the conductive track. This treatment is particularly advantageous when the insulating material has a certain degree of incompatibility with the techniques used to carry out the metallization of the insulating material.

[0028] According to one aspect of the invention, the surface treatment is carried out using one of the following technologies or their combination: • plasma surface treatment, • flame surface treatment, • surface treatment by high-frequency electric discharge, • UV surface treatment.

[0029] These different techniques advantageously make it possible to promote the metallization of the insulating material, in particular when the surface thereof is not flat.

[0030] According to another aspect of the invention, at least one removable protective cover is arranged on the support before step 1. This advantageously makes it possible to provide areas of the support which will not be covered with insulating material. Indeed, during step 1 each protective cover is covered with insulating material, thus protecting the support located below. It is then sufficient to remove each cover to reveal areas of the support which are not covered with insulating material.

[0031] According to an additional aspect of the invention, steps 1, 2 and 3 are repeated in order, at least once. This advantageously makes it possible to produce several successive layers of electronic circuit, each comprising electronic components and / or conductive tracks, these successive layers each time being at least partially insulated from each other by a layer of insulating material.

[0032] According to one aspect of the invention, the electronic circuit obtained during steps 1, 2 and 3 is electrically connected with at least one other electronic circuit of a lower layer. This advantageously makes it possible to electrically connect several successive layers of electronic circuit.

[0033] By "lower layer" is meant here the layer located immediately below the layer comprising insulating material and the electronic circuit obtained during steps 1, 2 and 3, or another layer located even below. This lower layer may be a layer obtained during steps 1, 2 and 3. It may also be the support on which at least one layer obtained during steps 1, 2 and 3 is deposited.

[0034] The invention and its various applications will be better understood upon reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0035] The figures are presented for information purposes only and in no way limit the invention. For reasons of clarity of the figures, the thicknesses of certain layers are considerably exaggerated.

[0036] [Fig.l] is a schematic sectional view of a support comprising a substrate equipped with an electronic circuit comprising five electronic components integrated on a conductive track.

[0037] [Fig.2] is a schematic sectional view of the support of [Fig.l] on which is deposited a layer of insulating material according to step 1 of the method of the invention.

[0038] [Fig.3] is a schematic sectional view of the support of [Fig.2] where holes are formed in the layer of insulating material (step 2 of the process).

[0039] [Fig.4] is a schematic sectional view of the support of [Fig.3] on which two electronic components and a conductive track are integrated on the outer layer of insulating material, the conductive track also being integrated into two holes (step 3 of the process).

[0040] [Fig.5] is a schematic sectional view of the support of [Fig.4] on which another layer comprising insulating material and an electronic circuit is superimposed by repeating steps 1 to 3 of the method of the invention once.

[0041] [Fig.6] is a table giving several variants of parylene. DETAILED DESCRIPTION

[0042] Unless otherwise specified, the same element appearing in different figures has a single reference.

[0043] By convention, in the present application, the terms "conductor" mean "conductor of electricity, having the function of allowing an electric current to pass", while the terms "insulator" mean "electrical insulator, having the function of preventing the passage of any electric current, for example between two conductive parts subjected to a difference in electric potential".

[0044] The invention relates to a method for multilayer integration of electronic components 5 and conductive tracks 4 on a support 1 comprising a substrate 2' equipped with an electronic circuit 3' comprising at least one conductive track 4' and / or one electronic component 5', even when the surfaces of said support 1 on which the electronic components 5 and the conductive tracks 4 are integrated are not flat surfaces. The electronic circuit 3' may be an electronic circuit 3 obtained by the method of the invention or another pre-existing electronic circuit 3'.

[0045] Thus, the method of the invention can be used indifferently to integrate additional electronics on existing 2' substrates already equipped with one or several 3' electronic circuits or to integrate multilayer electronics on a 2' substrate initially devoid of electronic circuits, the first 3' electronic circuit layer then being able to be integrated in a conventional manner.

[0046] The method of the invention comprises three successive main steps, which can be repeated individually or in order, all of these steps making it possible to integrate at least one electronic component 5 and / or at least one conductive track 4 on an electronic circuit 3' so as to form an additional layer of electronic circuit 3 preferably connected at least partially to the layer of electronic circuit 3' located below. By electronic circuit 3, we mean an assembly comprising at least one electronic component 5 and / or at least one conductive track 4.

[0047] By way of example, [Fig. 1] shows a support 1 comprising an electronic circuit 3' comprising a conductive track 4' on which five electronic components 5' are integrated. The steps of the invention will be described with reference to [Fig. 2]-[Fig. 4] which illustrate the multilayer integration of electronic circuits 3 comprising conductive tracks 4 and electronic components 5 on this support 1.

[0048] The support 1 may be any part comprising a substrate 2' equipped with an electronic circuit 3'. The support 1 is for example a ceramic, a plastic support, an electronic card comprising a printed circuit, a plas-tronics substrate, a substrate obtained by selective metallization, or any other support 1 integrating electronic components 5' and conductive tracks 4'. The electronic circuit 3' may also have been obtained by the method according to the invention.

[0049] The deposition of track 4' on a plastic substrate can in particular be done by the following methods: • aerosol printing (AJP), • inkjet printing, • extrusion of conductive paste • direct laser structuring (LDS), • print and metallize (print-then-plate in English), • bi-injection (two-s / zot molding in English), • transfer of material by laser heating (laser induced forward transfer in English).

[0050] For the case where the substrate is a ceramic, the deposition of the track 4' can in particular be done by high temperature firing technology of ceramic components (HTCC for High Temperature Cofired Ceramicf by simultaneous firing at low temperature of ceramics LTCC for Low Temperature Cofired Ce ramie) or by a process already used on inertial sensors for example, in particular the deposition in thick ink-based layer (ceramic thickfilm in English).

[0051] In a first step, the entire support 1 is covered with a layer of insulating material 6 (see [Fig.2]), that is to say, all the external surfaces of the support 1 are covered, as well as all the elements mounted thereon, in particular the substrate 2' and the electronic circuit 3'. In the case where electronic components 5' are mounted on the support 1 at a distance from the conductive track 4', for example by being mounted by fixing or power supply tabs, the insulating material 6 also covers the external face of said tabs, the underside of said electronic components 5' and the surface of the conductive track 4' which is hidden under these electronic components 5'.

[0052] This deposition of a layer of insulating material 6 is preferably conformal.

[0053] By insulating layer is meant here a film of sealing and corrosion protection material, while by conformal layer is meant a film of material of low, regular and uniform thickness. By conformal insulating layer is also meant a notion of quasi-hermeticity, with a moisture penetration which is for example a hundred times lower than epoxy.

[0054] The deposition of an insulating material 6 is preferably carried out by a vapor deposition (CVD) technique, which allows the insulating material 6 to insinuate itself everywhere, to cover all the external surfaces of the support 1, whatever the shape of the latter, and to form a very thin conformal layer of insulating material 6 whose thickness can be controlled, for example with a deposition tolerance of approximately 0.1 μm.

[0055] The deposition is preferably carried out without crosslinking of the insulating material 6.

[0056] The layer of insulating material 6 deposited during this first step preferably has a thickness of between 0.1 pm and 200 pm, more preferably of between 0.5 pm and 75 pm and even more preferably of between 5 pm and 15 pm.

[0057] The insulating material 6 used is preferably parylene, which is the name of a range of polymers derived from paraxylene, also known as polypa-raxylylene, poly (p-xylylene), paraxylene, para-xylylene, p-xylylene or p-quinodimethane, and which are very well suited to the needs of the invention.

[0058] In the basic unit of parylene, the substitution of aromatic hydrogens by elements or groups modifies its properties. There are thus numerous variants of parylene in the range of polymers derived from paraxylene. In its basic form, consisting only of hydrogen and carbon atoms, we speak of parylene N.

[0059] The table in [Fig.6] gives several variants of parylene.

[0060] Among these variants, parylenes F and HT exhibit satisfactory temperature resistance, whereas parylene N exhibits degraded adhesion at 70°C. However, plasma or laser etching of F and HT parylenes has a lower etching rate than for N and C parylenes. Also, in applications, the parylene used is chosen according to the operating temperatures and the desired etching speed.

[0061] It will be noted that parylene is a non-crosslinked semi-crystalline polymer, with a crystallinity rate of the order of 50%, which can be increased by heat treatment. It is thus distinguished from epoxy which is a crosslinked three-dimensional polymer.

[0062] Thus, although parylene is preferred, the insulating material 6 is preferably based on any type of solid semi-crystalline molecule having electrical insulation properties.

[0063] According to a preferred embodiment, the deposition of parylene is a chemical vapor deposition (CVD) coating process that uses a solid precursor called p-xylylene dimer or p-cyclophane. According to a preferred embodiment, this dimer is sublimed at high temperature in an evaporation chamber, then thermally cracked in a pyrolysis chamber to form gaseous p-xylylene monomers. These monomers then condense on the surface to be coated in a deposition chamber at low pressure and room temperature, thus forming a parylene polymer film. We can therefore speak of polymerization in the sense that there is formation of a polymer from monomers, but it is a very particular polymerization that is done without catalyst, without solvent and without elimination of by-product, therefore very far from what occurs for example with an epoxy, a silicone or any other organic material of this type.To date, the exact mechanism of polymerization of p-xylylene does not yet appear to be completely elucidated, but it would involve the formation of free radicals or diradicals which add together to form linear chains.

[0064] In the case where it is desired to avoid part of the support 1 being covered with insulating material 6, it is possible to position a removable protective cover on the support 1 before the first step, a cover which is then removed before continuing with the following steps of the method.

[0065] In a second step, holes 7 are made through the external layer of insulating material 6 (see [Fig. 3]). These holes 7, or vias, are obtained by selectively removing part of the insulating material 6.

[0066] By opening out, we mean the fact that where a hole 7 is made, all the insulating material 6 is removed, allowing access to what is underneath in order to electrically connect them to conductive tracks 4 and / or to electronic components 5 deposited subsequently.

[0067] By selective removal of insulating material 6, we mean the fact that during this step, only the insulating material 6 is removed, without degrading the other materials or the elements located below it, for example without damaging the support 1 or the electronic circuit 3'3' located under the insulating material 6.

[0068] In the case where there is a pre-existing layer of insulating material 6 under the layer of insulating material 6 in which holes are to be made, two scenarios arise: • If there is no contact on this lower layer and an etching has already been started on the surface layer, it is possible to continue the etching through this layer. • If there is contact on this lower layer, the etching stops due to the difference in sensitivity on the contact.

[0069] The holes 7 made during this second step are known as “vias” by those skilled in the art. They have, for example, a round, square or rectangular cross-section.

[0070] These holes 7 are for example formed above conductive tracks 4' or electrical connectors of an electronic component 5' of the lower layer in order to create electrical contact zones with the elements of said lower layer.

[0071] Several technologies can be used to carry out the selective removal of insulating material 6. The technologies preferably used are laser etching and plasma etching.

[0072] Laser etching, for example by excimer laser or femtosecond laser, makes it possible in particular to remove the insulating material 6 selectively by adjusting the wavelength and the excitation duration of said laser, with a very precise cutting path, which can be programmed, and it does not require the use of a mask or other technique aimed at protecting the surface in which holes 7 are formed.

[0073] Excimer laser etching removes material by combustion. It is an inexpensive technology, but tends to distort the etching flanks through heating. Argon fluoride excimer lasers are preferred.

[0074] Femtosecond laser etching removes material by vaporization. It is an even more precise technology than the excimer laser and does not distort the etching flanks, but is more expensive. The femtosecond laser has the advantage of having a very short pulse time and no degradation of the material.

[0075] Plasma etching, for example oxygen plasma, nitrogen plasma or rare gas plasma, makes it possible in particular to remove the insulating material 6 quickly and inexpensively. Generally, however, this etching must be carried out through a mask provided to protect the insulating material 6 in which no hole 7 is desired. Such a mask, for example made of metal, is preferably a plate of material which is more resistant to the plasma used than the insulating material 6, and which has cutouts through which the plasma is projected, and which correspond to the areas where we want to make 7 holes.

[0076] Oxygen plasma etching makes it possible to remove the material by chemical attack when the insulating material 6 is a material containing a significant quantity of carbon, such as parylene. It does not attack metals, which in particular makes it possible not to attack the conductive tracks 4' and the other metallic elements of the electronic circuit 3, 3' located below the insulating material 6.

[0077] Nitrogen plasma etching (or nitride plasma) is a technique used to selectively modify or remove materials in the presence of activated nitrogen gas in a low-pressure environment. It is primarily used for dry etching, reactive etching, or surface cleaning applications. However, nitrogen plasma etching is generally not recommended for the modification or etching of parylene, unlike oxygen (O2) plasma etching, which is more commonly used. This is because parylene is a highly inert and chemically resistant polymer, and is therefore less reactive to the active nitrogen in the nitrogen plasma than more reactive materials such as other polymers.Additionally, parylene has high erosion resistance, meaning it is difficult to remove by conventional etching methods, and nitrogen plasma may not be powerful enough to effectively remove parylene. Finally, nitrogen plasma etching is likely to damage underlying electronic components or other materials present in parylene in addition to parylene.

[0078] Rare gas plasma etching, for example argon plasma etching, allows material to be removed by mechanical etching. This technique, although less expensive, is also less selective than oxygen plasma etching.

[0079] It is possible to combine different plasmas. For example, oxygen and argon plasma etching is very advantageous in that it allows for improved cleaning efficiency and surface quality when making holes 7.

[0080] During a third step, an electronic circuit 3 is integrated into the assembly resulting from the previous steps (see [Fig.4]). Thus, one or more conductive tracks 4 and one or more electronic components 5 are integrated into the external layer of insulating material 6 and / or into a hole 7.

[0081] The integration of a conductive track 4 is carried out by selective metallization of one or more parts of the external layer of insulating material 6 and one or more holes 7. Several conductive tracks 4 can thus be deposited, without them necessarily being electrically connected to each other during their deposition. They can be connected subsequently.

[0082] The conductive tracks 4 are preferably mainly based on gold, palladium, copper, silver, carbon or a mixture thereof. They can be deposited in the form of a liquid or aerosol conductive ink.

[0083] Several technologies can be used for the deposition of a conductive track 4. Among the technologies preferably chosen, mention may be made of aerosol printing (known by the acronym AJP, from the English Aerosol Jet Printing), inkjet printing (jetting in English) and laser structuring with chemical activation (known by the acronym LSCA, from the English Laser Structuration Chemical Activation).

[0084] The little-known LSCA process combines laser engraving and electroless metal deposition.

[0085] Sintering, for example laser sintering, also makes it possible to improve the electrical and thermal conductivity of the conductive tracks 4.

[0086] Similarly, a surface treatment of the external layer of insulating material 6 may be provided before the third step in order to improve the adhesion of this layer with the conductive track 4. This treatment is preferably carried out by plasma, by flaming (also known as flame treatment), by high-frequency electrical discharge (also known as Corona treatment) and / or by UV treatment.

[0087] The integration of an electronic component 5 on the external layer of insulating material 6 and in at least one hole 7 is carried out in a conventional manner. The electronic components 5 are preferably surface mounted by soldering.

[0088] In the case where the electronic component 5 comprises electrical contacts, at least one electrical contact can be mounted in a hole 7 or on a conductive track 4. For reasons of simplification of the figures, these electrical contacts are not shown.

[0089] The three steps of the method make it possible to integrate a layer of conductive tracks 4 and electronic components 5 on a support 1, and to connect all or part of these conductive tracks 4 and electronic components 5 with conductive tracks 4' and electronic components 5' pre-existing on the support 1.

[0090] These steps can be repeated individually, for example in order to deposit the insulating material 6, to form holes 7 and / or to integrate electronic components 5 and conductive tracks 4 several times, respectively during the first, second and third step of the method.

[0091] The three steps of the method can also be repeated in order to integrate other similar layers by superimposing them, thus offering a very large number of possibilities for routing and arranging the electronic components 5, in particular the possibility of providing several conductive tracks 4 each at a different electrical potential.

[0092] A support 1 thus comprising two superimposed layers according to the method of the invention is shown in [Fig.5], illustrating one example among the numerous pos- three-dimensional integration possibilities of the invention.

[0093] Indeed, the method of the invention makes it possible to design electronic circuits not only in two dimensions, but also in three dimensions, which in particular makes it possible to considerably increase the integration potential of the equipment. The method of the invention makes it possible to design electronic circuits in which the routing and arrangement of the electronic components can be three-dimensional.

[0094] It will also be noted that the invention, depending on the technologies used for each step, can be used both in the field of electronics and in the field of microelectronics.

[0095] Although described through a certain number of examples, variants and embodiments, the method according to the invention comprises various variants, modifications and improvements which will appear obvious to those skilled in the art, it being understood that these variants, modifications and improvements are part of the scope of the invention.

Claims

Claims

1. Method for integrating electronic components (5) and conductive tracks (4) on a support (1), said support (1) comprising a substrate (2') equipped with an electronic circuit (3'), characterized in that it comprises the following successive steps: - step 1: depositing an insulating material (6) on the support (1) so as to cover the entire support (1), including the substrate (2') and the electronic circuit (3'), with an external layer of insulating material (6), - step 2: selective removal of a portion of the insulating material (6) so as to form at least one hole (7) opening through the external layer of insulating material (6), - step 3: integrating an electronic circuit (3) on the external layer of insulating material (6) and / or in at least one hole (7).

2. Method according to claim 1, characterized in that the deposition of the insulating material (6) of step 1 is carried out by a vapor deposition process.

3. Method according to any one of the preceding claims, characterized in that the insulating material (6) is parylene, namely a material chosen from polymers derived from paraxylene.

4. Method according to any one of the preceding claims, characterized in that the layer of insulating material (6) obtained in step 1 has a thickness of between 0.1 qm and 200 qm, preferably between 0.5 qm and 75 qm and more preferably between 5 qm and 15 qm.

5. Method according to any one of the preceding claims, characterized in that the selective removal of step 2 is carried out using one of the following technologies or their combination: - excimer laser etching, - femtosecond laser etching, - oxygen plasma etching, - nitrogen plasma etching, - rare gas plasma etching.

6. A method according to any preceding claim, ca- characterized in that the electronic circuit (3) integrated in step 3 comprises at least one electronic component (5) and / or a conductive track (4).

7. Method according to the preceding claim, characterized in that step 3 comprises a step of selective metallization of at least a part of the external layer of insulating material (6) and / or of at least one hole (7) so as to deposit a conductive track (4) there.

8. Method according to the preceding claim, characterized in that the deposition of the conductive track (4) during step 3 is carried out using one of the following technologies or their combination: - aerosol printing (AJP), - inkjet printing, - chemically activated laser structuring (LSCA).

9. A method according to any one of the preceding claims, characterized in that steps 1, 2 and 3 are repeated in order, at least once.

10. Method according to any one of the preceding claims, characterized in that the electronic circuit (3) obtained during steps 1, 2 and 3 is electrically connected with at least one other electronic circuit (3, 3') of a lower layer.

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