Handling multiple invalidations of a cache memory

Abstract

The invention relates to a processor comprising multiple cores (10), each including a local cache (L1); multiple memory banks (12) forming a memory shared by the multiple cores; a directory-based cache coherence protocol manager (DIR), comprising for each core a circuit (16) for consolidating multiple cache line invalidation (INVAL) commands received from the different memory banks. The consolidation circuit includes a counter of received invalidation commands (PARCNT); a selection circuit (32) configured to, depending on whether the count (N) of received invalidation commands is equal to or greater than 1, transmit to the cache either the single received invalidation command or an invalidation command consolidating the cache lines identified in the received invalidation commands, in a format usable by the cache to simultaneously invalidate the identified cache lines. Figure for the abstract: Fig. 3

Description

Title of the invention: Management of multiple cache invalidations technical field

[0001] The invention relates to cache coherency management in a multi-core processor system whose cores can simultaneously access different banks forming a shared memory. Background

[0002] Several cache coherency protocols exist designed to ensure, in a multicore system, that the local cache of each processor core reflects the data updated in shared memory by the other cores.

[0003] A commonly used operation in consistency protocols is the invalidation of cache lines. At some point, the same memory block, or cache line, may be duplicated in different local caches. If a core writes to memory at an address corresponding to this cache line, the copies in the other cores become obsolete.

[0004] To account for this, when a core writes to memory, the cache coherence protocol sends an invalidation command to other cores that have the corresponding cache line. This invalidation command instructs the local cache controllers to invalidate their local copies. A core accessing a cache line thus invalidated in its local cache will have to retrieve the updated line from memory again.

[0005] To manage the sending of invalidation commands, the consistency protocol can be based on a directory in which the memory controller records the cache lines used and the cores that have them in their caches.

[0006] When shared memory is structured into multiple banks simultaneously accessible by all cores, each bank is likely to send a simultaneous invalidation command to the relevant cores. Thus, a given core can receive several simultaneous invalidation commands. The processing of these multiple commands by the cache controller can result in a latency of several cycles during which the memory banks that sent these invalidation commands cannot normally acknowledge the write accesses that triggered them.

[0007] To avoid such latency, techniques have been proposed that allow the cache controller to process several invalidation commands simultaneously. An example of such a technique is described in US patent 6701417, which uses a protocol based on directories and write-through caches. More specifically Essentially, this patent proposes partitioning the local cache into several banks, each designed to handle a specific invalidation command. Thus, the cache controller can process a maximum of as many invalidation commands simultaneously as there are banks. Summary

[0008] A method for managing cache coherency in a multi-core processor system is generally provided, where each core has a respective cache and access to several banks of memory shared between the cores, the method comprising the steps of managing a directory in each memory bank for the implementation of directory-based cache coherence; accessing a current memory address by a core for writing; searching in the directory managing the current address for cores that have a cache line corresponding to the current address; sending to the cores identified by the directory respective commands for invalidating the cache line, the commands including the memory address of the cache line; and for each core, serving multiple invalidation commands received from different memory banks.The multiple invalidation command service includes the steps of counting the number of invalidation commands received since the last clock cycle; when the count of received invalidation commands is one, passing the received invalidation command to the cache; and when the count of received invalidation commands is greater than one, passing to the cache a single command consolidating the cache lines identified in the received invalidation commands, in a format usable by the cache to simultaneously invalidate the identified cache lines.

[0009] Each core can have a respective multi-way set associative cache, the method then comprising the steps of registering in directories the paths in which the caches store the cache lines; transmitting the paths in the invalidation commands sent to the cores; and including in the consolidated invalidation command, for each invalidation command received, a pair of coordinates including a set index, extracted from the memory address, and the path.

[0010] The method may include the step of responding via the cache to the consolidated invalidation command by simultaneously invalidating each cache line located at the intersection of the set and the path determined by a respective pair of coordinates.

[0011] The service for multiple invalidation commands may include the steps of forming a bit mask comprising a bit set to 1 at positions identified by indexes of sets extracted from the memory addresses of the received invalidation commands; when the count of received invalidation commands exceeds a threshold, include the bitmask in the consolidated invalidation command; and respond via the cache to the consolidated command by simultaneously invalidating the cache sets marked in the bitmask.

[0012] The directory can store the cores and lanes for each cache line in the form of a combined bitmask marking the cores having the line in their cache and the lanes in which the line is present in the caches of those cores, the lane information passed in the invalidation commands then including the bits of the bitmask identifying the lanes.

[0013] Consolidated invalidation commands can be configured to carry a field comprising a fixed number of bits, the first part of which identifies a command type among an original invalidation command, a consolidated command with coordinates, and a consolidated command with bitmask, and the second part defines for the respective types: the cache line address, the coordinate pairs, and the bitmask.

[0014] A processor is also provided comprising multiple cores, each with a local cache; multiple memory banks forming a shared memory for the multiple cores; a directory-based cache coherence protocol manager, comprising for each core a circuit for consolidating multiple cache line invalidation commands received from the different memory banks. The consolidation circuit includes a counter for received invalidation commands; a selection circuit configured to, depending on whether the count of received invalidation commands is equal to 1 or greater, transmit to the cache either the single received invalidation command or an invalidation command consolidating the cache lines identified in the received invalidation commands, in a format usable by the cache to simultaneously invalidate the identified cache lines.

[0015] Each core can have a respective multi-way set-associative cache, the processor further comprising a directory associated with each bank, configured to record with each cache line, the lanes in which the cache line is present in the different cores and to include the lanes in the invalidation commands sent to the cores; and the consolidation circuit configured to include in the consolidated invalidation command, for each cache line invalidation command received, a pair of coordinates including a set index, extracted from a memory address of the cache line, and the lane.

[0016] The consolidation circuit can be configured to include in the consolidated invalidation command, when the count of received invalidation commands is greater than a threshold, a bit mask marking cache sets to be invalidated, where each set includes the cache line identified by a respective received invalidation command.

[0017] According to an alternative, in a multi-core processor system, where each core has a respective multi-way set-associative cache and access to several banks of memory shared between the cores, a cache coherence management method comprises the steps of managing a directory in each memory bank for the implementation of directory-based cache coherence; writing to a current memory address by a core; searching the directory managing the current address for cores that have a cache line corresponding to the current address; sending the respective cache line invalidation commands to the cores identified by the directory, the commands including the memory address of the cache line; for each core, serving multiple invalidation commands received from different memory banks;to record in directories the paths in which the caches store the cache lines; to transmit the paths in the invalidation commands sent to the cores; to serve the multiple invalidation commands received by a core by transmitting to the core's cache a single consolidated command including, for each received invalidation command, a pair of coordinates including a set index, extracted from the memory address of the cache line, and the path; and to respond with a cache to a consolidated invalidation command by simultaneously invalidating each cache line located at the intersection of the set and the path determined by a respective pair of coordinates.

[0018] The multiple invalidation command service may include the steps of counting the number of invalidation commands received since a last clock cycle; forming a bit mask including a bit set to 1 at the positions identified by the set indices; when the count of received invalidation commands is greater than a threshold, including the bit mask in the consolidated invalidation command in place of the coordinate pairs; and responding from the cache to the consolidated command by simultaneously invalidating the cache sets marked in the bit mask. Brief description of the drawings

[0019] Embodiments will be set forth in the following description, which is not exhaustive and relates to the accompanying figures, among which:

[0020] The [Fig. 1] partially represents an embodiment of a multicore processor architecture configured to implement a directory-based cache coherence protocol;

[0021] Fig. 2A represents three types of consolidated invalidation commands, according to one embodiment, allowing a cache controller to simultaneously invalidate multiple cache lines;

[0022] Figure 2B represents an example of a record in a directory used for a cache consistency protocol; and

[0023] The [Fig.3] is a block diagram of a logic circuit configured to generate the consolidated commands of the [Fig.2A]. Detailed description

[0024] The cache coherence protocol described in US patent 6701417 requires a particular cache structure and the number of invalidation commands that can be processed simultaneously is limited to the number of cache banks, in practice four.

[0025] A cache coherence protocol is described below in which the cache controller can simultaneously process all invalidation commands that may arrive at it, at the cost of a performance compromise beyond a certain threshold number of commands processed simultaneously. In the worst case, for a multi-way set-associative cache, the compromise is the gross invalidation of an entire set of cache lines, instead of invalidating a single cache line.

[0026] The concept of simultaneous processing of several invalidation commands is relative to a core clock cycle. In practice, the processing is carried out asynchronously by combinational logic circuits that produce the desired operations in a time that varies depending on the case, but which remains less than one clock period.

[0027] Furthermore, the protocol is adaptive by selecting between several modes depending on the number of invalidation commands to be processed. In the first mode, selected for a single command to be processed, a classic invalidation command can be used, which is precise, allowing the identification of the cache line in question and invalidating it only if it is still present in the cache, i.e., listed in the cache's label memory.

[0028] In a crude mode, which can be selected for any number of commands to be processed, a consolidated command is produced which simultaneously invalidates the sets containing the relevant cache lines.

[0029] A less aggressive intermediate mode is preferably used up to a certain threshold of the number of commands to be processed, producing a consolidated invalidation command that identifies each cache line by a pair of coordinates (set containing the line, lane containing the line). The cache controller then simultaneously invalidates all lines identified by these pairs of coordinates. The presence of these lines in the cache is not checked, which is a small price to pay for the ability to process these multiple invalidation commands simultaneously. In practice, invalidating a line that is not in the cache invalidates a memory location intended to hold a cache line. This location may be empty, in which case it is already invalid and the operation has no effect. can also contain a new cache line, in which case this new line is invalidated "for nothing", but this simply results in later latency to reload the line when the core tries to access it.

[0030] The number of invalidations that can be processed in this mode depends on the size of a parameter of the consolidated control, which size conditions the number of pairs that can be transmitted.

[0031] The efficiency of this protocol, in terms of granularity in selecting cache lines to invalidate, is related to the frequency of cases where bursts of multiple simultaneous invalidation commands occur, and to the number of commands to be processed in each burst. In practice, it turns out that cases where only one invalidation command needs to be processed are more frequent than bursts of several commands. Moreover, bursts with a small number of commands (for example, between 2 and 4) are more frequent than those with a larger number of commands.

[0032] Figure 1 partially represents a multi-core processor architecture usable for implementing such a directory-based cache coherence protocol. Two processor cores 10 have simultaneous read and write access (RW) to several banks 12 (only three of which are shown) of shared memory through a matrix switch ("crossbar") managed by ARBITERs. Each core includes a local Level 1 cache (LL).

[0033] Cache consistency is managed by a DIR directory, which can be centralized or distributed, as shown, in each memory bank 12. The directories are configured to record the cache lines in use in each core. Each DIR directory associated with a bank lists only the cache lines corresponding to the physical addresses assigned to the bank. The directories communicate with the cores via their respective "master-sides" 16, which can be part of the L1 caches or the matrix switch. The master-sides are connected to the DIR directories by point-to-point signaling links, shown as dashed lines.

[0034] Conventionally, a directory receives a new record each time a core misses a read from its cache and retrieves the corresponding cache line from the database. The new record identifies the cache line and the core. A record is kept in the directory until that cache line is invalidated. Thus, the directory information may become outdated in the meantime.

[0035] Directory records are generally stored in associative memory indexed by the physical addresses of cache lines.

[0036] When a given core performs a write access to a memory line subject to consistency checks, this event is reported to the directories. The directory responsible for maintaining the consistency of that address then issues an INVAL invalidation to the other cores registered as owners of this cache line.

[0037] In order to manage multiple invalidations simultaneously according to the adaptive mode described above, each master side includes a CONSLD consolidation circuit that receives individual invalidation commands from all directories. From the individual invalidation commands, this circuit produces a consolidated invalidation command C-INVAL for the corresponding L1 cache memory.

[0038] As previously indicated, the consolidated command can be of two, or preferably three types: PRECISE, ARRAY_OF_SLOTS, and MASK_OF_SETS.

[0039] Fig. 2A illustrates an example of formats for the three types of consolidated commands, assuming for the sake of example that the physical memory addresses are 40 bits and the cache is an associative cache with 64 sets of 8 paths whose lines have 64 bytes (i.e. a cache of 32 kB).

[0040] Each consolidated command comprises two identifier bits of type IType[65:64] followed by a 64-bit field IData[63:0] whose function depends on the type. A binary identifier of 00 indicates that there are no invalidations to process.

[0041] The binary identifier 01 corresponds to the PRECISE type. This consolidated command is generated when a single invalidation command has been pending since the last clock cycle. Its IData field provides what the single incoming invalidation command normally provides, namely the physical address @PHY[39:0] used for memory access. In principle, a number of the least significant bits of the physical address, called the offset and defining the position of the data in a cache line, are not useful, so we can remove 6 of these least significant bits here and keep only @PHY[39:6]. In the truncated address thus, the 6 least significant bits [11:6] constitute what is called the index and are used to identify the set containing the cache line.The remaining most significant bits [39:12] are what is called the label or "tag", which is used to consult the cache's label memory, which identifies, among other things, the path containing the cache line. If the label memory does not provide a corresponding value, it means that the cache line has been evicted after the directory issued the invalidation command.

[0042] A consolidated command of type PRECISE is treated by the cache controller as a classic invalidation command, invalidating the unambiguously identified cache line.

[0043] The binary identifier 10 corresponds to the ARRAY_OF_SLOTS type. This consolidated command is generated when two or more invalidation commands are received simultaneously on the same clock cycle. The number of commands that can be processed simultaneously is limited by the size of the IData field, here 64 bits. This IData field In this example, four 14-bit data points are used to identify four cache lines to be invalidated. The 56 bits corresponding to these data points can be right-aligned in the IData field. Each 14-bit data point corresponds to a pair of coordinates, namely, in this example, a 6-bit index IDX[5:0] and an 8-bit lane W[7:0]. The cache line to be invalidated is therefore the one located at the intersection of the set identified by the index IDX and the lane identified by the W field.

[0044] For reasons discussed later, the W field in this example is an 8-bit mask, identifying one to eight lanes by the position of a bit at 1. According to an alternative, the lane number can be coded on 3 bits, in which case the IData field could contain 7 pairs of coordinates.

[0045] In this example, the IDX indices correspond to bits [11:6] of the respective physical addresses provided by the individual incoming invalidation commands. If fewer than four invalidation commands are to be processed, the W masks associated with the missing commands can be set to 0, indicating that they will be ignored.

[0046] As for the values ​​of the W fields identifying the channels, the DIR directories are configured to further record the channels in which the lines are stored in the caches, and also broadcast these channels in the invalidation commands. These channels broadcast by the invalidation commands are then included in the W fields of the consolidated invalidation command of type ARRAY_OF_SLOTS.

[0047] At the DIR directory level, ideally each cache line is recorded with the cores that possess it and, for each core, the channel in which it is located. This can represent a significant number of bits to manipulate for each line in a system with a large number of cores. For example, for 16 cores with 8-way caches, 16 three-bit fields, or 48 bits, would be needed to encode one of eight channels for each of the 16 cores.

[0048] Figure 2B illustrates a directory registration embodiment that reduces complexity and hardware cost, but at the cost of reduced channel identification accuracy. In each directory, for each cache line registered @PHY[39:6], a core mask CORE[15:0] with one bit for each core and a channel mask W[7:0] with one bit for each channel are maintained. This reduces the number of bits to 24 for a 16-core system with 8-channel caches. It is then the W channel mask of this registration that is transmitted in the corresponding invalidation command.

[0049] With such lane masks, if several cores use the same cache line but that line is stored in a different lane in each core, the lane mask for that cache line would have several bits set to 1.

[0050] The cache controller is configured to process such a consolidated command in reading each pair of coordinates (IDX, W) and, for each pair, invalidating the cache lines at the intersection of the set identified by IDX and the channels marked in W. If the channel mask W contains more than one 1 bit, additional cache lines, if they exist in the cache, will be unnecessarily invalidated, but this is the price to pay for simplifying the directory structure. In practice, situations where more than one channel is marked in a channel mask are infrequent.

[0051] A cache line can be invalidated by the cache controller conventionally by toggling a validity flag in a flip-flop matrix representing the intersections of the cache sets and lanes. Each of these flip-flops is individually accessible by the controller's logic circuits, so these circuits can be configured to simultaneously toggle any number of flags. Once a flag is thus set to "invalid", a subsequent core read access to that location fails after checking the flag ("cache miss") and is redirected to shared memory to reload an up-to-date cache line.

[0052] The binary identifier 11 corresponds to the MASK_OF_SETS type. This consolidated command is generated when the number of invalidations to be processed exceeds the number of commands that a consolidated command of the ARRAY_OF_SLOTS type can process, namely 4 in this example. The IData field is then an S-MASK[63:0] set mask where each bit set to 1 indicates that the set corresponding to the bit's position in the mask should be invalidated. Thus, the size of the IData field is at least equal to the number of sets in the cache, 64 in this example.

[0053] To generate the S-MASK, the index fields of the physical addresses of the pending invalidation commands are used, namely the @PHY[11:6] values. The @PHY[11:6] values ​​determine the positions of the bits to be set to 1 in the S-MASK. This S-MASK can then be used by the cache controller to simultaneously invalidate all sets marked in this mask.

[0054] Figure 3 is a block diagram of a logic circuit configured to generate consolidated commands, including the contents of the IData field for each type of consolidated command. Such a circuit can be integrated into each master side, at the CONSLD block level of Figure 1. The circuit operates on all point-to-point connections between the master side and the memory bank directories.

[0055] From each of the memory banks, 16 in this example, the circuit receives a bundle of INVAL_i conductors used to transmit an invalidation command. One conductor carries an EN_i flag indicating the presence of an invalidation command, the following conductors carry the address of the cache line to be invalidated @PHY[39:6], and the last conductors carry the channel mask. W[7:0]. The EN_i flags are supplied to individual inputs of a parallel PARCNT counter, which provides the number of active commands N at any given time. The concatenation of these flags forms a 16-bit mask of active commands EN[15:0]. The count N controls two four-way multiplexers 30 and 32, which respectively produce the IType and IData parameters of the consolidated invalidation command C-INVAL.

[0056] When N = 0, the multiplexer 30 selects the binary value 00 for IType, and the multiplexer 32 selects the value 0 for IData.

[0057] When N = 1, the multiplexer 30 selects the binary value 01 for IType, and the multiplexer 32 selects the output of a combinational logic circuit CL0 for IData.

[0058] The CL0 circuit receives all cache line addresses @PHY[39:6] and forwards the one for which the EN_i flag is active.

[0059] When 1 < N < 4, the multiplexer 30 selects the binary value 10 for IType, and the multiplexer 32 selects the output of a combinational logic circuit CL1 for IData.

[0060] Circuit CL1 receives all IDX index values ​​contained in the least significant bits of the cache line addresses, namely the @PHY[11:6] bits in this example, and also receives the W[7:0] channel masks. The circuit forms the value pairs (IDX index, W channel mask) for only those values ​​that have an active EN_i flag, and positions them in 56 bits used to form the IData field.

[0061] When N > 4, the multiplexer 30 selects the binary value 11 for IType, and the multiplexer 32 selects the output of a combinational logic circuit CL2 for IData.

[0062] The CL2 circuit receives all the IDX index values ​​contained in the cache line addresses, namely the @PHY[11:6] bits in this example. The circuit forms a 64-bit mask by setting to 1 all the bits at the positions determined by the indices whose EN_i flag is active.

[0063] According to an alternative to the PRECISE-type consolidated invalidation command, since the directories store and transmit the W channel information, the CL0 circuit can be designed simply to extract the IDX, W pair from the single received invalidation command, effectively forming a special case of an ARRAY_OF_SLOTS type command. This saves a clock cycle required to consult the cache label memory, at the cost of the risk of unnecessarily invalidating a evicted cache line or additional cache lines if the W mask marks multiple channels. Such an alternative is in fact implemented by omitting the CL0 circuit and using the CL1 circuit for counts N between 1 and 4.

Claims

Demands

1. A method for managing cache coherency in a multicore processor system, wherein each core (10) has a respective cache (L1) and access to multiple banks (12) of memory shared between the cores, the method comprising the following steps: managing a directory (DIR) in each memory bank for implementing directory-based cache coherence; writing to a current memory address by a core; searching the directory managing the current address for cores that have a cache line corresponding to the current address; sending respective invalidation (INVAL) commands to the cores identified by the directory, the commands including the memory address of the cache line; and for each core, serving multiple invalidation commands received from different memory banks;characterized in that the service step of the multiple invalidation commands comprises the following steps: counting the number (N) of invalidation commands received since a last clock cycle; when the count of received invalidation commands is one, transmitting the received invalidation command (PRECISE) to the cache; and when the count of received invalidation commands is greater than one, transmitting to the cache a single command (C-INVAL) consolidating the cache lines identified in the received invalidation commands, in a format usable by the cache to simultaneously invalidate the identified cache lines.

2. A method according to claim 1, wherein each core has a respective multi-way set associative cache, the method further comprising the following steps: registering in directories (DIR) the paths (W) in which the caches store the cache lines; transmitting the paths in the invalidation commands sent to the cores; and including in the consolidated invalidation command, for each received invalidation command, a pair of coordinates including a set index (IDX), extracted from the memory address, and the path (W).

3. A method according to claim 2, comprising the step of responding by the cache to the consolidated invalidation command by simultaneously invalidating each cache line located at the intersection of the set and the path determined by a respective pair of coordinates.

4. A method according to claim 2, wherein the service step of multiple invalidation commands comprises the following steps: forming a bit mask (MASK_OF_SETS) comprising a bit set to 1 at positions identified by set indexes (IDX) extracted from the memory addresses of the received invalidation commands; when the count of received invalidation commands exceeds a threshold, including the bit mask in the consolidated invalidation command; and responding from the cache to the consolidated command by simultaneously invalidating the cache sets marked in the bit mask.

5. A method according to claim 2, wherein the directory stores the cores and lanes for each cache line in the form of a combined bitmask marking the cores having the line in their cache and the lanes in which the line is present in the caches of those cores, and the lane information passed in the invalidation commands includes the bits of the bitmask identifying the lanes.

6. A method according to claim 2, wherein the consolidated invalidation commands are configured to carry a field comprising a fixed number of bits of which: a first part (IType) identifies a command type among an original invalidation command, a consolidated command with coordinates, and a consolidated command with bitmask, and a second part (IData) defines for the respective types: the cache line address, the coordinate pairs, and the bitmask.

7. Processor comprising: multiple cores (10) each comprising a local cache (L1); multiple memory banks (12) forming a memory shared by the multiple cores; a directory-based cache coherence protocol manager (DIR), comprising for each core a circuit (16) for consolidating multiple cache line invalidation (INVAL) commands received from the different memory banks, the consolidation circuit comprising: a counter of received invalidation commands (PARCNT); a selection circuit (32) configured to, depending on whether the count (N) of If the number of received invalidation commands is equal to 1 or greater, pass to the cache either the single received invalidation command or an invalidation command consolidating the cache lines identified in the received invalidation commands, in a format usable by the cache to simultaneously invalidate the identified cache lines.

8. Processor according to claim 7, wherein each core has a respective multi-way set-associative cache, the processor further comprising: a directory (DIR) associated with each bank, configured to record with each cache line, the lanes in which the cache line is present in the different cores and to include the lanes (W) in the invalidation commands sent to the cores; and the consolidation circuit configured to include in the consolidated invalidation command, for each cache line invalidation command received, a pair of coordinates including a set index (IDX), extracted from a memory address of the cache line, and the lane (W).

9. A processor according to claim 8, wherein the consolidation circuit is configured to include in the consolidated invalidation command, when the count of received invalidation commands is greater than a threshold, a bitmask marking cache sets to be invalidated, where each set includes the cache line identified by a respective received invalidation command.

10. A method for managing cache coherency in a multicore processor system, wherein each core (10) has a respective multi-way set-associative cache (L1) and access to multiple banks (12) of memory shared between the cores, the method comprising the following steps: managing a directory (DIR) in each memory bank for implementing directory-based cache coherence; writing to a current memory address by a core; searching the directory managing the current address for cores that have a cache line corresponding to the current address; sending to the cores identified by the directory respective invalidation (INVAL) commands for the cache line, the commands including the memory address of the cache line; and for each core, serving multiple received invalidation commands from different memory banks; characterized in that it comprises the following steps: save in directories (DIR) the paths (W) in which the caches store the cache lines; transmit the channels in the invalidation commands sent to the cores; and to serve the multiple invalidation commands received by a core by transmitting to the core cache a single consolidated command (C-INVAL) including, for each received invalidation command, a pair of coordinates including a set index (IDX), extracted from the memory address of the cache line, and the channel (W); and respond with a cache to a consolidated invalidation command by simultaneously invalidating each cache line located at the intersection of the set and the path determined by a respective pair of coordinates.

11. A method according to claim 10, wherein the service step of the multiple invalidation commands comprises the following steps: counting the number (N) of invalidation commands received since a last clock cycle; form a bit mask (MASK_OF_SETS) including a bit set to 1 at the positions identified by the set indices (IDX); when the number of received invalidation commands exceeds a threshold, include the bitmask in the consolidated invalidation command instead of the coordinate pairs; and respond via the cache to the consolidated command by simultaneously invalidating the cache sets marked in the bitmask.

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