METHOD FOR FABRICATING A STACKED STRAINED SILICON-ON-INSULATOR STRUCTURE USING A 2D MATERIAL-BASED LAYER TRANSFER TECHNIQUE

Abstract

The invention relates to a method of manufacturing a stacked structure comprising a layer of semiconductor material adhered to a substrate, comprising: manufacturing a heterostructure by:forming an interlayer made of a two-dimensional material on a growth substrate (1);patterning the interlayer with a plurality of openings to form a patterned interlayer (3);growing a semiconductor material on the patterned interlayer (3) by epitaxial lateral overgrowth to form a continuous epitaxial layer (4) on the patterned interlayer;forming a first assembly by bonding the heterostructure with a handle substrate (6), the continuous epitaxial layer being located at the bonding interface;separating the first assembly at the level of the patterned interlayer (3) so as to obtain a second assembly resulting from the transfer of the continuous epitaxial (4) layer from the heterostructure towards the handle substrate (6). Figure pour l’abrégé : Figure 7

Description

Title of Invention: Method of manufacturing a stacked structure of the strained-SOI type using a 2D material-based layer transfer technique Technical Field

[0001] The field of the invention is that of methods for manufacturing a stacked structure comprising a layer of semiconductor material adhered to a substrate. More particularly, the invention relates to processes that implement a 2D material-based layer transfer technique in order for instance to manufacture a stacked structure of the strained-SOI type. DESCRIPTION OF RELATED ART

[0002] Remote epitaxy is an emerging technology for producing single-crystalline, free-standing thin films and structures. The method uses 2D van der Waals materials as semi-transparent interlayers that enable epitaxy and exfoliation of épitaxial layers at the 2D layer interface by mechanical délamination, known as 2D material-based layer transfer (2DLT).

[0003] As for instance described in WO 2019 / 099461 Al, the 2DLT process may use a patterned 2D layer with a plurality of openings therein and the layer transfer is performed by first depositing a stressor layer made of nickel on the épitaxial layer previously grown on the patterned 2D material layer and then applying a tape layer on the stressor layer. The stack consisting of the tape layer, the stressor layer and the épitaxial layer can then be exfoliated following a detachment induced at the 2D patterned layer by mechanical energy. After exfoliation, the tape layer and the stressor layer are respectively released and etched away by a Fe-C13 solution. However, iron is an unwanted contaminant for making semiconductor devices in general. BRIEF DESCRIPTION OF THE INVENTION

[0004] The invention aims at proposing a 2DLT technique that would not require the use of a stressor layer and be therefore free of its associated contamination. To this purpose is proposed a method of manufacturing a stacked structure comprising a layer of semiconductor material adhered to a substrate, comprising: - manufacturing a heterostructure by: • forming an interlayer made of a two-dimensional material on a growth substrate; • patteming the interlayer with a plurality of openings to form a patterned interlayer; • growing a semiconductor material on the patterned interlayer by épitaxial latéral overgrowth to form a continuous épitaxial layer on the patterned interlayer; - forming a first assembly by bonding the heterostructure with a handle substrate, the continuous épitaxial layer being located at the bonding interface; - separating the first assembly at the level of the patterned interlayer so as to obtain a second assembly resulting from the transfer of the continuous épitaxial layer from the heterostructure towards the handle substrate.

[0005] Patteming the interlayer is performed so that 1% to 10% of a surface of the growth substrate on which the patterned interlayer is located is uncovered with the remainder being covered by the two-dimensional material.

[0006] Bonding the heterostructure with the handle substrate comprises one of a surface activated bonding, an atomic diffusion bonding and a hydrophilic bonding ac-companied by a bonding strength reinforcement annealing.

[0007] Certain preferred, but non-limiting aspects of the method are as follows : - the handle substrate includes a top oxide layer which is located at the bonding interface when forming the first assembly; - the handle substrate further includes a trap rich layer underneath the top oxide layer; - it further comprises planarizing the top oxide layer before forming the first assembly; - the continuous épitaxial layer is a relaxed layer and manufacturing the het-erostructure further comprises the épitaxial déposition of a strained layer on the continuous épitaxial layer; - it further comprises removing the continuous épitaxial layer from the second assembly; - the strained layer is a strained Silicon layer; - the growth substrate comprises a graded buffer and a relaxed growth layer on the graded buffer, the graded buffer having a lattice parameter graded between a first lattice parameter and a second lattice parameter and the relaxed growth layer having the second lattice parameter; - it further comprises, after separating the first assembly at the level of the patterned interlayer, recycling the growth substrate, wherein said recycling comprises polishing the relaxed growth layer; - the continuous épitaxial layer is a relaxed layer; - it further comprises planarizing the continuous épitaxial layer before forming the first assembly; - patteming the interlayer leaves a peripheral ring of the two-dimensional material on the growth substrate; - two neighbouring openings of the patterned interlayer are separated by a distance which is less than 40 micrometers, preferably less than 20 mi-crometers. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Other aspects, aims, advantages and features of the invention will better appear upon reading the following detailed description of preferred embodiments thereof, provided as a non-limiting example, and done in reference to the appended drawings, in which: - Figures 1 to 9 illustrate a possible embodiment of a method according to the invention; - Figures 10 and 11 show two different embodiments of an heterostructure which can be used in a method according to the invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] The invention relates to a method of manufacturing a stacked structure comprising a layer of semiconductor material adhered to a substrate, which method implements a 2DLT process. More particularly, the 2DLT process makes use of a patterned 2D material layer with a plurality of openings therein.

[0010] This method comprises manufacturing an heterostructure. With reference to [Fig.l], this manufacturing starts with providing a growth substrate 1.

[0011] Then, with reference to [Fig.2] manufacturing the heterostructure comprises forming an interlayer 2 made of a two-dimensional material on the growth substrate 1. This formation may be performed after planarization of the surface of the growth substrate 1, for example by means of Chemical mechanical polishing. This formation may include the déposition of the two-dimensional material on the growth substrate 1. Non-exhaustively, this déposition can be performed by means of MBE (Molecular Beam Epitaxy), CVD (Chemical Vapor Déposition) or ALD (Atomic Layer Epitaxy).

[0012] The two-dimensional material can be hexagonal boron nitride h-BN, graphene or more generally any 2D "Van der Waals" material allowing remote epitaxy. The interlayer 2 of two-dimensional material is thus constituted of monoatomic sheets having weak interactions between them and whose number is limited to allow the remote epitaxy of a layer of semiconductor material.

[0013] With reference to [Fig.3], manufacturing the heterostructure further comprises patterning the interlayer 2 with a plurality of openings to form a patterned interlayer 3.

[0014] Patterning the interlayer offers several advantages as for instance discussed in Kim, H., Lee, S., Shin, J. et al. Graphene nanopattern as a universal epitaxy platform for single-crystal membrane production and defect réduction. Nat. Nanotechnol. 17, 1054-1059 (2022). https: / / doi.org / 10.1038 / s41565-022-01200-6. In particular, patterning the interlayer can reduce the interface toughness between the growth substrate 1 and a continuous épitaxial layer 4 grown on the patterned interlayer as discussed below.

[0015] The openings may be made by etching the 2D material following a lithographie process. The openings may be trenches that delineate strips of 2D material. The trenches may be parallel to each other. A width of the trenches may be comprised between several tens of nanometers to several micrometers. Two neighbouring openings of the patterned interlayer are separated by a distance (the width of the stripes in case of parallel trenches) which is less than 40 micrometers, preferably less than 20 micrometers. This distance between openings is calibrated against latéral to vertical growth speed différence and CTE matching of materials so as to prevent bow, warp or cracks from occurring.

[0016] In a preferred embodiment, patterning the interlayer is performed so that the patterned interlayer 3 has an opening ratio comprised between 1% and 10%, i.e., 1% to 10% of a surface of the growth substrate on which the patterned interlayer is located is uncovered with the remainder being covered by the two-dimensional material. In other words, the growth substrate has a 2D material coverage percentage comprised between 90% and 99%.

[0017] The 1% lower bound is calibrated for a preferred embodiment described later (where a strained Si layer is grown on a continuous épitaxial layer 4 made of relaxed SiGe which is itself grown on a 2D material patterned with parallel trenches) and allows reaching coalescence for thicknesses not causing CTE mismatch issues. The 10% upper bond allows operating in the exfoliation régime, and not in the other two régimes, namely spalling or délamination.

[0018] In a possible embodiment, patterning the interlayer is performed so as to leave a pe-ripheral ring of the two-dimensional material on the growth substrate. The presence of such a peripheral ring facilitâtes the initiation of the later séparation at the level of the patterned interlayer.

[0019] With reference to [Fig.4], manufacturing the heterostructure further comprises growing a semiconductor material on the patterned interlayer by épitaxial latéral overgrowth to form a continuous épitaxial layer 4 on the patterned interlayer 3. More particularly, growing the semiconductor material starts with the localized growth of seeds in the openings patterned in the 2D material. The latéral growth of these seeds is then activated which results in the seeds growing laterally over the 2D material and finally coalescing to produce the continuous épitaxial layer 4.

[0020] In a preferred embodiment, the continuous épitaxial layer 4 is then planarized, for instance by means of a chemical-mechanical polishing CMP, to improve its mor-phological quality and more particularly to obtain a uniform and controllable thickness and fewer coalescent defects.

[0021] In another embodiment shown on [Fig.5], manufacturing the heterostructure may further comprise performing the épitaxial déposition of one (or more) additional layer(s) 5 on the continuous épitaxial layer 4. A bilayer can thereby be formed which is separated from the growth substrate 1 by the pattemed interlayer 3. The additional layer 5 may be a strained layer, as will be exemplified below.

[0022] Once the heterostructure is manufactured, with reference to [Fig.6] the method of the invention comprises forming a first assembly by bonding the heterostructure with a handle substrate 6, the continuous épitaxial layer 4 being located at the bonding interface. In the case where an additional layer 5 has previously been formed on the continuous épitaxial layer, the bilayer which includes the continuous épitaxial layer 4 is located at the bonding interface.

[0023] In a preferred embodiment, the handle substrate 6 includes a top oxide layer 7 which is located at the bonding interface when forming the first assembly. The handle substrate 6 may further include a trap rich layer underneath the top oxide layer.

[0024] The top oxide layer 7 may be planarized, for instance by means of a chemical-me-chanical polishing CMP, before forming the first assembly. In particular, such pla-narization proves to be advantageous to reduce the surface roughness of the top oxide layer when grown on a trap rich layer.

[0025] In an example embodiment, the handle substrate 6 is a Silicon substrate and the top oxide layer 7 may hâve been formed by thermal oxidation of the Silicon handle substrate.

[0026] Bonding the heterostructure with the handle substrate 6 is performed in such a way as to achieve an interface bonding energy at the bonding interface of the heterostructure and the handle substrate that is greater than the interface toughness, through the patterned interface 3, between the growth substrate 1 and the continuous épitaxial layer 4. Stated differently, the bonding strength is such compared to the pattemed interface toughness that the later application of dissembling mechanical forces to the first assembly leads to the séparation of the first assembly at the patterned interface rather than at the bonding interface.

[0027] When the growth of the continuous épitaxial layer 4 proceeds in the openings, the resulting interface energy is quite high as it is related to the binding energy between atoms of the 2D material and the overgrown layer whereas when the growth of the continuous épitaxial layer 4 proceeds on the 2D material in between the openings, the resulting interface energy is quite low as no bonds are formed between the 2D material and the overgrown layer, only a weak van der Waals interaction. Therefore, the opening ratio is a trade-off between the required global interface energy to allow the later séparation and the procès s time needed to perform the épitaxial latéral overgrowth of the continuous épitaxial layer (this procès s time being ail the more important as the openings are large as indeed the larger the openings, the thicker the growth is to be performed to reach coalescence).

[0028] In a possible embodiment, bonding the heterostructure with the handle substrate comprises a surface activated bonding SAB or an atomic diffusion bonding ADB. In such manner, a high bonding strength is achieved without the need for a bonding strength reinforcement annealing. This proves advantageous over the regular Smart Cut™ process implemented with trap rich layers for which during a heat treatment (such as the one for strengthening hydrophilic bonding) grains reorganize leading to a localized deformation at the bonding interface, and therefore a localized weak bonding energy. Later, during splitting, the splitting wave will tend to pass through the weak bonded area and no layer transfer occurs around these régions. With the use of a 2D layer, there are no splitting waves. Furthermore, no heat treatments are required for SAB and ADB techniques.

[0029] In another possible embodiment, bonding the heterostructure with the handle substrate comprises a hydrophilic bonding and forming the first assembly further comprises performing a bonding strength reinforcement annealing, for instance between 900°C and 1100°C. A plasma treatment of the yet to-be-bonded surfaces may further be implemented, which allows for an increased bonding strength.

[0030] Once the first assembly is formed by bonding the heterostructure with the handle substrate 6, with reference to [Fig.7], the method of the invention comprises separating the first assembly at the level of the patterned interlayer 3 so as to obtain a second assembly (shown on [Fig.8]) resulting from the transfer of the continuous épitaxial layer 4 from the heterostructure towards the handle substrate 6. This séparation can be a mechanical detachment at the patterned interlayer induced by pulling apart the heterostructure and the handle substrate, for instance using blade insertion at the interface. Advantageously, this séparation can be performed at room température.

[0031] When the heterostructure includes a bilayer, with reference to [Fig.9], the method may further comprises removing the continuous épitaxial layer 4 from the second assembly. This removing may comprise a sélective wet or dry etching of the continuous épitaxial layer 4 in which the additional layer 5 acts as an etch-stop layer.

[0032] Figures 10 and 11 show two possible embodiments of a heterostructure which includes a bilayer 4, 5 in which the additional layer 5 is a strained layer grown by het-eroepitaxy on the continuous épitaxial layer 4. The additional layer may be a strained layer as a resuit of: - The continuous épitaxial layer 4 being a relaxed layer, its thickness being above a critical thickness which is the thickness up to which relaxation does not occur and beyond which relaxation occurs by plastic deformation; - The additional layer 5 being made in a material which has a different lattice parameter than the material of the épitaxial layer and its thickness is below the critical thickness.

[0033] These two embodiments allow for transferring such a strained layer on the handle substrate by detachment at the 2D patterned interface 3. The transferred layer remains strained after its transfer onto the handle substrate.

[0034] As shown on [Fig. 10], the growth substrate 1 may be a Silicon substrate on which is formed a 2D interlayer, for instance made of graphene. The 2D interlayer is patterned and the continuous épitaxial layer 4 is formed on the patterned 2D interlayer 3. The continuous épitaxial layer 4 may be a relaxed layer having a plateau of constant lattice, such as a relaxed SiGe layer with for instance a 20% Ge content. The additional layer 5 may be a strained Silicon layer.

[0035] As shown on [Fig. 11], the growth substrate 1 may be a Silicon substrate on which is formed a graded buffer 8 and a relaxed growth layer 9 on the graded buffer 8. The graded buffer has a lattice parameter graded between a first lattice parameter and a second lattice parameter and the relaxed growth layer has the second lattice parameter. The graded buffer may be a SiGe graded buffer which Ge content increases as the distance from the growth substrate 1 increases, for instance from 0% to 20% Ge content. The relaxed growth layer 9 may be a SiGe layer with a 20% Ge content. A 2D interlayer, for instance made of graphene, is formed on the relaxed growth layer 9. The 2D interlayer is patterned and the continuous épitaxial layer 4 is formed on the patterned 2D interlayer 3. The continuous épitaxial layer 4 may be a relaxed layer having a plateau of constant lattice, such as a relaxed SiGe layer with for instance a 20% Ge content. The additional layer 5 may be a strained Silicon layer..

[0036] After the heterostructure is separated at the 2D patterned interlayer, it may be recycled as follows to be once again used in the method of the invention. First, remaining portions of the patterned interlayer can be removed, for instance by oxygen treatment in the case of graphene. Then, in the case of [Fig. 10], grinding and polishing of the growth substrate can be performed before it can be used in a new cycle starting with the formation of a new 2D interlayer. In the case of [Fig.l 1], polishing of the relaxed growth layer 9 can be performed before a new 2D interlayer is former thereon. In a preferred embodiment, the initial thickness of the relaxed growth layer 9 is of several micrometers thereby allowing performing several recycling loops. Indeed, polishing the relaxed growth layer 9 in a recycling loop may remove a thickness comprises between 3 pm-4pm.Performing several recycling loops may necessitate performing CTE compensation as for instance disclosed in US 2008 / 017952 Al by including a strained transitional layer in the graded buffer. .

[0037] In addition to allowing the transfer of the continuous épitaxial layer onto the handle substrate without the need for a stressor layer, the invention also proves advantageous in that it provides a method for transferring a strained layer onto a handle substrate that overcomes the drawbacks of the prior art solutions.

[0038] Considering the transfer of a strained Silicon layer, a prior art solution which makes use of the Smart Cut™ process to manufacture a strained Silicon on insulator structure is for instance exposed in WO 2007 / 019260 Al. It comprises forming a donor substrate by growing a strained Si layer on a relaxed SiGe layer and forming a cleave plane in the relaxed SiGe layer by implantation of ionic species. The donor substrate is then bonded to a handle substrate before it is separated at the cleave plane, thereby transferring the strained Si layer onto the handle substrate. Afterwards, the transferred strained Si layer is annealed to cure damages induced by the implantation, thereby improving its crystallinity. However, a high number of dislocations is still observed and it gets difficult to reduce the threading dislocation density below 105 / cm2. In addition, many macroscopie defects are présent in the final structure, especially within the thin buried oxide layer.It shall also be noted that this prior art solution hinders the intégration of a trap rich layer in the handle substrate because of the transfer sensitivity to the nanotopology / roughness of the bonded wafers. .

[0039] By contrast to this prior art solution, the présent invention has the following benefits. The number of dislocations in the strained Si film is reduced thanks to performing epitaxy through the patterned interlayer. In addition, because the detachment of the heterostructure at the 2D interlayer layer is completely different from the Smart Cut™ splitting, defectivity in the transferred layer is improved. Another benefit is also the fact that the 2D material covers the entire substrate surface ([Fig.2]) allowing a full wafer layer transfer without non bonded edge crown which also simplifies the recycling process. Another benefit is that it is compatible with the presence of a trap rich layer. And finally, because the invention does not rely of an implantation of ionic species, there is need to for an annealing treatment to recover the implantation damages and the invention can be performed at very low thermal budget.

Claims

Claims

1. A method of manufacturing a stacked structure comprising a layer of semiconductor material adhered to a substrate, comprising: - manufacturing a heterostructure by: • forming an interlayer (2) made of a two-dimensional material on a growth substrate (1); • patterning the interlayer with a plurality of openings to form a pattemed interlayer (3); • growing a semiconductor material on the patterned interlayer (3) by épitaxial latéral overgrowth to form a continuous épitaxial layer (4) on the pattemed interlayer; - forming a first assembly by bonding the heterostructure with a handle substrate (6), the continuous épitaxial layer being located at the bonding interface; - separating the first assembly at the level of the patterned in terlayer (3) so as to obtain a second assembly resulting from the transfer of the continuous épitaxial (4) layer from the heterostructure towards the handle substrate (6);wherein patterning the interlayer (2) is performed so that 1% to 10% of a surface of the growth substrate on which the pattemed interlayer is located is uncovered with the remainder being covered by the two-dimensional material; wherein bonding the heterostructure with the handle substrate comprises one of a surface activated bonding, an atomic diffusion bonding and a hydrophilic bonding accompanied by a bonding strength reinforcement annealing.

2. The method of claim 1, wherein the handle substrate includes a top oxide layer (7) which is located at the bonding interface when forming the first assembly.

3. The method of claim 2, wherein the handle substrate further includes a trap rich layer underneath the top oxide layer.

4. The method of claim 3, further comprising planarizing the top oxide layer (7) before forming the first assembly.

5. The method of one of claims 1 to 4, wherein the continuous épitaxial; layer (4) is a relaxed layer and wherein manufacturing the het-erostructure further comprises the épitaxial déposition of a strained layer (5) on the continuons épitaxial layer (4).

6. The method of claim 5, further comprising removing the continuous épitaxial layer (4) from the second assembly.

7. The method of one of daims 5 and 6, wherein the strained layer is a strained Silicon layer.

8. The method of any one of daims 1 to 7, wherein the growth substrate comprises a graded buffer (8) and a relaxed growth layer (9) on the graded buffer, the graded buffer having a lattice parameter graded between a first lattice parameter and a second lattice parameter and the relaxed growth layer having the second lattice parameter.

9. The method of claim 8, further comprising, after separating the first assembly at the level of the pattemed interlayer (3), recycling the growth substrate, wherein said recycling comprises polishing the relaxed growth layer (9).

10. The method of one of daims 1 to 9, wherein the continuous épitaxial layer (4) is a relaxed layer.

11. The method of one of daims 1 to 10, further comprising planarizing the continuous épitaxial layer (4) before forming the first assembly.

12. The method of one of daims 1 to 11, wherein patteming the interlayer (2) leaves a peripheral ring of the two-dimensional material on the growth substrate.

13. The method of one of daims 1 to 12, wherein two neighbouring openings of the patterned interlayer are separated by a distance which is less than 40 micrometers, preferably less than 20 micrometers.

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