Method of manufacturing a vertical gallium nitride structure and a device based thereon

Abstract

Method for manufacturing a structure (Stck3) comprising a plurality of GaN layers (GaN(n+)_1, Gan(p-), GaN(n-)_DL, GaN(n+)_2)) and intended to form a vertical GaN device, comprising the steps of: providing (110) a first substrate (Sub1); forming (130) a nucleation GaN layer (Nuc) on the first substrate (Sub1); forming (150) by epitaxy a stack (Stck1) comprising a plurality of GaN layers on the nucleation layer; on the stack (Stck1), forming (170) a first metal layer (M1); providing (120) a second substrate (Sub2) on which a second metal layer (M2) is formed (140); assembling (200) the stack (Stck1) to the second substrate (Sub2) by direct contact and bonding of the two metal layers (M1, M2); detaching (210) the first substrate (Sub1) from the stack (Stck1) at the nucleation layer (Nuc) by light irradiation through the first substrate (Sub1). Figure 1

Description

Title of the invention: Method for manufacturing a vertical gallium nitride structure and a device based on this structure TECHNICAL FIELD OF THE INVENTION

[0001] The invention relates to a method for manufacturing a vertical gallium nitride structure including a step of transferring layers onto a substrate. This vertical gallium nitride structure is also used to form a semiconductor device of which an active component is made up of the gallium nitride layer. TECHNOLOGICAL BACKGROUND

[0002] Among semiconductor materials, gallium nitride GaN is considered as an alternative to silicon Si for many applications. The very high breakdown voltages, high electron mobility and saturation speed of GaN make it an ideal candidate for high frequency, high power applications with high switching speed.

[0003] The wide band gap of GaN also means that the performance of GaN transistors is maintained at higher temperatures than that of silicon transistors, because it mitigates the effects of thermal generation of charge carriers inherent in any semiconductor. Thus, GaN-based semiconductor devices exhibit relative temperature immunity compared to silicon.

[0004] GaN-based semiconductor devices can have a wide variety of structures. Among these structures, we speak of a horizontal GaN device when the current flowing through the device follows a path located substantially in the extension plane of the superimposed layers forming the device. Conversely, we speak of a vertical GaN device when the current flowing through the device follows a path substantially perpendicular to the extension plane of the superimposed layers forming the device, as illustrated by the current Ipath in [Fig. 2]. For example, we can refer to the article by Langpoklakpam et al., “Vertical GaN MOSFET Power Devices”, Micromachines 2023, 14, 1937.

[0005] Two approaches are used to make vertical GaN devices, applied for example to field effect transistors, pn junction diodes or Shottky diodes. Both approaches result in devices formed from a stack of GaN semiconductor layers and metallic electrical contact points distributed on both sides of the device. The contact points may for example consist of a pair of anode and cathode on two opposite sides of a voltage rectifier device, or of a gate electrode and one or more source electrodes on a first face of a field effect transistor and a drain electrode on the opposite face of the transistor.

[0006] A first approach for obtaining such structures comprises epitaxial deposition of GaN semiconductor layers on a substrate formed from a silicon wafer or a composite structure comprising an upper layer formed from silicon. In a second approach, a bulk GaN substrate can be used.

[0007] The first approach results in layers with high Threading Dislocation Density (TDD) and thermal and electrical conductivity issues. The second approach requires very expensive GaN wafers that are not available in large diameters, and thermal management is still an issue. Statement of the invention

[0008] An object of the invention is to provide a method of manufacturing a vertical GaN device solving the problems mentioned above.

[0009] In order to achieve these objects, one aspect of the invention is a method of manufacturing a structure comprising a plurality of GaN layers, this structure being intended to form a vertical GaN device, the method comprising the steps of providing a first substrate; forming a nucleation GaN layer on one face of the first substrate; on the nucleation GaN layer, epitaxially forming a stack comprising a plurality of GaN layers; on the stack, forming a first metal bonding layer; providing a second substrate; on the second substrate, forming a second metal bonding layer; assembling the stack to the second substrate by direct contact and metal bonding of the two metal bonding layers; detaching the first substrate from the stack at the nucleation layer by light irradiation through the first substrate and absorption of this irradiation by the nucleation layer;and eliminate the nucleation layer. ;

[0010] The method according to the invention makes it possible to produce a semiconductor structure formed from high-quality crystalline gallium nitride GaN without using a bulk gallium nitride substrate. An immediate advantage of this method is therefore better integration, possibly on large-sized substrates not limited by those of a GaN wafer, of a vertical GaN device of excellent quality, and this at a controlled cost.

[0011] Furthermore, this method is simple to implement, all of the layers forming the stack of GaN layers being formed successively on the side of the crystallographic designation faces (0001) of the GaN layers. The entire method requires only a single layer transfer - bonding of the stack onto a second substrate followed by the detachment of the first substrate on which the stack was initially formed, without requiring a mechanochemical polishing treatment to remove the first substrate. Thus, with a single layer transfer, this process makes it possible to obtain a structure with surfaces of the GaN layers oriented opposite the second substrate.

[0012] According to additional non-limiting characteristics of the invention, considered individually or in any technically feasible combination:

[0013] - the second substrate may be formed from polycrystalline silicon carbide;

[0014] - the step of removing the nucleation layer may also include removing mination of a portion of that of the GaN layers which was formed in direct contact with the nucleation layer;

[0015] - the step of removing the nucleation layer can be implemented by polishing mechanical-chemical;

[0016] - the nucleation GaN layer may have a free face of crystallographic designation graph (0001);

[0017] - the nucleation layer can be formed by ALD - Atomic Layer Deposition in English terminology;

[0018] - each of the GaN layers of the stack can be formed on and in contact direct with a crystallographic designation face (0001) of a previously deposited GaN layer;

[0019] - each of the GaN layers of the stack and the nucleation GaN layer can be formed so as to present, immediately after its formation, a free face of crystallographic designation (0001);

[0020] - the first substrate may be a sapphire wafer;

[0021] - the formation of the stack may comprise, in this order, the formation by epitaxy of a first layer of n+ type GaN, a layer of p- type GaN, a layer of n- type GaN, and a second layer of n+ type GaN;

[0022] - the second substrate may be a silicon carbide wafer, preferably a wafer of n+ type polycrystalline silicon carbide which may have an electrical resistivity of less than 10 mOhm.cm;

[0023] - the method may further comprise the step of forming: - a drain electrode on a free face of the second substrate; a source electrode on a free face of the first n+ type GaN layer; and a gate structure passing through the first n+ type GaN layer, the p- type GaN layer, and in contact with the n- type GaN layer.

[0024] A first additional advantage of the method according to the invention is the possibility of better thermal management of the device when the latter is integrated on a substrate of high thermal conductivity such as a silicon carbide SiC substrate.

[0025] A second additional advantage of the process is that after metal-to-metal bonding, it does not require high-temperature heat treatment, thus limiting the thermal budget of a device being manufactured and increasing its compatibility with integration processes.

[0026] A third additional advantage of the method is that the stack comprising the gallium nitride layers can be easily detached from its substrate by light irradiation while limiting the uncontrolled effects on the structure during the light irradiation, thanks to the proximity between the layer absorbing this radiation and the substrate. BRIEF DESCRIPTION OF THE FIGURES

[0027] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which:

[0028] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which:

[0029] [Fig.l] [Fig.l] illustrates a method of manufacturing a structure comprising a plurality of GaN layers;

[0030] [Fig.2] [Fig.2] illustrates a structure obtained according to the method illustrated by [Fig.l] and a device obtained from this structure; and

[0031] [Fig.3] [Fig.3] illustrates the manufacturing processes of the structure and device illustrated by [Fig.2]. DETAILED DESCRIPTION OF THE INVENTION Method of carrying out the invention

[0032] An embodiment of the invention is described with the aid of Figures 1 to 3.

[0033] [Fig.2] illustrates in (A) a Struct structure comprising a plurality of gallium nitride GaN layers and which is intended to be used to subsequently form a vertical GaN device. Each gallium nitride GaN layer has a hexagonal lattice crystallographic structure, in particular a “wurtzite” type crystallographic structure, having a “c” axis (the “c” axis being the direction perpendicular to the plane in which the structure has hexagonal symmetry). The “N-Dir” arrow indicates the direction of orientation of the nitrogen-gallium bonds oriented along the “c” axis of the gallium nitride layers. As indicated in the figure, the gallium nitride layers have their crystallographic designation faces (000-1) upwards, sometimes called “nitrogen faces”.

[0034] [Fig.2] illustrates in (B) an example of a vertical GaN device V.Dev, here a field effect transistor, which can be easily obtained from the structure illustrated in (A). As indicated in the figure, the gallium nitride layers have their crystallographic designation faces (000-1) upwards.

[0035] [Fig.l] and [Fig.3] illustrate a method 100 for manufacturing the structure Struct according to the invention.

[0036] In a step 110, a first substrate Subi is provided. It may be a sapphire substrate, such as a wafer, preferably having a C orientation and polished on both sides.

[0037] In a step 130, a nucleation GaN layer is formed on one face of the first substrate Subi. This layer can be formed by ALD (Atomic Layer Deposition in English terminology, which can be translated as atomic layer deposition in French) and more specifically by Remote Plasma Atomic Layer Deposition in English terminology (atomic layer deposition by remote plasma). It is thus possible to form a nucleation GaN layer 10 to 40 nm thick, the free face of this layer being a face of crystallographic designation (0001) sometimes called the “gallium face” of the GaN layer.

[0038] The purpose of this nucleation layer is to promote a good quality crystalline structure during the following stages of formation of GaN layers by epitaxy.

[0039] Step 130 may also comprise a heat treatment by heating the nucleation layer to 1130°C for two hours, for example in an atmosphere comprising one or a plurality of H2, NH3, N2, such as for example an NH3 / N2 gas at 80% NH3.

[0040] In a step 150, a Stckl stack composed of a plurality of GaN layers is successively formed by epitaxy, the first of which is formed in direct contact with the bare nucleation layer. The layers are formed in such a way that each of the gallium layers of the Stckl stack is formed on and in direct contact with a crystallographic designation face (0001) of a previously deposited GaN layer. Thus, each of the GaN layers of the Stckl stack and of the bare nucleation GaN layer naturally has, just after its formation, a free crystallographic designation face (0001).

[0041] The formation of the Stckl stack comprises, in this order, the epitaxial formation of a first GaN(n+)_l layer of n+ type GaN (thickness between 0.2 and 2 micrometers), a GaN(p-) layer of p- type GaN (thickness between 0.1 and 1 micrometers), a GaN(n-)_DL layer of n- type GaN (thickness between 1 and 30 micrometers), and a second GaN(n+)_2 layer of n+ type GaN (thickness between 0.2 and 2 micrometers). The indications "p" and "n" indicate a doping type, p-type or n-type, of the GaN. The indications "+" and "-" indicate relative concentrations of doping elements. Thus, a layer with an n+ designation contains a greater concentration of n-type dopant than a layer with an n- designation, and a layer with a p+ designation contains a greater concentration of p-type dopant than a layer with an in p- dication. It is difficult to define ranges of values ​​for these concentrations, these depending on the intended applications. However, we can give an example of n-type GaN doped with Si, for which values ​​of the doping concentrations (i) "n+", and (ii) "n-" can correspond respectively to concentrations (i) greater than 2.1018 at / cm3, and (ii) ranging from 1.1015 to 1.1017 at / cm3. Similarly, we can give an example of p-type GaN doped with Mg, for which values ​​of the doping concentrations (i) "p+", and (ii) "p-" can correspond respectively to concentrations (i) greater than 3.1019 at / cm3, and (ii) ranging from 1.1017 to 1.1018 at / cm3.

[0042] It is important to note that the first GaN(n+)_l layer formed on the Bare nucleation layer must have a thickness greater than that which it will have to have in the completed Struct structure. Indeed, during a subsequent step, a part of this layer will be eliminated in order to obtain a satisfactory surface state and a good crystalline state of the remaining part. Its thickness after its formation must therefore represent the sum of its desired thickness in the Struct structure and the thickness Thck which it is planned to eliminate (during step 230 detailed below).

[0043] In a step 170, a first metallic bonding layer M1 is formed on the stack Stck1, preferably so as to form an ohmic contact with the last GaN(n+)_2 layer forming the stack. It may be a Ti / Al bilayer, the titanium being in contact with the GaN(n+)_2 layer. This first metallic layer may be formed for example by PVD (Physical Vapor Deposition in English terminology) or by sputtering, or any other deposition method known to those skilled in the art.

[0044] In parallel with steps 110 to 170, a second substrate Sub2 is provided in a step 120. This second substrate may be a wafer of silicon carbide SiC, preferably a wafer of polycrystalline silicon carbide pSiC of type n+. For example, it is possible to use nitrogen-doped polycrystalline silicon carbide, having an electrical resistivity of less than 10 mOhm.cm, preferably less than 5 mOhm.cm, more preferably less than 2 mOhm.cm. A substrate of this type, with high thermal conductivity, allows better thermal management of a semiconductor device formed from the structure Struct: it promotes the evacuation of the heat produced by the device in operation.Furthermore, compared to silicon, it has a low difference in coefficient of thermal expansion with GaN and high electrical conductivity, making it very advantageous for high power applications that require high current, high temperatures and high thermal conductivity. Alternatively, other types of substrates, such as those commonly used in the semiconductor industry could be used, the invention not being limited to SiC.

[0045] In a step 130, a second metal bonding layer M2 is formed on the second substrate Sub2, similarly to the Ml layer formed on the Stckl stack.

[0046] In a step 200, the first stack Stckl is assembled to the second substrate Sub2 by direct contact and metallic, or metal-metal, bonding of the two metallic bonding layers M1 and M2. A second stack Stck2 is thus obtained, comprising the two substrates Subi and Sub2 as well as all of the layers formed on these substrates and included between them.

[0047] The principle of the assembly is to put the two metal layers in intimate contact and to heat the assembly thus formed to a temperature, for example, for a bonding between two layers M1, M2 in aluminum, between 500 and 600°C, for example 500°C, for a duration of between 1h and 4h, in an inert or reducing atmosphere. The bonding is thus definitive.

[0048] It should be noted that the temperature and duration of the assembly annealing may vary depending on the nature of the metal(s) considered; for example, in the case of copper-copper bonding, annealing between 300 and 400°C for 1 to 4 hours will typically be chosen.

[0049] In a step 210, the first substrate Subi is detached from the stack Stckl at the level of the Bare nucleation layer by light irradiation through the first substrate Subi and absorption of this irradiation by the Bare nucleation layer. The absorption of energy by the Bare layer degrades it and induces detachment. The light irradiation can be carried out by laser irradiation, using a wavelength at which the first substrate Subi is substantially transparent and the nucleation layer is substantially absorbent. For example, a KrF laser with a wavelength of 248 nm and pulse widths of 40 ns can be used. This can be a procedure called LLO, Laser Lift Off in English terminology. The light irradiation is also absorbed over a thickness of a few tens of nanometers by the GaN layer GaN(n+)_l.

[0050] During step 210 of detachment of the first substrate, the bare nucleation layer has been damaged by light irradiation. The remains of this nucleation layer must be removed.

[0051] The portion of the first GaN(n+)_l layer in contact with the nucleation layer has also been damaged during the step of detaching from the first substrate. Furthermore, independently of the detachment step, the portion of the first GaN(n+)_l layer closest to the bare nucleation layer is often of lower crystalline quality than the portion of the first GaN(n+)_l layer furthest from the bare nucleation layer. In order to keep only a portion of the first GaN(n+)_l layer of high crystalline quality, it is necessary to eliminate a certain thickness of this layer.

[0052] In a step 230, the bare nucleation layer and a portion of the first GaN(n+)_l layer are removed, possibly by plasma etching or by a polishing operation such as a CMP operation, Chemical Mechanical Polishing in English terminology: the CMP operation is applied (i) to the entire thickness of the bare nucleation layer, or what remains of it after the detachment step 210, and (ii) to a certain thickness Thck of the first GaN(n+)_l layer, approximately 50 nm for example. Following step 230, a stack Stck3 is obtained, extending from the second substrate Sub2 to the first thinned GaN(n+)_l layer, as illustrated in (A) of [Fig.2].

[0053] At this step, the Stck3 stack can in principle serve as a basis for manufacturing various vertical GaN devices. A step 250 of manufacturing such a device can lead to a vertical GaN device V.Dev such as the field effect transistor illustrated in (B) of [Fig.2].

[0054] Step 250 may comprise the steps (i) of forming a drain electrode D on a free face of the second substrate Sub2, (ii) of forming a source electrode S on a free face of the first n+ type GaN layer (GaN(n+)_l), and (iii) of forming a gate structure passing through the first GaN(n+)_l layer, the GaN(p-) layer, and in contact with the GaN(n-)_DL layer. The GaN(n-)_DL layer then has the function of a drift layer. The gate structure comprises a gate electrode G electrically insulated from the GaN(n+)_l, GaN(p-) and GaN(n-)_DL layers by a gate dielectric layer GI.

[0055] In this document, the figures are not necessarily to scale. Some features and components may be shown exaggerated relative to other components or in a somewhat schematic form, and some details of conventional elements may not be shown in the interest of clarity and conciseness.

[0056] Of course, the invention is not limited to the embodiments described and variant embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

Claims

1. Method for manufacturing a structure (Stck3) comprising a plurality of GaN layers (GaN(n+)_l, Gan(p-), GaN(n-)_DL, GaN(n+)_2)), this structure being intended to form a vertical GaN device, comprising the steps of: - providing (110) a first substrate (Subi); - forming (130) a nucleation GaN layer (Bare) on one face of the first substrate (Subi); - on the nucleation GaN layer (Bare), forming (150) by epitaxy a stack (Stckl) comprising a plurality of GaN layers; - on the stack (Stckl), forming (170) a first metal bonding layer (Ml); - providing (120) a second substrate (Sub2); - on the second substrate (Sub2), forming (140) a second metal bonding layer (M2); - assembling (200) the stack (Stckl) to the second substrate (Sub2) by direct contact and metallic bonding of the two metallic bonding layers (Ml, M2);- detaching (210) the first substrate (Subi) from the stack (Stckl) at the level of the nucleation layer (Bare) by light irradiation through the first substrate (Subi) and absorption of this irradiation by the nucleation layer (Bare); and - eliminating (230) the nucleation layer (Bare).;

2. The manufacturing method according to claim 1, wherein the second substrate is formed of polycrystalline silicon carbide.

3. The manufacturing method according to claim 1 or 2, wherein the step of removing (230) the nucleation layer (Bare) also comprises removing a portion of that (GaN(n+)_l) of the GaN layers which has been formed in direct contact with the nucleation layer (Bare).

4. The method of any one of claims 1 to 3, wherein the step of removing (230) the nucleation layer is carried out by chemical mechanical polishing.

5. The method according to any one of claims 1 to 4, wherein the nucleation GaN layer (Bare) has a free face of crystallographic designation (0001).

6. The method according to any one of claims 1 to 5, in which, the nucleation layer is formed by ALD - Atomic Layer Deposition in English terminology.

7. The method according to any one of claims 1 to 6, wherein each of the GaN layers ((GaN(n+)_l, Gan(p-), GaN(n-)_DL, GaN(n+)_2))) of the stack (Stckl) is formed on and in direct contact with a crystallographic designation face (0001) of a previously deposited GaN layer (Bare, GaN(n+)_l, Gan(p-), GaN(n-)_DL).

8. The method according to any one of claims 1 to 7, wherein each of the GaN layers ((GaN(n+)_l, Gan(p-), GaN(n-)_DL, GaN(n+)_2))) of the stack (Stckl) and of the nucleation GaN layer (Nue) is formed so as to have, just after its formation, a free face (T.Surf) of crystallographic designation (0001).

9. The method of any one of claims 1 to 8, wherein the first substrate (Subi) is a sapphire wafer.

10. The method according to any one of claims 1 to 9, wherein the formation (150) of the stack (Stckl) comprises, in this order, the epitaxial formation of a first n+ type GaN layer (GaN(n+)_l), a p- type GaN layer (GaN(p-)), an n- type GaN layer (GaN(n-)_DL), and a second n+ type GaN layer (GaN(n+)_2).

11. The method according to any one of claims 1 to 10, wherein the second substrate (Sub2) is a silicon carbide wafer, preferably an n+ type polycrystalline silicon carbide wafer having an electrical resistivity of less than 10 mOhm.cm.

12. A method of forming a transistor comprising the method according to any one of claims 10 to 11, and further comprising the step (250) of forming: - a drain electrode (D) on a free face of the second substrate; - a source electrode (S) on a free face of the first n+ type GaN layer (GaN(n+)_l); and - a gate structure passing through the first n+ type GaN layer (GaN(n+)_l), the p- type GaN layer (GaN(p-)), and in contact with the n- type GaN layer (GaN(n-)_DL).

Images