Avionics computer including a communications gateway.
The avionics computer employs a communication gateway with PCIe and Ethernet interfaces and FIFO queues to adapt data transmission speeds, addressing the challenge of integrating PCIe and Ethernet protocols in aircraft networks and ensuring efficient data transfer.
Patent Information
- Application Number
- FR2024002553
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-03-14
- Publication Date
- 2025-09-19
AI Technical Summary
Existing avionics computers face challenges in efficiently transmitting data between PCIe and Ethernet communication protocols while adhering to deterministic switched Ethernet standards, particularly in aircraft networks.
An avionics computer with a first communication gateway that includes a PCIe interface connected to a processor and an Ethernet interface connected to a switch, utilizing FIFO queues and timing clock signals to adapt data transmission speeds and ensure compliance with Ethernet communication protocols.
Facilitates seamless data communication between PCIe and Ethernet protocols, ensuring efficient data transfer and compliance with ARINC 664 part 7 standards, protecting the processor from high-frequency data transmission.
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
Title of the invention: Avionics computer including a communications gateway.
[0001] The invention relates to the field of avionics computers communicating with each other via an Ethernet-type communication network. Many modern aircraft use avionics computers communicating via an Ethernet-type communication network, in particular using a deterministic switched Ethernet-type communication protocol compliant with the ARINC 664 part 7 standard. An avionics computer then comprises at least one Ethernet-type communication port. In particular, an avionics computer may furthermore integrate a switch provided to allow data frame communications between the avionics computer and other avionics computers of the aircraft via such an onboard communication network of the aircraft implementing an Ethernet-type communication protocol. Such an avionics computer is for example disclosed by the document FR3103340.In one embodiment, the avionics computer comprises a processor connected to a PCI Express type bus, also called PCIe. When the switch is installed on an electronic card separate from an electronic card on which the processor is installed, it is envisaged to use communication between these two electronic cards by means of the PCIe type bus. There is then a need to transmit data from the PCIe type bus to the switch and vice versa, while respecting constraints relating to the Ethernet communication protocol, the communication protocol on the PCIe type bus as well as the data processing capabilities received by the processor. Statement of the invention
[0002] The present invention aims in particular to provide a solution to this problem. It relates to an avionics computer intended to be installed on board an aircraft, such as:
[0003] - the avionics computer integrates a switch designed to allow commu communications of data frames between the avionics computer and other avionics computers of the aircraft via an on-board communication network of the aircraft implementing an Ethernet type communication protocol; and
[0004] - the avionics computer comprises a processor connected to a communication bus PCIe type.
[0005] The avionics computer is remarkable in that it comprises a first communication gateway comprising a first PCIe type interface connected to the processor by means of a PCIe type communication bus and a second interface, of the Ethernet type, connected to the switch, the first communication gateway being such that:
[0006] - the first interface comprises a reception channel and a transmission channel of data ;
[0007] - the second interface comprises a reception channel and a transmission channel of data;
[0008] - the first communication gateway comprises a first queue of FIFO type sized to store a data frame and intended to receive data from the receive channel of the first interface and to output data to the transmit channel of the second interface; and
[0009] - the first communication gateway is configured such that a record Registration of a complete data frame in the first FIFO queue triggers the sending of said data frame on the data transmission channel of the second interface.
[0010] Thus, the first communication gateway allows the communication of data frames between the processor and the switch, and vice versa, using the PCIe type bus. The use of the first FIFO type queue makes it possible to achieve an adaptation between a first data transmission speed on the PCIe type bus and a second data transmission speed to the switch.
[0011] In one embodiment:
[0012] - the first FIFO type queue comprises a first memory area and a second memory area, each sized to store one data frame;
[0013] - a recording of a complete data frame in the first queue FIFO type corresponds to a recording of the complete data frame in one of the first memory area and the second memory area;
[0014] - the first communication gateway is configured in such a way that following a recording a complete data frame in the first FIFO type queue, the first communication gateway checks whether a reading of the other of the first memory zone and the second memory zone is in progress, waits if a reading is in progress for this reading to be completed, then orders an exchange of the first memory zone and the second memory zone; and
[0015] - the first communication gateway is configured such that when a data frame is recorded in the other of the first memory area and the second memory area, the first communication gateway controls the sending of said data frame on the data transmission channel of the second interface.
[0016] In one embodiment:
[0017] - the first communication gateway comprises a second queue of FIFO type sized to store a data frame and intended to receive data from the receive channel of the second interface and to output data to the transmit channel of the first interface;
[0018] - the first communication gateway is configured to produce a signal timing clock having a so-called timing frequency based on a clock of the PCIe type communication bus to which the first PCIe type interface of the first gateway is connected, the timing clock signal having timing edges at said timing frequency; and
[0019] - the first communication gateway is configured in such a way that following a recording a complete data frame in the second FIFO type queue, the first communication gateway commands the sending of said data frame on the data transmission channel of the first interface after a timing edge of the timing clock signal subsequent to the recording of the complete data frame.
[0020] Advantageously, in this embodiment:
[0021] - the second FIFO type queue comprises a first memory area and a second memory area, each sized to store one data frame;
[0022] - a recording of a complete data frame in the second queue FIFO type corresponds to a recording of the complete data frame in one of the first memory area and the second memory area;
[0023] - the first communication gateway is configured in such a way that following a recording a complete data frame in the second FIFO type queue, the first communication gateway waits for a timing edge of the timing clock signal, then checks whether a reading of the other of the first memory area and the second memory area is in progress or whether a new writing of said one of the first memory area and the second memory area is in progress, waits if a reading or a writing is in progress for this reading or this writing to be completed, then commands an exchange of the first memory area and the second memory area; and
[0024] - the first communication gateway is configured such that when a data frame is recorded in the other of the first memory area and the second memory area, the first communication gateway controls the sending of said data frame on the data transmission channel of the first interface.
[0025] In one embodiment, the first communication gateway is implemented in an FPGA type logic circuit comprising an AXI type data parallelization stage linked to the PCIe type communication bus to which the first PCIe type interface of the first gateway is connected. In particular, the switch is also implemented in said FPGA type logic circuit.
[0026] In one embodiment, the first PCIe type interface of the first gateway and the processor are directly connected to the same PCIe type communication bus.
[0027] In one embodiment, the avionics computer further comprises a second communication gateway comprising a first PCIe type interface connected to the processor by means of a first PCIe type communication bus and a second PCIe type interface connected to the first gateway by means of a second PCIe type communication bus.
[0028] In particular, in this embodiment:
[0029] - the avionics computer comprises two electronic boxes of architectures si military, each electronic box comprising at least a first electronic card comprising on the one hand a PCIe type interface connected to an inter-electronic box PCIe type bus and another PCIe type interface, and on the other hand a second electronic card comprising a PCIe type interface connected to the inter-electronic box PCIe type bus and another PCIe type interface connected to the other PCIe type interface of the first electronic card; and
[0030] - the processor is hosted on the first electronic card of one of the two electronic boxes, the first communication gateway is hosted on the first electronic card of the other of the two electronic boxes and the second communication gateway is hosted on the second electronic card of the other of the two electronic boxes.
[0031] The invention also relates to an aircraft comprising such an avionics computer. Description of the embodiments
[0032] The invention will be better understood by reading the following description and examining the attached figures.
[0033] [Fig.l] illustrates an aircraft equipped with an avionics computer according to an embodiment of the invention.
[0034] [Fig.2] schematically illustrates an avionics computer according to an embodiment of the invention.
[0035] [Fig.3] schematically illustrates an embodiment of a first communication gateway of the avionics computer shown in [Fig.2].
[0036] [Fig.4a] schematically illustrates an embodiment of a first row waiting for the first communication gateway shown in [Fig.3].
[0037] [Fig.4b] schematically illustrates an embodiment of a second row waiting for the first communication gateway shown in [Fig.3].
[0038] [Fig.5] schematically illustrates a particular embodiment of the first communication gateway illustrated in [Fig.3].
[0039] [Fig.6] schematically illustrates an avionics computer according to a particular embodiment of the invention.
[0040] The aircraft 1 shown in [Fig. 1] comprises an avionics computer such as the avionics computer 10 shown in [Fig. 2]. The avionics computer 10 comprises a processor 14, labeled “Proc” in the figure, connected to a communication bus 18 of the PCIe type by a bidirectional link 16. The avionics computer 10 integrates a switch 28, labeled “SW” in the figure, provided to allow data frame communications between the avionics computer and other avionics computers of the aircraft via an onboard communication network of the aircraft implementing an Ethernet type communication protocol. In particular, this communication protocol is of the deterministic switched Ethernet type, compliant with the ARINC 664 part 7 standard. The switch 28 comprises a set of communication ports provided to be connected to these other avionics computers of the aircraft.These communication ports are connected to a set of Ethernet-type Eth connectors of the avionics computer by a set of links 29. The avionics computer 10 further comprises a first communication gateway 24 comprising a first PCIe-type interface 23 connected to the processor 14 by means of a PCIe-type communication bus via a link 22. The communication gateway 24 also comprises a second Ethernet-type interface 25 connected to the switch 28. More particularly, this second Ethernet-type interface 25 is connected to a communication port 21 of the switch 28, internal to the avionics computer 10, by means of a link 26 provided to allow the exchange of signals conforming to an Ethernet-type communication protocol.
[0041] More particularly, as shown in [Fig. 3], the first communication gateway 24 comprises a first queue 30 of the FIFO type sized to record a data frame and designed to receive data from a reception channel 23a of the first interface 23 and to provide output data to a transmission channel 25a of the second interface 25. The reception channel 23a is connected to the processor 14 by means of the communication bus 18 of the PCIe type, via a link 22a. The transmission channel 25a is connected to the communication port 21 of the switch 28 by a link 26a. The first communication gateway 24 is configured such that a recording of a complete data frame in the first FIFO type queue 30 triggers the sending of said data frame on the data transmission channel 25a of the second interface 25.
[0042] In the embodiment illustrated in [Fig. 4a], the first FIFO queue 30 comprises a first memory area 34a and a second memory area 34b, each sized to record a data frame. The first queue 30 further comprises a controller 37. A recording of a complete data frame in the first FIFO queue 30 corresponds to a recording of the complete data frame in one of the first memory area 34a and the second memory area 34b. The controller 37 is configured such that following a recording of a complete data frame in the first FIFO queue 30, the controller 37 checks whether a reading of the other of the first memory area and the second memory area is in progress, waits if a reading is in progress until this reading is completed, then commands an exchange of the first memory area 34a and the second memory area 34b.The controller 37 is further configured such that when a data frame is recorded in the other of the first memory area 34a and the second memory area 34b, the controller 37 controls the sending of said data frame on the data transmission channel 25a of the second interface 25.
[0043] Advantageously, as shown in [Fig. 3], the first communication gateway 24 further comprises a second queue 32 of the FIFO type sized to record a data frame and designed to receive data from a reception channel 25b of the second interface 25 and to provide data as output to a transmission channel 23b of the first interface 23. The reception channel 25b is connected to the communication port 21 of the switch 28 by a link 26b. The transmission channel 23b is connected to the processor 14 by means of the communication bus 18 of the PCIe type, via a link 22b. The first communication gateway 24 comprises a clock divider 31, labeled “Clk” in [Fig.3], configured to produce a timing clock signal having a so-called timing frequency based on a clock of the communication bus 18 of the PCIe type to which the first PCIe type interface 23 of the first gateway 24 is connected. The timing clock signal has timing edges at said timing frequency. According to a first alternative, the timing edges correspond to rising edges of the timing clock signal. According to a second alternative, the timing edges correspond to falling edges of the timing clock signal. According to a third alternative, the timing edges correspond to both rising edges and edges. descendants of the timing clock signal. The first communication gateway 24 is configured such that following a recording of a complete data frame in the second FIFO type queue 32, the first communication gateway commands the sending of said data frame on the data transmission channel 23b of the first interface 23 after a timing edge of the timing clock signal subsequent to the recording of the complete data frame. Waiting for this timing edge to send the data frame to the processor 14 makes it possible to protect the processor 14 in the event of transmission of data frames at a high frequency by the switch 28. Indeed, in such a case, the frequency of reception of the data frames by the processor 14 is limited to the reception of a data frame at each timing edge of the timing clock signal.
[0044] In the embodiment illustrated in [Fig.4b], the second FIFO queue 32 comprises a first memory area 36a and a second memory area 36b, each sized to record a data frame. The second queue 32 further comprises a controller 39. The controller 39 is connected as an input to an output of the clock divider 31. Recording a complete data frame in the second FIFO queue 32 corresponds to recording the complete data frame in one of the first memory area 36a and the second memory area 36b.
[0045] The controller 39 is configured such that following a recording of a complete data frame in the second FIFO type queue 32, the controller 39 waits for a timing edge of the timing clock signal, then checks whether a reading of the other of the first memory area 36a and the second memory area 36b is in progress or whether a new writing of said one of the first memory area and the second memory area is in progress. It waits if a reading or a writing is in progress until this reading or this writing is finished, then it commands an exchange of the first memory area 36a and the second memory area 36b. The controller 39 is further configured such that when a data frame is recorded in the other of the first memory area 36a and the second memory area 36b, the controller 39 controls the sending of said data frame on the data transmission channel 23b of the first interface 23.
[0046] In operation, when the processor 14 sends data on the PCIe type communication bus 18 for transmission on the Ethernet type communication network, this data is received, via the link 22a, on the reception channel 23a of the first interface 23 of the communication gateway 24. As it is received, this data is recorded in the first FIFO type queue 30. More particularly, this data is recorded in one of the first memory area 34a and the second memory area 34b. When the controller 37 determines that the data corresponding to a complete data frame has been recorded in said memory area, it checks whether a reading of the other of the first memory area and the second memory area is in progress. If a reading is in progress, the controller 37 waits for this reading to be completed, then it commands an exchange of the first memory area 34a and the second memory area 34b. Without departing from the scope of the invention, the exchange of the two memory areas 34a and 34b can be carried out both by an exchange of pointers pointing to these two memory areas, and by an exchange of the contents of the two memory areas.After the exchange of the two memory areas, it is considered that the received data corresponding to said data frame are thus recorded in the other of the first memory area 34a and the second memory area 34b, regardless of the mode of carrying out the exchange of the memory areas. When a data frame is recorded in the other of the first memory area 34a and the second memory area 34b, the controller 37 commands the sending of said data frame on the data transmission channel 25a of the second interface 25. This has the effect of extracting this data from said other memory area and consequently of emptying this other memory area according to a usual principle of reading a FIFO type queue. When sending the data on the data transmission channel 25a, the controller 37 encapsulates this data in accordance with the Ethernet type communication protocol used by the switch 28 and by the Ethernet type communication network.This data is then transmitted to the switch 28 via the link 26a.
[0047] When the switch 28 sends data to the processor 14, this data is received, via the link 26b, on the reception channel 25b of the second interface 25 of the communication gateway 24. This data is transmitted by the switch 28, in accordance with the Ethernet type communication protocol used by the switch 28 and by the Ethernet type communication network. The controller 39 deencapsulates the useful data received in a data frame. As it is received, this data is recorded in the second FIFO type queue 32. More particularly, this data is recorded in one of the first memory area 36a and the second memory area 36b.When the controller 39 determines that the data corresponding to a complete data frame has been recorded in said memory area, it waits for a timing edge of the timing clock signal, then it checks whether a read of the other of the first memory area 36a and the second memory area 36b is in progress or whether a new write of said one of the first memory area and the second memory area is in progress. If a read or a write is in progress, the controller waits until this read or this write is completed, then it commands an exchange of . the first memory area 36a and the second memory area 36b. Without departing from the scope of the invention, the exchange of the two memory areas 36a and 36b can be carried out both by an exchange of pointers pointing to these two memory areas, and by an exchange of the contents of the two memory areas. After the exchange of the two memory areas, it is considered that the received data corresponding to said data frame are thus recorded in the other of the first memory area 36a and the second memory area 36b, regardless of the mode of carrying out the exchange of the memory areas. When a data frame is recorded in the other of the first memory area 36a and the second memory area 36b, the controller 39 controls the sending of said data frame on the data transmission channel 23b of the first interface 23.This has the effect of extracting this data from said other memory area and consequently of emptying this other memory area according to a usual principle of reading a FIFO type queue. The data sent on the data transmission channel 23b are transmitted, via the link 22b, to the PCIe type communication bus 18 and thus to the processor 14.
[0048] In a particular embodiment, as illustrated in [Fig. 5], the first communication gateway 24 is implemented in a logic circuit of the FPGA type comprising a stage 33 for parallelizing data of the AXI type (acronym for “Advanced extensible Interface” in English) in connection with the communication bus 18 of the PCIe type to which the first interface 23 of the PCIe type of the first communication gateway 24 is connected. This thus allows on the one hand serial type data exchanges between the stage 33 and the communication bus 18 of the PCIe type and on the other hand parallel type data exchanges between the stage 33 and the queues 30 and 32.
[0049] Advantageously, the first communication gateway 24 and the switch 28 are implemented in the same logic circuit 27 of FPGA type.
[0050] In a first embodiment, the first PCIe type interface 23 of the first gateway 24 and the processor 14 are directly connected to the same PCIe type communication bus 18. The term “directly connected” means that, on the one hand, the first interface 23 is connected to the communication bus 18 without passing through a gateway or another interface on an electronic card separate from that on which the first interface 23 is implemented and, on the other hand, that the processor 14 is connected to the communication bus 18 without passing through a gateway or another interface on an electronic card separate from that on which the processor 14 is installed.
[0051] In a second embodiment, as shown in [Fig.6], the avionics computer 10 further comprises a second communication gateway 54 comprising a first PCIe type interface connected to the processor 14 by means of a first communication bus 18 of PCIe type via a link 56 and a second interface of PCIe type connected to the first gateway 24 by means of a second communication bus 19 of PCIe type via a link 55. The first gateway 24 is connected to the second communication bus 19 via the link 22.
[0052] In particular, the avionics computer 10 comprises two electronic boxes 40, respectively 50, of similar architectures. Each electronic box comprises at least a first electronic card 12, respectively 20, comprising a PCIe type interface connected to an inter-electronic box communication bus 18 of the PCIe type via a link 16, respectively 58. The first electronic card also comprises another PCIe type interface connected to a communication bus 19', respectively 19, of the PCIe type internal to the electronic box.Each electronic box 40, 50 further comprises a second electronic card 42, respectively 52 comprising a PCIe type interface connected to the inter-electronic box communication bus 18 via a link 46, respectively 56, and another PCIe type interface connected to the other PCIe type interface of the first electronic card 12, respectively 20, by means of the communication bus 19', respectively 19, internal to the electronic box, via a link 48, respectively 55.
[0053] The processor 14 is hosted on the first electronic card 12 of one 40 of the two electronic boxes, the first communication gateway 24 is hosted on the first electronic card 20 of the other 50 of the two electronic boxes and the second communication gateway 54 is hosted on the second electronic card 52 of the other 50 of the two electronic boxes. This has the advantage of allowing the use of two electronic boxes that are similar in terms of their hardware. Only the electronic components and the software are configured differently for these two electronic boxes.
[0054] In operation, when the processor 14 transmits a data frame to the switch 28, the data from the processor 14 is transmitted to the PCI type communication bus 18 via the link 16. This data is then transmitted to the second communication gateway 54 via the link 56. The data is received by the second communication gateway 54 which retransmits it to the first communication gateway 24 via the link 55, the PCIe type communication bus 19 and the link 22. As mentioned previously, the first communication gateway 24 then transmits corresponding data frames, conforming to the Ethernet communication protocol, to the switch 28.
[0055] When the switch 28 sends a data frame to the processor 14, the data encapsulated in a data frame conforming to the Ethernet communication protocol is transmitted to the first communication gateway 24 via the link 26. As mentioned previously, the first communication gateway 24 then transmits corresponding data, via its first interface 23. This data is transmitted to the second communication gateway 54 via the link 22, the communication bus 19 of the PCIe type and the link 55. The data is received by the second communication gateway 54 which retransmits it to the communication bus 18 of the PCIe type via the link 56. This data is then transmitted to the processor 14 via the link 16.
Claims
Claims
1. 1) Avionics computer (10) intended to be installed on board a aircraft (1), such as: - the avionics computer integrates a switch (28) designed to allow data frame communications between the avionics computer and other avionics computers of the aircraft via an onboard communications network of the aircraft implementing an Ethernet type communications protocol; and - the avionics computer comprises a processor (14) connected to a communication bus (18) of the PCIe type, characterized in that it comprises a first communication gateway (24) comprising a first interface (23) of the PCIe type connected to the processor (14) by means of a communication bus of the PCIe type and a second interface (25), of the Ethernet type, connected to the switch (28), the first communication gateway being such that: - the first interface (23) comprises a reception channel (23a) and a data transmission channel (23b); - the second interface (25) comprises a reception channel (25b) and a data transmission channel (25a); - the first communication gateway (24) comprises a first FIFO type queue (30) sized to record a data frame and designed to receive data from the reception channel (23a) of the first interface and to provide output data to the transmission channel (25a) of the second interface; and - the first communication gateway (24) is configured in such a way that a recording of a complete data frame in the first FIFO type queue (30) triggers the sending of said data frame on the data transmission channel (25a) of the second interface (25).
2. 2) Avionics computer according to claim 1, characterized in that: - the first FIFO type queue (30) comprises a first memory area (34a) and a second memory area (34b), each sized to record a data frame; - a recording of a complete data frame in the first FIFO type queue (30) corresponds to a recording of the complete data frame in one of the first memory areas and the second memory area; - the first communication gateway (24) is configured such that following a recording of a complete data frame in the first FIFO type queue (30), the first communication gateway checks whether a reading of the other of the first memory zone (34a) and the second memory zone (34b) is in progress, waits if a reading is in progress for this reading to be completed, then commands an exchange of the first memory zone (34a) and the second memory zone (34b); and - the first communication gateway (24) is configured such that when a data frame is recorded in the other of the first memory area and the second memory area, the first communication gateway controls the sending of said data frame on the data transmission channel (25a) of the second interface (25).
3. 3) Avionics computer according to one of claims 1 or 2, ca characterized in that: - the first communication gateway (24) comprises a second FIFO type queue (32) sized to record a data frame and designed to receive data from the reception channel (25b) of the second interface (25) and to provide output data to the transmission channel (23b) of the first interface (23); - the first communication gateway (24) is configured to produce a timing clock signal having a so-called timing frequency based on a clock of the PCIe type communication bus to which the first PCIe type interface (23) of the first communication gateway (24) is connected, the timing clock signal having timing edges at said timing frequency; and - the first communication gateway (24) is configured in such a way that following a recording of a complete data frame in the second FIFO type queue (32), the first communication gateway (24) commands the sending of said data frame on the data transmission channel (23b) of the first interface (23) after a timing edge of the timing clock signal subsequent to the recording of the complete data frame.
4. 4) Avionics computer according to claim 3, characterized in that: - the second FIFO queue (32) comprises a first memory area (36a) and a second memory area (36b), each sized to record a data frame; - a recording of a complete data frame in the second FIFO queue (32) corresponds to a recording of the complete data frame in one of the first memory area (36a) and the second memory area (36b);- the first communication gateway (24) is configured such that following a recording of a complete data frame in the second FIFO type queue (32), the first communication gateway waits for a timing edge of the timing clock signal, then checks whether a reading of the other of the first memory area (36a) and the second memory area (36b) is in progress or whether a new writing of said one of the first memory area and the second memory area is in progress, waits if a reading or a writing is in progress for this reading or this writing to be completed, then commands an exchange of the first memory area (36a) and the second memory area (36b);and - the first communication gateway (24) is configured such that when a data frame is recorded in the other of the first memory area (36a) and the second memory area (36b), the first communication gateway controls the sending of said data frame on the data transmission channel (23b) of the first interface (23).;
5. 5) Avionics computer according to any one of the preceding claims, characterized in that the first communication gateway (24) is implemented in an FPGA type logic circuit comprising an AXI type data parallelization stage (33) linked to the PCIe type communication bus (18) to which the first PCIe type interface (23) of the first gateway is connected.
6. 6) Avionics computer according to the preceding claim, characterized in that the switch (28) is also implemented in said FPGA type logic circuit.
7. 7) Avionics computer according to any one of the preceding claims, characterized in that the first PCIe type interface (23) of the first communication gateway (24) and the processor (14) are directly connected to the same PCIe type communication bus (18).
8. 8) Avionics computer according to any one of the preceding claims, characterized in that it further comprises a second communication gateway (54) comprising a first PCIe type interface connected to the processor by means of a first PCIe type communication bus (18) and a second PCIe type interface connected to the first communication gateway (24) by means of a second PCIe type communication bus (19).
9. 9) Avionics computer according to the preceding claim, characterized in that: - it comprises two electronic boxes (40, 50) of similar architectures, each electronic box comprising at least a first electronic card (12, 20) comprising on the one hand a PCIe type interface connected to a bus (18) of PCIe type between electronic boxes and another PCIe type interface, and on the other hand a second electronic card (42, 52) comprising a PCIe type interface connected to the bus (18) of PCIe type between electronic boxes and another PCIe type interface connected to the other PCIe type interface of the first electronic card (12, 20);and - the processor (14) is hosted on the first electronic card (12, 20) of one of the two electronic boxes (40, 50), the first communication gateway (24) is hosted on the first electronic card (12, 20) of the other of the two electronic boxes (40, 50) and the second communication gateway (54) is hosted on the second electronic card (42, 52) of the other of the two electronic boxes.;
10. 10) Aircraft (1), characterized in that it comprises an avionics computer (10) according to any one of the preceding claims.
Citation Information
Patent Citations
Aircraft avionics system.
FR3103340A1
Interface Device and Method for Exchanging User Data
US20170149518A1