Resistive random access memory with reduced disturbance current in a shared source line memory cell architecture

FR3161303A1Pending Publication Date: 2025-10-17WEEBIT NANO LTD
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Patent Information

Application Number
FR2024003832
Authority / Receiving Office
FR · FR
Patent Type
Applications
Current Assignee / Owner
Filing Date
2024-04-12
Publication Date
2025-10-17

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Abstract

A resistive RAM (MEM) having a shared source line architecture, comprises an array (ARR) of memory cells (BC, BC0, BC1, BC2, BC3), each of the memory cells comprising a ReRAM resistor (VarR), the array (ARR) comprising: a first column of memory cells (BC0) comprising a first bit line (BL0) and a source line (SL0), and a second column of memory cells (BC1) comprising a second bit line (BL1) and the source line (SL0), the resistive RAM being configured to, during a programming (SET) or resetting (RESET) operation of a memory cell (BC0) of the first column, open a current path (Tr2, Tr5, Tr8, Tr11) between the source line (SL0) and the second bit line (BL1) so as to bypass a memory cell (BC1) of the second column sharing a word line (WL) with the memory cell (BC0) of the first column. Figure to be published with the abstract: Fig. 7
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Citation Information

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