Radio frequency switch

Abstract

Radio Frequency Switch This description relates to a radio frequency switch (250) comprising a control circuit (206) configured to: - in radio frequency signal transmission mode, control a switching circuit (204) with a first state derived from the output of a charge pump circuit (314, 320); and - in radio frequency signal reception mode, deactivate said charge pump circuit (314, 320) and control the switching circuit (204) with a second state derived from a reference voltage (GND, VDD). Figure for the abbreviation: Fig. 3

Description

Title of the invention: Radio frequency switch technical field

[0001] This description relates generally to radio frequency switches and the methods of operating these switches. Previous technique

[0002] Radio frequency systems use, in certain half-duplex architectures, radio frequency switches to alternately connect the same antenna to a radio frequency signal transmission circuit and then to a radio frequency signal reception circuit.

[0003] In the case where these radio frequency switches are made with silicon-on-insulator (SOI) technology, the signals that control them may generate interference during the use of the receiving circuit. Summary of the invention

[0004] There is a need to provide a radio frequency switch that does not generate spurious signals in the receiving circuit.

[0005] One embodiment overcomes all or part of the disadvantages of known switches.

[0006] One embodiment provides a radio frequency switch comprising a control circuit configured to: - in a radio frequency signal transmission mode, control a switching circuit with a first state derived from the output of a charge pump circuit; and - in a radio frequency signal reception mode, deactivate said charge pump circuit and control the switching circuit with a second state from a reference voltage.

[0007] An embodiment provides a method of operating a radio frequency switch comprising a control circuit, the method comprising: in a mode of transmitting radio frequency signals, the control of a switching circuit with a first state from an output of a charge pump circuit; in a mode of receiving radio frequency signals, the deactivation of said charge pump circuit and the control of the switching circuit with a second state from a reference voltage.

[0008] According to one embodiment, the control circuit comprises: a first node configured to receive a signal to activate the transmission mode; and an inverter block connecting the first node to a control node of a first transistor whose first conduction node is configured to receive the reference voltage.

[0009] According to one embodiment, an output node of the charge pump circuit is connected to a control node of the switching circuit.

[0010] According to one embodiment, a second conduction node of the first transistor is connected to the output node of the charge pump circuit.

[0011] According to one embodiment, the control circuit includes an oscillator connecting the first node to an input node of the charge pump circuit.

[0012] According to one embodiment, the reference voltage is ground.

[0013] According to one embodiment, the first transistor is an NMOS transistor.

[0014] According to one embodiment, the charging pump circuit is configured to provide a negative voltage on its output node when it receives an alternating signal.

[0015] According to one embodiment, the inverter block comprises a first and a second inverter; the first inverter being configured to receive another reference voltage on a first power node and ground on the second power node, the first inverter further comprising an input node connected to the first node and an output node connected to a first power node of the second inverter; the second inverter comprising an input node configured to be connected to ground, an output node connected to the control node of the first transistor and a second power supply node connected to the output node of the charge pump circuit.

[0016] According to one embodiment, the reference voltage is VDD.

[0017] According to one embodiment, the first transistor is a PMOS transistor.

[0018] According to one embodiment, the charging pump circuit is configured to provide a positive voltage greater than VDD on its output node when it receives an alternating signal.

[0019] According to one embodiment, the inverter block comprises an inverter circuit having: an input node configured to receive the reference voltage, a first power supply node connected to the output node of the charge pump circuit and a second power supply node connected to the first node; and an output node connected to the control node of the first transistor.

[0020] According to one embodiment, the switching circuit comprises silicon-on-insulator transistors.

[0021] According to one embodiment, the output node of the charge pump circuit is connected to the switching circuit via a voltage level shift circuit that is reconfigurable depending on the implementation of the charge pump circuit.

[0022] According to one embodiment, the switch comprises a first charge pump circuit and a second charge pump circuit as described above; the respective output nodes of the first and second charge pump circuits being connected to the switching circuit via a voltage level shift circuit reconfigurable according to the implementation of the first or second charge pump circuit.

[0023] According to one embodiment, the switching circuit comprises: N second transistors connecting a transmitter circuit output node to an antenna node; N third transistors connecting the antenna node to a receiving circuit input node; N fourth transistors connecting ground to the output node of the transmitting circuit; and N fifth transistors connecting ground to the input node of the receiving circuit; the control circuit being configured to drive the Nth second and Nth fifth transistors with a respective Nth first signal from the voltage level shifting circuit and to drive the Nth third and Nth fourth transistors with an Nth second signal complementary to the Nth first signal; N being an integer greater than or equal to 1.

[0024] According to one embodiment, N is equal to 1, the switching circuit comprising: a second transistor connecting an output node of the transmitting circuit to an antenna node; a third transistor connecting the antenna node to a receiving circuit input node; a fourth transistor connecting ground to the output node of the transmitting circuit; and a fifth transistor connecting ground to the input node of the receiving circuit; the control circuit being configured to drive the second and fifth transistors with a first signal from the voltage level shifting circuit and to drive the third and fourth transistors with a second signal complementary to the first signal.

[0025] One embodiment provides a radio frequency system comprising a switch as described above and an antenna connected to the antenna node. Brief description of the drawings

[0026] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0027] Fig. 1 represents, in a very schematic and block-like manner, an example of a radio frequency system of the type to which the described embodiments apply;

[0028] [Fig.2] represents, in a very schematic way, a circuit of the system of [Fig.1];

[0029] [Fig.3] represents a circuit of [Fig.2] according to one embodiment;

[0030] [Fig.4] represents a circuit of [Fig.3] according to one embodiment;

[0031] [Fig.5] represents a circuit of [Fig.4] according to another mode of operation;

[0032] [Fig.6] represents the circuit of [Fig.4] or 5 according to one embodiment;

[0033] [Fig.7] represents a circuit of [Fig.3] according to one embodiment;

[0034] [Fig.8] represents a circuit of [Fig.7] according to an embodiment

[0035] [Fig.9] represents a circuit of [Fig.7] according to an embodiment

[0036] [Fig. 10] represents a circuit of [Fig. 7] according to one embodiment;

[0037] [Fig.1 1] represents a circuit of [Fig.7] according to one embodiment;

[0038] [Fig. 12] represents a circuit of [Fig. 7] according to one embodiment;

[0039] [Fig. 13] represents a circuit of [Fig. 7] according to one embodiment;

[0040] Figure 14 represents a timing diagram of the operation of a circuit in Figure 7; and

[0041] Fig. 15 represents a circuit of Fig. 3 according to one embodiment. Description of the implementation methods

[0042] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0043] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0044] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0045] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0046] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0047] Fig. 1 represents, in a very schematic way and in block form, an example of a radio frequency system 100 of the type to which the described embodiments apply.

[0048] The system 100 includes a memory, for example non-volatile 104 (MEM), for example of type FLASH memory or Phase change memory (PCM), capable of communicating, via a communication bus 114, with a memory interface 106 (MEM INTERFACE) configured to write or read data into and from the memory 104.

[0049] The system 100 further includes, for example, a processing unit 110 (CPU) comprising one or more processors under the control of instructions stored in an instruction memory 112 (INSTR MEM). The instruction memory 112 is, for example, a volatile random access memory (RAM). The processing unit 110 and the memory 112 communicate, for example, via a system bus 140 (data, address, and control bus). The non-volatile memory 104 is connected to the system bus 140 via the non-volatile memory interface 106 and via the bus 114. The system 100 further includes an input / output interface 108 (I / O interface) connected to the system bus 140 for communication with the outside world.

[0050] The system 100 may incorporate other circuits implementing other functions (for example, one or more volatile and / or non-volatile memories, or other processing units), symbolized by a block 116 (FCT) in [Fig. 1]. Among these other circuits, the system 100 includes, for example, a radio frequency signal management circuit 118 (RF) connected to an antenna circuit 120 (ANTENNA). The function of the circuit 118 is, for example, the generation, reception, routing, and adaptation of radio frequency signals.

[0051] In one example, system 100 is part of a set dealing with the Internet of Things (IoT), Wireless Local Area Networks (WLAN), or even WIFI networks.

[0052] Figure 2 represents, in a very schematic way, a circuit of the system of Figure 1. More particularly, the figure represents an example of circuit 118.

[0053] In the example shown, circuit 118 comprises a radio frequency signal transmitter circuit 210 (TX) and a radio frequency signal receiver circuit 220 (RX). Circuit 210 is connected to a node Na. Node Na is connected to an NRF_out node via a switch 208. The NRF_out node is itself connected, preferably connected, to the antenna circuit 120. Circuit 220 is connected to a node Nb. Node Nb is connected to the NRF_out node via a switch 212. Node Na is connected to ground via a switch 222. Node Nb is connected to ground via a switch 224.

[0054] The set of switches 208, 212, 222 and 224 form a switching circuit 204. The switching circuit 204 is controlled by the control circuit 206 to form a switch 250.

[0055] In an example not shown, the circuit 204 comprises several circuits similar to the circuit formed by transistors 208, 222 or 212, 224.

[0056] In operation, in a radio frequency signal reception mode, the control circuit 206 applies complementary control signals VCTRL_TRX and VCTRLn_TRX respectively to transistors 212, 222 and 208,224 so that switches 212 and 222 are closed, i.e. they are conducting, and so that switches 208 and 224 are open, i.e. non-conducting.

[0057] In transmit mode, the control circuit 206 applies the VCTRL_TRX and VCTRLn_TRX signals so that switches 212 and 222 are open, i.e., non-conducting, and so that switches 208 and 224 are closed, i.e., conducting. A half-duplex architecture is thus formed in which the antenna 120 is alternately connected to the transmit circuit 210 via node Na and then to the receive circuit 220 via node Nb.

[0058] In the receive mode, the voltages across transistors 208 and 224 are low and the voltages across transistors 212 and 222 are almost zero, while in the transmit mode, the voltages across transistors 212 and 222 are high (for example, several volts or tens of volts) and the voltages across transistors 208 and 224 are almost zero.

[0059] In one example, switches 208, 212, 222, and 224 are transistors manufactured using silicon-on-insulator (SOI) technology. In another example, these transistors are manufactured using fully depleted silicon-on-insulator (FDSOI) technology. In this case, in order to withstand the high emission mode voltages applied to transistors 212 and 222, it is necessary to apply a significant negative voltage (in the case of NMOS transistors) or positive voltage (in the case of PMOS transistors) (for example, respectively less than -VDD or greater than +VDD) to the gates of transistors 212 and 222 to maintain their performance and ensure their non-conducting behavior in the open state. This significant voltage is often obtained by using, for example, charge pumps powered by an alternating signal such as a square wave clock signal.The voltages generated by charge pumps are likely to contain spurious signals present in the radio frequency spectrum (spurs). These spurious signals degrade the receive sensitivity of radio frequency systems.

[0060] To overcome these drawbacks, the described embodiments propose using the radio frequency switch comprising the control circuit 206 configured for: - in transmission mode, control the switching circuit 204 with a first state derived from the output of a charge pump circuit; and - in the receive mode, deactivate said charge pump circuit and control the switching circuit 204 with a second state from a reference voltage.

[0061] The term “state” is similarly understood to mean the term “signal” or “voltage at the gate-source voltage value of the transistor”.

[0062] This allows the charge pump circuit to be switched off during receive mode, where maximum sensitivity is required. This prevents spurious signals from the charge pump circuit's operation during receive mode, where high sensitivity is necessary. The reference voltage, applied to the switching circuit while the charge pump circuit is off, maintains system functionality. Although the reference voltage may be lower (in absolute value) than the voltage supplied by the charge pump circuit, the power required during receive mode is significantly lower than during transmit mode. When a charge pump circuit is switched off, its output impedance becomes high, thus creating isolation from the switching circuit.

[0063] The advantage of disabling the charge pump circuit also lies in lower consumption and in the fact that a charge pump circuit has a high impedance when not activated.

[0064] Another advantage of this solution is that it avoids the use of frequency filters based on resistors and capacitors which take up a significant amount of space and are expensive.

[0065] Figure 3 represents a circuit of Figure 2 according to one embodiment. More particularly, Figure 3 represents an example of circuit 206 connected, preferably linked, to circuit 204.

[0066] In the example of [Fig.3], a block 350 provides a TX Enable signal on a connected NI node, preferably connected, to an input of the circuit 206. The TX Enable signal is high when the transmit mode is activated.

[0067] In the example shown, circuit 206 comprises two charge pump circuits 314 (CP(2*VDD)), 320 (CP(-2*VDD)), both connected to a supply voltage rail VDD and to ground. The two charge pump circuits 314 and 320 are connected at their inputs to a node N3 receiving an alternating signal, for example a clock signal, from a circuit 316 connecting node NI and node N3. The two charge pump circuits 314 and 320 are connected, preferably connected, to node NI so as to receive, on an enable input, the TX_Enable signal.

[0068] Circuit 314, for example, allows a voltage of +2*VDD to be generated at node N2 from the supply voltage VDD. Circuit 320, for example, allows a voltage of -2*VDD to be generated at node N4 from the voltage VDD.

[0069] Circuits 314 and 320 are implemented according to the application, that is to say, either one or the other is used.

[0070] In another example not shown, only one of the two charge pump circuits is implemented depending on the application.

[0071] In the example shown, node N2 is connected to the voltage rail VDD via a switch 322. The switch 322 is controlled by a signal from an inverter circuit 318 which is connected, preferably connected, to node NI. In this example, node N4 is connected to ground via a switch 310. The switch 310 is controlled by a signal from an inverter circuit 312 which is connected, preferably connected, to node NI.

[0072] In the example shown, circuit 206 further includes circuit 330 having one or more reconfigurable control circuits. Circuit 330 includes an input connected, preferably connected, to node N2, with N inputs each receiving a respective signal EN_sw <n:l>, an input receiving the TX Enable signal and an input connected, preferably connected, to node N4. Circuit 330, for example, includes two outputs on which the VCTRL_TRX and VCTRLn_TRX signals are generated, driving the transistors of circuit 204. The respective signals EN_sw <n:l>control the actuation of the transistors in circuit 204. They are, for example, emitted by a processing unit (CPU) or generated by circuit 206.

[0073] In the example not shown where the circuit 204 comprises several circuits similar to the circuit formed by the transistors 208, 222 or 212, 224 each of these circuits receiving the VCTRL_TRX and VCTRLn_TRX signals appropriately.

[0074] The switch 310 is for example implemented by an NMOS type transistor which constitutes a pull-down transistor with the substrate of the transistor linked to the output of the charge pump circuit 320.

[0075] Switch 322 is, for example, formed by a PMOS transistor. This transistor is designated 322 because it has the same function as switch 322. Inverter 318 has a first power supply node configured to receive the TX Enable signal and a second power supply node connected, preferably connected, to node N2. Inverter 318 is configured to receive the VDD voltage at an input node. Inverter 318 has an output node connected to a control node of transistor 322. A conduction node of transistor 322, as well as its substrate node, are connected, preferably connected, to node N2. Another conduction node of transistor 322 is connected, preferably connected, to a voltage rail configured to receive the VDD voltage.

[0076] Transistor 322 is a pull-up transistor. The transistor substrate is connected to the output of charge pump circuit 314 via node N2. This results in the highest voltage being obtained in either transmit or receive mode: Vgs = 0V in transmit mode since the sources and gates are connected to the output of charge pump circuit 314, and Vgs = -VDD in receive mode.

[0077] The signal at node N2 is called VDD_sw and the signal at node N4 is noted VSS_sw.

[0078] In operation, in the case where circuit 320 is implemented: - In transmit mode, the TX Enable signal is high (e.g., VDD), which applies the VSS_sw signal to the control node of transistor 310. The VSS_sw signal is then at zero or negative voltage, for example -VDD or -2*VDD from the output of the charge pump circuit 320, which makes transistor 310 non-conducting; and - In receive mode, the TX Enable signal is low (e.g., 0V), which applies the VDD voltage to the control node of transistor 310, causing transistor 310 to conduct. The charge pump circuit 320 is also disabled, and the VSS_sw signal therefore corresponds to ground.

[0079] In the case where circuit 314 is implemented: - In transmit mode, the TX Enable signal is high (e.g., VDD), which applies the VDD_sw signal to the control node of transistor 322. The VDD_sw signal is then at a voltage greater than or equal to VDD, for example, 2*VDD, which comes from the output of the charge pump circuit 314, thus making transistor 322 non-conducting; and - In receive mode, the TX Enable signal is low (e.g., 0V), which applies zero voltage to the control node of transistor 322, causing transistor 322 to conduct. The charge pump circuit 314 is also disabled. Consequently, the VDD_sw signal is VDD.

[0080] Figure 4 represents a circuit of Figure 3 according to one embodiment. More particularly, Figure 4 represents an example of the implementation of circuit 330. Figure 4 illustrates more precisely the operation of circuit 330 when circuit 320 or 314 is activated, with the charge pumps active, i.e. in emission mode.

[0081] In the example shown, the circuit 330 includes an inverter 440 having a first supply node connected, preferably connected, to an output of an inverter 410 to receive a voltage called VI and a second supply node connected, preferably connected, to an output node of an inverter 430 where the voltage is called V5. An input node of the inverter 440 is connected, preferably connected, to an output node of an inverter 420 where the voltage is called V3. The VCTRL_TRX signal is found on an output node of inverter 440. A power supply node of inverter 410 is connected, preferably, to node N2. A power supply node of inverter 430 is connected, preferably, to node N4. An input node of inverter 420 is configured to receive either one of the EN_sw signals <n:l>, or be connected, preferably connected, to the main power rail of the VDD circuit.

[0082] In one example, the circuit 330 comprises N circuits such as that formed by the inverters 410, 420, 430 and 440 with the input node of the inverter 420 configured to receive either one of the EN_sw signals <n:l>, either be connected, preferably linked, to the main power rail of the VDD circuit. The EN_sw signals <n:l>serve as control for circuit 330 so that the appropriate VTRL_TRX / VTRLn_TRX voltages are applied at the output of circuit 330.

[0083] In the emission mode: - the 410 inverter has a power supply node configured to receive the VDD_sw signal, another power supply node at 0V and its input node at 0V (in the case where the EN_SW signal is in the low state) or VDD_sw (in the case where the EN_SW signal is in the high state); - the 420 inverter has one power supply node configured to receive the VDD_sw signal and another power supply node at 0V and its input node at VDD; and - The inverter 430 has a 0V supply node and another supply node configured to receive the VSS_sw signal as a reference, and its input node configured to receive the VSS_sw signal (when the EN_SW signal is low) or 0V (when the EN_SW signal is high). Thus, the voltage present at the output of the inverter 440, i.e., VCTRL_TRX, is VSS_sw (when the EN_SW signal is low) or VDD_sw (when the EN_SW signal is high).

[0084] Figure 5 represents a circuit of Figure 3 in a different operating mode. Figure 5 illustrates more precisely the operation of circuit 330 of Figure 3 when circuit 320 or 314 is deactivated, i.e., in receive mode. In this example, the input node of inverter 420 is configured to receive one of the EN_sw signals. <n:l>.

[0085] In reception mode: - the 410 inverter has a power node configured to receive VDD, another power node is at 0V and its input node is at 0V; - the 420 inverter has a power supply node configured to receive VDD, another power supply node is at 0V and its input node is at 0V (in the case where the EN_SW signal is low) or VDD (in the case where the EN_SW signal is high); and - The 430 inverter has a VDD supply node, another 0V supply node as a reference, and its input node configured to receive the VDD signal. Thus, the voltage present at the output of the 440 inverter, i.e., VCTRL_TRX, is 0V (when the EN_SW signal is low) or VDD (when the EN_SW signal is high).

[0086] The advantage of the circuit 330 in Figures 4 and 5 is that it allows addressing both reception and transmission operating modes, whether with a pump charging circuit 314 giving a positive voltage or a pump charging circuit 320 giving a negative output voltage or both.

[0087] Fig. 6 represents the circuit of Fig. 4 or 5 according to one embodiment.

[0088] The [Fig.6] includes an upper part 602 which represents the generation of the The voltage VCTRL_TRX and a lower part 604 which represents the generation of the voltage VCTRLn_TRX and which is similar to the upper part. Only the upper part is described in detail below.

[0089] In part 602, a level-decreaser 612 connects a node N5 to an input node of a logic gate 633 configured to perform a NAND logic function from the signal present at this input node and ground. The level-decreaser 612 is configured to be off in receive mode, i.e., these power supply nodes are grounded, and in transmit mode, to shift the voltage domain present at node N5 (e.g., VDD / GND) to a lower voltage domain (e.g., GND / VSS). An output node of gate 633 is connected, preferably connected, to an input node of an inverter 637. Inverter 637 and gate 633 have a power node connected, preferably connected, to an output node of an inverter 640 having an input node connected, preferably connected, to the NI node, as well as another power node set to VSS as a reference.The 640 inverter includes a power node configured to be connected, preferably connected, to VDD and another power node configured to be connected, preferably connected, to ground (GND).

[0090] In part 602, a logic gate 631 is configured to perform a NOT-OR (NOR) function between the TX Enable signal present on node NI and that present on node N5. Gate 631 has one supply node to VDD and another supply node to ground.

[0091] Part 602 further includes a logic gate 622 configured to perform a NOT-OR (NOR) function between the signal present at one of its input nodes connected, preferably connected, to node N5 and the signal present at another input node which is connected, preferably connected, to an output node of an inverter 642. The inverter 642 has a power supply node connected, preferably connected, to VDD and a another power supply node connected, preferably connected, to ground. The 642 inverter has an input node connected, preferably connected, to the NI node. An output node of the 622 gate is connected, preferably connected, to a 624 inverter having a power supply node connected, preferably connected, to VDD and another power supply node connected, preferably connected, to ground.

[0092] In part 628, an NMOS transistor 623 and a PMOS transistor 626 have a conduction node N7 in common. Another conduction node of transistor 626 is connected, preferably connected, to the output node of inverter 624, and another conduction node of transistor 623 is connected, preferably connected, to the output node of inverter 637. The control nodes of transistors 623 and 626 are connected, preferably connected together, to the output node of gate 631.

[0093] In the example in [Fig.6], a node N3 is configured to receive the EN_sw signal <n:l>Node N3 is connected, preferably connected, to a first branch comprising two inverters 606, 618 in series between node N3 and node N5. Node N3 is connected, preferably connected, to a second branch comprising an inverter 610 connecting node N3 to part 604. Inverters 606, 610, and 618 have one power node connected, preferably connected, to VDD and another power node connected, preferably connected, to ground.

[0094] Voltage V5 is read from the output node of inverter 637, voltage V3 is read from an output node of logic gate 631, voltage VI is read from an output node of inverter 624, and the signal VCTRL_TRX is read from node N7. The signal VCTRLn_TRX is read from node N6 of the 604 section, which is equivalent to node N7.

[0095] The assembly formed by the inverters 624, 642 and the gate 622 has the function of forcing VI to VDD in the receive mode and of allowing VI to switch from VDD to ground in the transmit mode. The assembly formed by the inverters 640, 637 and the gate 633 forces V5 to ground in the receive mode and allows V5 to switch from ground to VSS in the transmit mode.

[0096] During operation, the TX Enable signal is low in receive mode, VDD is then, for example, at 1.5V and VSS at 0V. The TX Enable signal is high in transmit mode, VDD is then increased, for example, to 2.5V and VSS is decreased, for example, to -2.5V.

[0097] In receive mode, circuit 612 is deactivated and: - in the case where the EN_sw signal <n:l>When V is at 0V, ground (in other words, 0V) is applied to node N5 and node NI. VI and V3 are then at VDD and V5 is grounded. VCTRL_TRX is then ground. - in the case where the EN_sw signal <n:l>is at 1, node N5 is at VDD and node NI is still grounded. VI is then at VDD, while V3 and V5 are grounded. VCTRL_TRX is then VDD.

[0098] In transmit mode, circuit 612 is activated and: - in the case where the EN_sw signal <n:l>is at 0, the ground is applied to node N5 and node NI is at VDD. VI and V3 are then grounded and V5 at VSS. VCTRL_TRX is then at VSS. - in the case where the EN_sw signal <n:l>is at 1, node N5 and node NI are at VDD. VI is then at VDD, while V3 and V5 are grounded. VCTRL_TRX is then VDD.

[0099] When the voltage values ​​controlling switches 208, 212, 222, and 224 are changed, the switching times of the switches are affected. This is because the charging time constant of the transistor gates is constant, as is their threshold voltage. However, the final value of the charge is different, and the charging and discharging curves of the transistor gates differ depending on the value of the control voltage. If the control voltage is close to the threshold voltage, then, due to the unchanged gate time constant, the gate voltage reaches the threshold later on the charging curve. It would therefore be advantageous to be able to limit these changes in the switching time or minimize the reaction time from the change of state of the EN_sw control signals. <n:l>.

[0100] The examples in Figures 4, 5, and 6 thus implement a digital buffer circuit, materialized by two inverters in series, when one of the charge pump circuits is deactivated. The behavior of the circuit in [Fig. 6], which acts as a level shifter, is conditioned by the digital bit EN_sw <n:l>which is the same as the one that conditions the activation or deactivation of the charging pump circuits.

[0101] Figure 7 represents a circuit of Figure 3 according to one embodiment. More Specifically, [Fig.7] illustrates one embodiment of the 350 circuit. [Fig.7] proposes a solution to limit changes in the switching time of the transistors.

[0102] In the example shown, state change detection circuits 701, 702, 703 and 704 include an input node configured to receive the control signals from the EN_sw respectively <l>, EN_sw <2> , EN_sw <k>an EN_sw <n>Each circuit 701, 702, 703, and 704 comprises a flip-flop 741 having a data input D connected, preferably connected, to an exclusive OR (XOR) logic gate 742 and receiving the respective signal EN_sw <l>, EN_sw <2> , EN_sw <k>or EN_sw <n>Each flip-flop has its output Q connected, preferably connected, to an input node of the respective XOR gate 742. The control inputs G of the flip-flops 741 in each of the circuits 701, 702, 703, and 704 are connected, preferably connected, together and to the NI node. The respective output signal of each circuit 701, 702, 703, and 704 is called the State_change. Each output of the circuits 701, 702, 703 and 704 is connected, preferably connected, to a respective input node of a NOR gate 710. The signal at the output of gate 710 is called State_change_n. The output node of gate 710 is connected, preferably connected, to an input node of a NOR gate 720. Another input node of logic gate 720 is configured to receive a Tx_state_n signal that drives the activation of the transmit signal of circuit 204. The subscript "n" in Tx_state_n indicates that it is an active-low signal. The Tx_state_n signal is common to all transmit and receive paths. An output node N9 of gate 720 is connected, preferably connected, to a delay block 730. The signal at node N9 is called EN_TX. Block 730's function is to delay falling edges only. An output node of block 730 is connected, preferably directly, to node N1 to generate the TX_enable signal.

[0103] In operation, the previous state of the EN_sw signals<N: 1> is stored on the D input of the flip-flops and propagated to the Q outputs. When one of the EN_sw signals changes state <n:l>The respective 742 gate compares the new state to the previous one and changes its output to a high digital state (=1) if the new state is different from the previous state. Consequently, the State_change_n signal is changed to 0 by the 710 gate and then combined with the Tx_state_n signal to generate the TX_enable signal, which activates the charge pump circuit(s). In one example, the charge pumps are all activated simultaneously, which speeds up switching. In another example, the charge pumps are all deactivated to ensure the absence of spurious noise. Activating the TX_enable signal activates the G gates of the flip-flops, which updates their outputs and forces the outputs of all 742 gates back to 0.This will disable the charge pump circuit (when receive mode is enabled), but since a delay is introduced on the falling edges of the EN_TX signal, the charge pump circuit remains active for a few ps, which is long enough to allow the gates of the transistors in circuit 204 to charge or discharge once the threshold voltage has passed.

[0104] Figures 8 to 13 show a circuit of [Fig. 7] according to different embodiments. More specifically, Figures 8 to 13 show different embodiments of the delay circuit 730.

[0105] The delay circuit 730 of [Fig. 8] comprises a PMOS transistor 810 and an NMOS transistor 820, each having a conduction node connected, preferably connected, to a node N8, and their respective control nodes connected, preferably connected, together. Another conduction node of transistor 810 is connected, preferably connected, to a voltage rail configured to receive the voltage VDD, for example, and another conduction node of transistor 820 is connected, preferably connected, to the network. Node N8 is connected to the network via a capacitor 830 and connected to node NI via an inverter circuit 840.

[0106] In one example, the gate width-to-length ratio of transistor 810 is much lower than the gate width-to-length ratio of transistor 820. This allows for a much higher channel resistance for transistor 810 compared to transistor 820. Thus, the time constant formed by the channel resistance and the capacitance 830 is much larger when transistor 810 is active than when transistor 820 is active. This means that node N8 takes longer to charge (i.e., reach VDD) than to discharge (i.e., go to ground GND), and therefore to reach the switching threshold of inverter 840. This results in a delay at the output of inverter 840 when it transitions to the low state.

[0107] The delay circuit 730 of [Fig.9] is similar to that of [Fig.8] except that the circuit 840 is replaced by a Schmitt trigger 940.

[0108] The advantage of the circuit in [Fig.9] compared to that in [Fig.8] is to obtain reduced noise sensitivity and a greater induced delay.

[0109] The delay circuit 730 of [Fig. 10] is similar to that of [Fig. 8] except that a resistor 1010 connects the conduction node of transistor 810 which is not connected to VDD to node N8.

[0110] The circuit in [Fig. 10] makes it possible to obtain a significant time constant (and therefore a significant delay) with a reasonably sized capacitor. Indeed, the width-to-length ratio of the transistor gate is limited for a given technology, and therefore so is the maximum channel resistance of a transistor. If it is desired to increase the resistance value beyond the technological limit, it is necessary either to add a resistor in series with the transistor 810, as is the case in the example in [Fig. 10], or to connect several transistors in series.

[0111] The delay circuit 730 of [Fig. 11] is similar to that of [Fig. 10] except that the circuit 840 is replaced by a Schmitt trigger 940.

[0112] The advantage of the circuit in [Fig. 11] compared to that of [Fig. 10] is that it provides reduced noise sensitivity and a larger induced delay. Compared to the example in [Fig. 9], it allows for a large time constant (and therefore a large delay) with a reasonably sized capacitor.

[0113] The delay circuit 730 of [Fig. 12] is similar to that of [Fig. 8] except that transistor 810 is connected to the voltage rail receiving VDD via four PMOS transistors 1210, 1220, 1230, 1240 in series, with their respective control nodes all connected together to node N7. The addition of the transistors PMOS 1210, 1220, 1230, 1240 allows increasing the channel resistance and therefore the time constant as well as the gate delay.

[0114] The delay circuit 730 of [Fig. 13] is similar to that of [Fig. 12] except that the inverter 840 is replaced by a Schmitt flip-flop 940.

[0115] In figures 8 to 13, the signal at node N8 is called EN_TXn.

[0116] Fig. 14 represents a timing diagram of the operation of the circuit of Fig. 7.

[0117] More specifically, [Fig. 14] represents the signals TX Enable, EN_TXn, EN_TX, State_change_n, State_change, EN_sw(Nl) and one of the signals EN_sw <n:l>.

[0118] In the example shown, before a time t0, the TX Enable signal is low, the EN_TXn signal is high, the EN_TX signal is low, the State_change_n signal is high, the State_change signal is low, the EN_sw signal <n-l>is at the high level and EN_sw <n:l>is at the high level.

[0119] At time tO, the signal EN_sw <n-l>goes to a low level which causes the State_change signal to go high, then the State_change_n signal to go low, then the EN_TX signal to go high, then the EN_TXn signal to go low, and finally the TX_Enable signal to go high.

[0120] At a time t1, subsequent to t0 and corresponding to the activation time of the gate G of the 741 flip-flops by the TX_Enable signal, the EN_sw(nl) signal, which corresponds to the previous state of the D inputs, goes low and remains low. This causes the corresponding State_change signal to go low and then the State_change_n signal to go high. Gate 720 then sets the EN_TX signal low. Circuit 730 then slowly raises the EN_TXn signal until its level is high enough to trigger the TX_Enable signal to go low at a time t2. The various signals in [Fig. 14] then remain stable, for example, until the next state change of a control signal. The time window between times t1 and t2 defines the delay or lag allowing fast switching of the transistors in circuit 204.

[0121] Figure 15 represents a circuit of Figure 3 according to one embodiment. More particularly, Figure 15 represents an implementation of the charging pump circuit 320, the circuit 312 and the switch 310.

[0122] In the example shown, the inverter block 312 is implemented with a first and second inverter 1508, 1510 and the switch 310 is implemented in the form of an NMOS transistor.

[0123] The first inverter 1508 has a first power supply node connected, preferably connected, to a voltage rail receiving the voltage VDD and a second power supply node connected, preferably connected, to ground. The first inverter 1508 further includes an input node connected, preferably connected, to the NI node and a output node connected, preferably connected, to a first feed node of the second inverter 1510.

[0124] The second inverter 1510 includes an input node configured to be connected to ground, an output node connected to the control node of transistor 310 and a second power supply node connected to the output node N4 of the charge pump circuit 320.

[0125] A conduction node of transistor 310, as well as its substrate node, are connected, preferably connected, to node N4. Another conduction node of transistor 310 is connected, preferably connected, to ground.

[0126] This allows the lowest voltage to be obtained in either transmit or receive mode at the substrate node, ensuring that the diode between the substrate and the source remains reverse-biased. The transistor's Vgs voltage, in transmit mode, is 0V since the sources and gates are connected to the output of the charge pump circuit 320. In receive mode, Vgs = VDD.

[0127] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to them. In particular, the use of circuit 350 is not mandatory for the operation of the circuit in [Fig. 3]. Those skilled in the art may implement only one of the two charge pump circuits depending on the requirements of the transistors to be driven. Similarly, only one of the two parts 602 or 604 of the circuit in [Fig. 6] may be implemented, and any additional signal may be generated by any circuit according to the knowledge of those skilled in the art.

[0128] Finally, the practical implementation of the described embodiments and variants is within the grasp of a person skilled in the art, based on the functional specifications given above. In particular, switches 310 or 322 and the respective inverters 312 and 318 may be implemented in a manner other than that shown in [Fig. 6]. Similarly, the delay circuit 730 may be implemented in ways other than those shown in Figures 8 to 13, provided that this allows for a time window where the TX_Enable signal temporarily transitions from low to high before returning to low, thus defining a time window that enables rapid switching of the transistors in circuit 204.

[0129] Even though two mutually exclusive radio frequency paths RX, TX have been described, those skilled in the art may consider implementing N mutually exclusive RX paths and N mutually exclusive TX paths. In this case, the switching circuit 204 comprises: N second transistors 208 connecting a transmitter circuit output node (Na) to the antenna node NRF_out; N third transistors 212 connecting the antenna node (NRF_out) to the input node of the receiving circuit Nb; N fourth transistors 222 connecting ground to the output node of the Na emission circuit; and N fifth transistors 224 connecting ground to the input node of receiver circuit Nb, N being an integer greater than or equal to 1.

[0130] In this case, the control circuit 206 controls the Nth second and Nth fifth transistors 208, 224 with a respective Nth first signal VCTRL_TRX <n>originates from the voltage level shift circuit 330 and also controls the Nth third and Nth fourth transistors 212,222 with an Nth second signal VCTRLn_TRX <n>complementary to the Nth first VCTRL_TRX signal <n> .< / n> < / n> < / n> < / n:l> < / n:l> < / n:l> < / n> < / k> < / l> < / n> < / k> < / l> < / n:l> < / n:l> < / n:l> < / n:l> < / n:l> < / n:l> < / n:l> < / n:l> < / n:l> < / n:l> < / n:l> < / n:l> < / n:l>

Claims

Demands

1. Radio frequency switch (250) comprising a control circuit (206) configured to: - in a radio frequency signal transmission mode, control a switching circuit (204) with a first state from an output of a charge pump circuit (314, 320); and - in a radio frequency signal reception mode, deactivate said charge pump circuit (314, 320) and control the switching circuit (204) with a second state from a reference voltage (GND, VDD).

2. Method of operating a radio frequency switch comprising a control circuit, the method comprising: in a radio frequency signal transmission mode, controlling a switching circuit (204) with a first state from an output of a charge pump circuit (314,320); in a radio frequency signal reception mode, deactivating said charge pump circuit (314,30) and controlling the switching circuit (204) with a second state from a reference voltage (GND, VDD).

3. Switch according to claim 1 or method according to claim 2, wherein the control circuit (206) comprises: a first node (NI) configured to receive a transmit mode enable signal (TX Enable); and an inverter block (312, 318) connecting the first node to a control node of a first transistor (310, 322) whose first conduction node is configured to receive the reference voltage (GND, VDD).

4. Switch according to claim 1 or 3, or method according to claim 2 or 3, wherein an output node (N2, N4) of the charge pump circuit is connected to a control node of the switching circuit.

5. Switch or method according to claim 3 or 4, wherein a second conduction node of the first transistor is connected to the output node (N2, N4) of the charge pump circuit.

6. A switch or method according to any one of claims 3 to 5, wherein the control circuit (206) comprises a oscillator (316) connecting the first node (NI) to an input node (N3) of the charge pump circuit.

7. Switch according to any one of claims 1 or 3 to 6 or method according to any one of claims 2 to 6, wherein the reference voltage is ground.

8. Switch or method according to claim 7 in its dependence on claim 3, wherein the first transistor (310) is an NMOS transistor.

9. Switch or method according to claim 8, wherein the charge pump circuit (320) is configured to provide a negative voltage on its output node (N4) when it receives an alternating signal.

10. A switch or method according to claims 8 or 9 in their dependence on claim 3, wherein the inverter block (312) comprises a first and a second inverter; the first inverter being configured to receive another reference voltage (VDD) on a first supply node and ground on the second supply node, the first inverter further comprising an input node connected to the first node (NI) and an output node connected to a first supply node of the second inverter; the second inverter comprising an input node configured to be connected to ground, an output node connected to the control node of the first transistor (310) and a second supply node connected to the output node (N4) of the charge pump circuit (320).

11. Switch according to any one of claims 1 or 3 to 6 or method according to any one of claims 2 to 6, wherein the reference voltage is VDD.

12. Switch or method according to claim 11 in its dependence on claim 3, wherein the first transistor (322) is a PMOS transistor.

13. Switch or method according to claim 12, wherein the charge pump circuit (314) is configured to provide a positive voltage greater than VDD on its output node (N2) when it receives an alternating signal.

14. A switch or method according to claims 12 or 13 in their dependence on claim 3, wherein the reversing block (318) comprises a reversing circuit having: an input node configured to receive the reference voltage (VDD), a first power supply node connected to the output node (N2) of the charge pump circuit (314) and a second power supply node connected to the first node (NI); and an output node connected to the control node of the first transistor (322).

15. Switch according to any one of claims 1 or 3 to 14, or method according to any one of claims 2 to 14, wherein the switching circuit (204) comprises silicon-on-insulator transistors (212, 208, 222, 224).

16. Switch according to any one of claims 1 or 3 to 15, or method according to any one of claims 2 to 15, wherein the output node (N2, N4) of the charge pump circuit is connected to the switching circuit (204) via a voltage level shift circuit (330) reconfigurable according to the implementation of the charge pump circuit.

17. Switch according to any one of claims 1 or 3 to 16, or method according to any one of claims 2 to 16, comprising a first charge pump circuit (314) according to claim 9 and a second charge pump circuit (320) according to claim 13; the respective output nodes (N2, N4) of the first and second charge pump circuits being connected to the switching circuit (204) via a voltage level shift circuit (330) reconfigurable according to the implementation of the first or second charge pump circuit.

18. A switch or method or device according to claim 17, wherein the switching circuit (204) comprises: N second transistors (208) connecting a transmit circuit output node (Na) to an antenna node (NRF_out); N third transistors (212) connecting the antenna node (NRF_out) to a receive circuit input node (Nb); N fourth transistors (222) connecting ground to the transmit circuit output node (Na); and N fifth transistors (224) connecting ground to the receive circuit input node (Nb); the control circuit (206) being configured to control the Nth second and Nth fifth transistors (208, 224) with a respective Nth first signal (VCTL_TRX) <n>) from the voltage level shift circuit (330) and control the Nth third and Nth fourth transistors (212, 222) with an Nth second signal (VCTRLn_TRX <n>) complementary to the Nth first signal (VCTL_TRX <n>) ; N being an integer greater than or equal to 1.

19. Switch or method or device according to claim 18, in which N is equal to 1, the switching circuit (204) comprising: a second transistor (208) connecting a transmitter circuit output node (Na) to an antenna node (NRF_out); a third transistor (212) connecting the antenna node (NRF_out) to a receiver circuit input node (Nb); a fourth transistor (222) connecting ground to the output node of the transmitter circuit (Na); and a fifth transistor (224) connecting ground to the input node of the receiving circuit (Nb); the control circuit (206) being configured to control the second and fifth transistors (208, 224) with a first signal (VCTL_TRX) from the voltage level shift circuit (330) and to control the third and fourth transistors (212,222) with a second signal (VCTLn_TRX) complementary to the first signal (VCTL_TRX).

20. Radio frequency system comprising a switch according to claim 18 or 19 and an antenna (120) connected to the antenna node (NRF_out).< / n> < / n> < / n>

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