REALIZATION OF A 3D MICROELECTRONIC DEVICE WITH A HIGH ASPECT RATIO INTERCONNECTION ELEMENT

Abstract

A 3D microstructure is formed by bonding an upper plate (1) to a lower plate. A blind hole (120) with a high aspect ratio is formed in the upper plate (1) prior to the bonding of the plates, with a bottom extending through the thickness of the substrate (11) of the plate. The formation of the hole (120) is stopped at a predetermined distance (h) from the rear face (10) of the substrate (11). The hole is filled with metal to form a metallic pillar (120) for the purpose of creating an electrical and / or thermal metallic interconnection between the upper and lower plates after the hybrid bonding.After the upper plate (1) is flipped and bonded to the lower plate, a thinning of the rear substrate (11) of the upper plate (1) exposes the metal at the bottom of the blind hole made before the hybrid bonding. This makes the metal pillar a through-hole through the rear face of the thinned substrate (11). This pillar can constitute a through-hole via (TOV), essentially created before the plates are bonded. Figure 3.

Description

Title of the invention: REALIZATION OF A 3D MICROELECTRONIC DEVICE WITH A HIGH ASPECT RATIO INTERCONNECTION ELEMENT technical field

[0001] The invention relates generally to the field of the microelectronics or semiconductor industry. It relates more particularly to three-dimensional (3D) integration, by the vertical assembly of two two-dimensional (2D) microelectronic devices, each formed on a wafer or a die based on the respective semiconductor material, known as W2W (from the English "Wafer-to-Wafer") or D2W (from the English "Die-to-Wafer") or D2D (from the English "Die-to-Die") bonding, for the realization of a 3D microelectronic device.

[0002] More specifically, the invention relates to a method for manufacturing a 3D microelectronic structure (or 3D microstructure) obtained by bonding a first wafer, referred to as the upper wafer, to a second wafer, referred to as the lower wafer, with a high interconnection density between said wafers, as well as a 3D microelectronic structure obtained by implementing the method, for the fabrication of an integrated semiconductor product. In the context of this description, the term "wafer" refers to both a disc ("wafer") and a die ("die"): thus, the method for bonding two wafers that will be described applies equally to W2W, D2W, or D2D bonding.

[0003] It finds applications, in particular, in the manufacture of high-density integration microsystems and components, such as microelectromechanical systems (MEMS) or nanoelectromechanical systems (NEMS), actuators, radio frequency (RF) components, power devices, or microelectronic devices such as advanced microprocessors, graphics chips, optoelectronic circuits such as CMOS (Complementary Metal-Oxide-Semiconductor) image sensors (or imagers), display screens, or other. State of the art

[0004] The microelectronic devices used in the composition of semiconductor products integrated into a package (or integrated circuits) are produced by essentially planar technological steps. These steps are carried out on wafers or discs (the English word "wafer" literally translates to "slice"). (in French) based on semiconductor material, such as doped silicon. More specifically, a series of technological steps are implemented, starting from a flat substrate forming the support for the device, with access at each stage to the microstructure being fabricated via the top face of the wafer, also called the "front face". The size of a wafer is generally about 200 mm in diameter for 8" (i.e., 8 inches) technology or about 300 mm in diameter for 12" technology.

[0005] A wafer on which a microelectronic device is fabricated comprises a substantially planar substrate, with an active area in the upper part of said substrate in which the active components of the device are fabricated, and a multilayer interconnection structure formed above said active area of ​​the substrate. The interconnection structure is adapted to electrically connect the active components previously formed in the active area to each other and to electrical connection pads with other microelectronic devices integrated in the same package or with pins of the integrated circuit package through which the circuit can be electrically powered and used to perform its function in a given application.Where appropriate, the interconnection structure may also incorporate passive components (inductors, capacitors, resistors, heat sinks, etc.) made in the form of planar metallic elements, possibly multilayered, extending into the stacked interconnection layers.

[0006] The fabrication of the active components of the microelectronic device in the active area of ​​the substrate corresponds to the FEOL (Front-End-of-Line) phase of the device's manufacturing. The fabrication of the device's interconnection structure, on the other hand, occurs during the BEOL (Back-End-of-Line) phase of the manufacturing process. The FEOL phase will not be specifically addressed here, as the invention is implemented during the BEOL phase.

[0007] The interconnection structure comprises a stack of interconnection layers, arranged sequentially with alternating horizontal and vertical interconnection layers. The former include horizontal metallizations, i.e., metallic traces extending parallel to the wafer plane to electrically connect respective elements of the active components made in the active zone of the substrate, and / or, where applicable, metallic elements forming the aforementioned passive components. "Trace" means metallic structures extending in a plane parallel to the plane of the wafer substrate and whose dimensions (length and width) in said plane are substantially greater than their thickness in the direction orthogonal to said plane. The vertical interconnections, for their part, comprise vias which extend substantially perpendicularly to the plane of the wafer substrate in order to electrically connect metallic tracks and / or passive components belonging to respective horizontal interconnect layers.

[0008] Wafer bonding refers to a technology for vertically joining a first wafer, called the top wafer, to another wafer, called the bottom wafer, also known as the handle wafer, in reference to its function of supporting the resulting microstructure. To this end, the first wafer is inverted vertically, then aligned and deposited with its leading face onto the leading face of the handle wafer. If the top surfaces of the respective wafers brought into contact are extremely flat, Van der Waals forces—microscopic attractive interactions that exist for all materials—ensure adhesion between the top and bottom wafers. In the relevant technical field, the term "bonding" is used to describe an assembly based on the use of these adhesive forces.Adhesion is stronger when the contact surface between the two plates is large at the microscopic level.

[0009] Bonding two or more wafers stacked vertically, with or without an intermediate layer, allows for the creation of a 3D microstructure, even though only 2D fabrication technologies are separately implemented in the FEOL (Front-End-of-Line) phase of manufacturing to fabricate the microelectronic devices in each of the two wafers, respectively. Various technological protocols (process flows) exist for achieving such a 3D assembly. These various technological protocols can be adapted to the specific requirements of the intended applications, which are numerous and varied. This discussion will be limited to hybrid bonding solutions for W2W semiconductor wafers, compatible with a bond between assembled wafers that is at the wafer level (a so-called "wafer-level bonding").

[0010] A hybrid (or heterogeneous, oxide / oxide and metal / metal) direct bonding can be used in 3D integration. To join the two separate wafers, respective areas of dielectric material (such as silicon dioxide, SiO2, for example) on each wafer are bonded together, and respective areas of metallic material (such as copper, Cu, for example) on each wafer are also bonded together. However, only a mechanical bond is thus achieved, and there is no operational electrical continuity at the bond interface. The electrical connections between the upper and lower wafers, which are intended to enable the The desired device functionality can be achieved, after bonding, by forming through-silicon vias (TSVs). These are high-aspect-ratio vias that pass through the silicon dioxide (SiO2) and / or silicon (Si) layers of the top wafer after it has been flipped and bonded to the bottom wafer. Their function is to provide an electrical connection from the back side of the top wafer's substrate to elements of the bottom wafer, across the bonding interface. However, this technique offers only a low interconnection density between the wafers. Furthermore, its implementation is relatively lengthy and complex, as the TSV fabrication process involves many etching and deposition steps.Finally, this process includes steps carried out at high temperatures, which are likely to cause damage to the bonding interface between the wafers in the case of heterogeneous bonding (i.e., with different coefficients of thermal expansion between oxide areas and metal areas bonded two-by-two), potentially leading to bonding defects.

[0011] Hybrid bonding is a well-known approach, in itself, to those skilled in the art. According to this approach, two wafers are processed separately, following a conventional integration process up to and including the realization of the last of the standard metallization levels of their respective interconnection structure, namely the n stacked metallization levels also called levels M1, M2, ..., Mn. After this step, a penultimate (i.e., second-to-last) metallization level, called level HBV (from the English "Hybrid Bonding Vias"), as well as a final (i.e., last) metallization level called level HBM (from the English "Hybrid Bonding Metal"), are added vertically to the interconnection structure of each of the wafers.The HBV and HBM layers are typically produced by continuing the Damascus process after the n underlying metallization layers (i.e., the M1, M2, ..., Mn layers). The dielectric material in these HBV and HBM layers is therefore SiO2 deposited by chemical vapor deposition (CEVD). The HBM layer contains metallic elements forming conductive tracks that extend in the horizontal plane of this layer. These metallic elements, known as horizontal metallizations, serve to facilitate the bonding of the wafer for hybrid bonding with corresponding metallic elements of the other wafer.The HBV level, which is directly below the HBM level, contains exclusively vertical metallizations (perpendicular to the plane of the substrate) for the electrical connection of some of the metallic bonding elements of the HBM level with one or more metallic elements in the lower metallization levels of the stack of levels M1, M2, ..., Mn. .

[0012] TSVs can also be provided to, as an alternative or in addition, ensure thermal conduction in order to evacuate heat generated by the operation of the integrated microelectronic devices towards the upper face of the corresponding 3D microstructures and, ultimately, towards the outside of the integrated circuit package.

[0013] Furthermore, TSVs can also (i.e., in addition to their aforementioned functions of electrical connection and / or thermal conduction for heat dissipation) perform a marking function to facilitate the alignment of a microstructure during a subsequent manufacturing step. This function may even be specifically allocated to TSVs in some cases.

[0014] In existing art, illustrated for example by US patent 8860229, vertical TSV interconnections are made after the vertical assembly (Le., bonding) of the two wafers, to re-establish the electrical connection with elements of the lower wafer, in order to make them accessible from the upper face of the 3D microstructure, which corresponds to the rear face of the inverted upper wafer. This embodiment nevertheless presents difficulties. Indeed, in order to avoid degrading temperature-sensitive materials, particularly heat-sensitive materials constituting electronic or optoelectronic components that have been previously fabricated on the surface or in the active areas of at least one of the wafers, the TSVs fabricated in this way must be obtained by implementing low-temperature processes and are therefore slower and less efficient.Furthermore, due to the etching techniques used to create the trenches, the diameter of the resulting TSVs is limited to the thickness of the substrate layer to be penetrated. However, the thickness of the substrate of the upper wafer to be penetrated depends on the thinning process, the thickness homogeneity of the assembled substrates, and the processes performed on them.

[0015] US20150021785 discloses TSV-type interconnects embedded in the substrate of the top wafer before the bottom and top wafers are assembled. The TSVs are performed before the BEOL levels (collectively referred to as the "metallization structure" in this document) and before the bonding level (referred to as the "bonding structure" in this document). However, the interconnect rerouting is performed in a specific interconnect structure (referred to as the "interconnect" in this document) added above the wafer stack, i.e., on the back side of the top wafer after the 3D microstructure has been formed by bonding. The number of technological steps is therefore particularly significant. Furthermore, the interconnect structure, specifically added after bonding, complicates the fabrication of integrated circuits in separate manufacturing facilities.This does indeed complicate the use of subcontracting for . the execution of certain manufacturing phases for example in a first factory for the realization of the FEOL and the BEOL in CMOS technology, then in a second factory specializing in the realization of the TSV, and finally in a third factory having resources and skills for the realization of the bonding levels and the assembly of wafers. Description of the invention

[0016] The invention aims to provide an alternative to the existing art described above, making it possible to overcome the associated drawbacks by performing the interconnection before the assembly by bonding the upper and lower plates, but by performing the rerouting on the front face of said plates before bonding. This makes it possible, in particular, for example, to subcontract the bonding to a specialized manufacturing plant without having to then return the material to the initial plant where the first part of the BEOL has already been produced, in order to create a complementary interconnection structure as in the prior art according to document US20150021785.

[0017] To this end, the invention has as its first object a method for producing a three-dimensional, 3D microelectronic structure, comprising the hybrid bonding of an upper wafer onto a lower wafer after vertically flipping of said upper wafer, said lower wafer and said upper wafer each comprising a substantially flat silicon substrate as well as an interconnection structure formed above said silicon substrate, the method comprising, prior to the hybrid bonding: • the formation, within the thickness of the silicon substrate of the upper wafer, of a blind hole having a high aspect ratio, i.e. having a depth substantially greater than its surface area, for example 10 to 100 times greater, in a position laterally distant from any active component in an active zone of the substrate located in the upper part of said substrate, said formation being stopped at a height determined relative to the rear face of the substrate, • Filling the blind hole with metal to form a metallic pillar for the purpose of creating a metallic interconnection between the upper and lower plates after hybrid bonding, and the process further comprising, after reversing and bonding the upper plate to the lower plate, a thinning of the rear substrate of the upper plate to expose the metal at the bottom of the non-through hole made before the hybrid bonding, whereby the metal pillar is made to open through the rear face of the thinned substrate of the upper plate.

[0018] Thus, after the upper plate is flipped and bonded to the lower plate, a thinning of the rear substrate of the upper plate exposes the metal at the bottom of the blind hole made before the hybrid bonding, thereby making the metal pillar pass through the rear face of the thinned substrate. This pillar can constitute a through-via (TSV), which was nevertheless essentially created before the plates were bonded.

[0019] As will be understood, the aforementioned advantages of the invention derive in particular from the fact that it comprises a vertical interconnect of the metallic pillar type, capable of serving as a vertical vertical connection (VTC), which penetrates only partially into the substrate and is subsequently revealed by thinning said substrate after bonding, such that it is only after this revelation that the metallic pillar becomes truly through-hole. Furthermore, the embodiments include the use of the metallization level dedicated to hybrid bonding (the final metallization level, referred to as the HBM level) to redistribute the conductive traces for the electrical connection of the microelectronic devices of the two vertically assembled wafers. No additional metallization structure is required, unlike the solution described in US20150021785.

[0020] Advantageously, the process allows the temperature-critical steps for the formation of the TSV to be carried out before the wafer assemblies. This eliminates thermomechanical stresses in the case of surfaces to be bonded or substrates that are heterogeneous (having areas with different coefficients of thermal expansion, or CTE) and / or exposes heat-sensitive materials, thus preventing the degradation of temperature-sensitive materials.

[0021] The process also allows the assembly of heterogeneous structures, including, for example, silicon and gallium nitride (GaN), as used in the fabrication of LEDs, in the active areas of at least one of the wafers. Indeed, gallium nitride (GaN) is not heat-sensitive but has a different CTE than silicon (Si), making the assembly heterogeneous (the CTE of GaN is approximately -60 ppm / K and that of Si is approximately 3 ppm / K).

[0022] Some preferred but not limiting aspects of the process are the following.

[0023] The method may further include, after the formation of the metal pillar but before the vertical turning and the bonding of the upper plate onto the lower plate, the creation of a bonding connection structure above the interconnection structure of said upper plate, said bonding connection structure being adapted to ensure the resumption of electrical connections between respective interconnection structures of the upper and lower plates, and comprising metallizations in continuity with the metal pillar.

[0024] The realization of the bonding connection structure may include the realization of a horizontal metallization level preceded by the realization of a vertical metallization level between said horizontal metallization level and the interconnection structure of the upper plate.

[0025] The formation of the non-through hole can be stopped upon detection of a determined stop element present at the desired level for the bottom of said non-through hole.

[0026] For example, the stopping element may be a buried oxide layer.

[0027] The thinning of the rear substrate of the upper wafer can be stopped upon detection of the same stop element as the stop element for the formation of the non-through hole.

[0028] In embodiments, the method may further include, after thinning the back substrate of the upper wafer, the formation of a brazable metal alloy ball above and in electrical and thermal continuity with the metal pillar, for the electrical connection of the 3D microelectronic structure.

[0029] Active components made in the active area of ​​the substrate of the lower wafer may include LEDs.

[0030] A second aspect of the invention relates to a three-dimensional, 3D microelectronic structure for an integrated semiconductor product, said 3D microelectronic structure comprising a metallic pillar or a through via and being realized by implementing the method according to the first aspect above. Brief description of the drawings

[0031] Other aspects, objects, advantages, and features of the invention will become clearer upon reading the following detailed description of preferred embodiments thereof. This description is given by way of non-limiting example. It is made with reference to the accompanying drawings, in which: Fig. 1 is a vertical cross-sectional view of an example of a 2D microelectronic device, adapted for the realization of a 3D microstructure by hybrid bonding with another similar device, after completion of the FEOL and BEOL phases of fabrication; [Fig.2] is a schematic representation illustrating the 2D microstructure of [Fig.1] after the formation of a metal column in a blind hole intended to form a TSV; [Fig.3] is a vertical cross-sectional view of the 2D microstructure of [Fig.2] with the realization of two final levels of metallization dedicated to the bonding of the corresponding plate with another plate in the context of a hybrid bonding between these two plates; [Fig.4A] schematically illustrates the bonding of two plates; [Fig.4B] is a further view of the 3D microstructure obtained by the hybrid bonding illustrated by [Fig.4A]; [Fig.5] is a vertical cross-sectional view of the 3D microstructure of [Fig.4B] after thinning of the back substrate of the upper plate, revealing the metal pillar intended to form a TSV; Figure 6 is a view of the 3D microstructure similar to that of Figure 5, after the application of a passivation layer to the back substrate of the upper wafer; Figure 7 is a view of the 3D microstructure similar to those of Figure 4B and Figure 5, after the additional application of solder beads intended for the electrical connection of the 3D microstructure; and [Fig.8] is a step diagram illustrating groups of steps in implementing the process according to the invention. Detailed description of implementation methods

[0032] In the figures and throughout the description, the same numerical references designate identical or similar elements. Furthermore, the various elements are not drawn to scale, in order to prioritize the clarity of the figures. Moreover, the different embodiments and variants presented are not mutually exclusive and may be combined.

[0033] In what follows, the terms "approximately", "around", and "in the order of" mean to the nearest 10%, and preferably to the nearest 5%. Furthermore, the expressions "between A and B", and equivalent expressions mean that the bounds A and B are inclusive, unless explicitly stated otherwise.

[0034] By the expression "formed from", used in reference to a material and an element of interest, it is understood that the material is a compound formed from a plurality of elements of which at least the said element of interest is included.

[0035] The expression "material comprising predominantly" an element of interest means a material of which at least 50% by volume is formed by, or comprises, said element of interest.

[0036] The term "wafer" is an English term that designates a very thin plate (also called a "wafer" due to its small thickness) of single-crystal semiconductor material, on which microelectronic devices can be fabricated. Wafers are thus used to manufacture microelectronic devices. Wafers are made of a doped semiconductor material, such as silicon (Si), gallium arsenide (GaAs), or indium phosphide (InP). Wafers generally have dimensions ranging from 25.4 mm (1" technology) to 300 mm (12" technology), with a thickness of approximately 0.7 mm. Wafers are used in the microelectronics industry as a substrate for manufacturing microstructures. This manufacturing process employs design techniques such as For example, and without limitation: doping, etching, deposition of other materials, and photolithography. The doped semiconductor material from which the wafer is made therefore serves as a substrate for the creation of the microstructures forming the active microelectronic devices that are part of the composition of integrated circuits, transistors, power semiconductor products, MEMS or NENS, etc.

[0037] In the manufacture of an integrated circuit, the FE (Front End) phase refers to all the technological manufacturing steps of the circuit before it is packaged. The FE includes the FEOL (Front End Of The Line) phase as well as the BEOL (Back End Of The Line) phase. The FEOL refers to the first phase, in which all the manufacturing steps of the active components (transistors), for example in CMOS technology, are carried out, in the active area of ​​the wafer up to (but not including) the first level of metallization of the interconnect structure placed on top.BEOL refers to the second phase of integrated circuit fabrication, which begins with the first layer of metallization. This phase involves the stacking of metallization layers that form the interconnect structure. The active components in the active area of ​​the wafer are interconnected according to a routing plan that ensures the wiring of these active components to the wafer. In this second phase, individual microelectronic devices forming the passive components (capacitors, inductors, resistors, etc.) can also be fabricated at different metallization levels within the interconnect structure. Commonly used metals are copper (Cu) and aluminum (Al). BEOL begins when the first metal layer is deposited onto the wafer.By extension, the term "BEOL" sometimes refers to the interconnect structure which includes the insulating (dielectric) layers, the metal traces (horizontal electrical connections), the vias (vertical electrical connections between the traces), and the splice sites for electrical connections between the microstructure and the package of the integrated circuit.

[0038] Through Silicon Vias (TSVs) are vertical connecting elements, or vias, with a high aspect ratio, meaning they have a relatively large height along the direction orthogonal to the plane of the wafer or stacked wafers compared to their cross-section in a plane parallel to said plane of the wafers. In principle, and unless otherwise stated in the context of the following description, TSVs are through-vias, that is, vertical connections etched through the entire thickness of the silicon substrate of the upper wafer after the bonded wafers have been thinned. They are metal-filled holes that can directly interconnect two stacked wafers by vertical assembly. Depending on the process, TSVs can be connected at the front, middle, or rear of the integrated circuit line. In the context of classic 3D integration, TSVs are combined with direct bonding whereby the dielectric layers respectively formed at the top of the interconnect structure of each of the wafers are bonded together after vertically flipping the top wafer to form a 3D stack of wafers.

[0039] The expression "chemical-mechanical polishing" or CMP (from the English "Chemical-Mechanical Polishing"), already used in the introduction, refers to a surface smoothing process of a wafer using the combined action of mechanical and chemical forces, resulting in the removal of the material(s) on the surface of the wafer and the erasure of any surface topography, with the result of the planarization of the surface of the wafer exposed to this process.

[0040] The "Damascene process" is a technique for forming metallic elements (also called "metallizations") in copper, which consists of etching trenches and via holes in a layer of dielectric material, then filling the trenches and via holes and the surface with copper, and finally flattening the copper using chemical mechanopolishing (CMP) to form conductive tracks and vias.

[0041] The "annealing" of a material is an operation corresponding to a heating cycle, consisting of a step of gradually increasing the temperature to temperatures ranging from approximately 250°C to 450°C, followed by controlled cooling. Annealing allows the physical characteristics of the material subjected to this heat treatment to be modified.

[0042] Electrochemical deposition (ECD) is a deposition technique used for filling trenches or via boreholes with a metal such as copper. Its operating principle is as follows: the wafer is configured as a negative electrode (cathode) and is immersed in an electrolyte, i.e., an electrolytic solution containing metallic salts. Copper is deposited from an anode, i.e., a positive counter-electrode, made of copper. To do this, the metal ions in the anode are reduced by applying a potential difference between the anode and the cathode. For the reaction to occur homogeneously over all desired portions of the wafer surface, these portions must be conductive.In other words, it is therefore necessary that the resistivity of the bonding layer on the targeted portions of the wafer be as low as possible.

[0043] The term "photoresist" refers to a material, more particularly a polymer resin, that is sensitive to light and is used to form a pattern on the substrate, using an optical mask made up of opaque and transparent areas that define the pattern to be reproduced on the wafer. The photoresist is illuminated through this mask, and its properties are modified in the transparent areas of the optical filter. Thus, for example, a photoresist "positive" is a light-sensitive polymer which, when exposed to ultraviolet (UV) light, transforms into a soluble material: the areas exposed to this illumination can then be dissolved using a solvent, leaving behind a hollow patterned layer which can be used as a mask for the formation of a structure through the mask thus formed, for example by etching an underlying material which is selective to the mask material, by ion implantation, or by depositing a new material in the areas exposed by the mask.

[0044] Finally, a three-dimensional orthogonal (X,Y,Z) direct frame of reference is defined here and for the remainder of the description, where the X and Y axes form a plane parallel to the principal plane of the "handle" plate under consideration, and where the Z axis is oriented substantially orthogonally to the principal plane of said plate, this Z axis being oriented along the direction of gravity. In the remainder of the description, the terms "vertical" and "vertically" are understood to refer to an orientation substantially parallel to the Z axis, and the terms "horizontally" and "horizontally" to refer to an orientation substantially parallel to the (X,Y) plane.Furthermore, the terms "above" and "below" and their derivatives (such as "above" and "below", or "over" and "underneath"), as well as the terms "lower" and "upper", used to describe an element of the microstructure under consideration, are understood to be relative to an increasing positioning when moving away from the wafer upwards, i.e., along the vertical direction +Z.

[0045] The terms "back" and "front," on the other hand, are used with reference to the face of a wafer through which the various treatments are, or have been, carried out to produce the microstructure in question. Since these treatments are systematically carried out from above when the wafer is placed flat in a chamber used to perform the treatment, the "front" face is generally (and by default) the upper face of the wafer. However, when a wafer or a chip cut from a wafer is turned vertically, its front face becomes the lower face and its back face becomes the upper face.The term "rear" applied to the semiconductor substrate of an individual wafer or chip is also used in reference to this convention, in the sense that it designates the part of the substrate that is furthest from the face of said wafer or chip where treatments have been carried out in the substrate, and which is always referred to as the rear face even if the wafer has been turned vertically so that this face is now on top and facing upwards.

[0046] By "layer" is meant a substantially horizontal extent of a material whose thickness along the vertical axis Z is less, for example ten times or even twenty times, than its horizontal dimensions (width and length) in the horizontal plane XY.

[0047] By "alloy bump" (or "bump" in English), we mean a volume of a conductive material, for example based on a brazable alloy such as SnAgCu or SAC (tin, silver, and copper), whose thickness along the Z-axis is substantially equal to its longitudinal dimensions of width and length in the XY plane, and whose longitudinal dimensions are less than or equal to the thickness along the Z-axis of a layer in which it is formed. The shape of the bump, in a horizontal cross-section (parallel to the XY plane), may be rounded, for example, a circle or an ellipse. It may also be polygonal, for example, a square or a rectangle.Such a solderable alloy pad, also called a solder ball, serves to enable the assembly and / or electrical connection of the 3D microstructure with, where applicable, other microstructures or other elements of the integrated electronic circuit

[0048] . The "aspect ratio" or "form ratio" or "form factor" of a motif in a microelectronic structure designates the ratio of the height of said motif (along the vertical Z-axis) to the area (i.e., to the horizontal dimensions or surface dimensions) of the motif in a cross-sectional plane (which is the horizontal XZ plane). The value of the aspect ratio is denoted "N:l", where N is a specific number that is compared to a unit area. A motif with an aspect ratio equal to one (N=l), denoted "1:1", is a motif that is as tall (or deep) as it is horizontally extended.A pattern with an aspect ratio greater than one (N > 1) is a pattern that extends substantially vertically (along the Z direction). Conversely, a pattern with an aspect ratio less than one (N < 1) is a pattern that extends substantially horizontally (in the XY plane). A high aspect ratio (N > 1, for example, N between 10 and 20, or even between 10 and 100) defines a tall, narrow pattern, such as a pier (or column) constructed to create a through-via, for example. It is substantially taller than it is horizontally extended. In other words, its vertical dimension (height or depth) is substantially greater than its horizontal dimensions (i.e., the dimensions that define its surface area in the horizontal plane). The adverb "substantially" means that there is a ratio between the dimensions being compared that is between 10 and 20, or even between 10 and 100, for example.

[0049] Specific embodiments will be described with reference to the non-limiting example of application to the fabrication of a 3D microelectronic structure for the manufacture of an integrated semiconductor product, for example, using CMOS technology. The embodiments of this 3D microstructure and the implementation methods of the process described can be adapted to the specific characteristics of each application concerned, without departing from the principles of the invention. The drawings in [Fig. 1] to [Fig. 7] are vertical cross-sectional views of an example of a 2D microelectronic device at various stages of its fabrication according to a conforming process to implementations of the process of the invention. The step diagram of [Fig.8] schematically illustrates eight groups of technological steps included in the realization of the microstructure, each allowing to reach an intermediate state of said microstructure as represented on each of the figures from [Fig.1] to [Fig.7], respectively.

[0050] Of course, the breakdown of the process into individual steps as described below, as well as their grouping in accordance with the step diagram in [Fig. 8], is purely arbitrary for the purposes of this description and does not limit the scope of the invention. Similarly, intermediate technological steps exist but have not been presented in order to avoid obscuring this description with unnecessary details. Only those steps or groups of steps that are useful for understanding ways of implementing the process of creating a 3D microstructure by the vertical assembly of two identical or similar 2D microelectronic devices, with the formation of at least one TSV, are described, in accordance with the teaching of the invention.

[0051] With reference to [Fig.1], a first microelectronic device, for example a CMOS technology device, is made on a wafer 1, comprising a substrate 11. It should be noted that in what follows, the reference "1" will be used interchangeably to designate the microelectronic device in question and the semiconductor wafer which carries it.

[0052] The substrate 11 is, for example, a silicon substrate, preferably a SOI substrate (silicon-on-insulator). An SOI substrate is advantageous because the buried oxide (BOX) can be used as a far-end substrate passivation (FBEOL). Alternatively, the substrate 11 can also be a pure silicon (Si) substrate. The rear face 10 of the wafer 1 is the underside of the substrate 11. Above the substrate 11, the device 1 comprises a layer 12 of electrically insulating (dielectric) material. The layer 12 is itself covered by a passivation layer 13.

[0053] In its upper part, located directly below the layer of electrically insulating material 12, the substrate 11 includes active components, not shown, such as transistors, photonic devices such as LEDs, photodiodes, etc. Such components, where applicable, are manufactured using, for example, the technological manufacturing steps that are the classic steps of CMOS microelectronics, in order to produce an integrated circuit for a specific application. This phase of circuit manufacturing (or FEOL phase) will not be addressed in this description, as the invention is implemented during the subsequent BEOL phase, namely the phase of realizing the structure interconnection. This interconnection structure will now be described, again with reference to [Fig. 1].

[0054] The electrically insulating (dielectric) material of layer 12 can be silicon dioxide (SiO2), for example. In some embodiments, this layer can be obtained by plasma-enhanced chemical vapor deposition (or PECVD).

[0055] The passivation layer 13 is, for example, a silicon nitride (SiN) layer. Its function is to stabilize the state of the electrically insulating material layer 12 after the formation of said layer, and to prevent contamination of the active area of ​​the substrate, in particular by diffusion of copper or water. The silicon nitride layer 13 can be deposited by low-pressure chemical vapor deposition (LPCVD) or by plasma-enhanced chemical vapor deposition (PECVD), followed by chemical treatment with phosphoric acid (H3PO4).

[0056] The fabrication of the passivation layer 13 completes the FEOL phase of the manufacturing process, which is followed by the BEOL phase. At the end of the FEOL phase of wafer 1 fabrication, said wafer is as shown at the bottom of [Fig. 1]. Wafer 1 then comprises only the substrate 11, which is coated with the layer of electrically insulating material 12, itself covered with the passivation layer 13. The subsequent manufacturing steps belong to the BEOL phase of said fabrication. The BEOL phase includes, in particular, the fabrication of an interconnection structure for the microelectronic device on wafer 1.

[0057] This microelectronic device 1 comprises an interconnection structure formed by a stack of n layers, each corresponding to a respective metallization level, where n is an integer strictly greater than one. These n interconnection layers are essentially made of an electrically insulating (dielectric) material, such as silicon dioxide (SiO2). They contain metallic elements (also called "metallizations" for short), namely conductive tracks (horizontal metallizations) or vias (vertical metallizations). These metallic elements are produced by depositing metal in trenches or via holes, respectively, previously formed by any suitable process, in the dielectric material of the corresponding interconnection layer. The trenches and via holes are generally formed by photolithographic etching and then filled with metal.The metal in question is usually copper (Cu), but it could possibly be another metal, such as aluminium (Al) or tungsten (W), for example.

[0058] The respective metallization levels of the interconnecting structure are commonly referred to by the acronyms M1, M2, ..., Mn in the relevant literature. In the layer stacking that forms the interconnecting structure, There is an alternation of horizontal metallization levels comprising conductive tracks made by depositing metal in trenches formed in the dielectric material of the corresponding layer, and vertical metallization levels comprising vias made by depositing metal in via holes formed in the dielectric material of the corresponding layer. The vias of a vertical metallization level are arranged to couple respective conductive tracks of a metallization level above with conductive tracks of a metallization level below and / or with active elements of the active zone of the substrate 11.

[0059] In the example of [Fig. 1], n is equal to three (n=3): the interconnection structure comprises three layers 14, 17, and 20 stacked vertically, in that order, above the insulating layer 12 with which the substrate 11 is coated. They are formed successively above the substrate 11, one after the other, starting with the lowest layer and ending with the highest layer. In this example, layer 14 is the lowest layer of the interconnection structure, or the lowest layer, that is to say, also the one closest to the substrate 11. It corresponds to the first level of metallization, denoted M1 in [Fig. 1] and thereafter. It is formed directly above substrate 11. In the opposite direction along the vertical Z, layer 20 is the uppermost layer of the interconnection structure, or highest layer, that is to say also the one that is furthest from substrate 11.It corresponds to the last metallization level, denoted M3, of the interconnect structure of the microelectronic device. Layers 14 and 20 are horizontal metallization layers. They include conductive tracks 15 and 21, respectively. Finally, layer 17 is an intermediate layer between the two aforementioned layers 14 and 20; it is a vertical metallization layer of the interconnect structure, formed above the lower layer 14 and below the upper layer 20. It includes vias 18.

[0060] The vias 18 serve to electrically connect the metallization elements to which they are respectively coupled, i.e., with which they are in electrical continuity. In the example shown in [Fig. 1], several vias 18 are made in electrical continuity with a first of the tracks 21 of the metallization level M3 formed directly above the metallization level M2, and also in electrical continuity with a first of the conductive tracks 15 made in the metallization level ML. This allows the passage of a greater current between the tracks thus connected by a plurality of vias, without modification of the aspect ratio of said vias.

[0061] Where appropriate, one or more vias can ensure the electrical continuity of functional connecting elements made in metallization levels that are more vertically spaced in the stack of the n interconnecting layers, and even directly with active elements made in the active zone of substrate 11. These vias can pass through one (or more) intermediate layer(s) of silicon dioxide (SiO2) based dielectric material before reaching a horizontal metallization in an interconnect layer corresponding to a horizontal metallization level located lower in the stack, or an active element of the active zone of substrate 11.

[0062] The metallizations in the Ml-Mn metallization levels have an average dimension in the horizontal XY plane which is between a few tens of nanometers and a few tens of microns, for example between 20nm and 20pm, preferably between 200nm and 1Opm, and preferably even more between 800nm ​​and 5pm, for example on the order of 1pm or 2pm.

[0063] It should be noted that each of the dielectric material layers 12, 14, and 17 is coated with a passivation layer 13, 16, and 19, respectively, which separates it from the dielectric material layer 14, 17, or 20, respectively, which is above it. The passivation layer 13 has already been described above. The passivation layers 16 and 19 are similar to it and can be made in the same way.

[0064] Therefore, the adverb "essentially," which can be used with reference to the composition of the hybrid layer of each of the Ml to Mn metallization levels, should be understood to mean that these levels may also include, for example, a passivation layer intended to passivate the dielectric material that forms part of the composition of said level. Furthermore, the expressions "directly above" or "directly below," used in relation to two metallization levels among the Ml to Mn metallization levels, should simply be understood to mean that there is no other metallization level between the two levels concerned. However, this does not preclude one of the metallization levels from including, on top of said level and therefore below the metallization level above it, a passivation layer, for example, a silicon nitride (SiN) layer.In other words, this does not imply that all dielectric portions and / or all metallic portions of one of the Ml to Mn metallization levels are in direct contact with dielectric portions and / or metallic portions of another vertically adjacent Ml to Mn metallization level.

[0065] Of course, the invention is not limited by the number n of metallization levels of the interconnection structure, nor by the number or shape of the horizontal or vertical metallizations included in the corresponding layers, which are dictated only by the interconnection functions to be performed in the specific application concerned.

[0066] With further reference to the step diagram in [Fig. 8], step 1 of the process which is implemented in the BEOL phase of the fabrication of the 3D microstructure includes the formation of such an Ml-Mn interconnection structure. This formation is figured, that is, symbolically represented, by block 81 in the step diagram of [Fig.8].

[0067] The Ml-Mn interconnection structure can be formed by implementing the process known as the "Damascene method". This process comprises successively, for each level of Ml to Mn interconnection to be implemented in stacking (with n=3 in the example considered here): • the deposition of a layer of dielectric material on the upper face of the substrate of the microelectronic device, for the first interconnection layer, or on the upper face of an interconnection layer already made, for any interconnection layer following said first interconnection layer; • the etching, in this dielectric layer, of trenches (for horizontal interconnection layers) or of via passage holes (for vertical interconnection layers); • the deposition of copper (Cu) onto the etched dielectric layer, in order to fill the trenches and / or via holes, to obtain the desired metallic interconnecting elements; and, • the mechanochemical polishing (CMP) of excess copper in order to flatten the upper surface of the interconnection layer thus produced, with a view to the formation of another level of interconnection on top of the one which has just been produced.

[0068] At the end of step 1 (block 81 of the diagram in [Fig.8]), the microstructure is as shown in [Fig.1].

[0069] Now with reference to the diagram in [Fig.2], the second group of steps 2 to 6, which is represented by block 82 of the step diagram in [Fig.8], corresponds to the making of a blind hole 120 of TSV, which is specific to the implementation methods of the process of the invention. By "blind hole" of TSV or "non-through hole" of TSV, we mean a hole with a high aspect ratio (ratio N:1 with N»l) which is drilled in the wafer from the top face of said wafer for the purpose of making a TSV, which passes entirely vertically through the Ml-M n interconnection structure from one side to the other, and which penetrates into the interior of the silicon substrate 11 but does not pass through said substrate: it does not open out at the rear face 10 of the substrate 11. In other words, the hole 120 has a bottom in the thickness of the substrate 11 at a distance h (or height), determined from the rear face 10 of the substrate 11 along the vertical direction Z, which is non-zero.Furthermore, it is recalled that by the term "high aspect ratio" we mean an N:1 aspect ratio in which N is . substantially greater than one (N»l, for example N is between 10 and 20, or even between 10 and 100).

[0070] Step 2 consists of a photolithography operation performed with a suitable photoresist, the thickness of which can be between 1 and 100 µm, for example. This thickness must be greater the more isotropic and / or less selective the subsequent etching step(s) are, and the greater the risk of damaging the resin mask thus formed.

[0071] In step 3, the microstructure is etched to form the blind hole 120 for the through-via (TSV) to be produced. This etching may include: • firstly, a RIE type etching (“Reactive Ion Etching” in English), which is a relatively anisotropic dry etching, applied to the dielectric layer(s) of the Ml to Mn metallization levels of the interconnect structure, to a depth that can be between approximately 1 and approximately 10 pm, • followed by a DRIE type (“Deep Reactive Ion Etching” in English) etching of the silicon of the silicon substrate 101 to a depth which can be between about 1 pm and about 100 pm, for example, until reaching a determined depth (identified by the horizontal dotted line 121) inside the thickness of the silicon substrate 101.

[0072] The DRIE etching process combines plasma-assisted deposition and etching processes. While the silicon is etched as in RIE-type etching, for example under ion bombardment caused by radio-frequency excitation, it is also exposed to a fluorinated gas, for example sulfur hexafluoride (SF6) or octafluorocyclobutane (C4F8, also known as perfluorocyclobutane). This combined etching process allows the fluorinated component to be deposited on the vertical walls of the etched pattern in order to passivate them, particularly at the interface with the silicon substrate. Repeated cycles of etching and deposition with given gases and times allow the silicon to be etched deeply and anisotropically.

[0073] In some embodiments, the etching performed in this step 3 is selective at a stop element positioned at a predetermined depth within the thickness of the substrate 11 of the wafer 1, allowing the etching to be stopped at a desired and well-controlled depth. This stop element can be a stop layer, for example, a buried oxide layer or "Box" layer. Alternatively, the etching can be a time-stopped etch, in that the etch depth is determined by the etch time. This alternative embodiment eliminates the need for a specific SOI-type substrate and thus reduces manufacturing costs.

[0074] Once the etching is complete, in step 3a the resin residue is removed ("stripped") from the etching mask used for this etching. This can be done by chemical etching. For example, this removal can be by plasma stripping, which is a purely chemical and isotropic process. Alternatively, the resin mask can be removed by wet etching, for example with stripping solutions and / or solvents such as NMP (1-Methyl-2-Pyrrolidone). This type of etching is also purely chemical: the material to be removed is brought into contact with these products, which leads to the progressive consumption of the material.

[0075] In step 4 of step group 82, the internal walls of the blind hole 120 of TSV are then insulated, for example by depositing a film of silicon dioxide (SiO2) or silicon nitride (SiN). This deposition can be carried out, for example, by PECVD, which is a plasma-assisted chemical vapor deposition technique. The thickness of the insulating film thus produced can typically be between approximately 10 nm and approximately 2 pm.

[0076] Then, in step 5, the blind hole 120 of TSV is filled with metal, generally copper (Cu), to create a metal pillar 120 having the same dimensions as the blind hole (for convenience, the pillar thus created is also referred to hereafter by the same reference numeral as the blind hole in which it is made). To this end, the following steps can be performed successively: • firstly the deposition of an adhesion layer, for example in titanium (Ti), which can be carried out for example by a physical vapor phase deposition technique (or PVD, from the English "Physical Vapor Deposition"); • then the deposition of a diffusion barrier, for example of titanium nitride (TiN) or tantalum nitride (TaN), for example carried out by PVD or ALD (Atomic Layer Deposition), which is a technique for depositing atomic layers, i.e., layers at the atomic level. Alternatively, the deposition of the diffusion barrier in TiN or TaN can be carried out by PEALD (Plasma Enhanced Atomic Layer Deposition), which is a plasma-assisted version of the ALD technique. The typical thickness of the diffusion barrier layer is between approximately 10 nm and approximately 2 pm; and, • finally the deposition of an electrically conductive layer, for example copper (Cu), which can be carried out for example by an ECD technique (from the English "Electro-chemical Deposition"), and whose typical thickness is between about 10 nm and about 2 pm, to fill the blind hole 120.

[0077] The final step in the fabrication of a metal pillar in the blind hole 120 of TSV (which is still non-through at this stage) is step 6 of step group 82 in the step diagram of [Fig. 8]. This step 6 consists of flattening, for example produced by CMP, the aforementioned layers of electrical conduction, diffusion barrier and adhesion which were produced in step 5. To avoid any confusion, it is specified that this flattening is carried out on the front face of wafer 1.

[0078] At the end of the group of steps 82 comprising steps 2 to 6 described above, the microelectronic device of the upper wafer 1 is as schematically represented in [Fig.2].

[0079] It should be noted that the hole 120 of TSV is laterally offset from any active component present in the active zone of the substrate 11, in the upper part of said substrate, in order not to damage them.

[0080] It also goes without saying that the TSV hole 120 is made in an area of ​​the wafer that is laterally offset (i.e., in the horizontal plane of the wafer) from an area in which the metallizations of the M1 to Mn layers of the interconnecting structure are present. This results in a spacing between the TSV hole 120 and the metallizations in question, which prevents any inappropriate electrical interconnection.

[0081] Those skilled in the art will appreciate that implementing the method according to the invention makes it possible to create the holes for TSVs with direct access to the HBM metallization level on the front face of the insert 1, before it is flipped over and bonded to another insert. Compared to the conventional TSV formation, which is performed after bonding from the rear face of the flipped upper insert, the risk of lateral displacement of the TSVs from their desired position is greatly reduced.

[0082] Those skilled in the art will also appreciate that the metal pillar 120, intended to become a TSV (Tension-Specific Vessel), is formed in the upper plate 1 before the two plates 1 and 2 are bonded together. The temperature tolerance is approximately 450°C. Therefore, there is less risk of stress on the microstructure involved. Indeed, it is still a 2D microstructure, and not yet a 3D microstructure with a bonding interface that could be damaged by the temperature rise required for the formation of the TSV hole 120.

[0083] Finally, it should be noted that the metal pillar 120 thus produced can also serve as an alignment pattern (or "mark" or "marker"). This does not refer to alignment for bonding the lower and upper plates, but to aligning the plate to achieve the metallization levels for redistribution of interconnections (or RDL, from the English "Redistribution Loyer"), and / or for creating the reflow assembly bumps intended for assembling the 3D microstructure with other structures, if necessary. This avoids having to search for marks in the plate substrate. inferior after gluing, which is usually done by infrared (IR) detection, with relative accuracy.

[0084] The following group of steps 83 consists of the fabrication of the wafer elements participating in the interface for bonding with another wafer in the context of the vertical assembly of microelectronic devices by hybrid bonding. This fabrication is now described with reference to the diagram in [Fig. 3].

[0085] Hybrid bonding elements are specifically produced in a final metallization layer of each corresponding wafer, i.e., the highest metallization layer of the interconnection structure of said wafer, which is also the layer furthest from the substrate. In what follows and in the figures in the drawings, this layer is denoted "HBM" (from the English "Hybrid Bonding Metal") to distinguish it from the conventional M1 to Mn metallization layers of the BEOL (Hybrid Bonding Metal) which provide the electrical interconnection of elements within the wafer in question only and / or include passive elements of said wafer. The upper face of the bonding elements is therefore exposed on the surface of the interconnection structure of each respective wafer, which is also the surface of the wafer, at the end of the BEOL phase of the manufacturing process.

[0086] In embodiments of the process, the bonding interface 40 between wafer 1 as the upper wafer on another wafer 2 as the lower wafer, which will only appear from [Fig. 4B] onwards, comprises more particularly, within each of said wafers: • The aforementioned HBM level, which is a horizontal interconnection level dedicated to bonding and having for this purpose horizontal metallizations forming bonding elements, i.e., tracks ensuring support and possibly electrical connection to corresponding bonding elements of the other wafer; as well as • an underlying vertical interconnection level which is designated by the acronym HBV (for "Hybrid Bonding Vias" in English) in order also to distinguish it from the Ml to Mn metallization layers, and which ensures as needed the electrical connection of the metallic bonding elements of the HBM level with metallic elements of the Ml-Mn interconnection structure of the wafer in question.

[0087] In some embodiments, the HBM layer may further include dummy interconnecting elements (“dummies”), for example, non-functionalized metal studs (i.e., studs that do not have an operational function when the device is used). These dummy studs allow for a more homogeneous metallization density on the HBM layer, which is beneficial to the quality of the bonding.

[0088] Since the HBM level bonding elements are made of metal, and more specifically of copper (Cu) within a layer of dielectric material (SiO2) using the Damascus process, they are inherently electrically conductive and can therefore be used for electrical connection between the two stacked wafers. The bonding of the wafers is described as "hybrid" because the bonding interface 40 between the wafers is heterogeneous. It comprises: • metal-to-metal (Cu-Cu) zones corresponding to the respective bonding elements 21 associated with the two plates 1 and 2, on the one hand; and, • dielectric-dielectric portions 22 (SiO2-SiO2) corresponding to the zones between said bonding elements 21, on the other hand.

[0089] Advantageously, the last level of metallization of each 2D microstructure, i.e. of wafers 1 and 2, can be used to ensure the electrical connection of the 3D microstructure with its environment from the rear face of the upper wafer 1, unlike what is usually done and which consists of taking up, by TSVs made after bonding, the level of metallization Ml of one and / or the other of the stacked microelectronic devices.

[0090] Step group 84 of the diagram in [Fig. 8] shows the steps involved in performing a vertical assembly by hybrid bonding of wafers like the one in [Fig. 3]. [Fig. 4A] symbolically illustrates the hybrid bonding of wafer 1 of [Fig. 3] as the bottom wafer onto another wafer 2, also as the bottom wafer, corresponding to step 8 of the process. This can be a hybrid bond at the wafer level, i.e., a wafer-to-wafer bond, but it can also be a die-to-wafer hybrid bond or even a die-to-die hybrid bond. [Fig. 4B] illustrates the 3D microstructure obtained by this vertical assembly of wafers 1 and 2.

[0091] In the highly simplified example illustrated in the figures, the lower plate 2 is identical to the upper plate 1 except that it does not include a blind hole 120 filled with metal. The upper surface of each of the plates is ultra-polished.

[0092] As symbolically represented by an arrow in [Fig. 4A], the vertical assembly of the plates is carried out in step 8. For this purpose, the upper plate 1 is turned vertically and aligned in the horizontal XY plane (i.e., it is aligned both along the longitudinal X direction and along the transverse Y direction) with respect to the lower plate 2. This result is obtained by referencing connecting elements 21 of the plate 1 with corresponding connecting elements of the lower plate 2. This operation is carried out according to methods, and by the implementation of equipment which is known to the person in the trade, and whose detailed description would be outside the scope of this presentation.

[0093] The bonding of the upper plate 1 to the lower plate 2, as shown in [Fig. 4B], is achieved by the effect of Van der Waals forces, covalent bonds, and hydrogen bonds formed during contact, due to the particularly smooth and flat surface of the respective upper faces of the plates 1 and 2. The bonding is therefore direct—without glue—and takes place at room temperature. This avoids the risk of degradation and unwanted interaction of an adhesive during subsequent temperature treatment, if necessary. The contact of the plates can be carried out in a pressure range of 0.5 to 10 bar, and, for example, under an atmosphere containing hydrogen (H2), as well as nitrogen (N2), argon (Ar), or helium (He), or any combination of several of these gases, possibly with one or more other gases as well.

[0094] In step 9, the resulting 3D microstructure can undergo bonding annealing to strengthen the bonding interface 40 between wafers 1 and 2 and ensure the electrical connection between the metallic bonding elements that electrically connect wafers 1 and 2. For example, bonding annealing can be performed at 400 °C for two hours. To assess the quality of the bonding, scanning acoustic microscopy (SAM) can be used to detect any voids at the bonding interface 40.

[0095] The next step, namely step 10, which is the only step in block 85 of the diagram in [Fig. 8], is a specific step in the implementation of the method according to the invention. It involves revealing the rear end surface of the metal pillar formed in hole 120 of TSV, to obtain the 3D microstructure as shown in [Fig. 5].

[0096] In a manner known per se, the rear substrate 11 of the upper plate 1 is ultimately thinned, for example, by a process carried out from the upper face of the 3D microstructure shown in [Fig. 4B]. For example, the thinning is first initiated mechanically, for example by polishing (grinding), and then continued chemically. This allows for rapid initial mechanical thinning followed by less mechanically stressful chemical thinning, which reduces the risk of damage to the bonding interface 40. In some implementations, the chemical etching can be wet etching, performed by immersing the microstructure in a solution, for example, an acid. For etching silicon (Si), a commonly used solution is a solution of hydrofluoric acid (HF) mixed with nitric acid (HNO3).This solution is indeed capable of interacting with the layer. of silicon dioxide which forms naturally on the surface of the back substrate of the top wafer. Alternatively, chemical etching can be performed by a plasma generated from a highly reactive gas, for example a fluorine derivative such as sulfur hexafluoride (SF6).

[0097] What is specific here, however, is that the etching carried out in this step 10 is stopped at a determined depth in the thickness of the back substrate 11 of the wafer 1. This result can be obtained by implementing a selective etching with a stop element positioned at the desired depth. Such a stop element makes it possible to stop the etching at a depth equal to or slightly below the upper end of the metal pillar formed in the hole 120, i.e., from the bottom (being on the upper side due to the flipping of the wafer 1 carried out in step 8) of the hole 120 for the TSV which was filled with copper (Cu) in step 5, whereby the metal pillar 120 becomes functionally a TSV, in that it now passes through the thinned substrate 11 of the upper wafer 1. This stop element can advantageously be the same as that already used in step 3 to stop the etching carried out to create the blind hole 120.It should be noted that such a stopping element can be a stopping layer, such as a buried oxide layer ("Box"). Choosing such an etch with a stopping layer is particularly advantageous when the substrate 11 is a substrate-on-insulator (SOI). This solution offers the advantage of simplicity in implementation. However, such selective etching with a stopping element is not the only option. The same result can be obtained generically by thinning (mechanical, for example) with the stopping point controlled by the processing conditions and / or the processing time (time-controlled etching stopping). This alternative is particularly advantageous when the substrate is a pure silicon (Si) substrate.

[0098] Advantageously, the aforementioned identical stopping elements used for etching in step 3 and for etching in step 10 ensure that the latter etching can be stopped as soon as the metal pillar 120 is exposed, that is, when its upper horizontal face, corresponding to the bottom of the blind hole 120, is exposed on the upper face 10' of the thinned rear substrate 11 of the upper wafer 1. This reduces the risk of "under-etching," which would result in the metal not being exposed at the hole 120 and thus prevent the completion of the TSV, i.e., render it ineffective. It also limits "over-etching," which often leads to oversizing the thickness of the rear substrate 11 of the upper wafer 1.

[0099] More generally, the final thickness of the rear substrate 11 of the upper plate 1 in the 3D microstructure is well controlled, and this without the need to provide additional specific stopping means.

[0100] Next, with the group of steps represented by block 86 on the diagram in [Fig.8], a passivation of the upper surface of the 3D microstructure is carried out (that is to say, also, of the rear face of the substrate of the substrate 11 of the upper plate 1).

[0101] To this end, in step 11, a conformal deposition of a passivation layer 60 can be carried out on the upper surface of the 3D microstructure. The passivation layer is, for example, made of silicon dioxide (SiO2) and / or silicon nitride (SiN). This deposition can, for example, be carried out by PECVD. Its typical thickness can be between approximately 50 nm and approximately 2 pm. It should be noted that, in the specific case of using a substrate 11 of the SOI type, it is possible to use the buried oxide layer (BOX) as the passivation layer, so that the deposition of a passivation layer is not necessary. In other words, step 11 is not essential in this case.

[0102] In step 12, a photoresin etching mask is produced using a conventional photolithography process. The typical dimensions of the etching pattern (length and width) in the horizontal XY plane are between approximately 1 µm and approximately 100 µm. More specifically, this etching mask may include an opening aligned in the XY plane (i.e., along both the X and Y directions) with the TSV 120. Its opening may have substantially the same dimensions along the X and Y directions as the dimensions of the TSV 120's cross-section in the horizontal XY plane.

[0103] The passivation layer 60 is then selectively etched, in step 13, through the aforementioned photoresin etching mask, in order to reveal the bottom of the pillar 120 again as shown in [Fig. 6]. This can be achieved, for example, by performing an etch through the photoresin etching mask made in step 12, to which said etch is selective.

[0104] This etching can be chemical etching (or wet etching) using a hydrofluoric acid (HF) solution. Alternatively, it can be physical etching (or dry etching), i.e., plasma etching. However, the etching is preferably reactive ion etching (RIE), which is a variation of plasma etching combining the selectivity of chemical etching and the anisotropy of physical etching. In these cases, the group of steps 86 ends in step 14 with the removal ("stripping") of the photoresin mask. This can be carried out by chemical etching, for example with stripping solutions and / or solvents such as NMP (1-Methyl-2-Pyrrolidone).

[0105] The next group of steps, represented by block 87 in the diagram in [Fig. 8], consists of producing the brazable alloy bumps 80 (“bumps”, also called brazing beads), of the 3D microstructure. These bumps are intended for assembly with the less another microstructure with in the integrated circuit, or with electrical connection elements with the outside of said integrated circuit.

[0106] In a step 15, a selective adhesion sublayer 70 is deposited, in preparation for the deposition of metal (alloy) to form the brazing bead 80 shown. This could be, for example, a titanium (Ti) layer deposited by PVD. The passivation sublayer may optionally be supplemented by an electrically conductive sublayer, for example, a copper (Cu) layer deposited, for example, by PVD. The total thickness of these sublayers can be between approximately 50 nm and approximately 2 pm, for example.

[0107] In step 16, a new photoresin mask is then formed, for example by conventional photolithography. This mask may have an opening aligned in the XY plane (i.e., both along the X and Y directions) with the TSV 120. Its opening may be slightly longer along the X direction (as shown in [Fig. 7]) and wider along the Y direction than the corresponding dimensions of the TSV 120 cross-section in the horizontal XY plane, when the dimensions of a mounting pad to be formed are larger than said cross-section, as in the example shown. The thickness of the resin may be between approximately 1 µm and approximately 100 µm, for example.

[0108] Then, in step 17, the pads (“bumps”) or solder balls like the ball 80 shown are formed by depositing metal, for example a solderable alloy such as a tin / silver / copper alloy (SnAgCu), through the openings of the photoresin mask made in step 16. This deposit can be obtained, for example, by electrolytic deposition (or ECD, from the English “ (“Electro Chemical Deposition”) steps.

[0109] . In the application concerned here, namely the formation of the alloy "bumps" 80 SnAgCu, a layer of this alloy can be deposited on top of a stack consisting of a Cu layer (a few hundred nanometers to a few micrometers or microns thick) on which a Nickel (Ni) layer is deposited. All these layers can be deposited by ECD.

[0110] In embodiments, the thickness of the brazing beads 80 can be between approximately 200 nm and approximately 40 pm

[0111] Finally, in step 18, the photoresist mask prepared in step 16 and used in deposition steps 16 and 17 is stripped. This stripping can be carried out by chemical etching, for example with an NMP solution. A step is then performed to remove the titanium (Ti) adhesion sublayer and the copper (Cu) electrical conduction sublayer, for example by chemical etching.

[0112] In summary, the method offers an alternative to producing a TSV after the vertical assembly of the two plates. This known form of producing a TSV is replaced, according to embodiments of the invention, by the Initially, prior to bonding, a blind via hole is formed which penetrates the substrate 11 of the upper wafer 1 without passing through it, to a depth determined either by a stop element 121 or by the etching time, and which is filled with metal. After the upper wafer 1 is vertically rotated and bonded, its rear substrate 11 is thinned until the rear of the metal column 120 is exposed in the via hole, thus making the via pass-through in accordance with its function. As indicated in the introduction, the process is essentially implemented during the BEOL phase of manufacturing each wafer individually, which are then vertically joined to one another by hybrid bonding.More specifically, it is the formation of the metallic pillar 120 in the blind hole, intended to become a TSV (Tension-Specific Vessel), with the thinning of the back substrate of the upper wafer 1, that is carried out during the BEOL phase before bonding; its completion by said thinning is only achieved after bonding. Furthermore, the re-establishment of connections with the Ml-Mn interconnect structure of the lower wafer 2 is anticipated during the fabrication of the HBV and HBM metallization levels planned in each wafer above their respective Ml-Mn interconnect structure, for the bonding between the upper wafer 1 and the lower wafer 2 by hybrid bonding of said wafers.

[0113] Specific embodiments have just been described. Various variations and modifications will be apparent to those skilled in the art. In particular, there is no requirement that the horizontal cross-sectional dimensions of the metal pillar 120 and subsequently of the TSV (Technical Support Unit) made operational from said pillar 120 be constant over the entire height of said metal pillar or said TSV, respectively. In particular, these elements can be made in the form of several substantially vertical extension sections having more or less significant aspect ratios, which are stacked vertically during respective metal deposition stages, with thermal and / or electrical continuity between them, but each having different horizontal cross-sectional dimensions.

[0114] In addition, a person skilled in the art will appreciate that one or more metal or TSV pillars made in accordance with implementation methods may have, in an integrated circuit comprising a 3D microstructure made as described above, different respective functions within the same 3D microelectronic device, or within several 3D microelectronic devices included in the same integrated circuit: electrical connection for resuming buried connections, thermal conduction pillar for heat dissipation, alignment marker, or other.

[0115] Finally, the formation of the 80 connection pads by annealing on the TSVs is not mandatory. Depending on the applications and the functions assigned to the TSVs thus produced, it can be omitted for all or part of said TSVs.

Claims

Demands

1. A method for producing a three-dimensional, 3D microelectronic structure, comprising the hybrid bonding of an upper wafer (1) onto a lower wafer (2) after vertically flipping of said upper wafer (1), said lower wafer (1) and said upper wafer (2) each comprising a substantially planar silicon substrate and an interconnection structure formed above said silicon substrate, characterized in that it comprises, prior to the hybrid bonding: • the formation, in the thickness of the silicon substrate of the upper wafer, of a non-through hole (120) having a high aspect ratio, i.e. having a depth substantially greater than its surface, for example 10 to 100 times greater, in a position laterally distant from any active component in an active zone of the substrate located in the upper part of said substrate, said formation being stopped at a height (h) determined with respect to the rear face (10) of the substrate (11), • filling the blind hole with metal to form a metallic pillar (120) for the purpose of achieving a metallic interconnection between the upper and lower plates after hybrid bonding, and in that it further comprises, after turning over and gluing the upper plate (1) onto the lower plate (2), a thinning of the rear substrate of the upper plate (1) to expose the metal at the bottom of the non-through hole made before the hybrid gluing, whereby the metal pillar is made to open through the rear face (10) of the thinned substrate (11) of the upper plate (1).

2. A method according to claim 1, further comprising, after the formation of the metal pillar but before the vertical inversion and bonding of the upper plate (1) to the lower plate, the creation of a bonding connection structure (HBV, HBM) above the interconnection structure of said upper plate (1), said bonding connection structure (HBV, HBM) being adapted to ensure the resumption of electrical connections between structures of respective interconnection (Ml-Mn) of the upper plate (1) and of the lower plate (2), and comprising metallizations (21) in continuity with the metallic pillar (120).

3. Method according to claim 2, wherein the realization of the bonding link structure (HBV,HBM) comprises the realization of a horizontal metallization level (HBM) preceded by the realization of a vertical metallization level (HBV) between said horizontal metallization level (HBM) and the interconnection structure (Ml-Mn) of the upper plate (1).

4. A method of any one of claims 1 to 3, wherein the formation of the non-through hole (120) is stopped upon detection of a determined stopping element present at the desired level for the bottom of said non-through hole (120).

5. A method according to claim 4, wherein the stopping element is a buried oxide layer.

6. A method according to any one of claims 4 and 5, wherein the thinning of the rear substrate (11) of the upper wafer is stopped on detection of the same stopping element as the stopping element for the formation of the non-through hole (120).

7. A method according to any one of claims 1 to 6, further comprising, after thinning the back substrate (11) of the top wafer (1) the formation of a brazable alloy ball (80), in metal, above and in electrical and thermal continuity with the metal pillar (120), for the electrical connection of the 3D microelectronic structure.

8. A method according to any one of claims 1 to 7, wherein active components made in the active area of ​​the substrate of the lower wafer comprise LEDs.

9. Three-dimensional, 3D microelectronic structure for an integrated semiconductor product, said 3D microelectronic structure comprising a metallic pillar or a through-via (120) and being realized by implementing the method according to any one of claims 1 to 8.

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