Electronic chip assembly comprising adhesive pads directly connected to conductive tracks

Abstract

One aspect of the invention relates to an assembly (100) of electronic chips comprising: a first chip (10) and a second chip (20) superimposed and electrically and mechanically connected to each other, the first chip (10) comprising a first interconnection structure (12) and the second chip (20) comprising a second interconnection structure (22), the first interconnection structure (12) and the second interconnection structure (22) each comprising superimposed interconnection levels (221); first adhesive pads (31) disposed on the first interconnection structure (12); and second adhesive pads (32) disposed on the second interconnection structure (22), the second adhesive pads (32) being glued to the first adhesive pads (31); assembly in which: the last interconnection level of the first chip comprises first conductive tracks (1211);at least some of the first adhesive pads (31) are directly connected to the first conductive tracks (1211); and a gap (G) free of solid material separates the last interconnection level of the first chip (10) from the second chip (20) and extends between at least some of the first conductive tracks (1211). Figure to be published with the abbreviation: Figure 1;

Description

Title of the invention: Electronic chip assembly comprising adhesive pads directly connected to conductive tracks TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of three-dimensional assemblies of electronic chips. More particularly, the invention relates to an assembly comprising two electronic chips and adhesive pads for electrically connecting the two chips. The assembly is designed to reduce heat transfer between the two chips, crosstalk, and electrical losses. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] Three-dimensional (3D) integration consists of stacking several electronic chips (also called integrated circuits) and electrically connecting them, for example, using a bonding technique. This approach makes it possible, in particular, to reduce the size of so-called "heterogeneous" systems, which are composed of circuits belonging to different generations of the same semiconductor device technology or of circuits belonging to different technologies, for example, an image sensor comprising a photodiode array and a CMOS image processing circuit comprising logic circuits. 3D integration also makes it possible to increase the transistor density per unit area without reducing their size, to decrease power consumption, and / or to increase the operating speed of a system by replacing long horizontal interconnections with short vertical interconnections.

[0003] Several 3D stacking architectures can be distinguished, depending in particular on how the chips are stacked, the orientation of the chips and the type of bonding.

[0004] Stacking can be carried out using different approaches: wafer-to-wafer, die-to-wafer, or die-to-die. The wafer-to-wafer stacking technique is the fastest in terms of the number of chips bonded per hour, as it involves collective bonding at the scale of the silicon wafers. It is also the most precise for a given bonding speed. However, unlike the other two techniques, it does not offer the possibility of assembling only the functional chips (known as "Known Good Dies"), selected after a series of tests and wafer cutting. The die-to-die stacking technique is naturally the most time-consuming to implement, as the chips are bonded together in pairs after the wafers have been cut.

[0005] When the chips (or plates) are oriented in the same direction, the front face of one chip is bonded to the back face of another chip (this assembly method is called "face-to-back"). Conversely, when the chips (or plates) are assembled after one of them has been turned over, the chips are bonded face-to-face or back-to-back.

[0006] The article [“Hybrid bonding for 3D stacked image sensors: impact of pitch shrinkage on interconnect robustness”; J. Jourdon et al., 2018 IEEE International Electron Devices Meeting (IEDM), pp. 7.3.1-7.1.4, 2018] describes an example of a 3D stack comprising two electronic chips assembled face-to-face by hybrid bonding (Cu / SiO2). The upper chip is a back-illuminated image sensor (BSI), and the lower chip is an image processing logic circuit manufactured using CMOS technology. The two chips are joined by copper interconnect pads surrounded by silicon dioxide. The interconnect pads (also called “HBM pads” for “Hybrid Bonding Metal pads”) have a repetition pitch ranging from 1.44 pm to 8.8 pm.

[0007] In certain applications, the aim is to minimize heat transfer between the electronic chips in the stack. Typically, when a first chip is intended to operate at very low temperatures, it is necessary to limit as much as possible the heat transfer between this first chip and a second chip that dissipates heat or is subjected to a different temperature, without compromising electrical conductivity between the two chips.

[0008] Quantum computing chips designed to operate at temperatures close to absolute zero (typically below 1.5 K) and to contain quantum bits, commonly called qubits, whose state is highly temperature-sensitive, may be cited as an example. Such a quantum chip is generally disposed in a dilution cryostat and can be electrically coupled to a read / control circuit using CMOS technology, also disposed within the cryostat. This read / control circuit, commonly called "cryo-CMOS," is designed to generate minimal heat, but must nevertheless be thermally decoupled from the quantum chip to avoid impairing its operation.

[0009] Electronic chip assemblies obtained by hybrid metal / dielectric bonding (such as Cu / SiO2) are not the most suitable for these very low-temperature applications, because the dielectric material is responsible for thermal leakage between the chips. Furthermore, the dielectric material is responsible for electrical losses that can be significant depending on the dielectric permittivity of the material (that of SiO2, for example, is relatively low).

[0010] One solution for enabling excellent electrical conduction while limiting thermal conduction between two chips is to use one or more superconducting materials to create the interconnection between the two chips. Indeed, there are two main mechanisms for heat conduction at low temperatures. On the one hand, heat is transferred by free electrons from one material to the other. This phenomenon therefore only occurs in electrically conductive materials. On the other hand, heat is also transferred by the vibrations of the atomic lattice, in other words, the phonons, of the material(s) constituting the interconnection. In a superconducting material cooled below its critical temperature Tc (i.e., the superconductor-to-conductor phase transition temperature), in other words, in the superconducting state, the free electrons condense into Cooper pairs.These Cooper pairs have the unique property of not conducting heat. Using one or more superconducting materials to create the interconnect therefore reduces thermal conduction by free electrons. However, when the interconnect temperature approaches the critical temperature Tc, residual electrons that have not formed Cooper pairs continue to conduct heat.

[0011] For a given superconducting material, the lower the temperature, the more electrons organize themselves into Cooper pairs in the material, and therefore the less efficient the thermal conduction by the remaining free electrons. To significantly reduce thermal conduction by free electrons, it is generally estimated that a temperature T lower than Tc / 10 must be reached.

[0012] By way of example, the article [“Nb-Nb direct bonding at room temperature for superconducting interconnects”, M. Fujino et al., Journal of Applied Physics 133, 015301, 2023] describes the assembly of two silicon substrates by direct bonding of niobium superconducting interconnect pads. The superconducting interconnect pads, formed on the surface of each of the substrates, have a diameter of 200 pm and a repeating pitch of 650 pm.

[0013] The use of superconducting interconnect pads is a solution for reducing thermal conduction in a chip assembly operating at very low temperatures, but it provides no improvement in chip assemblies operating at room temperature. Furthermore, it has no effect on electrical losses or crosstalk, which are two important parameters, particularly for RF applications. Summary of the invention

[0014] There is a need to limit thermal conduction, electrical losses and crosstalk in an electronic chip assembly, regardless of the operating temperature of the assembly.

[0015] According to a first aspect of the invention, this need is met by providing an assembly of electronic chips comprising: • a first chip and a second chip superimposed and electrically and mechanically connected to each other, the first chip comprising: • a first substrate; • a first interconnection structure arranged on the first substrate and comprising a plurality of superimposed interconnection levels; the second chip comprising: • a second substrate; • a second interconnection structure arranged on the second substrate and comprising a plurality of superimposed interconnection levels; • a plurality of first bonding pads arranged on the first interconnection structure; and • a plurality of second bonding pads arranged on the second interconnection structure, the second bonding pads being bonded to the first bonding pads.

[0016] Furthermore, in this assembly, • the interconnection level of the first chip furthest from the first substrate, called the last interconnection level of the first chip, includes first conductive tracks that extend parallel to a plane of the first substrate; • at least some of the first adhesive pads are connected directly to the first conductive tracks; and • A gap of solid material separates the last interconnection level of the first chip from the second chip and extends between at least part of the first conductive tracks.

[0017] The absence of solid material, and more specifically dielectric material, reduces thermal conduction between the chips, crosstalk, and dielectric losses. The direct connection between the first adhesive pads and the first conductive tracks simplifies assembly fabrication and reduces the electrical resistance of the interconnections between the two chips, compared to a connection using conductors. Joule heating losses in the assembly are therefore reduced.

[0018] Preferably, the first conductive tracks of said at least a part have exposed side walls, at least over part of their height.

[0019] In a preferred embodiment of the assembly: • the interconnection level of the second chip furthest from the second substrate, called the last interconnection level of the second chip, includes second conductive tracks that extend parallel to a plane of the second substrate; • at least some of the second bonding pads are directly connected to the second conductive tracks; and • the empty space of solid material also extends between at least part of the second conductive tracks.

[0020] According to a development of this preferred embodiment, the second conductive tracks of said at least a part have exposed side walls, at least over a part of their height.

[0021] In addition to the characteristics mentioned in the preceding paragraph, the assembly of electronic chips according to the first aspect of the invention may have one or more additional characteristics from among the following, considered individually or in all technically possible combinations: • the first gluing pads present in a first direction a first step of repetition and the second gluing pads present in the first direction a second step of repetition equal to the first step of repetition; • the first repetition step is less than or equal to 10 pm, preferably between 1 pm and 7 pm; • the first gluing pads have a third repetition step in a second direction intersecting the first direction and the second gluing pads have in the second direction a fourth repetition step equal to the third repetition step; • the third repetition step is less than or equal to 10 pm, preferably between 1 pm and 7 pm; • the third repetition step is equal to the first repetition step; • the first and second adhesive pads are superconductors; • the first chip is a quantum circuit and the second chip is a circuit for reading and controlling the quantum circuit; • The first chip is an infrared bolometric sensor, and the second chip is a multiplexing circuit or a readout circuit for the infrared bolometric sensor; and • The first chip and the second chip are radio frequency circuits.

[0022] A second aspect of the invention relates to a method for manufacturing an assembly of electronic chips comprising a first chip and a second chip superimposed and electrically and mechanically connected to each other, the first chip comprising • a first substrate; • a first interconnection structure arranged on the first substrate and comprising a plurality of superimposed interconnection levels; the second chip comprising: • a second substrate; • a second interconnection structure arranged on the second substrate and comprising a plurality of superimposed interconnection levels;

[0023] The process comprises the following steps: • form a plurality of first bonding pads on the first interconnect structure, the interconnect level of the first chip furthest from the first substrate, called the last interconnect level of the first chip, comprising first conductive tracks extending parallel to a plane of the first substrate and a first dielectric layer encapsulating the first conductive tracks, at least some of the first bonding pads being directly connected to the first conductive tracks; • etch the first dielectric layer between at least part of the first conductive tracks; • form a plurality of second bonding pads on the second interconnection structure; • assemble the first chip and the second chip by gluing the first gluing pads to the second gluing pads, so that a gap of solid material separates the last level of interconnection of the first chip from the second chip and extends between said at least a part of the first conductive tracks.

[0024] Preferably, the first bonding pads are bonded to the second bonding pads by a direct bonding technique, advantageously by hydrophilic direct bonding.

[0025] In a preferred embodiment, the formation of the first bonding pads comprises the following sub-steps: • form a conductive layer on the last interconnection level of the first chip; • polish the conductive layer to obtain a surface roughness of less than 0.5 nm; • form an etching mask on the conductive layer; • etch the conductive layer through the etching mask; and • Remove the engraving mask.

[0026] According to a first development of this preferred embodiment, the first dielectric layer is etched before the removal of the etching mask.

[0027] According to a second development compatible with the first, the formation of the first bonding pads further comprises: • before the formation of the conductive layer, the deposition of a barrier layer on the last interconnection level of the first chip; and • after etching the conductive layer, etching the barrier layer.

[0028] According to a third development compatible with the first and second developments, the process further comprises the following steps: • between polishing the conductive layer and forming the etching mask, a protective layer is deposited on the conductive layer; • before etching the conductive layer, the protective layer is etched through the etching mask to expose the conductive layer; and • After removing the etching mask, remove the protective layer. BRIEF DESCRIPTION OF THE FIGURES

[0029] Other features and advantages of the invention will become clear from the description given below, by way of example and not limitation, with reference to the accompanying figures, among which: • [Fig.1] represents in cross-section a preferred embodiment of a chip assembly according to the first aspect of the invention; • [Fig.2] shows a top view of the gluing pads of one of the chips in the assembly of [Fig.1]; • Figures 3A-3E, 4A-4E and 5 represent steps in a manufacturing process for assembling electronic chips according to the second aspect of the invention.

[0030] For clarity, identical or similar elements are identified by identical reference signs throughout the figures. DETAILED DESCRIPTION

[0031] Figure 1 is a partial, schematic cross-sectional view of an assembly of electronic chips 100 according to a preferred embodiment of the invention. The assembly of electronic chips 100, hereinafter referred to simply as "assembly 100", comprises at least two electronic chips: a first chip 10 and a second chip 20. "Electronic chip" means an electronic component. Based on a semiconductor material, performing one or more electronic functions and integrating several electronic components in a small volume. The term "integrated circuit" will be considered a synonym for electronic chip.

[0032] The first chip 10 and the second chip 20 are stacked, that is, arranged one on top of the other. Thus, the assembly 100 can also be referred to as a "chip stack". In the orientation of [Fig. 2], the first chip 10, referred to as the upper chip, is arranged above the second chip 20, referred to as the lower chip. Furthermore, the first chip 10 and the second chip 20 are electrically and mechanically connected to each other.

[0033] The assembly 100 can be designed to operate at very low temperatures, i.e., at a temperature less than or equal to 1.5 K, typically less than or equal to 100 mK. It is designed to limit heat transfer between the chips 10 and 20 in order to prevent, for example, heat emitted by one of the chips from propagating to the other chip and preventing its operation (at very low temperatures) or impairing its performance. The assembly 100 finds particularly advantageous applications in the fields of quantum computing, superconducting electronics, and space applications.

[0034] By way of example, the first chip 10 is a quantum circuit, that is to say, a circuit designed to contain quantum bits or qubits, and the second chip is a circuit for reading and controlling the quantum circuit, for example using CMOS technology. To be brought to very low temperatures, the assembly 100 can be placed in a dilution cryostat.

[0035] According to another example, the first chip 10 is an infrared bolometric sensor (for example for space observation) and the second chip 20 is an infrared bolometric sensor readout circuit or a multiplexing circuit.

[0036] Alternatively, assembly 100 can be designed to operate at higher temperatures, for example at room temperature, for applications where thermal conduction between chips is less problematic. It finds particularly advantageous applications in the field of radio frequencies (RF). Indeed, it is also designed to limit electrical losses, more specifically Joule heating losses and dielectric losses, as well as crosstalk between chips and within the same chip.

[0037] Thus, the first chip 10 and the second chip 20 can be RF circuits, that is to say circuits operating with signals whose frequency is between 3 kHz and 300 GHz.

[0038] The first chip 10 comprises a first substrate 11 and a first interconnection structure 12 disposed on the first substrate 11. The first substrate 11 It comprises an active layer made of a semiconductor material, such as silicon. It contains electronic components or devices (not shown), such as transistors, photodiodes, memory cells, quantum devices, bolometers, etc. These electronic devices are formed, at least in part, within the semiconductor active layer. The first substrate 11 extends along an XY plane.

[0039] The first interconnection structure 12 comprises several superimposed interconnection levels 121, also called routing levels. The interconnection levels 121 are superimposed along a Z direction perpendicular to the XY plane of the substrate. The interconnection levels 121 can electrically connect the electronic devices of the first chip 10 to each other.

[0040] For the sake of clarity, only one interconnection level 121, the furthest from the first substrate 11, is shown in [Fig. 1]. This interconnection level 121 is called "level N", N being the total number of interconnection levels 121 in the first interconnection structure 12 (N > 2), or "last interconnection level" (their numbering, from 1 to N, being commonly carried out starting from the substrate).

[0041] Similarly, the second chip 20 comprises a second substrate 21 and a second interconnection structure 22 disposed on the second substrate 21. The second substrate 21 contains electronic devices (transistors, photodiodes, memory cells, quantum devices, etc.), formed at least in part in a semiconductor active layer (the semiconductor material may be different from that of the first substrate). The second substrate 21 extends along a plane parallel to the XY plane of the first substrate 11.

[0042] Similar to the first interconnection structure 12, the second interconnection structure 22 comprises several superimposed interconnection levels 221 (in the Z direction). The interconnection levels 221 can electrically connect the electronic devices of the second chip 20 to each other. Again, only the last interconnection level 221 of the second interconnection structure 22, the one furthest from the second substrate 21, is shown in [Fig. 1].

[0043] An interconnection level 121, 221 can be a so-called "line" level (generally designated as "M1", "M2", "M3"...) or a so-called "via" level ("V1", "V2", "V3"...). A line level comprises a plurality of conductive lines or tracks extending parallel to the XY plane of the first substrate 11, while a via level comprises conductive vias extending perpendicular to the XY plane of the first substrate 11, i.e., along the Z direction. Conductive vias have a cross-section, in a plane parallel to the XY plane, smaller than that of conductive tracks. Conductive tracks and conductive vias are typically formed of one or more stacked metals. Two consecutive line levels are advantageously separated and electrically connected by a via level. A conductive via (in a via level) therefore connects two conductive tracks belonging to different levels.

[0044] In addition to the conductive tracks and conductive vias, an interconnection level 121, 221 may include a dielectric layer encapsulating the conductive tracks or vias, as well as one or more interface layers such as a metal diffusion barrier layer, a hard mask layer, or a polishing stop layer. Interconnection levels 121, 221 are obtained, for example, by the process known as "Damascene".

[0045] The electronic devices of the same chip belong to a first functional block (or set of technology levels) called "Front End Of Line" or FEOL, while the interconnection levels 121, 221 of the same chip belong to a second functional block called "Back End Of Line" or BEOL.

[0046] In addition to the first and second chips 10, 20, the assembly 100 includes first adhesive pads 31 arranged on the first interconnection structure 12 and second adhesive pads 32 arranged on the second interconnection structure 22. The first adhesive pads 31 belong to a first level of adhesive superimposed on the last interconnection level 121 of the first interconnection structure 12, while the second adhesive pads 32 belong to a second level of adhesive superimposed on the last interconnection level 221 of the second interconnection structure 22.

[0047] The first adhesive pads 31 (hereinafter referred to as "first pads 31") and the second adhesive pads 32 (hereinafter referred to as "second pads 32") can also be called "first interconnect pads" and "second interconnect pads" respectively, insofar as they electrically and mechanically interconnect the two chips.

[0048] The first pads 31 may have identical shape and dimensions (within manufacturing tolerances). The second pads 32 may also have identical shape and dimensions. The shape and dimensions of the second pads 32 may differ from those of the first pads 31.

[0049] In a plane parallel to the XY plane of the first substrate 11, the first and second pads 31-32 can have a rectangular (for example square), round, hexagonal... cross-section. Their dimensions in this same plane can be between 100 nm and 1 mm, preferably between 100 nm and 7 pm, and even more preferably between 1 pm and 5 pm.

[0050] Each of the first pads 31 is glued to a second pad 32, and conversely, each of the second pads 32 is glued to a first pad 31. In other words, the first and The second pads 31-32 are connected in pairs. The first and second pads 31-32 provide the electrical and mechanical connection between the two chips.

[0051] Advantageously, the chips 10 and 20 are interconnected by means of the first and second pads 31-32 using a direct bonding technique, that is, without introducing an intermediate compound (such as an adhesive, wax, or low-melting-point alloy) at the bonding interface, and preferably by hydrophilic direct bonding. Thus, the interconnections between the chips 10 and 20 are free of any intermediate compound, and in particular, of solder material. Each interconnection preferably consists of a first pad 31 and a second pad 32.

[0052] The first pads 31 are electrically connected to the first interconnection structure 12. They are thus electrically connected to the electronic devices of the first chip 10.

[0053] More specifically, the last interconnection level 121 of the first chip 10 comprises first conductive tracks 1211, and at least some of the first pads 31 are directly connected to the first conductive tracks 1211. By "directly connected," it is meant that the first pads 31 are in direct contact with the first conductive tracks 1211, and not connected via a conductor as is the case in conventional chip assemblies. A first conductive track 1211 can be connected to one or more first pads 31 (which are thus electrically connected by the first track).

[0054] Preferably, each of the first pads 31 is connected directly to a first conductive track 1211.

[0055] The fact that the assembly 100 is devoid of conductive vias between the first pads 31 and the last interconnection level 121 of the first chip 10 (in other words, that the first bonding level is devoid of conductive vias) simplifies the fabrication of the assembly 100, since the manufacturing process then does not include the steps relating to the formation of these vias. Furthermore, the electrical resistance between the two chips of the assembly is reduced. Indeed, conductive vias have a higher electrical resistance than conductive tracks due to their smaller cross-section and the fact that they generally include a metallic diffusion barrier layer.

[0056] Furthermore, in the assembly 100, a space G separates the last interconnection level 121 of the first chip 10 and the last interconnection level 221 of the second chip 20. This space G also separates the pairs of first and second pads 31-32 from each other. This space G is free of solid material, and in particular of dielectric material. It may contain a gas or a mixture of gases, for example, air.

[0057] The space G constitutes an inter-chip cavity in which the first pads 31 and the second pads 32 extend. This inter-chip cavity is preferably open to the external environment. Thus, when using the assembly 100, for example in a dilution cryostat, the pressure of the gas or gas mixture in the space G can be reduced until a given vacuum level is obtained.

[0058] The material-free G-space improves thermal insulation between the chips 10 and 20 (by limiting the thermal transport of phonons between the chips), compared to two chips separated by an underfill material or an oxide (as in the case of hybrid Cu / SiO2 bonding, for example). Furthermore, the G-space limits crosstalk between RF signals propagating in the two chips. "RF signals" refers to signals with frequencies between 3 kHz and 300 GHz. Since the G-space also separates the first pads 31 from each other and the second pads 32 from each other, it also limits crosstalk between RF signals propagating in different interconnections. Finally, due to the absence of dielectric material between the bonding pads, dielectric losses are also reduced.

[0059] The distance d separating the last interconnection level 121 of the first chip 10 and the last interconnection level 221 of the second chip 20 is advantageously between 100 nm and 2 pm. It is measured perpendicular to the XY plane of the first substrate 11 (along Z).

[0060] Another feature of the assembly 100 is that the solid-free space G further extends between at least part of the first conductive tracks 1211 of the last interconnection level 121 of the first chip 10, and preferably between each pair of first conductive tracks 1211. This helps to further reduce crosstalk and dielectric losses.

[0061] Advantageously, the first conductive tracks 1211 of said at least a portion have exposed side walls, at least over a part of their height (measured along Z) and preferably over their entire height. The height of the first conductive tracks 1211 is, for example, between 10 nm and 2 pm.

[0062] Preferably, the space G surrounds the first pads 31, the second pads 32 and the first conductive tracks 1211.

[0063] In the preferred embodiment of the assembly 100 represented by [Fig. 1], what has just been described for the first chip 10 applies mutatis mutandis to the second chip 20. Thus, the last interconnection level 221 of the second chip 20 comprises second conductive tracks 2211 and at least some of the second pads 32 are directly connected to the second conductive tracks 2211. Preferably, each second pad 32 is directly connected to a second conductive track 2211.

[0064] Furthermore, the space G extends between at least a portion of the second conductive tracks 2211, and preferably between all the second conductive tracks 2211. Advantageously, the second conductive tracks 2211 of said at least a portion have exposed side walls, at least over a portion of their height and preferably over their entire height. The height of the second conductive tracks 2211 is, for example, between 10 nm and 2 pm.

[0065] The manufacturing time of assembly 100, electrical resistance (absence of via conductors between the second pads 32 and the second conductive tracks 2211), crosstalk and dielectric losses (absence of dielectric material between the second conductive tracks 2211) are further reduced.

[0066] The first pads 31 may have, in a first direction X of the XY plane, a first repetition pitch PXi less than or equal to 10 pm, and preferably between 1 pm and 7 pm. The second pads 32 then have, in the same direction X, a second repetition pitch Px2 equal to the first repetition pitch PXi.

[0067] Such repetition pitches ensure excellent mechanical strength between the chips 10 and 20 and allow for a high density of interconnections between the chips, compatible with certain high-integration-density applications. These repetition pitches are particularly compatible with the need for scalability in quantum circuits. Indeed, quantum circuits are designed to contain a very large number of qubits, which must be individually connected to the readout and control circuitry. The required number of interconnections between the chips is therefore very high, especially in quantum circuits with spin qubits in silicon.

[0068] The first and second pads 31-32 are made of one or more electrically conductive materials, preferably selected from titanium (Ti), aluminum (Al), gold (Au), copper (Cu), platinum (Pt), niobium (Nb), niobium-titanium (NbTi), niobium-germanium (Nb3Ge), niobium nitride (NbN), niobium alumina (Nb3Al), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), vanadium (V), and vanadium silicide (V3Si). The first pads 31 and / or the second pads 31-32 may be formed from an alloy of at least two of these materials. They may also comprise several stacked conductive layers formed from different materials.

[0069] The use of one or more superconducting materials to form the pads 31-32 reduces thermal conduction by electrons between the chips 10 and 20 during very low-temperature operation. Fully superconducting interconnections are also particularly advantageous when the first chip 10 is a quantum circuit with superconducting qubits, because they allow the phase and amplitude properties of the signal to be preserved when passing from one chip to another.

[0070] The first pads 31 may be made of a single superconducting material (preferably chosen from the aforementioned materials and their alloys). Similarly, the second pads 32 may be made of a single superconducting material, preferably identical to that of the first pads 31. The first and second pads 31-32 are, for example, made of niobium.

[0071] Alternatively, the first pads 31 and / or the second pads 32 each comprise a stack of a first superconducting layer and a second superconducting layer. The first superconducting layer is formed of a first superconducting material, for example TiN, and the second superconducting layer is formed of a second superconducting material different from the first superconducting material, for example niobium. The first superconducting layer is the one in contact with the chip 10, 20. Thus, when the first and second pads 31-32 all comprise stacks, the bonding occurs between the second superconducting layers.

[0072] The first and second superconducting materials can be chosen to form an acoustic mismatch interface (also called a Kapitza interface). Such an interface reflects some of the phonons and thus reduces the thermal conductivity of the interconnections through the phonons. Indeed, an interface thermal resistance is created at the interface between the first and second superconducting layers. This interface thermal resistance is greater when the difference in the speed of sound between the two superconducting materials is significant. This speed difference induces very efficient reflection of phonons at the interface, which is why the term "phonon mirror" is also used.

[0073] Examples of superconducting material pairs for creating an acoustic mismatch interface are described in patent applications FR3125359A1 and FR2984602A1.

[0074] According to another alternative, the first pads 31 and the second pads 32 each comprise a stack of several alternating first and second superconducting layers, in order to form a multitude of acoustic mismatch interfaces (preferably more than 10 interfaces) and thus drastically reduce thermal conduction by phonons between the two chips. The greater the number of interfaces, the more effective the phonon mirror.

[0075] Figure 2 shows an example of the layout of the first pads 31 on the first interconnect structure 12 of the first chip 10 or of the second pads 32 on the second interconnection structure 22 of the second chip 20. The first and second pads 31-32 here have a square section.

[0076] As shown, the first plots 31 may have a third repetition step PY1 in a second direction Y intersecting the first direction X, and the second plots 32 may have a fourth repetition step PY2 in the second direction Y, equal to the third repetition step PY1[. Thus, the first and second plots 31-32 are arranged in a regular lattice, or matrix, comprising rows and columns. The second direction Y is preferably perpendicular to the first direction X. The third repetition step PY1[ is advantageously less than or equal to 10 pm, preferably between 1 pm and 7 pm. It may be equal to the first repetition step PY1. The first or second plots 31, 32 then form a square mesh lattice.

[0077] The first and second pads 31-32 are functional pads in the sense that they are connected to the electronic devices of the chips 10, 20 by the interconnection structures 12, 22. They are advantageously contained in a so-called active area of ​​the surface of the chips 10, 20.

[0078] In addition to these functional pads, the assembly 100 may include, on the interconnection structure 12, 22 of each of the chips 10, 20, other pads, in particular non-functional connecting pads 33, also called "dummy" pads. These non-functional pads are exclusively dedicated to the bonding of two chips (see also [Fig. 1]). In other words, they are purely mechanical (and not electrical) connecting pads. They are not connected to any electronic devices of the chips 10, 20, nor even to the interconnection structures 12, 22.

[0079] The non-functional pads 33 are advantageously placed to avoid having large empty areas of pads, typically greater than 100x100 pm2, advantageously greater than 20x20 pm2. They are for example in the form of squares with sides of 2 pm to 100 pm and are spaced two by two with a distance of between 2 pm and 50 pm.

[0080] Finally, the assembly 100 may include, on the interconnection structure 12, 22 of each of the chips 10, 20, one or more test pads 34 allowing verification of the proper functioning of the chips before they are glued (see [Fig. 2]). These test pads 34 participate in the gluing process, just like the first and second pads 31-32 and the non-functional pads 33. These test pads 34 typically have dimensions much larger than those of the functional pads 31-32 and the non-functional pads 33.

[0081] The non-functional pads 33 and the test pads 34 of each chip are advantageously formed from the same material or materials as the first or second pads 31, 32.

[0082] The surface (of bonding) of the connecting pads, of all types combined (first / second pads, non-functional pads and test pads), is preferably greater than 25% of the surface of the first face 10a, 20a, more preferably greater than 40%.

[0083] Figures 3A to 3E, 4A to 4E and 5 schematically represent steps SI to S5 of a manufacturing process for the chip assembly 100.

[0084] The manufacturing process includes in particular a step SI of forming the first pads 31 on the first interconnection structure 12 of the first chip 10 and a step S3 of forming the second pads 32 on the second interconnection structure 22 of the second chip 20.

[0085] According to a preferred embodiment, the SI step of forming the first plots 31 comprises several sub-steps Sl-1 to Sl-4 represented by figures 3 A to 3D.

[0086] The first chip 10 is provided with a final interconnection level 121 comprising a first dielectric layer 1212 which encapsulates the first conductive tracks 1211. The first conductive tracks 1211 are flush with the surface of the first dielectric layer 1212. The final interconnection level 121 may have a thickness (equal to the thickness of the first dielectric layer 1212 and the first conductive tracks 1211) of between 10 nm and 2 pm, preferably between 100 nm and 1 pm. It preferably has a low topography (< 1 pm) and a flatness compatible with direct bonding techniques.

[0087] Substep Sl-1 of [Fig.3A] includes the formation of a conductive layer 51 on the last interconnection level 121 of the first chip 10. The thickness of the conductive layer 51 can be between 100 nm and 10 pm, for example equal to 200 nm or 400 nm.

[0088] The conductive layer 51 may comprise several sublayers formed of different conductive materials, in particular different superconducting materials in order to form one or more acoustic mismatch interfaces, as previously stated.

[0089] Substep Sl-1 may also include the deposition of a barrier layer 52 prior to the formation of the conductive layer 51. The barrier layer 52 enables the conductive layer 51 to adhere more closely to the surface of the first chip 10 and protects the conductive layer 51 from oxidation by forming a barrier to the diffusion of oxidizing species. It is made of an electrically conductive material, advantageously a superconductor, preferably titanium nitride (TiN). Titanium nitride is particularly well suited to a (super)conductive layer 51 comprising niobium (NbNbTi, Nb3Ge, NbN, Nb3Al...). The thickness of the barrier layer 52 may be between 5 nm and 200 nm, for example, 20 nm.

[0090] The conductive layer 51 is in electrical contact with the first conductive tracks 1211 (which open onto the surface of the first chip 10), via the barrier layer 52 where applicable, in order to connect the future first pads 31 directly to the first conductive tracks 1211.

[0091] Substep Sl-2 of [Fig. 3B] consists of polishing the conductive layer 51 to obtain a surface roughness compatible with direct bonding, typically less than 0.5 nm, preferably less than 0.2 nm. These roughness values ​​are expressed as root mean square (Rq). The Rq roughness (denoted Rq) is determined by statistical analysis of an atomic force microscope image, using a 1x1 pm² area as the sample.

[0092] This Sl-2 polishing substep can be accomplished by chemical mechanical polishing (or CMP).

[0093] The polished conductive layer 51 is then structured to form the first pads 31. This structuring is accomplished here in two sub-steps S1-3 and S1-4 illustrated by figures 3C and 3D.

[0094] In S1-3 (see [Fig. 3C]), an etching mask 53 is formed on the conductive layer 51. The etching mask 53 may be a resin mask or a hard mask. Its formation includes, in particular, a photolithography step. The etching mask 53 comprises initial patterns (formed by solid portions of the mask) whose shape and dimensions correspond to those of the first pads 31 to be formed. The etching mask 53 may also comprise other patterns corresponding to the other chip connection pads (non-functional pads 33 and test pads 34).

[0095] Then, during substep Sl-4 (cf. [Fig.3D]), the conductive layer 51, and the barrier layer 52 where applicable, are etched through the etching mask 53, thus obtaining the first pads 31 (and where applicable, the non-functional pads 33 and test pads 34).

[0096] Here, each first plot 31 comprises a portion of the conductive layer 51 and a portion of the barrier layer 52.

[0097] The conductive layer 51 and the barrier layer 52 are preferably etched by reactive-ion etching (or RIE).

[0098] The etching of the barrier layer 52 can be immediately following the etching of the conductive layer 51 and carried out in the same etching frame, preferably using the same chemistry.

[0099] Finally, the etching mask 53 is removed after the etching substep Sl-4.

[0100] Advantageously, the manufacturing process further comprises, between polishing the conductive layer 51 (substep Sl-2) and forming the etching mask 53 (substep Sl-3), the deposition of a protective layer on the conductive layer 51. This protective layer, also called an encapsulation layer, protects the conductive layer 51 from the formation of the etching mask 53, from the etching of the conductive layer 51, and from the removal of the etching mask 53, so that the first pads 31 have a top surface free from alteration (e.g., oxidation), defects, or residues. The protective layer is, for example, made of silicon dioxide (SiO2), silicon nitride (SiN), or titanium (Ti). Its thickness is preferably between 5 nm and 2 pm in the case of SiO2 or SiN, and between 5 nm and 500 nm in the case of titanium.

[0101] Between the formation of the etching mask 53 (substep S1-3) and the etching of the conductive layer 51 (substep S1-4), the protective layer is etched through the etching mask 53 to expose the conductive layer 51 (the so-called protective layer opening substep). The protective layer is removed after the etching mask 53 is removed, preferably by wet etching, for example in a dilute hydrofluoric acid (HF) solution.

[0102] With reference to [Fig.3E], the manufacturing process includes a step S2 of etching the first dielectric layer 1212 between at least a part of the first conductive tracks 1211. This etching aims to form a part of the empty space G of solid material between said conductive tracks 1211.

[0103] Advantageously, the first dielectric layer 1212 is selectively etched with respect to the first conductive tracks 1211 (and the first pads 31) so as to expose all the conductive tracks 1211, at least over a portion of their height, and preferably over their entire height. The first dielectric layer 1212 is preferably etched by reactive-ion etching (or RIE).

[0104] The S2 step of etching the first dielectric layer 1212 can be carried out before or after the removal of the etching mask 53. However, it is preferable that it be carried out before (and therefore before the removal of the protective layer, if applicable) so that the upper face of the first pads 31 is not exposed to this etching.

[0105] The formation of the second pads 32 on the second interconnect structure 22 of the second chip 20 can be accomplished in the same way as the formation of the first pads 31. Thus, the above description of step S1 applies mutatis mutandis to step S3, which includes, in particular, substeps S3-1, S3-2, S3-3, and S3-4, illustrated respectively by [Fig. 4A], [Fig. 4B], [Fig. 4C], and [Fig. 4D]. This will (advantageously) form a second barrier layer 52', a second conductive layer 51', (advantageously) a second protective layer, and a second hard mask 53'.

[0106] The second pads 32 are advantageously formed so as to be directly connected to the second conductive tracks 2211 of the last interconnection level 221. The second conductive tracks 2211 are coated with a The second dielectric layer 2212 is coated in the same way that the first conductive tracks 1211 are coated with the first dielectric layer 1212. Like the last interconnection level 121 of the first chip 10, the last interconnection level 221 of the second chip 20 can have a thickness between 10 nm and 2 pm, preferably between 100 nm and 1 pm. It preferably has a low topography (< 1 pm) and a flatness compatible with direct bonding techniques.

[0107] In order to also expose the second conductive tracks 2211 (to further reduce crosstalk and dielectric losses in the assembly), the manufacturing process may include, with reference to [Fig. 4E], a step S4 of etching the second dielectric layer 2212 between at least a portion of the second conductive tracks 2211. This step S4 may be carried out in the same way as step S3 of [Fig. 3E],

[0108] At the end of steps S2 and S3 (or S4), the first pads 31 protrude from the surface of the first chip 10 (formed by the first interconnection structure 12) and the second pads 32 protrude from the surface of the second chip 20 (formed by the second interconnection structure 22).

[0109] Step S5 of [Fig.5] consists of assembling the first and second chips 10, 20 by gluing the first pads 31 to the second pads 32, resulting in the assembly 100. This gluing is accomplished after flipping one of the two chips 10, 20, here the first chip 10 (this is called "flip-chip bonding" in English).

[0110] The bonding technique used is, in this preferred embodiment, a direct bonding technique, for example hydrophilic direct bonding or surface activated bonding (or SAB, for "Surface Activated Bonding" in English).

[0111] Hydrophilic direct bonding, or hydrophilic molecular adhesion bonding, is a bonding technique that utilizes hydrophilic bonding surfaces (as is the case for the upper faces of the first and second pads 31-32) and whose principle is based on the spontaneous adhesion of surfaces due to van der Waals forces (including hydrogen bonds and capillary bridges). It is simpler and faster to implement than surface activation bonding (SAB), as it can be performed at room temperature and atmospheric pressure, unlike surface activation bonding (SAB), which is carried out under ultra-high vacuum. Alignment of the first pads 31 with the second pads 32 is also easier than in the case of SAB. It can be performed in a hybrid bonding machine commonly used for 3D applications.Furthermore, it is not necessary to apply a compressive force between the two chips, as this type of bonding is spontaneous.

[0112] Moreover, direct hydrophilic bonding causes very few defects at the bonding interface, such as voids. Furthermore, it does not produce of an interface layer typically comprising implanted argon atoms (as may be the case for SAB).

[0113] Direct hydrophilic bonding can nevertheless be carried out under vacuum optionally, with a vacuum level between 102 Pa and 1000 Pa (104 mbar and 10 mbar), which is much easier and more economical to achieve than ultra-high vacuum (106-1010 Pa, i.e. 108-1012 mbar).

[0114] After bonding, the manufacturing process may also include a low-temperature annealing step of the assembly 100, in order to further create metallic bonds between the bonding pads and thus strengthen the retention between the chips. The annealing temperature is sufficiently low so as not to damage the electronic devices of the chips. It may be between 100 °C and 400 °C, preferably between 100 °C and 350 °C, and even more preferably between 100 °C and 300 °C. This annealing step is optional, since the adhesion strength of the chips bonded by direct gluing is already high.

[0115] Optionally, one of the two substrates 11 and 21 can also be thinned by grinding and / or etching (dry or wet)

[0116] Steps S1 to S5 (plus any annealing) of the manufacturing process are advantageously implemented at the wafer level. Thus, the first chip belongs to one wafer and the second chip belongs to a second wafer. The chip assembly 100 is then separated by cutting the assembly from the two wafers.

[0117] The first plate can include several copies of the first chip 10 and the second plate can include several copies of the second chip 20, in order to obtain several copies of the assembly 100.

[0118] Direct hydrophilic bonding between two plates generally does not require the application of force to the back faces of the plates. However, it may be advantageous to apply pressure after or during the bonding operation to ensure contact between all the pads. This is particularly useful if one or both plates exhibit significant deflections (typically between 100 µm and 500 µm).

[0119] After bonding, the plate assembly may undergo further manufacturing steps, some involving one or more fluids (gas, liquid, or plasma). To prevent fluid penetration into the space G between chips 10 and 20, which could damage the chips, the bonding pads, or impair the bond quality, a peripheral sealing ring may be formed in the area between the plates. This sealing ring may comprise two parts, one on the surface of the first plate and the other on the surface of the second plate. Preferably, the first part of the sealing ring is formed simultaneously with the first two parts. The first two parts of the sealing ring are formed simultaneously with the second set of studs 31 (by etching the first conductive layer 51, previously deposited as a full plate). The first and second parts of the ring are brought into contact during the bonding step S5.

[0120] A peripheral sealing ring can alternatively be provided for each chip assembly (forming a half-ring on each chip), and not at the level of the wafer assembly, to facilitate degassing during annealing and thus avoid stresses due to pressure.

[0121] The peripheral sealing ring can have a width between 10 µm and 2 mm, depending on the number and nature of the technological steps to be carried out after bonding.

[0122] In one embodiment, only steps S1 to S4 of the manufacturing process are implemented at the wafer level. The bonding step S5 is implemented according to the chip-to-wafer or chip-to-chip approach, that is, after the first chip has been diced and / or the second chip has been diced.

[0123] The assembly of electronic chips and its manufacturing process are not limited to the embodiments described above.

[0124] In particular, the empty space G of solid material may not extend between second conductive tracks 2211 of the second chip 20 (by not etching the second dielectric layer 2212 of the last interconnection level 221).

[0125] Furthermore, the second interconnection structure 22 of the second chip 20 can be surmounted by a bonding layer comprising the second pads 32 and conductive vias connecting the second pads 32 to the second interconnection structure 22 (and more particularly to the last interconnection layer 221). The conductive vias are coated with dielectric material, as are the second conductive tracks 2211.

Claims

1. Demands Assembly (100) of electronic chips comprising: - a first chip (10) and a second chip (20) superimposed and electrically and mechanically connected to each other, the first chip (10) comprising • a first substrate (11); • a first interconnection structure (12) arranged on the first substrate (11) and comprising a plurality of superimposed interconnection levels (121); the second chip (20) comprising: • a second substrate (21); • a second interconnection structure (22) disposed on the second substrate (21) and comprising a plurality of superimposed interconnection levels (221); - a plurality of first bonding pads (31) arranged on the first interconnection structure (12); and - a plurality of second gluing pads (32) arranged on the second interconnection structure (22), the second gluing pads (32) being glued to the first gluing pads (31); assembly in which: - the interconnection level (121) of the first chip (10) furthest from the first substrate (11), called the last interconnection level of the first chip, includes first conductive tracks (1211) which extend parallel to a plane (XY) of the first substrate (11); - at least some of the first adhesive pads (31) are directly connected to the first conductive tracks (1211); and - a space (G) devoid of solid material separates the last interconnection level of the first chip (10) from the second chip (20) and extends between at least part of the first conductive tracks (1211).

2. Assembly (100) according to claim 1, wherein the first conductive tracks (1211) of said at least a part have exposed side walls, at least over a part of their height.

3. Assembly (100) according to any one of claims 1 and 2, wherein: - the interconnection level (221) of the second chip (20) furthest from the second substrate (21), referred to as the last interconnection level of the second chip, comprises second conductive tracks (2211) which extend parallel to a plane of the second substrate (21); - at least a portion of the second bonding pads (32) are directly connected to the second conductive tracks (2211); and - the space (G) free of solid material further extends between at least a portion of the second conductive tracks (2211).

4. Assembly (100) according to claim 3, wherein the second conductive tracks (2211) of said at least a part have exposed side walls, at least over a part of their height.

5. Assembly (100) according to any one of claims 1 to 4, wherein the first gluing pads (31) have in a first direction (X) a first repetition step (PXi) and wherein the second gluing pads (32) have in the first direction (X) a second repetition step (PX2) equal to the first repetition step (PYi).

6. Assembly (100) according to claim 5, wherein the first repetition step (Px) is less than or equal to 10 pm.

7. Assembly (100) according to any one of claims 5 and 6, wherein the first gluing pads (31) have a third repetition step (PY1) in a second direction (Y) secant to the first direction (X) and wherein the second gluing pads (32) have in the second direction (Y) a fourth repetition step (PY2) equal to the third repetition step (PYi).

8. Assembly (100) according to any one of claims 1 to 7, wherein the first bonding pads (31) and the second bonding pads (32) are superconducting.

9. Assembly (100) according to any one of claims 1 to 8, wherein the first chip (10) is a quantum circuit and the second chip (20) is a quantum circuit readout and control circuit.

10. Assembly (100) according to any one of claims 1 to 8, wherein the first chip (10) is an infrared bolometric sensor and the second chip (20) is a multiplexing circuit or an infrared bolometric sensor readout circuit.

11. Assembly (100) according to any one of claims 1 to 8, wherein the first chip (10) and the second chip (20) are radio frequency circuits.

12. A method for manufacturing an assembly (100) of electronic chips comprising a first chip (10) and a second chip (20) superimposed and electrically and mechanically connected to each other, the first chip (10) comprising: - a first substrate (11); - a first interconnection structure (12) disposed on the first substrate (11) and comprising a plurality of superimposed interconnection levels (121); the second chip (20) comprising: - a second substrate (21); - a second interconnection structure (22) disposed on the second substrate (21) and comprising a plurality of superimposed interconnection levels (221);method comprising the following steps: - forming (SI) a plurality of first bonding pads (31) on the first interconnection structure (12), the interconnection level (121) of the first chip (10) furthest from the first substrate (11), called the last interconnection level of the first chip, comprising first conductive tracks (1211) extending parallel to a plane (XY) of the first substrate (11) and a first dielectric layer (1212) encapsulating the first conductive tracks, at least a part of the first bonding pads (31) being directly connected to the first conductive tracks (1211); - etch (S2) the first dielectric layer (1212) between at least a part of the first conductive tracks (1211); - form (S3) a plurality of second bonding pads (32) on the second interconnection structure (22); - assemble (S5) the first chip (10) and the second chip (20) by bonding the first bonding pads (31) to the second bonding pads (32), so that a space (G) devoid of solid material separates the last interconnection level of the first chip (10) from the second chip (20) and extends between said at least a part of the first conductive tracks (1211).

13. Method according to claim 12, wherein the first bonding pads (31) are bonded to the second bonding pads (32) by a direct bonding technique, advantageously by hydrophilic direct bonding.

14. A method according to any one of claims 12 and 13, wherein the formation of the first bonding pads (31) comprises the following substeps: - forming (S 1-1) a conductive layer (51) on the last interconnection level of the first chip (10); - polishing (S 1-2) the conductive layer (51) so as to obtain a surface roughness of less than 0.5 nm; - forming (S 1-3) an etching mask (53) on the conductive layer (51); - etching (S 1-4) the conductive layer (51) through the etching mask (53); and - removing the etching mask (53).

15. Method according to claim 14, wherein the first dielectric layer (1212) is etched before the removal of the etching mask (53).

16. A method according to any one of claims 14 and 15, wherein the formation of the first bonding pads (31) further comprises: - before the formation of the conductive layer (51), the deposition of a barrier layer (52) on the last interconnection level of the first chip (10); and

17. - after the etching of the conductive layer (51), the etching of the barrier layer (52). A method according to any one of claims 14 to 16, further comprising the following steps: - between the polishing of the conductive layer (51) and the formation of the etching mask (53), the deposition of a protective layer on the conductive layer (51); - before etching the conductive layer (51), etching the protective layer through the etching mask (53) to expose the conductive layer (51); and - after removing the etching mask (53), the protective layer is removed.

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