Electronic circuit and its manufacturing process

Abstract

Electronic circuit and its manufacturing process. This description relates to an electronic circuit (10) comprising electronic components (T1), at least one of the electronic components comprising a semiconductor region (11_T1) comprising a stack of at least three semiconductor layers of the same semiconductor material in a first stacking direction (D). Figure for the abbreviation: Fig. 2

Description

Title of the invention: Electronic circuit and its manufacturing process technical field

[0001] This description relates generally to integrated electronic circuits and their manufacturing processes. Previous technique

[0002] An integrated electronic circuit may include thin film transistors, also called TFTs (English acronym for Thin Film Transistor).

[0003] A method for manufacturing a thin-film transistor comprises depositing successive thin layers, each a few hundred nanometers thick, onto a substrate. These layers are primarily composed of dielectric, semiconductor, and metallic materials. These layers can be produced by 3D printing.

[0004] Figure 1 is a partial, schematic, cross-sectional perspective view of an example of a planar thin-film transistor. The transistor T comprises a semiconductor layer 1 between a conductive layer 2 forming the drain contact and a conductive layer 3 forming the source contact. The transistor T further comprises an insulating layer 4 covering the semiconductor region 1 and the conductive regions 2 and 3, the portion of the insulating layer 4 covering the semiconductor region 1 forming the gate insulator of the transistor T. The transistor T further comprises a conductive layer 5 covering the insulating layer 4 and forming the gate of the transistor T. The transistor T is formed on a substrate 6, for example, a glass plate.

[0005] Generally, several copies of the electronic circuit comprising the thin-film transistors are formed on a plate which is then cut to separate the electronic circuits. The resulting electronic circuit thus has an essentially planar structure.

[0006] Depending on the intended application, assembly steps must then generally be provided to integrate the electronic circuit into an electromechanical system, taking into account the planar structure of the electronic circuit, in particular to ensure the mechanical integrity of the electronic circuit within an electromechanical system, the interconnection of the electronic circuit with other elements, etc. The design of the electromechanical system integrating the electronic circuit can therefore be complex.

[0007] It would be desirable to simplify the design of an electromechanical system incorporating an electronic circuit. Summary of the invention

[0008] An embodiment overcomes all or part of the drawbacks of known electronic circuits and their manufacturing processes.

[0009] One embodiment provides for an electronic circuit comprising electronic components, at least one of the electronic components comprising a semiconductor region comprising a stacking of at least three semiconductor layers of the same semiconductor material in a first stacking direction.

[0010] According to one embodiment, all the electronic components are embedded in a dielectric matrix comprising a stacking of at least three dielectric layers of the same dielectric material along the first stacking direction or a second stacking direction inclined with respect to the first stacking direction.

[0011] According to one embodiment, said electronic component is a thin-film transistor further comprising an electrically insulating region in contact with the semiconductor region and forming the gate insulator of the thin-film transistor, and a first electrically conductive region covering the electrically insulating region, in contact with the electrically insulating region, and forming the gate of the thin-film transistor,the electrically insulating region comprising a stacking of at least three electrically insulating layers of the same electrically insulating material along the first stacking direction or a third stacking direction inclined with respect to the first stacking direction and the first electrically conductive region comprising a stacking of at least three first electrically conductive layers of the same electrically conductive material along the first stacking direction or a fourth stacking direction inclined with respect to the first stacking direction.

[0012] According to one embodiment, the thin-film transistor further comprises a second electrically conductive region in contact with the semiconductor region and a third electrically conductive region in contact with the semiconductor region, the second electrically conductive region comprising a stack of at least three second electrically conductive layers of the same electrically conductive material along the first stacking direction or a fifth stacking direction inclined with respect to the first stacking direction and the third electrically conductive region comprising a stack of at least three third electrically conductive layers of the same electrically conductive material along the first stacking direction or a sixth stacking direction inclined with respect to the first stacking direction.

[0013] According to one embodiment, the semiconductor region has the shape of a tube or a sector of a tube.

[0014] According to one embodiment, the semiconductor region has the shape of a hollow sphere or a hollow sphere cap.

[0015] One embodiment also provides for an electromechanical system comprising a body in which is embedded at least one electronic circuit as defined above.

[0016] An embodiment also provides a method for manufacturing an electronic circuit comprising electronic components, at least one of the electronic components comprising a semiconductor region, the formation of the semiconductor region comprising the formation of a stack of at least three semiconductor layers of the same semiconductor material in a first stacking direction.

[0017] According to one embodiment, the process includes the formation of a dielectric matrix comprising a stacking of at least three dielectric layers of the same dielectric material along the first stacking direction or a second stacking direction inclined with respect to the first stacking direction in which all the electronic components are embedded.

[0018] According to one embodiment, said electronic component is a thin-film transistor further comprising an electrically insulating region in contact with the semiconductor region and forming the gate insulator of the thin-film transistor, and a first electrically conductive region covering the electrically insulating region, in contact with the electrically insulating region, and forming the gate of the thin-film transistor,the formation of the electrically insulating region comprising the formation of a stack of at least three electrically insulating layers of the same electrically insulating material along the first stacking direction or a third stacking direction inclined with respect to the first stacking direction and the formation of the first electrically conductive region comprising the formation of a stack of at least three first electrically conductive layers of the same electrically conductive material along the first stacking direction or a fourth stacking direction inclined with respect to the first stacking direction. Brief description of the drawings

[0019] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0020] Fig. 1, described above, is a partial and schematic cross-sectional perspective view of an example of a planar structure thin-film transistor;

[0021] [Fig.2] is a partial and schematic cross-sectional view of an electronic circuit comprising electronic components;

[0022] [Fig.3], [Fig.4], [Fig.5], and [Fig.6] are partial and schematic perspective views of embodiments of thin-film transistors;

[0023] [Fig.7] is a partial and schematic cross-sectional view of an embodiment of a capacitor;

[0024] [Fig.8] is a partial and schematic cross-sectional view of an embodiment of a light-emitting diode;

[0025] [Fig.9] is a functional and simplified electrical diagram of an inverter made by thin-film transistors;

[0026] [Fig. 10] is a partial and schematic perspective view of an embodiment of the inverter according to the electrical diagram of [Fig. 9];

[0027] [Fig.1 1] is a functional and simplified electrical diagram of a NOT AND logic gate implemented by thin film transistors;

[0028] [Fig. 12] is a partial and schematic perspective view of an embodiment of a NOT AND logic gate according to the electrical diagram of [Fig. 11];

[0029] [Fig. 13] is a side view of the developed structure of the NOT AND logic gate according to the embodiment of [Fig. 12];

[0030] [Fig. 14] is a partial and schematic perspective view of another embodiment of an inverter;

[0031] [Fig. 15] is a partial, schematic perspective view of one embodiment of an electronic circuit; and

[0032] [Fig. 16] is a partial and schematic perspective view of an embodiment of an electromechanical system. Description of the implementation methods

[0033] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0034] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0035] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0036] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0037] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "on the order of" mean to the nearest 10%, preferably to the nearest 5%. Furthermore, the terms "insulator" and "conductor" are taken to mean "electrically insulating" and "electrically conductive", respectively.

[0038] In the following description, to describe the structure of an electronic component, the reference used to designate a semiconductor region of the electronic component includes the number 11 followed by an underscore and the reference of the electronic component, the reference used to designate a conductive region of the electronic component includes the number 12, 13, or 15 followed by an underscore and the reference of the electronic component, and the reference used to designate an insulating region of the electronic component includes the number 14 followed by an underscore and the reference of the electronic component.For example, in the case of a thin-film transistor, the reference used to designate the semiconductor region of the transistor in which the channel is formed during operation includes the number 11 followed by an underscore and the transistor reference; the reference used to designate the drain contact of the transistor includes the number 12 followed by an underscore and the transistor reference; the reference used to designate the source contact of the transistor includes the number 13 followed by an underscore and the transistor reference; the reference used to designate the insulating region of the transistor in which the gate insulator is formed includes the number 14 followed by an underscore and the transistor reference; and the reference used to designate the conducting region of the transistor in which the gate is formed includes the number 15 followed by an underscore and the transistor reference.

[0039] Figure 2 is a partial, schematic cross-sectional view of an electronic circuit 10 comprising electronic components, of which only one electronic component T1 is shown in Figure 2. The electronic component T1 may comprise at least one semiconductor region 11_T1, at least one conductive region 12_T1, 13_T1, 15_T1, and / or at least one insulating region 14_TL. All the electronic components of the electronic circuit 10 are integrated into a dielectric matrix 16. The matrix 16 may be made of the same insulating material as the insulating region 14_T1 or of a different insulating material than that of the insulating region 14_TL.

[0040] By way of example, the electronic component Tl shown in [Fig. 2] corresponds to a thin-film transistor. The transistor Tl comprises three conductive regions 12_T1, 13_T1, 15_T1, of which a drain conductive region 12_T1 is in contact with the semiconductor region 11_T1 and a source conductive region 13_T1 is in contact with the semiconductor region 11_T1. The insulating region 14_T1 is in contact with the semiconductor region 11_T1 and forms the gate insulator of transistor T1, and the conductive region 15_T1 covers the insulating region 14_T1, in contact with the insulating region 14_T1, and forms the gate of transistor T1.

[0041] According to one embodiment, each thin-film transistor Tl and the matrix 16 are produced by 3D printing. 3D printing, or additive manufacturing, encompasses manufacturing processes that create three-dimensional parts by adding a fluid material in successive layers. Examples of 3D printing processes include inkjet printing, gravure printing, screen printing, flexography, spray coating, and drop-casting. Preferably, each thin-film transistor Tl is produced by inkjet printing.

[0042] According to one embodiment, for each electronic component of the electronic circuit 10, the semiconductor region 11_T1, the insulating region 14_T1, and / or the conductive region 12_T1, 13_T1, and 15_T1 is formed by stacking contiguous layers along a stacking direction D, each layer being able to correspond to a cord or contiguous cords formed in a plane perpendicular to the stacking direction D. Similarly, the matrix 16 of the electronic circuit 10 is formed by stacking layers along the stacking direction D, each layer of the matrix 16 comprising contiguous cords formed in a plane perpendicular to the stacking direction D. More specifically, the semiconductor region 11_T1 is formed by a stacking of contiguous semiconductor layers 11_T1 along the stacking direction D. The insulating region 14_T1 is formed by a stacking of insulating layers 14_T1 joined together along the stacking direction D.The conductive region 12_T1, 13_T1, and / or 15_T1 is made by a stacking of contiguous conductive layers 12L, 13L, 15L along the stacking direction D. The matrix 16 is made by a stacking of contiguous dielectric layers 16L along the stacking direction D.

[0043] According to one embodiment, the average thickness of each layer 1 IL, 12L, 13L, 14L, 15L, 16L, measured along the stacking direction D, is between 0.1 µm and 1 mm. According to one embodiment, the number of 1 IL semiconductor layers per semiconductor region 11_T1 is greater than 3, and is, for example, between 3 and 300. According to one embodiment, the number of 14L insulating layers per insulating region 14_T1 is greater than 3, and is, for example, between 3 and 300. According to one embodiment, the number of conductive layers 12L, 13L, 15L per conductive region 12_T1, 13_T1, 15_T1 is greater than 3, and is, for example, between 3 and 300. According to one embodiment, the minimum thickness of the The minimum thickness of the semiconductor region 11_T1, along a direction perpendicular to the stacking direction D, is between 0.1 pm and 100 pm. In one embodiment, the minimum thickness of the conducting region 12_T1, 13_T1, 15_T1, along a direction perpendicular to the stacking direction D, is between 0.1 pm and 25 pm. In one embodiment, the minimum thickness of the insulating region 14_T1, along a direction perpendicular to the stacking direction D, is between 0.1 pm and 100 pm.

[0044] The stacking direction D depends on the relative orientation between the device implementing the additive manufacturing process and the already formed layers of the electronic circuit 10. In the embodiment illustrated in [Fig.2], the stacking direction D is the same for the semiconductor region 11_T1, the conductive regions 12_T1, 13_T1, 15_T1, the insulating region 14_T1, and the matrix 16. According to another embodiment, the stacking directions among the stacking direction during the formation of the semiconductor region 11_T1, the stacking direction during the formation of the conductive regions 12_T1, 13_T1, 15_T1, the stacking direction during the formation of the insulating region 14_T1, and the stacking direction during the formation of the matrix 16, are not all identical.This can occur when the relative orientation between the device implementing the additive manufacturing process and the already formed layers of the electronic circuit 10 is changed during the fabrication of at least two regions among the semiconductor region 11_T1, the conductive regions 12_T1, 13_T1, 15_T1, the insulating region 14_T1, and the matrix 16. In another embodiment, the stacking direction of at least one region among the semiconductor region 11_T1, each conductive region 12_T1, 13_T1, 15_T1, the insulating region 14_T1, and / or the matrix 16 is not constant throughout the formation of that region. This can occur when the relative orientation between the device implementing the additive manufacturing process and the already formed layers of the electronic circuit 10 is changed during the fabrication of the region.It is subsequently assumed that the stacking direction is at least constant for the formation of three successive layers of the region.

[0045] According to one embodiment, the transistor T1 is an organic field-effect transistor, also called an OFET (Organic Field-Effect Transistor). According to one embodiment, the semiconductor material composing the semiconductor region 11_T1, the conducting material composing the conducting regions 12_T1, 13_T1, 15_T1, the insulating material composing the insulating region 14_T1, and / or the dielectric material composing the matrix 16 is an organic material.

[0046] The semiconductor material composing the semiconductor region 11_T1 is chosen from the group comprising a P-type semiconductor polymer, for example poly(vinyltriphenylamine) known by the abbreviation PvTPA, poly(vinyldimethoxy-triphenylamine) known by the abbreviation PvDMTPA, poly(vinyldimethoxy-triphenyldiamine) known by the abbreviation PvDMTPD, 2,9-didecyl-dinaphtho[2,3-b:20,30-f]thieno[3,2-b]thiophene known by the abbreviation C10-DNTT, poly(3-hexylthiophene) known by the abbreviation P3HT and its derivatives, poly-(2,5-bis(3-alkylthiophene-2-yl)thieno[3,2-b]thiophene) known by the abbreviation pBTTT, the 2,7-dioctyl[l]benzothieno[3,2-b][l]benzothiophene known by the abbreviation C8-BTBT, poly(3-hexylthiophene) known by the abbreviation P3HT, poly-(2,5-bis (3-alkylthiophene-2-yl) thieno[3,2-b]thiophene) known by the abbreviation pBTTT, 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane known by the abbreviation F4-TCNQ, 5,6,11,12-Tetraphenylnaphthacene known by the abbreviation rubrene, 2-Decyl-7-phenyl[l]benzothieno[3,2-b][l]benzothiophene known by the abbreviation DPh-BTBT-10, or an N-type semiconductor polymer, for example poly{[N,N'-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,'-(2,2'-bithiophene)} or poly[[l,2,3,6,7,8-hexahydro-2,7-bis(2-octyldodecyl)-1,3,6,8-dioxobenzo[Imn][3,8]phenanthroline-4,9-diyl][2,2'-bithiophene]-5,5'-diyl] known as the abbreviation P(NDI2OD-T2), N,N'-Dioctyl-3,4,9,10-perylenedicarboximide known by the abbreviation PTCDLC8, 4,4'-(2X4β2-benzo[l,2-c:4,5-c']bis[l,2,5]thiadiazole-4,8-diyldi-5,2-thiophenediyl)bis[2-dodecyl benzonitrile], 4,8-Bis[5-(4-cyano-3-alkylphenyl)-2-thienyl]benzo[l,2-c:4,5-c']bis[1,2,5]thiadiazole known by the abbreviation TU-3. ,

[0047] The conductive material composing the conductive regions 12_T1, 13_T1, 15_T1 is chosen from the group comprising a conductive polymer, for example PEDOT:PSS which is a mixture of two polymers, poly(3,4-ethylenedioxythiophene) (PEDOT) and sodium poly(styrene sulfonate) (PSS), a polymer loaded with metallic nanoparticles or more generally a polymer loaded with electrically conductive nanoparticles, for example carbon nanowires, carbon nanotubes (CNTs), silver nanowires, silver nanoflakes, graphene oxide, and a mixture of at least two of these materials. The insulating material composing the insulating region 14_T1 is chosen from the group including ABS, SU-8, polyimide, polyamide, polycarbonate, polypropylene, polystyrene (PS), acrylic or epoxy acrylic or any polymer having a sufficiently low dielectric constant (typically less than 5).The dielectric material composing matrix 16 is chosen from the group including poly(vinylidene fluoride) (PVDF) and its derivatives such as poly(vinylidene fluoride - trifluoroethylene) [P(VDF-TrFE)], poly(vinylidene fluoride - -co- . chlorotrifluoroethylene) (PVDF-CTFE), poly(methyl methacrylate) (PMMA), low-density polyethylene (LDPE) or including the group of conjugated polymers, for example phthalocyanine (H2Pc) and its derivatives such as copper phthalocyanine (CuPc) and poly-CuPc, or including the group of elastomers such as silicone (RTV), polyisobutylene (PIB). The polymer can be filled with inorganic ceramic powders such as alumina (Al₂O₃), or barium titanate (BaTiO₃) and its derivatives such as Ba₂O, 5Sr₂O, 5TiO₃ (BST), strontium titanate (SrTiO₃, also known as ST), Bi₂O, 5Na₂O, 5TiO₃ (BNT), silver niobate (AgNbO₃, also known as AN), potassium niobate (K₂O, 5Na₂O, 5NbO₃, also known as KNN), and bismuth ferrite (BiFeO₃, also known as BF). Filling ratios can reach a maximum of 80% by volume.

[0048] Embodiments of electronic components and electronic circuits will now be described. For these electronic components and electronic circuits, the matrix 16 described previously is not shown.

[0049] Figure 3 is a partial, schematic perspective view of another embodiment of a thin-film transistor T2. The transistor T2 comprises all the elements of the transistor T1 described in relation to Figure 2. The semiconductor region 11_T2 has the shape of a tube with axis A and a circular base, having an inner face 20_T2, an outer face 21_T2, and two opposite edges 22_T2, only one edge 22_T2 being visible in Figure 3. The semiconductor region 11_T2 is surrounded by the insulating region 14_T2, which has the shape of a tube with axis A, the insulating region 14_T2 being in contact with the semiconductor region 11_T2. The insulating region 14_T2 is surrounded by the conductive region 15_T2 which has the shape of a tube with axis A, the conductive region 15_T2 being in contact with the insulating region 14_T2.The drain conductive region 12_T2 and the source conductive region 13_T2 each have the shape of an annular sector and rest on one of the edges 22_T2 of the semiconductor region 11_T2, in contact with the semiconductor region 11_T2. In [Fig.3], the drain conductive region 12_T2 and the source conductive region 13_T2 are located diametrically opposite with respect to the axis A.

[0050] Figure 4 is a partial, schematic perspective view of an embodiment of a thin-film transistor T3. The transistor T3 comprises all the elements of the transistor T2 described in relation to Figure 3, except that the drain conductive region 12_T3 and the source conductive region 13_T3 each correspond to a conductive track extending along axis A on the inner face 20_T3 of the semiconductor region 11_T3. In Figure 4, the drain conductive region 12_T3 and the source conductive region 13_T3 are located diametrically opposite each other with respect to axis A.

[0051] Figure 5 is a partial, schematic perspective view of another embodiment of a thin-film transistor T4. The transistor T4 comprises all the elements of the transistor T1 described in relation to Figure 2, except that the semiconductor region 11_T4 has the shape of a sector of a tube with axis A and a circular base, for example, a half-tube, having an inner face 20_T4 and an outer face 21_T4. The semiconductor region 11_T4 is covered, on the side of the outer face 21_T4, by the insulating region 14_T4, which has the shape of a sector of a tube with axis A and a circular base, for example, a half-tube, the insulating region 14_T4 being in contact with the semiconductor region 11_T4. The insulating region 14_T4 is covered, on the side opposite the external face 21_T4, by the conducting region 15_T4 which has the shape of a sector of a tube with axis A and circular base, for example a half-tube, the conducting region 15_T4 being in contact with the insulating region 14_T4.The drain conductive region 12_T4 and the source conductive region 13_T2 each correspond to a conductive track extending along axis A on the inner face 20_T4 of the semiconductor region 11_T4. The angle of the tube sector along axis A forming the semiconductor region 11_T4 is specifically chosen based on the desired channel length of transistor T2. This advantageously allows the desired channel length of transistor T4 to be varied while maintaining the radius of the circular base of the semiconductor region 11_T4. In [Fig. 5], the semiconductor region 11_T4 has the shape of a half-tube, and the drain conductive region 12_T4 and the source conductive region 13_T4 are located diametrically opposite each other with respect to axis A.

[0052] Generally, the electronic component comprises at least one semiconductor region formed by a stacking of contiguous semiconductor layers along a stacking direction, each semiconductor layer having the shape of a strip along a straight line or a curve, preferably an open or closed curve. In the case where each semiconductor layer of the semiconductor region exactly overlaps the underlying semiconductor layer, the semiconductor region has the general shape of a cylinder, in the mathematical sense of the term, extending along the stacking direction. In the case where at least some of the semiconductor layers of the semiconductor region only partially overlap the corresponding underlying semiconductor layer, the semiconductor region may exhibit curvature in a plane containing the stacking direction.

[0053] Figure 6 is a partial, schematic, partially cutaway perspective view of another embodiment of a thin-film transistor T5. The transistor T5 comprises all the elements of the transistor T1 described in relation to Figure 2, except that the semiconductor region 11_T5 has the shape of a hollow sphere centered at C, having an inner face 20_T5 and an outer face 21_T5. The semiconductor region 11_T5 is surrounded by the insulating region 14_T5, which has the shape of a hollow sphere centered at C. The insulating region 14_T5 is in contact with the semiconductor region 11_T5. The insulating region 14_T5 is surrounded by the conducting region 15_T5, which has the shape of a hollow sphere centered at C. The conducting region 15_T5 is in contact with the insulating region 14_T5. The drain conducting region 12_T5 and the source conducting region 13_T5 each have the shape of a sector of the cap of a hollow sphere centered at C and rest on the inner face 20_T5 of the semiconductor region 11_T5, in contact with the semiconductor region 11_T5. In [Fig.6], the drain conductive region 12_T5 and the source conductive region 13_T5 are located diametrically opposite with respect to the center C.The connection of the source conductive region 12_T5 and the drain conductive region 13_T5 to other electronic components can be achieved by means of conductive vias, not shown, passing through the semiconductor region 11_T5, the insulating region 14_T5, and the conductive region 15_T5 to come into contact with the drain conductive region 12_T5 and the source conductive region 13_T5, these vias being electrically isolated from the semiconductor region 11_T5 and the conductive region 15_T5.

[0054] More generally, instead of a hollow sphere, the semiconductor region 11_T5 can have the shape of any hollow volume, for example the shape of a hollow torus, or of a hollow polyhedron, for example a hollow cube.

[0055] Figure 7 is a partial, schematic cross-sectional view of an embodiment of a CAP capacitor. The CAP capacitor comprises an insulating region 14_CAP sandwiched between two conducting regions 12_CAP and 13_CAP. The insulating region 14_CAP and the conducting regions 12_CAP and 13_CAP are each in the shape of a tube with axis A and a circular base. The insulating region 14_CAP has an inner face 23_CAP and an outer face 24_CAP. The insulating region 14_CAP is surrounded by the conducting region 12_CAP, the conducting region 12_CAP being in contact with the outer face 24_CAP of the insulating region 14_CAP. The conducting region 13_CAP is surrounded by the insulating region 14_CAP, the conducting region 13_CAP being in contact with the inner face 23_CAP of the insulating region 14_CAP. The conductive regions 12_CAP and 13_CAP form the plates of the CAP capacitor.

[0056] Fig. 8 is a partial, schematic cross-sectional view of an embodiment of a light-emitting diode LED.

[0057] The light-emitting diode LED comprises a semiconductor region 11_LED, two conductive regions 12_LED and 13_LED, and two interface regions 11'_LED and 11"_LED. The semiconductor region 11_LED, the conductive regions 12_TAP and 13_CAP, and the interface regions 11'_LED and 11"_LED are each in the shape of a circular tube with axis A. The semiconductor region 11_LED is sandwiched between the interface regions 11'_LED and 11"_LED, the conductive region 12_LED The interface region 11_LED is surrounded by the interface region 11_LED, and the conductive region 13_LED is surrounded by the interface region 11_LED. The semiconductor region 11_LED corresponds to the active region of the light-emitting diode (LED), that is, the region in which the electromagnetic radiation supplied by the LED is emitted. The conductive regions 12_LED and 13_LED form the electrodes of the LED. In one embodiment, the outer electrode 12_LED is transparent to the light radiation L emitted by the semiconductor region 11_LED. The interface region 11_LED and 11_LED can correspond to an electron-injecting layer or a hole-injecting layer.

[0058] In general, the electronic components of the electronic circuit 10 may correspond to other electronic components than those described previously and may include a resistor, a photodiode, a solar cell, etc.

[0059] The electronic components described above can be arranged to form elementary electronic circuits. Examples of electronic circuits comprising at least two thin-film transistors will now be described. In particular, examples of electronic circuits corresponding to logic gates will be described.

[0060] Figure 9 is an electrical diagram of an INV inverter. The INV inverter implements the NOT logic function. The INV inverter comprises a P-channel transistor T6 and an N-channel transistor T7. The gates of transistors T6 and T7 are connected to an IN_INV node, which represents the input of the INV inverter. The source of transistor T6 is intended, during operation, to be connected to a source with a high reference potential Vdd. The source of transistor T7 is intended, during operation, to be connected to a source with a low reference potential Vss. The drain of transistor T6 is connected to the drain of transistor T7. The drain of transistor T6 and the drain of transistor T7 are connected to an OUT_INV node, which represents the output of the INV inverter.

[0061] Figure 10 is a partial, schematic perspective view of an embodiment of an INV1 inverter whose electrical diagram corresponds to the INV inverter of Figure 9. Each transistor T6 and T7 of the INV1 inverter shown in Figure 10 has the structure shown in Figure 5. In particular, the semiconductor region 11_T6 of transistor T6 and the semiconductor region 11_T7 of transistor T7 each have the shape of a sector of a tube with axis A and a circular base, the semiconductor region 11_T6 not being in contact with the semiconductor region 11_T7 in Figure 10. Furthermore, the insulating region 14_T6 of transistor T6 is contiguous with the insulating region 14_T7 of transistor T7, the insulating regions 14_T6 and 14_T7 forming a tube with axis A. In addition, the gate-conducting region 15_T6 of transistor T6 is contiguous with the gate-conducting region 15_T7 of transistor T7, the gate-conducting regions 15_T6 and 15_T7 forming a tube with axis A. The drain conductive region 12_T6 is contiguous with the drain conductive region 12_T7 of transistor T7.

[0062] Figure 11 is an electrical diagram of a NAND electronic circuit. The NAND electronic circuit implements the NOT AND logic function. The NAND electronic circuit comprises two P-channel transistors, T8 and T9, and two N-channel transistors, T10 and T11. The gates of transistor T8 and T10 are each designed to receive a signal A during operation. The gates of transistor T9 and T11 are each designed to receive a signal B during operation. The sources of transistors T8 and T9 are designed to be connected to a high reference potential source Vdd during operation. The source of transistor T11 is designed to be connected to a low reference potential source Vss during operation. The drain of transistor T10 is connected to the drains of transistors T8 and T9. The source of transistor T10 is connected to the drain of transistor T11.The drains of transistors T8 and T9 and the drain of transistor T10 are connected to an OUT_NAND node which represents the output of the NAND electronic circuit.

[0063] [Fig. 12] is a partial and schematic perspective view of an embodiment of the NAND logic gate according to the electrical diagram of [Fig. 11] and [Fig. 13] is a side view of the developed structure of the NAND logic gate of [Fig. 12],

[0064] Each transistor T8, T9, T10 and T11 of the NAND logic gate shown in [Fig. 12] has the structure shown in [Fig. 5], with transistors T8 and T10 located above transistors T9 and T11 in [Fig. 12]. Furthermore, the semiconductor region 11_T8 of the P-channel transistor T8 is contiguous with the semiconductor region 11_T9 of the P-channel transistor T9, the entire assembly of semiconductor regions 11_T8 and 11_T9 having the shape of a sector of a tube with axis A and circular base. The semiconductor region 11_T10 of the N-channel transistor T10 is contiguous with the semiconductor region 11_T11 of the N-channel transistor T11, the entire assembly of semiconductor regions 11_T10 and 11_T11 having the shape of a sector of a tube with axis A and a circular base. The entire assembly of semiconductor regions 11_T8 and 11_T9 is not in contact with the entire assembly of semiconductor regions 11_T10 and 11_T11 in [Fig. 12].

[0065] Furthermore, the insulating region 14_T8 of transistor T8, the insulating region 14_T9 of transistor T9, the insulating region 14_T10 of transistor T10, and the insulating region 14_T11 of transistor T1 are joined, the set of insulating regions 14_T8, 14_T9, 14_T10, and 14_T11 forming a tube with axis A and a circular base. The gate conductive region 15_T8 of transistor T8 is joined with the gate conductive region 15_T10 of transistor T10, the set of gate conductive regions 15_T8 and 15_T10 forming a tube with axis A and a circular base. The gate conductive region 15_T9 of transistor T9 is joined with the gate conductive region 15_T11 of transistor T11. the set of grid conductive regions 15_T9 and 15_T11 forming a tube of axis A with a circular base, and located, in [Fig. 12], below the tube forming the grid conductive regions 15_T8 and 15_T10 and separated from it.

[0066] In the embodiments described above, the thin-film transistors are single-gate transistors. According to one embodiment, at least some transistors in the electronic circuit may be double-gate thin-film transistors.

[0067] [Fig. 14] is a partial, schematic perspective view of an embodiment of an INV2 inverter illustrating the use of double-gate thin-film transistors. The INV2 inverter comprises all the elements of the INV1 inverter shown in [Fig. 10] and further comprises additional insulating regions 25_T6, 25_T7, each corresponding to a sector of a circular-based tube with axis A, the insulating region 25_T6 being located on the side of the inner face 21_T6 of transistor T6, in contact with the semiconductor region 11_T6, and the insulating region 25_T7 being located on the side of the inner face 21_T7 of transistor T7, in contact with the semiconductor region 11_T7.The INV2 inverter further includes additional conductive regions 26_T6 and 26_T7, each corresponding to a sector of a circular-based tube with axis A. Conductive region 26_T6 overlaps and is in contact with insulating region 25_T6, and conductive region 26_T7 overlaps and is in contact with insulating region 25_T7. These additional conductive regions 26_T6 and 26_T7 act as second gates for transistors T6 and T7. Advantageously, these second gates allow for better control of the electrical properties of transistors T6 and T7.

[0068] Figure 15 is a partial, schematic perspective view of one embodiment of the electronic circuit 30. The electronic circuit 30 comprises several electronic components or elementary electronic circuits 32, for example, according to the embodiments described above. In one embodiment, the electronic components or elementary electronic circuits 32 are stacked to form several stacks 34 of electronic components or elementary electronic circuits 32, four stacks 34 being shown by way of example in Figure 15. The electronic components or elementary electronic circuits 32 of the same stack 34 or of different stacks 34 can be connected to each other by conductive tracks formed in the same way as the conductive regions described above. In one embodiment, the stacks 34 are embedded in the matrix 16.The volume density of electronic components in the electronic circuit 30 can advantageously be high.

[0069] Figure 16 is a partial, schematic perspective view of an embodiment of an electromechanical system 40 comprising electronic circuits 30, two electronic circuits 30 being shown as an example in [Fig. 16]. The electronic circuits 30 are embedded in the matrix 16, the external shape of which can correspond to the desired shape of the electromechanical system 40. According to one embodiment, the electromechanical system 40 can advantageously be manufactured entirely by 3D printing. In this case, there are no assembly steps required for the electronic circuits 30 within the electromechanical system 40, as the electronic circuits 30 are formed simultaneously with the electromechanical system 40.

[0070] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will be apparent to those skilled in the art. In particular, the capacitor CAP shown in [Fig. 7] and the light-emitting diode LED shown in [Fig. 8] can have a half-tube structure, as with transistor T4 shown in [Fig. 5], or a hollow sphere structure, as with transistor T5 shown in [Fig. 6].

[0071] Furthermore, in the embodiments described above, electronic circuits have been described in which electronic components are formed in a stacked manner along the same direction as the stacking direction of the contiguous layers deposited by additive manufacturing to form the different regions of these components. However, it is clear that electronic components, in particular thin-film transistors, can be formed in a stacked manner along a direction other than the stacking direction of the contiguous layers deposited by additive manufacturing to form the different regions of these components.As an example, first and second thin-film transistors can be formed according to the embodiments described previously in relation to Figures 3, 4, and 5, and can be stacked radially with respect to axis A, that is, so that the semiconductor regions of these transistors have the shape of tubes, or tube sectors, with axis A, the semiconductor region of the first transistor being located inside the conducting region of the second transistor. Similarly, as another example, first and second thin-film transistors can be formed according to the embodiment described previously in relation to [Fig.6], and can be stacked radially with respect to the center C, that is, so that the semiconductor regions of these transistors have the shape of hollow spheres, or caps of hollow spheres, with center C, the semiconductor region of the first transistor being located inside the conducting region of the second transistor.

[0072] Furthermore, in the embodiments described above, electronic circuits have been described in which electronic components are formed by additive manufacturing with the same stacking direction of the adjacent layers deposited to form the different regions of these components. However, it is clear that the electronic circuit may include first and second electronic components, including thin-film transistors, whereby the first electronic component is formed by additive manufacturing with a first stacking direction of the contiguous layers deposited to form the different regions of this first component and the second electronic component is formed by additive manufacturing with a second stacking direction of the contiguous layers deposited to form the different regions of this second component, the first stacking direction being inclined with respect to the second stacking direction.

[0073] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Electronic circuit (10; 30) comprising electronic components (T1; T2; T3; T4; T5), at least one of the electronic components comprising a semiconductor region (11_T1; 11_T2; 11_T3; 11_T4; 11_T5) comprising a stacking of at least three semiconductor layers of the same semiconductor material in a first stacking direction (D).

2. Electronic circuit according to claim 1, wherein all the electronic components (T1; T2; T3; T4; T5) are embedded in a dielectric matrix (16) comprising a stacking of at least three dielectric layers (16L) of the same dielectric material along the first stacking direction (D) or a second stacking direction inclined with respect to the first stacking direction.

3. An electronic circuit according to claim 1 or 2, wherein said at least one of the electronic components (T1; T2; T3; T4; T5) is a thin-film transistor (T1; T2; T3; T4; T5) further comprising an electrically insulating region (14_T1; 14_T2; 14_T3; 14_T4; 14_T5) in contact with the semiconductor region (11_T1) and forming the gate insulator of the thin-film transistor (T1; T2; T3; T4; T5), and a first electrically conductive region (15_T1; 15_T2; 15_T3; 15_T4; 15_T5) covering the electrically insulating region (14_T1; 14_T2; 14_T3; 14_T4; 14_T5), in contact with the electrically insulating region (14_T1; 14_T2; 14_T3; 14_T4; 14_T5), and forming the gate of the thin-film transistor (T1; T2; T3; T4;T5), the electrically insulating region comprising a stack of at least three electrically insulating layers (14L) of the same electrically insulating material along the first stacking direction (D) or a third stacking direction inclined with respect to the first stacking direction and the first electrically conducting region comprising a stack of at least three first electrically conducting layers (15L) of the same electrically conducting material along the first stacking direction (D) or a fourth stacking direction inclined with respect to the first stacking direction.;

4. Electronic circuit according to claim 3, wherein the thin-film transistor (T1; T3; T4; T5) further comprises a second electrically conductive region (12_T1; 12_T3; 12_T4; 12_T5) in contact with the semiconductor region (11_T1; 11_T3; 11_T4; 11_T5) and a third electrically conductive region (13_T1; 13_T3; 13_T4; 13_T5) in contact with the semiconductor region (11_T1; 11_T3; 11_T4;11_T5), the second electrically conductive region comprising a stacking of at least three second electrically conductive layers (12L) of the same electrically conductive material along the first stacking direction (D) or a fifth stacking direction inclined with respect to the first stacking direction and the third electrically conductive region comprising a stacking of at least three third electrically conductive layers (13L) of the same electrically conductive material along the first stacking direction (D) or a sixth stacking direction inclined with respect to the first stacking direction.;

5. Electronic circuit according to any one of claims 1 to 4, wherein the semiconductor region (11_T1; 11_T2; 11_T3; 11_T4) has the shape of a tube or a tube sector.

6. Electronic circuit according to any one of claims 1 to 4, wherein the semiconductor region (11_T5) has the shape of a hollow sphere or a hollow sphere cap.

7. Electromechanical system (40) comprising a body (16) in which is embedded at least one electronic circuit according to any one of claims 1 to 6.

8. Method of manufacturing an electronic circuit (10; 30) comprising electronic components (T1; T2; T3; T4; T5), at least one of the electronic components comprising a semiconductor region (11_T1; 11_T2; 11_T3; 11_T4; 11_T5), the formation of the semiconductor region comprising the formation of a stack of at least three semiconductor layers of the same semiconductor material in a first stacking direction (D).

9. A method according to claim 8, comprising the formation of a dielectric matrix (16) comprising a stack of at least three dielectric layers (16L) of the same dielectric material according to the first stacking direction (D) or a second stacking direction inclined relative to the first stacking direction in which all the electronic components are embedded (T1; T2; T3; T4; T5).

10. A method according to claim 8 or 9, wherein said at least one of the electronic components (T1; T2; T3; T4; T5) is a thin-film transistor (T1; T2; T3; T4; T5) further comprising an electrically insulating region (14_T1; 14_T2; 14_T3; 14_T4; 14_T5) in contact with the semiconductor region (11_T1) and forming the gate insulator of the thin-film transistor (T1; T2; T3; T4; T5), and a first electrically conductive region (15_T1; 15_T2; 15_T3; 15_T4; 15_T5) covering the electrically insulating region (14_T1; 14_T2; 14_T3; 14_T4; 14_T5), in contact with the electrically insulating region (14_T1; 14_T2; 14_T3; 14_T4; 14_T5), and forming the gate of the thin-film transistor (T1; T2; T3; T4;T5), the formation of the electrically insulating region comprising the formation of a stack of at least three electrically insulating layers (14L) of the same electrically insulating material along the first stacking direction (D) or a third stacking direction inclined with respect to the first stacking direction and the formation of the first electrically conductive region comprising the formation of a stack of at least three first electrically conductive layers (15L) of the same electrically conductive material along the first stacking direction (D) or a fourth stacking direction inclined with respect to the first stacking direction.;

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