Method for making a CFET transistor device

Abstract

Method for embedding a CFET transistor device. This description relates to a method for embedding a CFET transistor device, comprising at least: - fabrication, on a first substrate (108), of a first semiconductor superlattice (102) surmounted by a first interface layer (122) comprising at least amorphous semiconductor or metal or a semiconductor-metal composite; - fabrication, on a second substrate (116), of a second semiconductor superlattice (110) surmounted by a second interface layer (128) comprising at least amorphous semiconductor or metal or a semiconductor-metal composite; - bonding the first and second interface layers to each other; and wherein the first and second interface layers are configured to be selectively etched with respect to the semiconductor superlattices. Figure for the abstract: Fig. 3

Description

Title of the invention: Method for implementing a CFET transistor device. Technical field

[0001] This description relates generally to the field of semiconductor device manufacturing, and more particularly to the realization of CFET (Complementary Field-Effect Transistors) devices. Previous technique

[0002] A CFET transistor device comprises, on a substrate, superimposed semiconductor nanosheets forming the active regions of transistors of different conductivity types, nMOS and pMOS. The nanosheets forming the active regions of the nMOS transistors are separated from those forming the active regions of the pMOS transistors by dielectric material.

[0003] The nanosheet stacks used for the realization of a CFET transistor device can be manufactured in two different ways: monolithic or sequential.

[0004] The monolithic fabrication of these stacks consists of successively creating, one on top of the other, on a substrate and by continuous epitaxy, two stacks of layers, or superlattices, used to create the active regions of different types of transistors. Each stack of layers typically comprises layers of silicon and layers of SiGe arranged alternately on top of each other. The thickness of each of these layers is generally about 10 nm, and the percentage of germanium in the SiGe layers is generally between about 20% and 30%.

[0005] The two superlattices are generally separated from each other by a sacrificial layer of SiGe with a significantly higher germanium content than the SiGe layers of the superlattices. This allows for selective etching of the sacrificial layer, for example with a solution of Br2 or ammonia and hydrogen peroxide, or with gaseous hydrogen chloride, relative to the layers of the superlattices. The free space created by etching this sacrificial layer is then filled with a dielectric material to electrically separate and insulate the two superlattices from each other.

[0006] However, the monolithic fabrication of superlattices by epitaxy presents constraints because, given the number of SiGe layers required, the percentage of germanium required, and the thickness of the superlattices, the structure to be fabricated has a The total thickness is very close to its critical plastic relaxation thickness, which results in the generation of numerous crystal defects and dislocations if this critical thickness is exceeded. This process requires performing epitaxy at a temperature below approximately 550°C, or even below approximately 500°C, using dedicated precursors such as Si2H6 and Ge2H6. These precursors are not readily usable because there is a risk of amorphous inclusion formation in the layers due to their high reactivity in the gas phase. The thickness of the superlattices and the number of their layers are therefore limited. Furthermore, the limited percentage of germanium achievable in the SiGe layers of the superlattices and in the sacrificial layer complicates the selective etching techniques required.

[0007] Another constraint related to the monolithic realization of superlattices is that it is not possible to realize two superlattices whose semiconductor layers would have different crystalline orientations in order to optimize the electrical characteristics for each type of transistor (the mobility of electrons being better in a semiconductor with a crystalline orientation (100), and that of holes being better in a semiconductor with a crystalline orientation (110)).

[0008] The sequential fabrication of these stacks consists of separately producing, on different substrates, the stacks of layers used to create the active regions of different types of transistors in the form of two independent and distinct structures, and then joining them by bonding. One of the two substrates used is then removed, leaving only one to support the resulting assembly.

[0009] Compared to monolithic manufacturing, sequential manufacturing of supernetworks allows each of them to be optimized separately before bonding, and thus consider obtaining higher-performing CFET transistors.

[0010] The bonding is carried out between two dielectric layers, each formed at the top of one of the fabricated superlattices. Ideally, the thicknesses of these dielectric layers are small, typically such that the total thickness of the dielectric material between the superlattices is less than 50 nm. The bonding is generally a direct hydrophilic bond. A consolidation annealing of the bond at a temperature greater than or equal to 500°C, for example, on the order of 650°C or 700°C, is then carried out.

[0011] However, it is very difficult to achieve direct hydrophilic bonding with such thin dielectric layers because defects will be generated at the bonding interface during the annealing process used to consolidate the interface. Indeed, defects appear at the bonding interface when the consolidation annealing is carried out at a temperature of 500°C or higher. These defects are created This is due to water trapped at the bonding interface, which passes through the dielectric layers and reacts with the semiconductor against which the dielectric layers are placed. This reaction generates hydrogen gas, which becomes trapped and leads to the formation of bubbles at the bonding interface. Summary of the invention

[0012] There is a need to propose a method for implementing a CFET transistor device that does not have the disadvantages of known methods of implementation.

[0013] An embodiment overcomes all or part of the drawbacks of known methods and proposes a method for implementing a CFET transistor device, comprising at least:

[0014] - realization, on a first substrate, of a first stack comprising at a first semiconductor layer and a second semiconductor layer arranged one on top of the other, one of the first and second semiconductor layers being configured to be selectively etched with respect to the other, a first interface layer comprising at least amorphous semiconductor or metal or a semiconductor and metal compound being subsequently made on the first stack;

[0015] - realization, on a second substrate, of a second stack comprising at least a third semiconductor layer and a fourth semiconductor layer arranged one on top of the other, one of the third and fourth semiconductor layers being configured to be selectively etched with respect to the other, a second interface layer comprising at least amorphous semiconductor or metal or a semiconductor and metal compound being subsequently made on the second stack;

[0016] - bonding of the first and second interface layers to each other;

[0017] and in which the first and second interface layers are configured to be selectively etched with respect to the first, second, third and fourth semiconductor layers.

[0018] According to a particular embodiment, the process further comprises, after the first stacking and before the first interface layer is created, a first dielectric layer is created on the first stack, the first interface layer is then created on the first dielectric layer, and / or further comprises, after the second stacking and before the second interface layer is created, a second dielectric layer is created on the second stack, the second interface layer is then created on the second dielectric layer.

[0019] According to a particular embodiment, the fabrication of the first dielectric layer comprises a thermal or chemical oxidation of the first semiconducting layer or a chemical vapor deposition, and / or the fabrication of the second dielectric layer comprises a thermal or chemical oxidation of the third semiconducting layer or a chemical vapor deposition.

[0020] According to a particular embodiment, the first and third semiconductor layers comprise silicon, and / or the second and fourth semiconductor layers comprise SiGe.

[0021] According to a particular embodiment, the first and second interface layers comprise amorphous germanium, or amorphous SiGe with a germanium concentration greater than that of the second and fourth semiconductor layers, or titanium, or an amorphous compound of silicon, germanium and tin, or an amorphous III-V semiconductor.

[0022] According to a particular embodiment, the process further comprises, after the fabrication of the first dielectric layer and before the fabrication of the first interface layer, a deposition of a first layer of amorphous silicon on the first dielectric layer, the first interface layer being then fabricated on the first layer of amorphous silicon, and / or further comprises, after the fabrication of the second dielectric layer and before the fabrication of the second interface layer, a deposition of a second layer of amorphous silicon on the second dielectric layer, the second interface layer being then fabricated on the second layer of amorphous silicon.

[0023] According to a particular embodiment, the thickness of each of the first and second layers of amorphous silicon is between approximately 1 and 2 nm, and / or the thickness of each of the first and second interface layers is between approximately 5 and 50 nm, and advantageously between 5 nm and 10 nm.

[0024] According to a particular embodiment, the bonding is a surface activation bonding.

[0025] According to a particular embodiment, the bonding is an atomic diffusion bonding, and the first and second interface layers are deposited respectively within the same equipment as that used for the implementation of the bonding.

[0026] According to a particular embodiment, the process further comprises, after the bonding of the first and second interface layers to each other, a consolidation anneal carried out at a temperature lower than a temperature causing plastic relaxation of the layers subjected to this consolidation anneal.

[0027] According to a particular embodiment, one of the first and second substrates comprises crystalline orientation silicon (100), and / or the other of the first and second substrates comprises crystalline orientation silicon (110).

[0028] According to a particular embodiment, the first stack comprises several first semiconductor layers and several second semiconductor layers arranged alternately on top of each other, and / or the second stack comprises several third semiconductor layers and several fourth semiconductor layers arranged alternately on top of each other.

[0029] According to a particular embodiment, the process further comprises, after bonding, etching several trenches through the first and second stacks such that remaining portions of the first or second semiconductor layers and remaining portions of the third or fourth semiconductor layers form nanosheets configured to form the channels of the CFET transistors.

[0030] According to a particular embodiment, the process further comprises, after the engraving of the trenches, an engraving of the first and second interface layers selectively with respect to the first and second stacks, and then a deposition of at least one dielectric material in void spaces formed by the engraving of the first and second interface layers.

[0031] According to a particular embodiment, the method further comprises etching remaining portions of the first or second semiconductor layer and / or etching remaining parts of the third or fourth semiconductor layer, and deposition of a gate dielectric and a gate conductive material around first parts of the remaining portions of the semiconductor layers forming channels of the CFET transistors, and epitaxy forming source and drain of the CFET transistors. Brief description of the drawings

[0032] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0033] - [Fig.l], [Fig.2], [Fig.3], [Fig.4], [Fig.5], [Fig.6] and [Fig.7] schematically represent steps in an example of a process for manufacturing a CFET transistor device according to a first embodiment;

[0034] - Figure 8 schematically represents one of the steps in an example of a process realization of a CFET transistor device according to a second embodiment. Description of the implementation methods

[0035] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional, and material properties. In the figures, to facilitate their reading, the different elements and the different material layers are not shown at the same scale relative to each other.

[0036] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, various steps implemented after the dielectric deposition between the nanosheet stacks and relating to the fabrication of the CFET transistor elements other than the nanosheets are not detailed. Those skilled in the art will be able to implement such steps based on the description given here.

[0037] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements linked or coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0038] In the following description, when reference is made to absolute position qualifiers, such as "front," "back," "top," "bottom," "left," "right," etc., or relative position qualifiers, such as "above," "below," "superior," "inferior," etc., or to orientation qualifiers, such as "horizontal," "vertical," etc., unless otherwise specified, reference is made to the orientation of the figures in a normal operating position. However, these terms do not imply the actual position and orientation of the device during use.

[0039] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "in the order of" mean to the nearest 10%, preferably to the nearest 5%. Furthermore, unless otherwise indicated, the ranges of values ​​shown include the bounds of those ranges.

[0040] An example of a method for making a CFET transistor device according to a first embodiment is described below in relation to figures 1 to 7.

[0041] A first stack 102 comprising at least one first semiconductor layer 104 and at least one second semiconductor layer 106 arranged one on top of the other is produced by epitaxy on a first substrate 108. The first stack 102 forms a first super-lattice of semiconductor layers 104, 106 arranged on the first substrate 108. The first substrate 108 corresponds, for example, to a bulk semiconductor substrate or SOI (Silicon-On-Insulator), or any type of substrate suitable for the fabrication of the first stack 102. In the particular embodiment described here, the first substrate 108 corresponds to a bulk silicon substrate.

[0042] When the first semiconductor layer(s) 104 are intended for use in the realization of active regions of nMOS transistors, the first substrate 108 may comprise silicon with a crystalline orientation (100). When the first semiconductor layer(s) 104 are intended for use in the realization of active regions of pMOS transistors, the first substrate 108 may comprise silicon with a crystalline orientation (110). When the first substrate 108 is of the bulk type, the entire semiconductor, for example silicon, of the first substrate 108 may have this crystalline orientation. When the first substrate 108 is of the SOI type, the semiconductor of the surface semiconductor layer of the first substrate 108 may have this crystalline orientation, although the orientation of the semiconductor of the bulk layer of the SOI substrate may or may not be different.

[0043] In the example described, because the semiconductor layers 104, 106 of the first stack 102 are made by epitaxy from the top face of the first substrate 108, the crystalline orientation of the semiconductor from which the epitaxy is carried out is also that of the semiconductors of these layers 104, 106. Thus, electron mobility is favored when the active regions of nMOS transistors are made from a semiconductor with a crystalline orientation (100), and hole mobility is favored when the active regions of pMOS transistors are made from a semiconductor with a crystalline orientation (110).

[0044] The semiconductors of the first and second layers 104, 106 are such that one of the first and second layers 104, 106 can be selectively etched with respect to the other. This etching selectivity will subsequently be used, for example, to etch the second layer 106, particularly when creating a gate around a portion of the first layer 104 intended to form the channel of one of the CFET transistors, or to etch the first layer 104, particularly when creating a gate around a portion of the second layer 106 intended to form the channel of one of the CFET transistors. In the example described, the first stack 102 is constructed such that the first layer 104 contains silicon and the second layer 106 contains SiGe. Conversely, it is possible for the first layer 104 to contain SiGe and the second layer 106 to contain silicon.The layer not intended for etching may contain SiGe to promote hole mobility in pMOS transistor channels, or it may contain silicon. For example, the germanium content of the SiGe is between approximately 20% and 40%, and preferably between approximately 25% and 30%.

[0045] In the example described, the thickness of each of the first and second layers 104, 106 can be between about 5 nm and 15 nm, and preferably between about 8 nm and 12 nm.

[0046] The number of first layers 104 and second layers 106 of the first stack 102 depends on the number of nanosheets intended to form the active regions of the transistors, which will be subsequently fabricated from these nanosheets. Advantageously, the first stack 102 comprises several first layers 104 and several second layers 106 arranged alternately on top of each other. In the example of [Fig. 1], the first stack 102 comprises four first layers 104 and four second layers 106. For example, the first stack 102 may have a total number of layers 104, 106 ranging from three to fifteen, or even more, for example up to about thirty.

[0047] As an alternative to the example described above, the first stack 102 may include additional layers of materials in addition to those described above.

[0048] A second stack 110 comprising at least a third semiconductor layer 112 and at least a fourth semiconductor layer 114 arranged one on top of the other is carried out by epitaxy on a second substrate 116. The second stack 110 forms a second super-lattice of semiconductor layers 112, 114 arranged on the second substrate 116. The second substrate 116 corresponds, for example, to a bulk semiconductor or SOI substrate, or any type of substrate suitable for carrying out the second stack 110.

[0049] In the particular embodiment described here, the second substrate 116 corresponds to an SOI substrate. This SOI substrate comprises a bulk silicon layer, an embedded oxide layer, and a surface silicon layer. In the various figures, however, the second substrate 116 is represented as a single layer.

[0050] When the third semiconductor layer(s) 112 are intended for use in the realization of active regions of nMOS transistors (and therefore when the first semiconductor layer(s) 104 are intended for use in the realization of active regions of pMOS transistors), the second substrate 116 may comprise crystallinely oriented silicon (100). When the third semiconductor layer(s) 112 are intended for use in the realization of active regions of pMOS transistors (and therefore when the first semiconductor layer(s) 104 are intended for use in the realization of active regions of nMOS transistors), the second substrate 116 may comprise crystallinely oriented silicon (110). When the second substrate 116 is of the bulk type, the entire semiconductor, for example silicon, of the second substrate 116 may have this crystalline orientation. When the second substrate 116 is of type SOI, the semiconductor of the surface semiconducting layer of the second substrate 116 can have this crystalline orientation, that of the semiconductor of the bulk layer of the SOI substrate may be different or not.

[0051] In the example described, because the semiconductor layers 112, 114 of the second stack 110 are made by epitaxy from the top face of the second substrate 116, the crystalline orientation of the semiconductor from which the epitaxy is carried out is also that of the semiconductors of these layers 112, 114. Thus, electron mobility is favored when the active regions of nMOS transistors are made from semiconductor with crystalline orientation (100), and hole mobility is favored when the active regions of pMOS transistors are made from semiconductor with crystalline orientation (110).

[0052] The semiconductors of the third and fourth layers 112, 114 are such that one of the third and fourth layers 112, 114 can be selectively etched with respect to the other. This etching selectivity will subsequently be used to etch the fourth layer 114 when fabricating a gate around a portion of the third layer 112 intended to form the channel of one of the CFET transistors, or to etch the third layer 112, in particular, when fabricating a gate around a portion of the fourth layer 114 intended to form the channel of one of the CFET transistors. In the described embodiment, the second stack 110 is constructed such that the third layer 112 comprises silicon and the fourth layer 114 comprises SiGe. Conversely, it is possible for the third layer 112 to comprise SiGe and the fourth layer 114 to comprise silicon.The layer not intended for etching may contain SiGe to promote hole mobility in pMOS transistor channels, or it may contain silicon. For example, the germanium content of the SiGe is between approximately 20% and 40%, and preferably between approximately 25% and 30%.

[0053] In the example described, the thickness of each of the third and fourth layers 112, 114 can be between about 5 nm and 15 nm, and preferably between about 8 nm and 12 nm.

[0054] The number of third layers 112 and fourth layers 114 of the second stack 110 depends on the number of nanosheets intended to form the active regions of the transistors, which will be subsequently fabricated from these nanosheets. Advantageously, the second stack 110 comprises several third layers 112 and several fourth layers 114 arranged alternately on top of each other. In the example of [Fig. 1], the second stack 110 comprises four third layers 112 and four fourth layers 114. For example, the second stack 110 may comprise a total number of third layers 112 and fourth layers 114 between three and fifteen, or even more, for example up to about thirty, this number of layers being either identical or not to that of the number of layers of the first stacking 102.

[0055] As an alternative to the example described above, the second stack 112 may include additional layers of materials in addition to those described above.

[0056] The structures obtained at this stage of the process are shown schematically in [Fig.1].

[0057] In the particular embodiment described, a first dielectric layer 118 is formed at the top of the first stack 102, that is, on the last of the first layers 104 formed in the example described here (or on the first layer 104 when the first stack 102 has only one first layer 104). For example, the first dielectric layer 118 may correspond to a SiO2 layer produced by chemical oxidation or by chemical vapor deposition, assisted or not by plasma, at low temperature, that is, for example, at a temperature between 400°C and 500°C.Alternatively, this SiO2 layer can be deposited by high-temperature chemical vapor deposition or formed by thermal oxidation, for example at temperatures close to 700°C, the processing temperature for forming this layer being chosen such that plastic relaxation of the layers on which the first dielectric layer 118 is made is avoided. The thickness of the first dielectric layer 118 is, for example, between approximately 1 nm and 2 nm.

[0058] Alternatively, the first dielectric layer 118 may comprise an oxide other than SiO2, or a dielectric material other than an oxide.

[0059] Alternatively, the first dielectric layer 118 may correspond to a stack of several superimposed layers comprising different dielectric materials.

[0060] Alternatively, it is possible not to make the first dielectric layer 118 on the first stack 102.

[0061] In the first embodiment described, a first layer of amorphous silicon 120 is deposited on the first dielectric layer 118. This deposition is, for example, carried out in the same mold as that used for the epitaxy of the first and second semiconductor layers 104, 106, for example at a temperature of approximately 500°C, under a pressure of 20 Torr, and using Si2H6 compounds. Further implementation details for the fabrication of the first layer of amorphous silicon 120 are described in US patent 2022 / 319910 AL. This first layer of amorphous silicon 120 has, for example, a thickness of between approximately 1 nm and 2 nm.

[0062] A first interface layer 122 is then formed on the first layer of amorphous silicon 120. In the example described, the first interface layer 122 comprises amorphous SiGe having a germanium concentration higher than those of the second and fourth semiconductor layers 106, 114. For example, the germanium concentration of the SiGe in the first interface layer 122 is greater than or equal to approximately 50%. Alternatively, the first interface layer 122 may comprise amorphous germanium, or titanium, or an amorphous compound of silicon, germanium, and tin, or an amorphous III-V semiconductor such as GaAs or InP.Whatever the material or materials of the first interface layer 122, this material or these materials are chosen such that the first interface layer 122 can be selectively etched with respect to the layers of the first and second stacks 102, 110, i.e. with respect to the first, second, third and fourth layers 104, 106, 112, 114 in this example.

[0063] For example, the thickness of the first interface layer 122 is between approximately 5 nm and 50 nm, and advantageously between 5 nm and 10 nm. The first interface layer 122 can be produced by a deposition carried out in the same frame as that used for the epitaxy of the first and second semiconductor layers 104, 106, for example at a temperature of approximately 400°C, under a pressure of 100 Torr and using compounds of SiH4 or SiH2Cl2 or Si2H6, with compounds of GeH4. In the example, the first layer of amorphous silicon 120 forms a wetting layer facilitating the growth of the first interface layer 122 comprising amorphous SiGe or amorphous Ge and avoids the selectivity of the growth of these materials with GeH4 compared to the SiO2 of the first dielectric layer 118.

[0064] In the particular embodiment described, a second dielectric layer 124 is formed on top of the second stack 110, that is, on the last of the third layers 112 in the example described here (or on the third layer 112 when the second stack 110 has only one third layer 112). For example, the second dielectric layer 124 is similar to the first dielectric layer 118.

[0065] The features and embodiment variants previously described for the first dielectric layer 118 can be applied to the second dielectric layer 124.

[0066] In the first embodiment described, a second layer of amorphous silicon 126 is deposited on the second dielectric layer 124. The second layer of amorphous silicon 126 is, for example, similar to the first layer of amorphous silicon 120. The characteristics previously described for the first amorphous silicon layer 120 can be applied to the second layer of amorphous silicon 126.

[0067] A second interface layer 128, for example similar to the first interface layer 122, is then made on the second layer of amorphous silicon 126. The characteristics previously described for the first interface layer 122 can be applied to the second interface layer 128. In particular, whatever the material or materials of the second interface layer 128, this or these materials are chosen such that the second interface layer 128 can be selectively etched with respect to the layers of the first and second stacks 102, 110, i.e. with respect to the first, second, third and fourth layers 104, 106, 112, 114 in this example.

[0068] Before or after the creation of stacks 102, 110 and the various layers 118, 120, 122, 124, 126 and 128 previously described, one or more processing, preparation or cleaning steps of the surfaces of these layers or of the surfaces on which these layers are made can be implemented.

[0069] The structures obtained at this stage of the process are schematically represented in [Fig.2],

[0070] The first and second interface layers 122, 128 are then bonded together. In the example described here, this bonding is achieved by implementing surface activated bonding (SAB), or covalent bonding, of the first and second interface layers 122, 128 against each other. In such a bonding process, when determining the thicknesses of the interface layers 122, 128, it is necessary to take into account that this SAB bonding technique can consume a few nanometers of material from these interface layers 122, 128 during the surface activation of these layers. Such SAB bonding notably includes the application of ion bombardment to the surfaces to be bonded in order to form covalent bonds on these surfaces before they are brought into contact with each other.

[0071] The detailed implementation of such a SAB bonding is described, for example, in US document 2022 / 319910 A1, the details given in this document being applicable to the implementation of the bonding described in this example.

[0072] Optionally, a consolidation anneal of the bonding interface, making the resulting stack more robust against subsequent technological steps, can be implemented. Such an anneal can be carried out at a temperature higher than the temperatures at which the individual layers are previously produced, for example, above approximately 500°C. The duration of this anneal can be inversely proportional to the annealing temperature. For example, the annealing time can be a few The annealing process takes minutes when its processing temperature is around 400°C, and can last only a few seconds when its temperature is around 750°C. The thermal budget of this annealing is such that the assembly subjected to this annealing is not plastically relaxed and therefore not crystallographically defective.

[0073] The structure obtained at this stage of the process is shown in [Fig.3].

[0074] In the described embodiment, at least part of the second substrate 116 is removed. When the second substrate 116 is a SOI substrate, this removal may involve the removal of the bulk layer of the SOI substrate, for example, by successively implementing grinding, CMP (chemical-mechanical polishing), and wet etching steps using the buried oxide layer as a stop layer. The buried oxide layer is then removed, for example, using an HF solution. When the second substrate 116 is a bulk substrate, this removal may involve the removal of the entire second substrate 116, for example, by successively implementing grinding, CMP (chemical-mechanical polishing), and wet etching steps using the fourth semiconductor layer 114 as a stop layer.To facilitate the implementation of this removal, it is possible to plan, before the realization of the second stack 110 on the second substrate 116, the realization of a sacrificial etching stop layer comprising for example SiGe, the second stack 110 being carried out on this sacrificial layer.

[0075] The structure obtained at this stage of the process is shown in [Fig.4].

[0076] Trenches 130 are then etched through the first and second stacks 102, 110 and the various layers interposed between the stacks 102, 110. In the example of [Fig. 5], the trenches 130 are etched through all the layers present on the first substrate 108. For example, one or more photolithography and etching steps can be implemented to define and form the trenches 130 such that remaining portions of the first and second stacks 102, 110 and of the layers present between the stacks 102, 110 form fins, or fins (“fin” in English) of a width (dimension along the X-axis visible on [Fig. 5]) for example equal to a few tens of nanometers. The remaining portions of the first and third layers 104, 112 form, in this example, stacks of nanosheets configured to form the active regions of the CFET transistors of the device produced.

[0077] In the described embodiment, after the etching of the trenches 130, the first and second interface layers 122, 128 are selectively etched with respect to the other materials present, in particular with respect to the semiconducting layers 104, 106, 112, 114 of the first and second stacks 102, 110 (see [Fig. 6]). When the first and second interface layers 122, 128 contain For amorphous SiGe or amorphous Ge, selective etching of these layers can be carried out by wet chemical methods, for example using an SCI-type solution (a mixture of 30% ammonia, 30% hydrogen peroxide, and water, for example in proportions of 1:1:5) or a mixture of HF, nitric acid, and acetic acid, or with low-temperature gaseous hydrogen chloride in an epitaxial frame, or even with a CF4-based remote plasma. The voids 132 formed by this etching can then be filled with at least one dielectric material, for example by implementing a conformal deposition of dielectric material. Portions 134, including for example SiO2, can be obtained, these portions 134 separating and electrically insulating the semiconductor nanosheets from the stacks 102, 110.

[0078] The structure obtained at this stage of the process is shown in [Fig.7].

[0079] The CFET transistors are completed from the stacks of nanosheets obtained. The steps implemented to complete the realization of the CFET transistors are, for example, similar to those described in the document “3-D Self-aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore's Law Scaling”, C.-Y. Huang et al., Technical Digest, International Electron Devices Meeting, IEDM, 2020, pp. 20.6.1-20.6.4, or in the document by S. Liao et al., “Complementary Field-Effect Transistor (CFET) Demonstration at 48nm Gate Pitch for Future Logic Technology Scaling”, 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023, pp. 1-4.In general, the fabrication of CFET transistors from the structure obtained after the fabrication of the portions 134 involves at least the fabrication of gates which includes a selective etching of the remaining portions of the second and fourth semiconductor layers 106, 114 with respect to the layers 104, 112, and a deposition of a gate dielectric and a gate conductive material around a part of the remaining portions of the first and third semiconductor layers 104, 112, and the implementation of selective epitaxies to form protrusions on either side of the remaining portions of the first and third semiconductor layers 104, 112 and thus form source and drain regions of the transistors.

[0080] Alternatively, the fabrication of CFET transistors from the structure obtained after the fabrication of portions 134 may at least include the fabrication of gates which includes selective etching of the remaining portions of the first and third semiconductor layers 104, 112 with respect to layers 106, 114, and deposition of a gate dielectric and a gate conductive material around a portion of the remaining portions of the second and fourth semiconductor layers 106, 114, and the implementation of doping in protrusions selectively deposited on either side of the remaining portions of the second and Fourth semiconductor layers 106, 114 are used to form the source and drain regions of the transistors. Other steps, not detailed here, are also implemented to complete the fabrication of the CFET transistors. If selective etching of layers 106 and 112 relative to layers 104 and 114, or selective etching of layers 104 and 114 relative to layers 106 and 112, is desirable, this selective etching can be carried out in two steps, alternately protecting the flanks of the portions of the fins formed by the remaining portions of the first and second stacks 102, 110 and of the layers present between the stacks 102, 110 of [Fig. 7], which must be preserved during each of these etchings. For example, semiconductor nanosheets forming the channels of pMOS transistors may contain Si or SiGe, and semiconductor nanosheets forming the channels of nMOS transistors may contain Si.

[0081] An example of a method for making a CFET transistor device according to a second embodiment is described below in relation to [Fig.8].

[0082] As in the first embodiment, the first stack 102 is made on the first substrate 108, and the second stack 110 is made on the second substrate 116. The first dielectric layer 118 is also made on the first stack 102, and the second dielectric layer 124 is also made on the second stack 110, as in the first embodiment.

[0083] Unlike the first embodiment, the first and second interface layers 122, 128 are then formed directly on the first and second dielectric layers 118, 124, without first forming the first and second amorphous silicon layers 120, 126

[0084] In this second embodiment, the first and second interface layers 122, 128 can be fabricated respectively on the first and second dielectric layers 118, 124 directly in the ADB (Atomic Diffusion Bonding) equipment, which will then be used to bond the interface layers 122, 128 to each other. The first and second interface layers 122, 128 are, for example, fabricated by sputtering under ultra-high vacuum at low temperature. Such a deposition makes it possible to fabricate amorphous interface layers 122, 128, even if the dielectric layers 118, 124 are absent at the top of the stacks 102, 110. The resulting structures are shown in [Fig. 8].

[0085] The characteristics (materials, thicknesses, etc.) of the interface layers 122, 128 previously described in relation to the first embodiment can also be applied to the second embodiment. Furthermore, the various variants previously described in relation to the first embodiment (materials of the first and second dielectric layers 118, 124; first and second layers) dielectrics 118, 124 corresponding to one and / or the other to a stacking of several superimposed layers; absence of at least one of the first and second dielectric layers 118, 124) may apply to this second embodiment.

[0086] The first and second interface layers 122, 128 are then bonded to each other. In the described embodiment, this bonding is achieved by implementing an ADB bond of the first and second interface layers 122, 128 against each other. The detailed implementation of such an ADB bond is described, for example, in the document "Bonding performance in atomic diffusion bonding of wafers using amorphous Si thin films with smooth surface" by T. Amino et al., Japanese Journal of Applied Physics, 61, SF1002 (2022), the details given in this document being applicable to the implementation of the ADB bond.

[0087] As in the first embodiment, an optional annealing for consolidation of the bonding interface can be implemented.

[0088] The other steps implemented subsequently can be similar to those previously described in connection with the first embodiment: removal of part of the second substrate 116, etching of the trenches 130, etching of the first and second interface layers 122, 128, realization of the portions 134, completion of the realization of the CFET transistors.

[0089] The embodiment method described here proposes to fabricate, within the framework of a sequential fabrication of the superlattices, the first and second interface layers 122, 128 comprising amorphous semiconductor and / or metal. For example, when these interface layers 122, 128 contain SiGe, their amorphous nature allows for the fabrication of SiGe with a high percentage of germanium, for example greater than 50%, or even the use of pure germanium, regardless of the thickness of the interface layers 122, 128, while avoiding plastic relaxation of the compressive stresses that would appear if these layers were fabricated by epitaxy directly onto the first and second stacks 102, 110.The use of amorphous SiGe with a high percentage of germanium (greater than 50%, or greater than or equal to 75% or 80%) or even of pure amorphous germanium for the production of the interface layers 122, 128 further facilitates the selective etching of these layers with respect to those of the first and second stacks 102, 110. .

[0090] Furthermore, the nature of the materials of the first and second interface layers 122, 128 makes it possible to achieve a robust bonding interface, even after consolidation annealing at a relatively low temperature, thus preserving the physico-chemical integrity of the first and second stacks 102, 110. In addition, such an interface makes it possible to limit the infiltration of compounds during the subsequent implementation of wet chemical processes during the fabrication of the FET transistors.

[0091] Furthermore, reusing the first and second interface layers 122, 128 comprising amorphous semiconductor and / or metal avoids the formation of defects at the bonding interface between these layers, unlike a bonding that would be implemented between two dielectric layers.

[0092] The proposed manufacturing process makes it possible to carry out the first and second stacks with a large number of layers and with a total thickness that can be greater than that achievable with prior art processes.

[0093] The proposed manufacturing process also allows the creation of superlattices whose layers have different crystalline orientations.

[0094] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0095] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

1.

2. Demands Method for making a CFET transistor device, comprising at least: - fabrication, on a first substrate (108), of a first stack (102) comprising at least a first semiconducting layer (104) and a second semiconducting layer (106) arranged one on top of the other, one of the first and second semiconducting layers (104, 106) being configured to be selectively etched with respect to the other, a first interface layer (122) comprising at least amorphous semiconductor or metal or a composite of semiconductor and metal being fabricated subsequently on the first stack (102); - fabrication, on a second substrate (116), of a second stack (110) comprising at least a third semiconducting layer (112) and a fourth semiconducting layer (114) arranged one on top of the other, one of the third and fourth semiconducting layers (112, 114) being configured to be selectively etched with respect to the other, a second interface layer (128) comprising at least amorphous semiconductor or metal or a composite of semiconductor and metal being subsequently fabricated on the second stack (110); - bonding of the first and second interface layers (122, 128) to each other; and in which the first and second interface layers (122, 128) are configured to be selectively etched with respect to the first, second, third and fourth semiconductor layers (104, 106, 112, 114). A method according to claim 1, further comprising, after the formation of the first stack (102) and before the formation of the first interface layer (122), the formation of a first dielectric layer (118) on the first stack (102), the first interface layer (122) then being formed on the first dielectric layer (118), and / or further comprising, after the formation of the second stack (110) and before the formation of the second interface layer (128), a realization of a second dielectric layer (124) on the second stack (110), the second interface layer (128) being then made on the second dielectric layer (124).

3. A method according to claim 2, wherein the fabrication of the first dielectric layer (118) comprises a thermal or chemical oxidation of the first semiconducting layer (104) or a chemical vapor deposition, and / or wherein the fabrication of the second dielectric layer (124) comprises a thermal or chemical oxidation of the third semiconducting layer (112) or a chemical vapor deposition.

4. A method according to any one of the preceding claims, wherein the first and third semiconductor layers (104, 112) comprise silicon, and / or wherein the second and fourth semiconductor layers (106, 114) comprise SiGe.

5. A method according to claim 4, wherein the first and second interface layers (122, 128) comprise amorphous germanium, or amorphous SiGe having a germanium concentration greater than that of the second and fourth semiconductor layers (106, 114), or titanium, or an amorphous compound of silicon, germanium and tin, or an amorphous III-V semiconductor.

6. A method according to claims 3 and 5 or according to claims 2 and 5, further comprising, after the formation of the first dielectric layer (118) and before the formation of the first interface layer (122), a deposition of a first layer of amorphous silicon (120) on the first dielectric layer (118), the first interface layer (122) being subsequently formed on the first layer of amorphous silicon (120), and / or further comprising, after the formation of the second dielectric layer (124) and before the formation of the second interface layer (128), a deposition of a second layer of amorphous silicon (126) on the second dielectric layer (124), the second interface layer (128) being subsequently formed on the second layer of amorphous silicon (126).

7. A method according to claim 6, wherein the thickness of each of the first and second layers of amorphous silicon (120, 126) is between approximately 1 and 2 nm, and / or wherein the thickness of Each of the first and second interface layers (122, 128) is between approximately 5 and 50 nm, and advantageously between 5 nm and 10 nm.

8. A method according to any one of claims 6 or 7, wherein the bonding is a surface activation bonding.

9. A method according to any one of claims 1 to 5, wherein the bonding is an atomic diffusion bonding, and wherein the first and second interface layers (122, 128) are deposited respectively within the same equipment as that used for the implementation of the bonding.

10. A method according to any one of the preceding claims, further comprising, after the bonding of the first and second interface layers (122, 128) to each other, a consolidation anneal carried out at a temperature lower than a temperature causing plastic relaxation of the layers subjected to this consolidation anneal.

11. A method according to any one of the preceding claims, wherein one of the first and second substrates (108, 116) comprises silicon with crystal orientation 100, and / or wherein the other of the first and second substrates (108, 116) comprises silicon with crystal orientation 110.

12. A method according to any one of the preceding claims, wherein the first stack (102) comprises several first semiconductor layers (104) and several second semiconductor layers (106) arranged alternately on top of each other, and / or wherein the second stack (110) comprises several third semiconductor layers (112) and several fourth semiconductor layers (114) arranged alternately on top of each other.

13. A method according to any one of the preceding claims, further comprising, after bonding, etching several trenches (130) through the first and second stacks (102, 110) such that remaining portions of the first or second semiconductor layers (104, 106) and remaining portions of the third or fourth semiconductor layers (112, 114) form nanosheets configured to form the channels of the CFET transistors.

14. A method according to claim 13, further comprising, after the engraving of the trenches (130), an engraving of the first and second interface layers (122, 128) selectively with respect to the first and second stacks (102, 110), and then a deposition of at least one dielectric material (134) in void spaces (132) formed by the engraving of the first and second interface layers (122, 128).

15. A method according to claim 14, further comprising etching remaining portions of the first or second semiconductor layer (104, 106) and / or etching remaining parts of the third or fourth semiconductor layer (112, 114), and deposition of a gate dielectric and a gate conductive material around first parts of the remaining semiconductor layer portions forming channels of the CFET transistors, and epitaxy forming source and drain of the CFET transistors.

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