Passive electronic device

Abstract

Passive Electronic Device This description relates to an integrated passive electronic device (201) comprising a stacking, in order, from the top face of a support, of an insulating layer (113), a metallic layer (107), and a passivation layer (109) made of an electrically insulating material, the passivation layer (109) covering the top face and lateral sides of the metallic layer (107), wherein a buffer layer (117), made of another electrically insulating material, different from the material of the passivation layer (109), is formed on the upper edges of the metallic layer (107) between the metallic layer (107) and the passivation layer (109), the buffer layer (117) being in contact with the metallic layer (107). Figure for the abstract: Fig. 2

Description

Title of the invention: Passive electronic device technical field

[0001] This description relates generally to passive electronic devices and more particularly to integrated passive electronic devices. Prior art

[0002] Integrated passive electronic devices correspond to passive electronic components, such as resistors, inductors or capacitors, integrated alone or in groups in the same package or on the same substrate or support.

[0003] It would be desirable to improve at least some aspects of such devices. Summary of the invention

[0004] For this purpose, an embodiment provides an integrated passive electronic device comprising a stacking in order, from an upper face of a support, of an insulating layer, a metallic layer and a passivation layer in an electrically insulating material, the passivation layer covering the upper face and lateral sides of the metallic layer, in which a buffer layer, in another electrically insulating material, different from the material of the passivation layer, is formed on upper edges of the metallic layer between the metallic layer and the passivation layer, the buffer layer being in contact with the metallic layer.

[0005] According to one embodiment, the metallic layer is made of copper.

[0006] According to one embodiment, the passivation layer is made of a polymer material.

[0007] According to one embodiment, the passivation layer is made of polybenzoxazole, in benzocyclobutene and / or a polyimide.

[0008] According to one embodiment, the buffer layer is made of silicon nitride, alumina, aluminum oxide or aluminum nitride.

[0009] According to one embodiment, the buffer layer extends from the edges of the metallic layer on the upper face and the lateral sides of the metallic layer over a width greater than 1.5 pm.

[0010] According to one embodiment, the buffer layer covers a lower part of the lateral sides of the metallic layer.

[0011] According to one embodiment, the device comprises, between the insulating layer and the metallic layer, other insulating and metallic layers.

[0012] According to one embodiment, the buffer layer is made of a material having a breaking strength greater than that of the material of the passivation layer.

[0013] According to one embodiment, the lateral sides of the metallic layer include a portion not covered by the buffer layer.

[0014] Another embodiment provides a method for manufacturing an integrated passive electronic device comprising the following successive steps: - deposition of a buffer layer, on a stack comprising in order, from a top face of a support, an insulating layer and a metallic layer; - deposition of a passivation layer in an electrically insulating material, the passivation layer covering the buffer layer and the upper face and lateral sides of the metallic layer, the buffer layer being in contact with the metallic layer and being made of another electrically insulating material, different from the material of the passivation layer.

[0015] According to one embodiment, the process further comprises an isotropic etching step of the buffer layer so as to remove part of the buffer layer formed on the lateral sides of the metallic layer.

[0016] According to one embodiment, the buffer layer is deposited by a conformal deposition method.

[0017] According to one embodiment, a portion of the buffer layer located directly above a central portion of the metallic layer is removed. Brief description of the drawings

[0018] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0019] [Fig.1A] is a partial and schematic cross-sectional view, illustrating an example of a passive electronic device;

[0020] [Fig.1B] is a graph illustrating the distribution of mechanical stresses within the passive electronic device illustrated in [Fig.1A];

[0021] [Fig.2] is a partial and schematic cross-sectional view, illustrating an example of a passive electronic device according to a first embodiment;

[0022] [Fig. 3] is a partial, schematic cross-sectional view illustrating an example of a passive electronic device according to a second embodiment; and

[0023] [Fig.4] is a partial and schematic cross-sectional view illustrating an example of a passive electronic device according to a third embodiment. Description of the implementation methods

[0024] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0025] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, only a part of a passive device, corresponding to a passive component, has been described here; the device may include other components whose structures and connections have not been described.

[0026] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0027] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0028] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0029] Fig. 1A is a partial, schematic cross-sectional view illustrating an example of a passive electronic device 101.

[0030] The device 101 includes a support 103 on which is formed a stack comprising, in order, from an upper face of the support 103, an insulating layer 105, a metallic layer 107 and a passivation layer 109.

[0031] By way of example, the device 101 further comprises, between the insulating layer 105 and the metallic layer 107, another metallic layer 111 surmounted by another insulating layer 113.

[0032] By way of example, the support 103 is made of a semiconductor material, for example silicon, for example high-resistivity silicon, or of a non-semiconductor material, for example glass. By way of example, the support substrate 103 is made of a material having an electrical resistivity greater than 2.5 kQ.cm.

[0033] The insulating layer 105 is, for example, in contact, via its lower face, with the upper face of the support 103. By way of example, the insulating layer 105 covers the entire upper face of the support 103. By way of example, the insulating layer 105 is a layer made of a dielectric material, for example, an oxide, for example, undoped silicon glass (USG). By way of example, the insulating layer 105 has a thickness between 0.5 pm and 5 pm, for example, on the order of 1.2 pm.

[0034] By way of example, the metallic layer 111 is formed on, and for example in contact by its lower face with, the upper face of the insulating layer 105. The metallic layer 111 extends, for example, over only a portion of the surface of the insulating layer 105. By way of example, the metallic layer 111 is made of aluminum. By way of example, the metallic layer 111 has a thickness of between 0.5 µm and 5 µm, for example, on the order of 1.5 µm.

[0035] By way of example, the insulating layer 113 covers the metal layer 111 and a portion of the insulating layer 105 not covered by the metal layer 111, around the metal layer 111. By way of example, the insulating layer 113 is in contact, by its lower face, with the upper face of the metal layer 111 and a portion of the upper face of the insulating layer 105. By way of example, the insulating layer 113 covers the entire metal layer 111 except for a central portion of the metal layer 111 which is not covered by the insulating layer 113. By way of example, the insulating layer 113 also covers the lateral sides of the metal layer 111. The insulating layer 113 is, for example, made of a dielectric material, for example an oxide, for example undoped silicon glass (USG, etc.). (English "Undoped Silicon Glass").As an example, the insulating layer 113 has a thickness between 0.1 pm and 2 pm, for example on the order of 0.8 pm.

[0036] The metallic layer 107 covers the insulating layer 105. For example, the metallic layer 107 covers only a portion of the insulating layer 105. In the example of [Fig. 1A], the metallic layer 107 also covers the insulating layer 113 and the portion of the metallic layer 111 not covered by the insulating layer 113. For example, the metallic layer 107 is formed directly above the metallic layer 111 and, viewed from above, has a surface area smaller than that of the metallic layer 111. For example, the lower face of the metallic layer 107 is in contact with a portion of the upper face of the insulating layer 113 and the portion of the upper face of the metallic layer 111 not covered by the insulating layer 113. For example, the metallic layer 107 has a width L1 between 10 pm and 275 pm, for example, on the order of 263 pm. The metallic layer 107 is, for example, copper.The metallic layer 107 extends, for example, over a height H1 between 3 pm and 15 pm, for example on the order of 10 pm.

[0037] The passivation layer 109 covers, for example, the structure formed by the layers 105, 111, 113, and 107. More precisely, the passivation layer 109 covers the upper face and the lateral sides of the metallic layer 107. The passivation layer 109 also covers the portion of the upper face of the insulating layer 113 not covered by the metallic layer 107. By way of example, the passivation layer 109 has a flat upper face. The passivation layer 109 is, for example, made of an electrically insulating material. The passivation layer 109 is for example in a polymer material, for example in polybenzoxazole (PBO), benzocyclobutene (BCB) and / or in a polyimide (PI). As an example, the passivation layer 109 extends over the metal layer 107 to a thickness of between 2 pm and 6 pm, for example between 3 pm and 4 pm.

[0038] By way of example, device 101 corresponds to an integrated passive device (IPD) comprising a resistance, an inductance and a capacitance.

[0039] By way of example, the metal layers 107 and 111 have, in top view, a spiral shape extending over the surface of the support 103. The assembly formed by the layers 105, 111, 113, and 107 then corresponds to a coil or inductor of the IPD device 101. Alternatively, the metal layers 107 and 111 have, in top view, a round, square, rectangular, or any other shape. Alternatively, the device 101 corresponds to a passive component other than an inductor, for example, a resistor or a capacitor.

[0040] The support 103 carries for example one or more other components, not shown, such as capacitors or resistors formed near the inductance and electrically connected to the inductance.

[0041] In such a device, the inventors have observed that, during thermal cycling, as part of temperature reliability tests of the devices 101, the passivation layer 109 exhibits cracks extending, within the thickness of the passivation layer 109, from the upper edges of the metal layer 107. Such cracks can penetrate the thickness of the passivation layer 109 to reach, for example, the upper face of the passivation layer 109. By upper edges of the metal layer 107, we mean the junctions between the upper face of the metal layer 107 and each of the lateral flanks of the metal layer 107.

[0042] Such cracks can cause delamination of the metallic layer 107 or the passivation layer 109 and impact the reliability and service life of the components.

[0043] Fig. IB is a graph illustrating the distribution of the mechanical stress experienced within the passive electronic device illustrated in Fig. IA during thermal cycling.

[0044] The graph in [Fig. 1B] illustrates, by means of a curve 115, the mechanical stress received and accumulated along the lower face of the passivation layer 109, represented by a dashed line in [Fig. 1A]. More precisely, in the graph in [Fig. 1B], the curve 115 represents the evolution of the stress, on the ordinate, in megapascals (MPa), as a function of the position (Distance), in micrometers, along the lower face of the passivation layer 109, the origin of which is located, at X3, opposite the center of the metallic layer 107.

[0045] The evolution of the stress along the lower face of the passivation layer 109 shows that the stress is negative and minimal, in XI and XI', on either side of the metallic layer 107, directly above the layer 113, when the latter is in contact with the layer 105. This negative stress value means that the stress received is a compressive stress.

[0046] Along the lower face of the passivation layer 109, towards the center of the metal layer 107, the stress then increases to reach a positive and maximum stress, at X2 and X2' on the edges of the metal layer 107. This positive stress value means that the stress received is a tensile stress.

[0047] Along the central part of the metal layer 107, the stress decreases again, from the edges of the metal layer 107, to reach a constant value, here zero, at X3 in the center of the metal layer 107. This zero stress value means that, at these locations on the lower face of the passivation layer 109, the layer is not subjected to tensile stress or compressive stress.

[0048] The variation in stress is explained by the fact that the electronic device 101 is formed by a succession of several layers of different natures and materials. These layers have, in particular, different thermo-mechanical behaviors and, more specifically, different coefficients of thermal expansion (CTE, the English "Coefficient of Thermal Expansion").

[0049] During thermal cycling, the thermal expansions of the different layers accumulate, generating stress on the lower face of the passivation layer 109. When the locally applied stress exceeds the breaking point (also called ultimate tensile strength and expressed in MPa or N / mm2), the passivation layer 109 cracks, creating, from the point of rupture, the cracks mentioned in relation to [Fig. 1A].

[0050] Figure 2 is a partial, schematic cross-sectional view illustrating an example of a passive electronic device 201 according to a first embodiment. The device in Figure 2 comprises the same elements as the device in Figure 1A, arranged substantially in the same way, and differs from the device in Figure 1A in that it also includes a stress buffer layer 117 (SBL) between the metal layer 107 and the passivation layer 109.

[0051] In the embodiment illustrated in [Fig.2], the buffer layer 117 is formed on the upper edges of the metallic layer 107.

[0052] The buffer layer 117 is made of a material having, for example, a higher breaking strength than the material of the passivation layer 109. The buffer layer 117 is a layer made of a different material than the material of the passivation layer 109. By way of example, the buffer layer 117 is made of an insulating material, for example a dielectric material. The buffer layer 117 is for example made of silicon nitride, alumina, aluminum oxide or aluminum nitride.

[0053] By way of example, the buffer layer 117 is formed on the edges of the metal layer 107 and extends from the edges over the lateral and upper faces of the metal layer 107 to a width L2 greater than 1 µm, for example greater than 1.5 µm. The buffer layer 117 is in contact, by its lower face, with the upper face of the metal layer 107. By way of example, the buffer layer 117 is also in contact, by its upper face, with the lower face of the passivation layer 109.

[0054] By way of example, the buffer layer 117 is formed after the formation of the metallic layer 107 on the stack formed by the layers 105, 111, and 113 on the upper surface of the support 103. By way of example, the buffer layer 117 is formed before the formation of the passivation layer 109. The buffer layer 117 is, for example, formed across the entire plate, that is, over the entire upper surface of the aforementioned stack. By way of example, the buffer layer 117 is deposited by an evaporation deposition process. Alternatively, the buffer layer 117 is deposited by a sputtering deposition process. Yet another alternative, the buffer layer 117 is deposited by an atomic layer deposition (ALD) method. The buffer layer 117 is for example formed in a conformal manner with a thickness between 0.2 pm and 5 pm, for example on the order of 1 pm.

[0055] By way of example, the buffer layer 117 is, following its deposition, locally removed so as to be retained only on and in the vicinity of edges of the metal layer 107. By way of example, the local removal of the buffer layer 117 is carried out by an isotropic type etching so as to be able to remove portions of the buffer layer 117 on the lateral and upper flanks of the metal layer 107.

[0056] By way of example, the local removal of the buffer layer 117 is carried out by wet etching. Alternatively, the local removal of the buffer layer 117 is carried out by physical etching, for example by non-polarized plasma.

[0057] For example, after the formation of the buffer layer 117, the metallic layer 107 has a lower part of its lateral flanks exposed and not covered by the buffer layer 117. For example, after the formation of the buffer layer 117, the metallic layer 107 has a central part of its upper face free and not covered by the buffer layer 117.

[0058] By way of example, although not shown in [Fig. 2], after the formation of the passivation layer 109, it can be etched to form a through-hole opening onto the upper face of the layer metallic 107 allowing, with the help of a conductive layer, the formation of a contact resumption of the metallic layer 107.

[0059] An advantage of the present embodiment is that it allows the thermal expansion to be absorbed at the interface between the layers 107 and 109 and limits the stress received by the lower face of the passivation layer 109 above the buffer layer 117.

[0060] Another advantage of the present embodiment is that the stress received by the lower face of the passivation layer 109 is less than the breaking limit, thus reducing the risk of crack formation in the passivation layer 109.

[0061] Yet another advantage of the present embodiment is that the buffer layer 117 allows the redistribution of the stress accumulated at the edges of the metal layer 107 over the entire upper face of the metal layer 107.

[0062] Fig. 3 is a partial, schematic cross-sectional view illustrating an example of a passive electronic device 301 according to a second embodiment.

[0063] In particular, [Fig.3] illustrates a device 301 similar to the device 201 illustrated in [Fig.2] except that, in the device 301 illustrated in [Fig.3], the buffer layer 117 extends over a lower part of the lateral sides of the metal layer 107 and over the upper face of the oxide layer 113, around the metal layer.

[0064] Fig. 4 is a partial, schematic cross-sectional view illustrating an example of a passive electronic device 401 according to a third embodiment.

[0065] In particular, [Fig. 4] illustrates a device 401 similar to the device 201 illustrated in [Fig. 2], except that, in the device illustrated in [Fig. 4], the buffer layer 117 extends over the entire lateral sides of the metal layer 107. In this embodiment, the buffer layer 117 also extends over the upper face of the oxide layer 113, around the metal layer 107. Furthermore, in this embodiment, the buffer layer 117 extends over the upper face of the metal layer 107 over a larger area than described in the embodiment illustrated in relation to [Fig. 2]. In this embodiment, the buffer layer 117 extends over the entire surface of the upper face of the metallic layer except for a central portion with a width between 10 pm and 75 pm, for example on the order of 30 pm, allowing the resumption of contact of the metallic layer 107.

[0066] In this embodiment, contrary to what has been described in relation to [Fig. 2], the etching of the buffer layer can be anisotropic. Indeed, the portions of buffer layer 117 present on the lateral sides of the metal layer 107 are, in this embodiment, retained.

[0067] An advantage of the third embodiment is that it allows the buffer layer 117 to remain on the sides of the metallic layer 107 and thus simplify the step(s) of etching the buffer layer 117 following its deposition.

[0068] Many applications are likely to benefit from the advantages provided by the electronic device 201, this device 201 being able to be integrated into various types of components.

[0069] By way of example, the device 201 can be integrated into a component intended for the automotive industry. The electrification of motor vehicles is causing a sharp increase in the number of electronic components present in vehicles. By way of example, the device 201 can be integrated into a component intended for industrial use. In particular, the component is used, for example, for the development of green energy or for the electrification of infrastructure, for example, for charging stations or for solar energy collection. The component can also be used in the field of the Internet of Things or in the field of smart homes. The component is, for example, intended to be implemented in electrical power supply circuits for equipment.The component can also be used for the implementation of cloud computing systems, 5G radio frequency communication networks, data centers and servers.

[0070] By way of example, the device 201 can be integrated into a component intended for use in personal electronics, for example implementing radio frequency communication, in 5G communication systems, or more generally in any connected component. The component is, for example, a mobile phone, or smartphone, or is part of an Internet of Things network. The component is, for example, connected via 5G, Wi-Fi, or broadband communication. The component includes, for example, high-speed interfaces, for example with advanced filtering and protection against electrostatic discharge.

[0071] By way of example, the device 201 can be integrated into a component intended for use in communication equipment, or in computers and peripherals. The component is used, for example, in 5G infrastructures and dedicated data centers. The component can also be used in satellites comprising, for example, integrated passive components for radio frequency applications.

[0072] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will become apparent to those skilled in the art. In particular, although the stacking formed by layers 103, 105, 107, and 109 corresponds here to the stacking of a capacitor, it can be foreseen that a buffer layer 117, as described in the embodiments of Figures 2 A buffer layer can be formed in other types of passive components such as inductors (or coils) or resistors. Furthermore, such a buffer layer can be formed more generally at the interface between a metallic layer, for example copper, and a passivation layer, for example a polymer material, such as PBO, BCB, or polyimide, in order to reduce the stress formed on the edges of the copper layer.

[0073] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Integrated passive electronic device (201; 301; 401) comprising a stacking in order, from an upper face of a support, of an insulating layer (113), a metallic layer (107) and a passivation layer (109) of an electrically insulating material, the passivation layer (109) covering the upper face and lateral sides of the metallic layer (107), in which a buffer layer (117), of another electrically insulating material, different from the material of the passivation layer (109), is formed on upper edges of the metallic layer (107) between the metallic layer (107) and the passivation layer (109), the buffer layer (117) being in contact with the metallic layer (107).

2. Device according to claim 1, wherein the metallic layer (107) is made of copper.

3. Device according to claim 1 or 2, wherein the passivation layer (109) is made of a polymer material.

4. Device according to any one of claims 1 to 3, wherein the passivation layer (109) is made of polybenzoxazole, benzocyclobutene and / or a polyimide.

5. Device according to any one of claims 1 to 4, wherein the buffer layer (117) is made of silicon nitride, alumina, aluminum oxide or aluminum nitride.

6. Device according to any one of claims 1 to 5, wherein the buffer layer (117) extends from the edges of the metal layer (107) on the top face and side sides of the metal layer (107) over a width (L2) greater than 1.5 pm.

7. Device according to any one of claims 1 to 6, wherein the buffer layer (117) covers a lower part of the lateral flanks of the metallic layer (107).

8. Device according to any one of claims 1 to 7, comprising, between the insulating layer (105) and the metallic layer (109), other insulating (113) and metallic (111) layers.

9. Device according to any one of claims 1 to 8, wherein the buffer layer (117) is made of a material having a breaking strength greater than that of the material of the passivation layer (109).

10. Device according to any one of claims 1 to 9, wherein the lateral flanks of the metallic layer (107) have a portion not covered by the buffer layer (117).

11. Method of manufacturing an integrated passive electronic device (201; 301; 401) comprising the following successive steps: - deposition of a buffer layer (117), on a stack comprising in order, from an upper face of a support (103), an insulating layer (113) and a metallic layer (107); - deposition of a passivation layer (109) of an electrically insulating material, the passivation layer (109) covering the buffer layer (117) and the upper face and lateral sides of the metallic layer (107), the buffer layer (117) being in contact with the metallic layer (107) and being of another electrically insulating material, different from the material of the passivation layer (109).

12. A method according to claim 11, further comprising an isotropic etching step of the buffer layer (117) so as to remove a portion of the buffer layer (117) formed on the lateral sides of the metal layer (107).

13. A method according to claim 11 or 12 wherein the deposition of the buffer layer (117) is carried out by a conforming deposition method.

14. A method according to any one of claims 11 to 13, wherein a portion of the buffer layer (117) located above a central portion of the metallic layer (107) is removed.

Images