Current detection circuit

Abstract

Current Detection Circuit This description relates to a current detection circuit (150) for a first output current of a switched-mode power supply (100) comprising a sample-and-hold circuit (SnH151) adapted to store an image of said first output current during a non-conducting phase of a high-voltage switch (M101) of said switched-mode power supply (100). Figure for the abstract: Fig. 1

Description

Title of the invention: Current detection circuit technical field

[0001] This description relates generally to electronic systems and circuits, and more particularly to electronic systems and circuits adapted to provide a power supply. More specifically, this description relates to a switched-mode power supply and a circuit for providing a representation of the output current of a switched-mode power supply. Previous technique

[0002] There are several types of power supply circuits that deliver a current / voltage pair to a circuit, device, or electronic system, or more generally to a load. Linear power supplies and switched-mode power supplies are examples of power supply circuits.

[0003] A switched-mode power supply is a power supply circuit adapted to provide a direct current voltage from an input voltage. Switched-mode power supplies are generally DC / DC converters, taking a direct current voltage as input, but some switched-mode power supplies may include a rectifier stage allowing them to take an alternating current voltage as input, for example, the mains supply.

[0004] A switched-mode power supply is often equipped with one or more circuits for measuring the current and / or voltage it supplies. These circuits are used, for example, to verify the proper operation of the switched-mode power supply.

[0005] It would be desirable to be able to improve, at least in part, certain aspects of known switching power supplies, and, in particular, certain aspects of switching power supply current sensing circuits. Summary of the invention

[0006] There is a need for more efficient switching power supplies.

[0007] There is a need for switched-mode power supplies comprising circuits of improved current detection.

[0008] One embodiment overcomes all or part of the disadvantages of known switching power supplies.

[0009] One embodiment overcomes all or part of the drawbacks of known switching power supply current detection circuits.

[0010] One embodiment provides a current detection circuit adapted to measure an output current of a switching power supply.

[0011] One embodiment provides a current detection circuit comprising a sampling circuit.

[0012] One embodiment provides a circuit for detecting a first output current of a switching power supply comprising a sample-and-hold circuit adapted to store an image of said first output current during a non-conducting phase of a high-voltage switch of said switching power supply.

[0013] Another embodiment provides a current detection method using a first output current detection circuit of a switching power supply comprising a sample-and-hold circuit adapted to store an image of said first output current during a non-conducting phase of a high-voltage switch of said switching power supply.

[0014] According to one embodiment, said sample-and-hold assembly includes a switch and a capacitor.

[0015] According to one embodiment, said sample-and-hold assembly is adapted to be controlled by a sampling signal.

[0016] According to one embodiment, said sampling signal triggers the storage of said image of said first current with a time delay.

[0017] According to one embodiment, said sample-and-hold assembly is adapted to directly receive said first current.

[0018] According to one embodiment, said circuit comprising: - a control loop adapted to receive a first current to be detected; and - a first transistor and a second transistor mounted in current mirror, said first transistor being adapted to receive an output from said control loop, and said second transistor being adapted to provide said image of said first current, said sample-and-hold circuit being arranged between the control terminals of the first and second transistors.

[0019] According to one embodiment, said control loop includes a current comparator adapted to receive said first current.

[0020] According to one embodiment, said second transistor is adapted to receive, in addition, a second reference current.

[0021] According to one embodiment, said second reference current is adapted to be supplied by a digital-to-analog converter.

[0022] Another embodiment provides for a switched-mode power supply comprising a current detection circuit described above.

[0023] According to one embodiment, the switching power supply is a buck-type switching power supply, a boost-type switching power supply, or a buck-boost-type switching power supply.

[0024] Another embodiment provides for a device comprising a switching power supply described above.

[0025] According to one embodiment, the device is a microcontroller. Brief description of the drawings

[0026] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0027] [Fig.1] represents part of a switching power supply comprising a current detection circuit according to one embodiment;

[0028] [Fig.2] represents an embodiment of a current detection circuit;

[0029] Fig. 3 represents graphs illustrating the operation of the mode of realization of [Fig.2];

[0030] [Fig.4] represents other graphs illustrating the operation of the embodiment of [Fig.2];

[0031] [Fig.5] represents in more detail part of the embodiment of [Fig.1];

[0032] [Fig.6] represents in more detail part of the embodiment of [Fig.1];

[0033] [Fig.7] represents in more detail part of the embodiment of [Fig.2];

[0034] [Fig.8] represents in more detail part of the embodiment of [Fig.2];

[0035] [Fig.9] represents in more detail part of the embodiment of [Fig.2];

[0036] [Fig. 10] represents in more detail part of the embodiment of [Fig. 2]; and

[0037] [Fig.1 1] represents an application of the embodiments described. Description of the implementation methods

[0038] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0039] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0040] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0041] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0042] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0043] The embodiments described below relate to the implementation of a switched-mode power supply, and more particularly to the implementation of output current detection of this switched-mode power supply by a current detection circuit. The inventors observed that the detection of an overcurrent exceeding a threshold by an output current of a switched-mode power supply can be delayed in certain cases. The present description therefore proposes to overcome this problem by adding a sample and hold (SnH) circuit to the current detection circuit. This is described with reference to Figures 1 to 10.

[0044] Furthermore, the embodiments described below are particularly well suited for use in a generic microcontroller for small or large household appliances, electronic cigarettes, computer peripherals, mobile phones, etc. An application of these embodiments is described in more detail with reference to [Fig. 11].

[0045] Furthermore, the embodiments described above are particularly suitable for use in any type of industrial market where a switched-mode power supply is required. More specifically, such a switched-mode power supply may be intended for: - the automotive industry, for example in the field of automotive electrification or in the field of Advanced Driver Assistance Systems (ADAS); - the industrial industry, for example in the field of green energy, in the field of infrastructure electrification, the Internet of Things (IoT) and Smart Homes, where electricity and energy consumption and data exchange are key elements; - the personal electronics industry, for example in the field of mobile telephony and the Internet of Things (IoT), as well as in the field of broadband interfaces; and - the communications equipment, computer and peripherals industry, for example in the field of infrastructure and data centers, and in the field of low Earth Orbit (LEO) satellites.

[0046] The [Fig. 1] represents part of a switching power supply 100 comprising a current detection circuit 150 according to one embodiment.

[0047] Part 100 further includes a high-voltage switch M101, that is to say a switch adapted to receive, on one of its conduction terminals, a voltage to be converted VinlOO and to supply this voltage to an output of the switching power supply via a coil not shown in [Fig. 1]. A second terminal of switch M101 is connected, preferably connected, to a node A100. The control terminal of switch M101 is adapted to receive a control voltage from the switching power supply.

[0048] According to one embodiment, the high-voltage switch M101 is a metal-oxide-semiconductor field-effect transistor, or MOSFET, or MOS transistor. Furthermore, the switch M101 is a P-channel MOS transistor, or P-type MOS transistor, or PMOS transistor.

[0049] Similarly, a switching power supply typically includes, furthermore, a low voltage switch (not shown in [Fig.1]), that is to say a switch adapted to receive, on one of its conduction terminals, a reference voltage GND100, for example ground, and to supply this reference voltage to the output of the switching power supply via the coil not shown in [Fig.1].

[0050] The operation of a switched-mode power supply is based on a succession of alternating conduction and non-conduction phases of the high-voltage switch and the low-voltage switch. This operation is conventional and within the grasp of a person skilled in the art.

[0051] Part 100 further comprises two switches M102 and M103 arranged in series with each other and forming a parallel configuration with switch M101. By way of example, switches M102 and M103 are both switches of the same type as switch M101, that is, in the case illustrated in [Fig. 1], PMOS transistors. Thus, a first conduction terminal of switch M102 is connected, preferably connected, to the node supplying the voltage to be converted Vin100, and a second conduction terminal of switch M102 is connected, preferably connected, to a first conduction terminal of switch M103 and to a node B100. A second conduction terminal of switch M103 is connected, preferably connected, to node A100. The control terminals of switches M102 and M103 are adapted to receive control voltages of the same type as the control voltage received by the control terminal of switch M101.

[0052] The B100 node is a node providing an image of the output current of the switching power supply, and it is this image of the current that the current detection circuit 150 proposes to evaluate.

[0053] According to one example, part 100 further comprises an LC-type filtering circuit including an inductor L101 and a capacitor C101. This filtering circuit is disposed between node A100 and a node supplying the reference voltage GND100. More specifically, a first terminal of the inductor L101 is connected, preferably connected, to node A100, and a second terminal of the inductor L101 is connected, preferably connected, to a first terminal of the capacitor C101, denoted node OUT100. A second terminal of capacitor C101 is connected, preferably connected, to the node providing the reference voltage GND100. The node OUT100 is the output node of the switching power supply and provides an output voltage from the switching power supply.

[0054] As previously stated, part 100 is equipped with a current detection circuit 150 adapted to detect and evaluate an output current from the switching power supply, and, more particularly, an IsenselOl image of this output current provided by node B100.

[0055] According to one example, the circuit 150 includes a feedback loop adapted to receive the current IsenselOl to be measured. This feedback loop comprises, for example, a comparator circuit Compl51, two transistors M151 and M152, and a resistor R151. A non-inverting input (+) of the comparator circuit Compl51, or comparator Compl51, is adapted to receive the current to be measured IsenselOl, for example, via a resistor R101 in part 100. An inverting input (-) of the comparator circuit Compl51 is connected, preferably connected, to a first terminal of the resistor R151. A second terminal of the resistor R151 is connected, preferably connected, to a node C100. The transistors M151 and M152 are, for example, PMOS transistors.A first conduction terminal of transistor M151 is connected, preferably connected, to the node supplying the voltage VinlOO, and a second conduction terminal of transistor M151 is connected, preferably connected, to node C100. A control terminal of transistor M151 is adapted to receive a control voltage. A first conduction terminal of transistor M152 is connected, preferably connected, to node C100, and a second conduction terminal of transistor M151 is connected, preferably connected, to a node D100. A control terminal of transistor M152 is connected, preferably connected, to the output node of comparator circuit Compl51.

[0056] According to one example, the circuit 150 further comprises a current mirror assembly, or current mirror circuit, or simply current mirror. This assembly includes two transistors M153 and M154, which are, for example, N-channel MOS transistors, or N-type MOS transistors, or NMOS transistors. A first conduction terminal of transistor M153 is connected, preferably connected, to node D100, and a second conduction terminal of transistor M153 is connected, preferably connected, to the node providing the reference voltage GND100. A first conduction terminal of transistor M154 is connected, preferably connected, to an output node OUT150 of the circuit 150, and a second conduction terminal of transistor M154 is connected, preferably connected, to the node providing the reference voltage GND100. The control terminals of transistors M153 and M154 are connected to each other and to node D100.

[0057] According to one example, the circuit 150 further includes a current source CS 151 adapted to provide a temperature-independent current. The current source CS 151 is, for example, adapted to provide a reference current Irefl50 to the output node OUT150. According to one example, the current source CS 151 is powered by the voltage VinlOO. According to another example, the current source can be implemented in part by a digital-to-analog converter.

[0058] According to one embodiment, the circuit 150 further comprises a sample-and-hold circuit. This circuit allows the measured value of the current IsenselOl by the circuit 150 to be stored during a non-conducting phase of switch M101. Indeed, the circuit 150 is located at the output of switch M101 and can only measure the current IsenselOl during a conducting phase of switch M101, and of switches M102 and M103. An example of a sample-and-hold circuit is described in detail with reference to [Fig. 2]. Two possible placements of the sample-and-hold circuit are illustrated in [Fig. 1].

[0059] According to a first embodiment, illustrated by the SnH151 (SnH) sample-and-hold circuit in [Fig. 1], the SnH151 circuit is arranged at the input of the circuit 150. More particularly, the SnH151 circuit is arranged at the input of the feedback loop, i.e., for example, at the input of the comparator circuit Compl51. According to one example, an input terminal of the SnH151 circuit is connected, preferably connected, to node B100, or to a connection terminal of resistor R101, and an output terminal of the SnH151 circuit is connected, preferably connected, to the inverting input terminal of the comparator circuit Compl51.

[0060] According to a second embodiment, illustrated by the SnH152 (SnH) sample-and-hold circuit in [Fig. 1], the SnH152 circuit is arranged in the current mirror configuration. More specifically, the SnH152 circuit is positioned between the control terminals of transistors 153 and M154. By way of example, an input terminal of the SnH152 circuit is connected, preferably connected, to the control terminal of transistor M153, and an output terminal of the SnH152 circuit is connected, preferably connected, to the control terminal of transistor M154.

[0061] According to a third embodiment, not illustrated in [Fig.1], the sample-and-hold circuit can be arranged upstream of the current mirror setup, for example by being within another current mirror setup arranged upstream of that formed by transistors M153 and M154.

[0062] According to one embodiment, a method of using circuit 150 is as follows. The sample-and-hold circuit is activated to store the value of the current to be measured at the beginning of a non-conducting phase of switch M101. In one example, the sample-and-hold circuit is activated by a sampling signal, also called a control signal. In another example, the sample-and-hold circuit may not can be activated directly at the beginning of a non-conducting phase but may allow a delay to allow the current to stabilize.

[0063] Figure 2 represents a current detection circuit 200 of the type of circuit 150 described in relation to Figure 1. More particularly, Figure 2 illustrates an example of an embodiment of the first embodiment described in relation to Figure 1.

[0064] Circuit 200 comprises the same components as circuit 150. In other words, circuit 200 comprises: - the feedback loop comprising the comparator circuit Compl51, the resistor R151 and the transistors M151 and Ml52; and - the current mirror circuit comprising transistors M153 and M154.

[0065] According to one embodiment, the circuit 200 further comprises a sample-and-hold circuit SnH201 arranged like the circuit SnH152 described in relation to [Fig. 1]. The circuit SnH201 comprises, according to one embodiment, a switch 1201 and a capacitor C201. A first conduction terminal of the switch 1201 is connected, preferably connected, to the first conduction terminal of transistor M153 and to the control terminal of that same transistor, and a second conduction terminal of the switch 1201 is connected, preferably connected, to the control terminal of transistor M154. A control terminal of the switch 1201 is adapted to receive a control voltage. Such a control voltage is detailed in relation to Figures 3 and 4.One terminal of capacitor C201 is connected, preferably connected, to the control terminal of transistor Ml54, and a second terminal of capacitor C201 is connected, preferably connected, to the node providing the reference voltage GND100.

[0066] According to one example, the circuit 200 further comprises an inverter circuit INV201 and a buffer circuit B201. According to one example, an input terminal of the inverter circuit INV201 is connected, preferably connected, to node OUT150, and an output terminal of the inverter circuit INV201 is connected, preferably connected, to an input terminal of the buffer circuit B201. An output terminal of the buffer circuit B201 forms an output terminal of the circuit 200.

[0067] Figs. 3 and 4 are graphs illustrating the operation of the circuit 200 described in relation to Fig. 2.

[0068] Figure 3 includes the following graphs: - a curve 301 illustrating the evolution of an output current of the switching power supply; - a curve 302 illustrating the evolution of the output voltage of circuit 200 at the level of node OUT150; - a curve 303 illustrating the evolution of the output voltage of circuit 200 at the output of buffer circuit B201; - a curve 304 illustrating the evolution of the grid-source voltage of the Ml53 transistor which is an image of the current to be measured; - a curve 305 illustrating the evolution of the grid-source voltage of the Ml54 transistor which is an image of the current to be measured; - a curve 306 illustrating the evolution of the output voltage of a circuit of the type of circuit 200 but not including a sample hold circuit, at the level of the OUT150 node; - a curve 307 illustrating the evolution of the output voltage of a circuit of the type of circuit 200 but not including a sample-and-hold circuit, at the output of the buffer circuit B201; and - a curve 308 illustrating the evolution of the current image at the control terminal of transistor Ml54 of a circuit of the type of circuit 200 but not including a sample-and-hold circuit.

[0069] Figure 4 includes the following graphs: - a curve 401 illustrating the evolution of an output current of the switching power supply; - a curve 402 illustrating the evolution of the output voltage of circuit 200 at node OUT150; - a curve 403 illustrating the evolution of the output voltage of circuit 200 at the output of buffer circuit B201; - a 404 curve illustrating the evolution of the drain-source current of the Ml54 transistor; - a curve 405 illustrating the evolution of the output voltage of a circuit of the type of circuit 200 but not including a sample hold circuit, at the level of the OUT150 node; - a curve 406 illustrating the evolution of the output voltage of a circuit of the type of circuit 200 but not including a sample-and-hold circuit, at the output of the buffer circuit B201; and - a curve 407 illustrating the evolution of the drain-source current of the Ml54 transistor of a circuit of the type of circuit 200 but not including a sample-and-hold circuit.

[0070] These curves show that the use of a sampler circuit makes it possible to detect more quickly an exceedance of a threshold by the output current of the switching power supply.

[0071] Figure 5 represents a practical example of the realization of a portion of the part 100 described in relation to [Fig.1]. More specifically, [Fig.5] illustrates a practical example 500 of an implementation of the M101 switch described in relation to [Fig.1].

[0072] According to one example, the switch 500 comprises two transistors M501 and M502, for example, PMOS type transistors, arranged in parallel.

[0073] More specifically, according to one example, a source terminal of transistor M501 is connected, preferably connected, to a terminal supplying the Vin100 voltage, and a drain terminal of transistor M501 is connected, preferably connected, to a terminal supplying the GND100 reference voltage. According to another example, a source terminal of transistor M502 is connected, preferably connected, to a terminal supplying the Vin100 voltage, and a drain terminal of transistor M502 is connected, preferably connected, to a terminal supplying the GND100 reference voltage. The gate terminals of transistors M501 and M502 are connected to each other and to a node supplying a control voltage defining the conduction and non-conduction phases of transistors M501 and M502.

[0074] Figure 6 represents a practical example of an embodiment of a portion of part 100 described in relation to Figure 1. More specifically, Figure 6 illustrates a practical example 600 of an embodiment of switches M102 and M103 described in relation to Figure 1.

[0075] According to one example, the circuit 600 comprises two transistors M601 and M602, for example, PMOS type transistors, arranged in series.

[0076] More specifically, according to one example, a source terminal of transistor M601 is connected, preferably connected, to a terminal supplying the voltage Vin100, and a drain terminal of transistor M601 is connected, preferably connected, to a source terminal of transistor M602, and supplies the current IsenselOl. According to one example, a drain terminal of transistor M602 is connected, preferably connected, to the node supplying the reference voltage GND100.

[0077] Figure 7 represents a practical example of the implementation of a portion of the circuit 150 described in relation to Figure 1. More particularly, Figure 7 illustrates a practical example 700 of the implementation of the transistor M151 described in relation to Figure 1.

[0078] According to one example, the circuit 700 comprises four transistors M701, M702, M703 and M704, for example, PMOS type transistors, arranged in a bridge configuration. The resistor R151 is also shown in [Fig.7].

[0079] More specifically, by example, a source terminal of transistor M701 is connected, preferably connected, to a terminal supplying the voltage Vin1OO, and a drain terminal of transistor M701 is connected, preferably connected, to a source terminal of transistor M702. By example, a drain terminal of transistor M702 is connected, preferably connected, to node Cl00 and to a first terminal of resistor R151. By example, a source terminal of transistor M703 is connected, preferably connected, to a terminal supplying the voltage Vin1OO, and a drain terminal of transistor M703 is connected, preferably connected, to a source terminal of the transistor M704. According to an example, one drain terminal of transistor M704 is connected, preferably connected, to node C100 and to one terminal of resistor R151. All gate terminals of transistors M701, M702, M703 and M704 are connected together and to a node providing a control voltage.

[0080] Figure 8 represents a practical example of the implementation of a portion of the circuit 150 described in relation to Figure 1. More particularly, Figure 8 illustrates a practical example of the implementation of the comparator Compl51, the current mirror circuit, the sample-and-hold circuit SnH152 and the current source CS151 described in relation to Figure 1.

[0081] According to one example, circuit 800 comprises: - a Comp801 comparator which is a practical example of the Compl51 comparator; and - a current source.

[0082] According to one example, the comparator Comp801 comprises seven transistors M801, M802, M803, M804, M805, M806, and M808. Transistors M801, M802, and M808 are, for example, PMOS-type transistors. Transistors M803 through M807 are, for example, NMOS-type transistors.

[0083] Transistors M801 and M802 are configured in a current-mirror configuration. For example, the source terminal of transistor M801 forms the inverting terminal of comparator Comp801, and the drain terminal of transistor M801 is connected, preferably connected, to a terminal forming the output terminal of comparator Comp801 and thus is connected, preferably connected, to the gate terminal of transistor M152. Alternatively, the source terminal of transistor M802 forms the non-inverting terminal of comparator Comp801, and the drain terminal of transistor M802 is connected, preferably connected, to the terminal forming the output terminal of comparator Comp801 and thus is connected, preferably connected, to the gate terminal of transistor M152. The gate terminals of transistors M801 and M802 are connected to each other and to the drain terminal of transistor M802.

[0084] According to one example, transistors M803, M804, M805, and M806 are bridged. More specifically, according to one example, a drain terminal of transistor M803 is connected, preferably connected, to the source terminal of transistor M801, and a source terminal of transistor M803 is connected, preferably connected, to a drain terminal of transistor M805. According to one example, a source terminal of transistor M805 is connected, preferably connected, to the node providing the reference voltage GND100. According to one example, a drain terminal of transistor M804 is connected, preferably connected, to the source terminal of transistor M802, and a source terminal of transistor M804 is connected, preferably connected, to a drain terminal of transistor M806. According to one example, a source terminal of transistor M806 is connected, preferably connected, to the node providing the reference voltage GND100. According For example, the gate terminals of transistors M803 and M804 are connected to each other and to a node providing a control voltage. Transistors M803 and M804 are configured in a cascode configuration and limit the drain voltage of transistors M805 and M806. In another example, the gate terminals of transistors M805 and M806 are connected to each other and to a node providing a control voltage. Transistors M805 and M806 act as a current source and bias the structure formed by the 800 series circuit.

[0085] According to one example, a source terminal of transistor M8O8 is connected, preferably connected, to a terminal receiving the voltage VinlOO, and a drain terminal of transistor M8O8 is connected, preferably connected, to the drain terminal of transistor M801.

[0086] Transistors M153 and M154 are shown in [Fig.8], as well as the sample-and-hold circuit NH201 described in relation to [Fig.2].

[0087] According to one example, the current source includes a digital-to-analog converter comprising several PMOS-type transistors arranged in a matrix according to an arrangement known to those skilled in the art, and further comprises M811, M812, M813, M814 and M815 transistors.

[0088] According to one example, the M811 transistor is of the NMOS type and is mounted in cascode with the M154 transistor. According to one example, a source terminal of the M811 transistor is connected, preferably connected, to the source terminal of the M154 transistor, and a drain terminal of the M811 transistor is connected, preferably connected, to a node A100. A gate terminal of the M811 transistor is connected, preferably connected, to the A800 node.

[0089] According to one example, the M812 transistor is of the NMOS type. According to one example, a source terminal of the M812 transistor is connected, preferably connected, to the node receiving the reference voltage GND100, and a drain terminal of the M812 transistor is connected, preferably connected, to a node A100. A gate terminal of the M812 transistor is connected, preferably connected, to the source terminal of the M811 transistor.

[0090] According to one example, the M813 transistor is of the NMOS type. According to one example, a source terminal of the M813 transistor is connected, preferably connected, to the node receiving the reference voltage GND100, and a drain terminal of the M813 transistor is connected, preferably connected, to an output node OUT800. A gate terminal of the M813 transistor is connected, preferably connected, to node A800.

[0091] According to one example, the M814 transistor is of the PMOS type. According to one example, a source terminal of the M814 transistor is connected, preferably connected, to the node supplying the VinlOO voltage, and a drain terminal of the M814 transistor is connected, preferably connected, to an output node OUT800. A gate terminal of the M814 transistor is connected, preferably connected, to node A800.

[0092] According to one example, the M815 transistor is of the PMOS type. According to one example, a source terminal of the M815 transistor is connected, preferably connected to the node providing the VinlOO voltage, and a drain terminal of transistor M814 is connected, preferably connected, to node A800. Transistor M815 prevents node A800 from floating when circuit 800 is off.

[0093] Figure 9 represents a practical example of the implementation of a portion of the circuit 200 described in relation to Figure 2. More specifically, Figure 9 illustrates a practical example 900 of the implementation of the switch 1201 described in relation to Figure 2.

[0094] According to one example, circuit 900 comprises transistors M901, M902, M903, M904, M905, M906, M907, and M908 arranged in a bridge configuration, two inverters, and a NOR logic gate. Resistor R151 is also shown in [Fig. 7]. Transistors M901, M902, M904, M906, and M908 are NMOS type. Transistors M903, M905, and M907 are PMOS type.

[0095] According to one example, a drain terminal of transistor M901 is connected, preferably connected, to an input terminal of circuit 900, denoted A900, and a source terminal of transistor M901 is connected, preferably connected, to the node receiving the reference voltage GND100.

[0096] According to one example, a source terminal of transistor M902 is connected, preferably connected, to its drain terminal and to node A900. A gate terminal of transistor M902 receives a control voltage. According to one example, a source terminal of transistor M904 is connected, preferably connected, to its drain terminal. A gate terminal of transistor M904 receives a control voltage. According to one example, a source terminal of transistor M906 is connected, preferably connected, to its drain terminal and to the output terminal of circuit 900, designated node B900. A gate terminal of transistor M906 receives a control voltage.

[0097] According to one example, a source terminal of transistor M903 is connected, preferably connected, to its drain terminal and to node A900. A gate terminal of transistor M903 receives a control voltage. According to one example, a source terminal of transistor M905 is connected, preferably connected, to its drain terminal. A gate terminal of transistor M905 receives a control voltage. According to one example, a source terminal of transistor M907 is connected, preferably connected, to its drain terminal and to the output terminal of circuit 900, designated node B900. A gate terminal of transistor M907 receives a control voltage.

[0098] According to one example, a drain terminal of transistor M908 is connected, preferably connected, to node B900, and a source terminal of transistor M908 is connected, preferably connected, to the node receiving the reference voltage GND100.

[0099] An input terminal of the INV902 inverter receives a control voltage and an output terminal of the INV902 inverter is connected, preferably connected, to the gate terminal of the M904 transistor.

[0100] The input terminals of the NOR901 gate receive control voltages. The output terminal of the NOR901 gate is connected, preferably connected, to the input of the INV902 inverter. One output terminal of the INV902 inverter is connected, preferably connected, to the gate terminal of the M905 transistor.

[0101] Fig. 9 further represents capacitor C201.

[0102] Fig. 10 represents an example of a 1000 delay circuit that can apply an activation delay to the sample-and-hold circuit.

[0103] Such a circuit allows the current to be measured to stabilize before its value is stored in the sample-and-hold circuit.

[0104] According to one example, the circuit 1000 comprises several inverter circuits INV1001, INV1002, INV1003, INV1004, INV1005, INV1006, transistors M1001, M1002, M1003, M1004, M1005, M1006, and a capacitor C1001. Transistors M1001, M1002, M1003 and M1005 are of the PMOS type while transistors M1004 and M1006 are of the NMOS type.

[0105] According to one example, an input terminal of the INV1001 inverter is connected, preferably connected, to a node providing an EN1000 activation signal. An output terminal of the INV1001 inverter is connected to an input terminal of the INV1002 inverter and to an input terminal of the INV1003 inverter. An output terminal of the INV1002 inverter is connected, preferably connected, to a node providing an activation signal. An output terminal of the INV1003 inverter is connected, preferably connected, to a gate terminal of the M1003 transistor and to a gate terminal of the M1004 transistor.

[0106] According to one example, a source terminal of transistor M1001 is connected, preferably connected, to a node providing a supply voltage, and a drain terminal of transistor M1001 is connected, preferably connected, to a source terminal of transistor M1002. A drain terminal of transistor M1002 is connected, preferably connected, to a source terminal of transistor M1003. A drain terminal of transistor M1003 is connected, preferably connected, to a drain terminal of transistor M1004. A drain terminal of transistor M1004 is connected, preferably connected, to a node providing a reference voltage.

[0107] According to one example, a first terminal of the capacitor C1001 is connected, preferably connected, to the middle node between transistors M1003 and M1004. A second terminal of the capacitor C1001 is connected, preferably connected, to the node receiving the reference voltage.

[0108] According to one example, a source terminal of transistor M1005 is connected, preferably connected, to the node supplying the supply voltage, and a drain terminal of transistor M1005 is connected, preferably connected, to the drain terminal of transistor M1006. The source terminal of transistor M1006 is connected, preferably connected, to the node receiving the reference voltage. The gate terminals of transistors M1005 and M1006 are connected, preferably connected, to each other and to the middle node between transistors M1003 and M1004.

[0109] According to one example, an input terminal of the INV1005 inverter is connected, preferably connected, to the midpoint between transistors M1005 and M1006. An output terminal of the INV1005 inverter is connected to an input terminal of the INV1006 inverter. An output terminal of the INV1006 inverter is adapted to provide a delayed signal.

[0110] The [Fig. 11] represents, very schematically and in block form, an electronic device 1100 (CPU).

[0111] According to one example, the electronic device 1100 is a controller, a microcontroller, a processor or a microprocessor.

[0112] This device 1100 includes, for example, a digital core 1101 (D. Core) adapted to receive an input voltage Vcore.

[0113] This device 1100 includes, for example, a power management unit 1102 (PMU) comprising a switching power supply 1103. The switching power supply 1103 includes high-voltage and low-voltage transistors M101 (NMOS) and M102 (PMOS). The switching power supply 1103 is adapted to include a current-sensing circuit according to one embodiment. The device 1100 can supplement the switching power supply with an external inductor L1101 and capacitor Cl101. According to one example, the switching power supply is buck-type, boost-type, or buck-boost-type.

[0114] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0115] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Detection circuit (150; 200) of a first output current of a switching power supply (100; 1103) comprising a sample-hold circuit (SnH151, SnH201) adapted to store an image of said first output current during a non-conducting phase of a high-voltage switch (M101) of said switching power supply (100; 1103).

2. Current detection method using a detection circuit (150; 200) of a first output current of a switching power supply (100; 1103) comprising a sample-hold assembly (SnH151, SnH201) adapted to store an image of said first output current during a non-conducting phase of a high-voltage switch (M101) of said switching power supply (100; 1103).

3. Circuit according to claim 1, or method according to claim 2, wherein said sample-hold assembly (SnH151, SnH201) comprises a switch (1201) and a capacitor (C201).

4. Circuit according to claim 1 or 3, or method according to claim 2 or 3, wherein said sample-hold assembly (SnH151, SnH201) is adapted to be controlled by a sampling signal.

5. Circuit according to any one of claims 1, 3 or 4, or method according to any one of claims 2, 4, wherein said sampling signal triggers the storage of said image of said first current with a time delay.

6. Circuit according to any one of claims 1, 3 to 5, or method according to any one of claims 2 to 5, wherein said sample-hold assembly (SnH151, SnH201) is adapted to receive said first current directly.

7. A circuit according to any one of claims 1, 3 to 5, or a method according to any one of claims 2 to 5, wherein said circuit comprises: - a feedback loop adapted to receive a first current to be detected; and - a first transistor (M151) and a second transistor (M152) mounted in current mirroring, said first transistor (M151) being

8.

9.

10.

11.

12.

13.

14. adapted to receive an output from said feedback loop, and said second transistor (Ml52) being adapted to provide said image of said first current, said sample hold circuit (SnH151, SnH201) being disposed between the control terminals of the first and second transistors (M151, Ml52). Circuit or method according to claim 7, wherein said control loop includes a current comparator (Compl51) adapted to receive said first current. Circuit or method according to claim 7 or 8, wherein said second transistor (Ml52) is adapted to receive, in addition, a second reference current (Irefl50). Circuit or method according to claim 9, wherein said second reference current (Irefl50) is adapted to be supplied by a digital-to-analog converter. Switching power supply (100; 1103) comprising a current sensing circuit according to any one of claims 1, 3 to 10. Power supply according to claim 11, being a buck-type switching power supply, a boost-type switching power supply, or a buck-boost-type switching power supply. Device (1100) comprising a switching power supply (100, 1103) according to claim 11 or 12. Device according to claim 13, being a microcontroller.

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