Method for manufacturing a high-density electrical interconnection structure

Abstract

The invention relates to a method for manufacturing an electrical interconnection structure (1) comprising a step of providing (E0) an initial structure (10) comprising a substrate (3), an electrically conductive lower element (2), a cavity (20) formed in the substrate (3) and having an internal wall (23) defining internally an access to the lower element (2), and an electrically insulating layer (30); a step of forming (E1) an interconnection element (40) in the cavity (20); and a final polishing step (E3), in which a portion of the interconnection element (40) and at least a part of the electrically insulating layer (30) are removed simultaneously by mechanochemical polishing by means of a final polishing agent, thus forming the electrical interconnection structure (1).

Description

Title of the invention: Method for manufacturing a high-density electrical interconnection structure Technical field of the invention

[0001] The present invention relates to a method for manufacturing an electrical interconnection structure, in particular for establishing an electrical connection between two faces of a substrate. State of the art

[0002] In the field of microelectronics, the reduction of component dimensions has reached a limit. In order to increase the density of electronic components in a system, research is now focused on three-dimensional integration. Such integration makes it possible to stack chips in different layers and connect them via through-silicon vias, known in English as TSVs (Through Silicon Vias).

[0003] TSVs are electrical elements formed through the substrate material, so as to electrically connect two opposite faces of the substrate. Thus, electrical contacts can be made on a substrate face opposite the face where, for example, the microelectronic devices are located. A major advantage of TSVs is that they allow for a more compact structure.

[0004] In the case of 3D structures and, more generally, for complex devices, it is advantageous to design a structure comprising TSVs distributed at high density within the substrate. TSVs are increasingly used, for example in combination with hybrid bonding, to create multi-wafer (or multi-substrate) stacks intended for imaging applications in particular. In a "classic" three-layer 3L structure, the TSVs pass through the middle wafer (tier 2) when it is flipped over, and allow it to be electrically connected to the upper wafer (tier 3). Manufacturing processes therefore aim to maximize the number of TSVs opening onto a surface of the substrate per unit area.

[0005] Although current results allow for a very high quantity of TSVs per unit area, this density is limited by various factors stemming from the processes used. First, the distance between two closely spaced TSVs is constrained by the alignment accuracy of the lithography equipment, which requires a certain clearance between the TSVs and the pads to which they connect. For current applications, however, the accuracies obtained with these devices remain very good and do not significantly hinder the production of high-density TSVs.

[0006] A second limitation arises from the etching process in the formation of TSVs. More specifically, the "via last" approach is considered less expensive for TSV formation. This approach includes an etching step (called "etch back") which consists of etching the insulating material at the bottom of the cavity to allow re-establishment of contact with the electronic device on the front face of the substrate. During this step, faceting occurs in the insulating material overlying the TSV, which enlarges the TSV (on the order of a hundred nanometers per edge). The apparent diameter of the TSV is therefore increased, and TSVs cannot get closer to each other beyond this enlargement, otherwise they will short-circuit.

[0007] There is therefore a need to find a manufacturing process for an electrical interconnection structure that is inexpensive and that makes it possible to obtain a density of TSVs per unit area such that a spacing between two TSVs is less than 300 nm.

[0008] Object of the invention

[0009] The present invention aims to provide a solution that addresses all or part of the aforementioned problems.

[0010] This goal can be achieved through the implementation of a manufacturing process for an electrical interconnection structure comprising: - a step of making available an initial structure, said initial structure comprising: • a substrate having a top face and a bottom face opposite to the top face; • at least one lower electrically conductive element arranged on the underside of the substrate; • at least one cavity formed in the substrate and comprising a top opening leading from the top side of the substrate, said at least one cavity having an internal wall defining internally an access to the lower element from the top side of the substrate; • an electrically insulating layer comprising an upper portion arranged on the upper face of the substrate and a vertical portion arranged on the inner wall of said at least one cavity; - a step of forming an interconnecting element, in which an electrically conductive material is deposited on the upper surface of the substrate so as to form said interconnecting element in the cavity, the interconnecting element being electrically connected to the element lower on one side and opening through the upper orifice on the side of the upper face of the substrate on the other side; - a final polishing step, in which a portion of the interconnecting element and at least part of the upper portion of the electrically insulating layer are removed simultaneously by mechanochemical polishing via a final polishing agent, thus forming the electrical interconnecting structure.

[0011] The arrangements described above make it possible to propose a manufacturing process enabling the formation of an electrical interconnection structure with a high density of TSVs traversing the silicon.

[0012] The manufacturing process may also have one or more of the following characteristics, taken alone or in combination.

[0013] According to one embodiment, the substrate is a silicon substrate

[0014] According to one embodiment, the through-hole portion of the interconnecting element is a TSV, from the English Through Silicon Via.

[0015] Generally, the upper surface of the substrate is viewed from a plane that is usually horizontal. Thus, a "vertical portion" is understood to be a portion extending in a direction transverse to the upper surface of the substrate. This direction may, for example, be substantially perpendicular to a plane of extension of the upper surface of the substrate.

[0016] According to one embodiment, the step of forming the interconnecting element comprises: - the formation of a through-part within the cavity; and - the formation of an excess layer of the same conductive material as that of the through part and covering the upper portion of the electrically insulating layer.

[0017] Thus, it is possible to ensure that the interconnecting element passes through all the layers forming the initial structure, and emerges from the cavity beyond the electrically insulating layer.

[0018] According to one embodiment, the manufacturing process further comprises a primary polishing step, in which the excess layer of the interconnecting element is removed by mechanochemical polishing through a primary polishing agent.

[0019] In this way, it is possible to perform a primary polishing stage to remove a layer of material from the interconnecting element before carrying out the final polishing stage, which is specific to the simultaneous removal of two materials. It is thus possible to adapt the type of polishing agent to the type of mechanochemical polishing performed.

[0020] According to one embodiment, the primary polishing agent is different from the final polishing agent.

[0021] According to one embodiment, the final polishing step and the primary polishing step are carried out during the same operation.

[0022] In other words, the final polishing agent is the same as the primary polishing agent.

[0023] According to one embodiment, during the initial structure provision step, the electrically insulating layer includes a chamfer arranged between the upper portion and the vertical portion, the final polishing step then being carried out until a thickness of the electrically insulating layer removed by mechanochemical polishing is greater than or equal to a height of the chamfer.

[0024] According to one embodiment, the final polishing step is carried out until the thickness of the electrically insulating layer removed by mechanochemical polishing is equal to the height of the chamfer. In other words, the final polishing step is carried out until the chamfer is removed.

[0025] In this way, it is possible to obtain an interconnecting element in which the through-parts 41 do not have an increase in diameter at the upper orifice. Furthermore, it is possible to ensure the presence of a sufficiently thick electrically insulating layer to provide electrical insulation on both sides of the upper portion of the electrically insulating layer.

[0026] Generally, the height of the chamfer is measured transversely to the upper face of the substrate, and in particular perpendicularly to the upper face of the substrate.

[0027] According to one embodiment, the manufacturing process further includes a step of making interconnecting pads implemented after the final polishing step, in which at least one interconnecting pad is made vertically below the interconnecting element, on the upper face side.

[0028] Thus, it is possible to resume electrical contacts at the level of the interconnection elements emerging from the substrate.

[0029] In other words, an interconnection pad can be formed at the right of each through part 43 of the interconnection element.

[0030] According to one embodiment, during the interconnection element formation step, the deposited material comprises copper, tungsten, niobium, tantalum, nickel, aluminum, or any other suitable material to make a through-hole interconnection element.

[0031] In this way, it is possible to obtain an interconnecting element having good electrical conductivity properties.

[0032] According to one embodiment, the electrically insulating layer comprises a silicon oxide.

[0033] This type of insulating material is easy to lay down and has a low cost.

[0034] According to one embodiment, during the initial structure provisioning step, the initial structure comprises a plurality of cavities formed in the substrate, the interconnecting element formation step then comprising the formation of a plurality of through parts in said cavities.

[0035] In this way, at the end of the final polishing step, it is possible to form a structure comprising a plurality of TSVs, where each TSV corresponds to one of the through parts of the interconnecting element.

[0036] According to one embodiment, the removal of the excess layer during the primary polishing step allows the formation of a plurality of TSVs, where each TSV corresponds to one of the through parts, each TSV being electrically connected to one of the lower elements on one side and opening out on the side of the upper face of the substrate on the other.

[0037] Thus, the manufacturing process is adapted for the formation of a high-density TSV-based electrical interconnection structure, where the deposition of the TSV-forming material in the cavities is carried out collectively in all the cavities.

[0038] According to one embodiment, during the initial structure provisioning step, each cavity is separated from at least one other cavity by a distance that is strictly less than 10 pm, preferably strictly less than 5 pm, and preferably strictly less than 1 pm.

[0039] The manufacturing process is therefore suitable for manufacturing a high-density electrical interconnection structure.

[0040] According to one embodiment, during the final polishing step, the final polishing agent comprises: - 68 to 84% by mass of deionized water; - 15 to 30% silica by mass; - 1 to 2% by mass of organic matter.

[0041] Advantageously, it has been found that the use of such a final polishing agent makes it possible to make the removal of material during the final polishing step less selective.

[0042] Brief description of the drawings

[0043] Other aspects, objectives, advantages and features of the invention will become clearer upon reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and made with reference to the accompanying drawings in which:

[0044] [Fig.1] Fig.1 is a detailed schematic view of a succession of steps leading to the provision of the initial structure according to a particular embodiment of the invention.

[0045] [Fig.2] Fig.2 is a schematic view of the step of making available the initial structure and formation stage of the interconnecting element according to a particular embodiment of the invention.

[0046] [Fig.3] The [Fig.3] is a schematic view of the primary polishing stage and the final polishing stage according to a particular embodiment of the invention.

[0047] [Fig.4] Fig.4 is a schematic view of the step of making the studs interconnection according to a particular embodiment of the invention.

[0048] [Fig.5] The [Fig.5] is a schematic view showing the top of an interconnection structure manufactured according to the prior art (A) and the top of an interconnection structure obtained according to a particular embodiment of the invention (B). Detailed description

[0049] In the figures and throughout the description, the same reference numerals represent identical or similar elements. Furthermore, the various elements are not drawn to scale in order to enhance the clarity of the figures. Moreover, the different embodiments and variants are not mutually exclusive and may be combined.

[0050] As can be seen in Figures 1 to 4, the invention relates to a method for manufacturing an electrical interconnection structure 1.

[0051] The manufacturing process first includes a step of making available E0 an initial structure 10. [Fig.1] illustrates a non-limiting embodiment showing the succession of technological steps allowing to achieve the making available E0 of the initial structure 10.

[0052] This embodiment first provides E01 of an initial stack comprising a substrate 3 having a top face fs3 and a bottom face fi3 opposite to the top face fs3. For example, this substrate 3 can be a silicon substrate.

[0053] Generally, the upper face fs3 of the substrate 3 is viewed from a horizontally oriented plane. Thus, to facilitate understanding and description of the figures, the terms "horizontal" or "vertical" will be used in the following description, referring to the orientation of the described elements relative to the elongation plane of the substrate 3. However, these terms are not limiting with respect to the orientation of the elements in space. Similarly, the terms "above" or "below" are used in the following description to locate the elements according to the direction in which they are presented in the figures. These terms, however, do not in any way prejudge their relative position with respect to the severity in the final use of the electronic device.

[0054] The initial stack also includes at least one electrically conductive lower element 2 arranged on the underside of the substrate 3, i.e., below the substrate, according to the embodiment shown. In [Fig. 1], in particular, the initial stack comprises two lower elements 2. However, it is well understood that in the field of application considered, the number of lower elements is much greater. Although not limiting, a lower insulating layer 8 may be arranged between the underside of the substrate 3 and the lower element 2.

[0055] The initial stack also includes an insulating layer 30 disposed on the upper face fs3 of the substrate 3. The insulating layer 30 is therefore located on the side opposite the lower elements 2 with respect to the substrate 3. This insulating layer 30 may advantageously comprise a silicon oxide. This type of insulating material is easy to deposit and has a low cost.

[0056] During step E02, a layer of resin 6 can be deposited on the insulating layer 30, then exposed and developed by photolithography, in order to form openings 7 in the resin layer 6. Generally, such a step E02 is carried out so that an opening 7 is provided at the level of each lower element 2 at which a through access is to be made.

[0057] Several etching steps can then be implemented to create access to the lower elements 2 from the upper face fs3 of the substrate 3. First, step E03 consists of extending, by etching, the openings 7 in the insulating layer 30. Step E04 is then implemented to etch the material constituting the substrate 3, to extend the openings 7 vertically, and thus create a channel in the substrate 3. Such a step can, for example, be implemented by deep reactive ion etching (DRIE). Generally, the channels thus formed have a general cylindrical shape that extends vertically through the substrate 3 between the upper face fs3 and the lower face fi3.

[0058] In the case where a lower insulating layer 8 is present, an etching step E05 can be implemented to remove portions of this lower insulating layer 8 arranged above the lower elements 2. The result of steps E02 to E04 (or even E05) is to allow the formation of at least one cavity 20 provided in the substrate 3, and in particular a plurality of cavities 20 provided in the substrate 3. Each of the cavities then comprises a top opening 21 opening onto the side of the upper face fs3 of the substrate 3 and an internal wall 23.

[0059] Step E06 can then be implemented to remove the resin layer 6.

[0060] During step E07, an insulating material, for example a silicon oxide, is deposited so that the insulating layer 30 comprises an upper portion 31 arranged on the upper face fs3 of the substrate 3 and a vertical portion 33 arranged on the inner wall 23 of said at least one cavity 20. By "vertical portion 33" is meant a portion extending in a direction transverse to the upper face fs3 of the substrate 3. This direction may, for example, be substantially perpendicular to a plane of extension of the upper face fs3 of the substrate 3. In this way, it is possible to electrically isolate the substrate 3 from any conductive element formed in the cavity 20.

[0061] Following step E07, portions of the insulating layer 30 are placed at the bottom of each cavity 20 and electrically insulate the lower elements 2 from the space formed inside the cavity 20. A back etching step E08 (or "etch back" according to established Anglo-Saxon terminology) must therefore be carried out to etch said portions at the bottom of the cavity 20 and thus allow access to the lower elements 2. During this back etching step E08, a chamfer 35, or facet, is generally formed in the insulating layer 30. Thus, for each cavity 20, a chamfer 35 is arranged between the upper portion 31 and the vertical portion 33 of the insulating layer 30.

[0062] As can be seen in [Fig. 2], each chamfer 35 can be characterized by a chamfer height h35 measured transversely to the upper face fs3 of the substrate 3, and in particular perpendicularly to the upper face fs3 of the substrate 3; and by a chamfer width 135 measured perpendicularly to said chamfer height h35. In order to better visualize these dimensions 135 and h35, [Fig. 2] shows an enlargement of an area exhibiting chamfers 35.

[0063] As we will see later, in order to increase the density of the electrical connections between the upper face fs3 and the lower face fi3 of the substrate 3, each cavity 20 can be separated from at least one other cavity 20 by a distance that is strictly less than 10 pm, preferably strictly less than 5 pm, and preferably strictly less than 1 pm. Such a distance can therefore be provided in step E02. The manufacturing process can thus be adapted for the fabrication of a high-density electrical interconnection structure 1.

[0064] The set of steps E01 to E08 presents a particular embodiment of the implementation of the step of making the initial structure 10 available. These steps E01 to E08 therefore lead to the formation of the initial structure 10 comprising: - substrate 3; - the lower elements 2 arranged on the side of the lower face fi3 of the substrate 3; - the cavities 20 formed in the substrate 3, each comprising a top opening 21 opening onto the side of the upper face fs3 of the substrate 3, and having an internal wall 23 defining internally an access to one of the lower elements 2 from the upper face fs3 of the substrate 3; and - the electrically insulating layer 30 comprising an upper portion 31 arranged on the upper face fs3 of the substrate 3 and for each cavity 20, a vertical portion 33 arranged on the inner wall 23 of said cavity 20.

[0065] With reference now to [Fig. 2], the manufacturing process may comprise a series of steps leading to the formation El of an interconnecting element 40, in which an electrically conductive material is deposited on the upper face fs3 of the substrate 3 so as to form said interconnecting element 40 in the cavities 20. For example, this step of forming El of an interconnecting element 40 may be carried out by electrochemical deposition (or ECD), generally preceded by the conformal deposition of a barrier layer (for example, titanium nitride and titanium (TiN / Ti)) and a nucleation layer of a material corresponding to that to be deposited by electrochemical deposition, for example, copper. The deposited material may, in particular, comprise at least one chemical element selected from the group consisting of copper, tungsten, niobium, tantalum, nickel, or aluminum.In this way, it is possible to obtain an interconnecting element 40 with good electrical conductivity properties.

[0066] The formation step El of the interconnecting element 40 may in particular include the formation of a through part 43 in each of the cavities 20; and the formation of an excess layer 41 of the same conductive material as that of the through-part 43 and covering the upper portion 31 of the electrically insulating layer 30. It is therefore well understood that during the formation step El of the interconnecting element 40, it is possible to form a plurality of through-parts 43, connected to each other by the excess layer 4L. Thus, it is possible to ensure that the interconnecting element 40, and in particular that each through-part 43, passes through all the layers forming the initial structure 10, and opens out of the corresponding cavities 20 beyond the electrically insulating layer 30. Thus, the formation step El of the interconnecting element 40 can include the formation of a plurality of through-parts 43.

[0067] It follows that the interconnecting element 40 is electrically connected to the lower element 2 on one side and opens through the upper orifice 21 on the upper face fs3 of the substrate 3 on the other. It is therefore clearly understood that the through-holes 43 of the interconnecting element will ultimately provide an electrical connection through the thickness of the substrate 3. In other words, the parts through-holes of the interconnecting element 40 are intended to form TSVs, from the English Through Silicon Via, at the end of the manufacturing process.

[0068] As illustrated in [Fig. 3], the manufacturing process may further include a primary polishing step E2, carried out after the forming step E1 of the interconnecting element 40, in which the excess layer 41 of the interconnecting element 40 is removed by mechanochemical polishing using a primary polishing agent. In this way, it is possible to perform primary polishing that removes a thickness e41 of material from the interconnecting element 40 corresponding to the thickness of the excess layer 41.

[0069] Removing the excess layer 41 during the primary polishing step E2 allows the formation of a plurality of TSVs, where each TSV corresponds to one of the through-holes 43. Each TSV is electrically connected to one of the lower elements 2 on the one hand and opens onto the upper face fs3 of the substrate 3 on the other. Thus, the manufacturing process is suitable for forming an electrical interconnection structure 1 with several TSVs, where the deposition of the material forming the TSVs is carried out collectively in all the cavities 20.

[0070] Figure 3 also illustrates the implementation of a final polishing step E3, in which a portion of the interconnecting element 40 and at least part of the upper portion 31 of the electrically insulating layer 30 are simultaneously removed by mechanochemical polishing using a final polishing agent, thus forming the electrical interconnecting structure 1. For example, the final polishing agent may comprise: - 68 to 84% by mass of deionized water; - 15 to 30% silica by mass; - 1 to 2% by mass of organic matter.

[0071] Advantageously, it has been found that the use of such a final polishing agent makes it possible to make the material removal during the final polishing step E3 less selective.

[0072] Generally, the primary polishing agent differs from the final polishing agent. Thus, the primary polishing step E2 is carried out before the final polishing step E3, which is specific to the simultaneous removal of two materials. It is therefore possible to adapt the type of polishing agent to the type of mechanochemical polishing performed. However, it is possible for the final polishing agent to be the same as the primary polishing agent. In this case, the final polishing step E3 and the primary polishing step E2 are carried out successively, but during the same operation.

[0073] Advantageously, the final polishing step E3 can be carried out until a thickness e30 of the electrically insulating layer 30 removed by chemical polishing is greater than or equal to a height h35 of the chamfer 35. More particularly, the final polishing step E3 is carried out until the thickness e30 of the electrically insulating layer 30 removed by chemical polishing is equal to the height h35 of the chamfer 35. In other words, the final polishing step E3 is carried out until the chamfer 35 is removed.

[0074] The arrangements described above make it possible to obtain an interconnecting element 40 in which the through parts 43 do not have an increase in diameter at the upper orifice 21. Furthermore, it is possible to guarantee the presence of a remaining thickness of electrically insulating layer 30 sufficiently large to ensure electrical insulation on both sides of the upper portion 31 of the electrically insulating layer 30.

[0075] At the end of the primary polishing step E2 and / or the final polishing step E3, a structure is formed, comprising a plurality of TSVs, where each TSV corresponds to the through parts 43.

[0076] Finally, the manufacturing process may comprise a series of steps leading to the production E4 of interconnecting pads 50. The production E4 of the interconnecting pads is carried out after the final polishing step E3 illustrated in [Fig. 4]. During this step, at least one interconnecting pad 50 is produced directly above the interconnecting element 40, on the upper face side fs3. In other words, an interconnection pad 50 can be formed at the right of each through part 43 of the interconnection element 40. Thus, it is possible to resume electrical contacts at the through parts 43 emerging from the substrate 3. Schematically, [Fig.5] illustrates a comparison between the top of an electrical interconnection structure 1 manufactured according to the prior art (A) and the top of an electrical interconnection structure 1 obtained according to a particular embodiment of the invention (B).

[0077] The arrangements described above make it possible to propose a manufacturing process for forming an electrical interconnection structure 1 with a high density of TSVs passing through the silicon.

Claims

1. Demands Method for manufacturing an electrical interconnection structure (1) comprising: • a step of making available (EO) an initial structure (10), said initial structure (10) comprising: • a substrate (3) having a top face (fs3) and a bottom face (fi3) opposite the top face (fs3); • at least one lower electrically conductive element (2) arranged on the underside (fi3) of the substrate (3); • at least one cavity (20) formed in the substrate (3) and comprising a top opening (21) opening from the side of the top face (fs3) of the substrate (3), said at least one cavity (20) having an internal wall (23) defining internally an access to the lower element (2) from the top face (fs3) of the substrate (3); • an electrically insulating layer (30) comprising an upper portion (31) arranged on the upper face (fs3) of the substrate (3) and a vertical portion (33) arranged on the inner wall (23) of said at least one cavity (20); • a formation step (El) of an interconnecting element (40), in which an electrically conductive material is deposited on the upper face (fs3) side of the substrate (3) so as to form said interconnecting element (40) in the cavity (20), the interconnecting element (40) being electrically connected with the lower element (2) on one side and opening through the upper orifice (21) on the upper face (fs3) side of the substrate (3) on the other side; • a final polishing step (E3), in which a portion of the interconnecting element (40) and at least part of the upper portion (31) of the electrically insulating layer (30) are simultaneously removed by mechanochemical polishing via of a final polishing agent, thus forming the electrical interconnection structure (1).

2. A manufacturing method according to claim 1, wherein the formation step (El) of the interconnecting element (40) comprises: • the formation of a through-part (43) in the cavity (20); and • the formation of an excess layer (41) of the same conductive material as that of the through-part (43) and covering the upper portion (31) of the electrically insulating layer (30).

3. A manufacturing method according to claim 2, further comprising a primary polishing step (E2), in which the excess layer (41) of the interconnecting element (40) is removed by mechanochemical polishing through a primary polishing agent.

4. A manufacturing method according to any one of claims 1 to 3, wherein during the initial structure (10) provisioning step (E0), the electrically insulating layer (30) includes a chamfer (35) arranged between the upper portion (31) and the vertical portion (33), the final polishing step (E3) then being carried out until a thickness (e30) of the electrically insulating layer (30) removed by mechanochemical polishing is greater than or equal to a height (h35) of the chamfer (35).

5. A manufacturing method according to any one of claims 1 to 4, further comprising a step of making (E4) interconnecting pads (50) carried out after the final polishing step (E3), in which at least one interconnecting pad (50) is made in line with the interconnecting element (40), on the side of the upper face (fs3).

6. A manufacturing method according to any one of claims 1 to 5, wherein the electrically insulating layer (30) comprises a silicon oxide.

7. A manufacturing method according to any one of claims 1 to 6, wherein, during the initial structure (10) provisioning step (E0), the initial structure (10) comprises a plurality of cavities (20) formed in the substrate (3), the interconnecting element (40) formation step (E1) then comprising the formation of a plurality of traversing parts (43) in said cavities (20).

8. A manufacturing method according to claims 3 and 7, wherein the removal of the excess layer (41) during the primary polishing step (E2) allows the formation of a plurality of TSVs, where each TSV corresponds to one of the through parts (43), each TSV being electrically connected to one of the lower elements (2) on the one hand and opening out on the side of the upper face (fs3) of the substrate (3) on the other hand.

9. A manufacturing method according to any one of claims 1 to 8, wherein during the provisioning step (E0), each cavity (20) is separated from at least one other cavity (20) by a distance that is strictly less than 10 pm, preferably strictly less than 5 pm, and preferably strictly less than 1 pm.

10. A manufacturing process according to any one of claims 1 to 9, wherein in the final polishing step (E3), the final polishing agent comprises: • 68 to 84% by mass of deionized water; • 15 to 30% by mass of silica; • 1 to 2% by mass of organic matter.

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