Packaged chip device

Abstract

Packaged Chip Device This description relates to a packaged chip device (100) comprising: - at least one connection pad (110) on a first surface of the chip; - at least one pillar (108) extending from, and in contact with, said pad (110); said pillar being made of an alloy of a first element and a second element, a melting temperature of said alloy being higher than a melting temperature of at least one of the first and second elements and higher than 260 °C. Figure for the abbreviation: Fig. 1

Description

Title of the invention: Packaged chip device technical field

[0001] This description relates generally to devices with conditioned chips and their manufacturing process. Previous technique

[0002] Packaged chip devices, such as flip-chip devices, consist mainly of a chip that is connected to a substrate having conductive pads. Conventionally, spherical solder bosses, which melt at less than 250 °C, or copper pillars with solder caps, are used to connect the chips to the pillars.

[0003] Weld bosses can present certain limitations when the pitch is reduced to obtain a higher integration density. For a defined pitch, this solution also has a limited attainable height due to its spherical shape. Summary of the invention

[0004] There is a need to provide a conditioned chip device that is compatible with a reduction in step size and higher integration density at reasonable costs.

[0005] Furthermore, there is a need to provide a conditioned chip device that is compatible with the inspection constraints of automotive circuits.

[0006] One embodiment overcomes all or part of the known drawbacks of conditioned chip devices.

[0007] One embodiment provides for a conditioned chip device comprising: - at least one connection pad on a first surface of the chip; - at least one pillar extending from, and in contact with, said plot; said pillar being made of an alloy of a first element and a second element, a melting temperature of said alloy being greater than a melting temperature of at least one of the first and second elements and greater than 260 °C.

[0008] One embodiment provides a method for manufacturing a device with a packaged chip, comprising: - the formation of the chip of the conditioned chip device, the chip having at least one connection pad on a first surface; - the formation of at least one pillar extending from, and in contact with, said block, and consisting of an alloy of a first element and a second element, a melting temperature of said alloy being greater than a melting temperature of at least one of the first and second elements and greater than 260 °C.

[0009] According to one embodiment, the ratio between the longitudinal extension of the pillar and its width is greater than 0.4.

[0010] According to one embodiment, said ratio is greater than 1, preferably greater than 2.

[0011] According to one embodiment, the longitudinal extension of the pillar describes an angle having an absolute value between 15° and 80° or between 100° and 165° with respect to a surface of the block.

[0012] According to one embodiment, the formation of said pillar comprises: - a first step comprising the deposition of a first quantity of a first material, consisting of particles of the first element and particles of the second element, in contact with the pad; - a second step comprising a processing temperature configured to form said alloy.

[0013] According to one embodiment, the formation of said pillar comprises: - a third step comprising a deposit of a second quantity of the first material, in contact with an entire upper surface of the first material which has undergone heat treatment or parts thereof; - a fourth step comprising a heat treatment configured to form said alloy; the third and fourth steps being repeatable.

[0014] According to one embodiment, at least the first and second steps are implemented on the scale of a plate.

[0015] According to one embodiment, the first element is Sn and the second element is chosen from Cu, Ag or Au.

[0016] According to one embodiment, an insulating material is arranged around all or parts of the lateral surfaces.

[0017] According to one embodiment, the insulating material surrounds the entire conditioned chip device.

[0018] According to one embodiment, the insulating material is absent from the lateral surfaces of the pillar facing outwards.

[0019] According to one embodiment, said lateral surfaces of the pillar facing outwards are ground or cut.

[0020] According to one embodiment, the melting temperature of said alloy is greater than a remelting temperature profile defined by JEDEC.

[0021] One embodiment provides a circuit assembly comprising: - the conditioned chip device as described above; - a printed circuit board comprising at least one connection pad whose surface area, viewed from above, is larger than the chip; and - a soldering material, having a melting temperature below 260 °C and the formation of a meniscus between the lateral surface of the pillar facing outwards and said pad of the printed circuit board.

[0022] One embodiment provides a method for using a conditioned chip device as described above, comprising: soldering the pillar to at least one connecting pillar of a printed circuit board using a soldering material having a melting temperature below 260 °C. Brief description of the drawings

[0023] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0024] [Fig.1] represents an assembly of a device with a conditioned chip according to one embodiment;

[0025] [Fig.2] represents a method for manufacturing a device with a conditioned chip according to an embodiment;

[0026] [Fig.3] represents a method for manufacturing a device with a conditioned chip according to an embodiment;

[0027] [Fig.4] represents a method for manufacturing a device with a conditioned chip according to an embodiment;

[0028] Figure 5 represents an assembly of a device with a conditioned chip according to one embodiment; and

[0029] [Fig.6] represents a graph of heat flux as a function of temperature. Description of the implementation methods

[0030] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0031] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0032] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0033] In the following description, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative, such as the terms "above", "below", "superior", "inferior", etc., or to orienting qualifiers, such as the terms "horizontal", "vertical", etc., it refers, unless otherwise specified, to the orientation of the figures.

[0034] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean within 10% or 10°, preferably within 5% or 10°.

[0035] Packaged chip devices, for example flip-chip devices or wafer-on-chip encapsulation device (WLCSP) or module devices, are devices, for example semiconductor circuits, integrated circuit chips, passive circuits, or microelectromechanical systems, comprising external interconnections on one side for connection to the receiving substrate, or circuit, comprising conduction pads. These external interconnections are conventionally made of ball-shaped solder bosses having a melting temperature below 250 °C. Soldering processes and temperatures normally comply with standards as defined by JEDEC (Joint Electron Device Engineering Council).

[0036] Due to the ball-like shape of the bosses, the integration density is limited horizontally. The interconnection height is also limited. Another drawback of this solution is that the solder can be remelted in the event of reflow at the melting temperature, such as during a flip-chip assembly, for example.

[0037] In order to increase the integration density or increase the interconnection height, pillars formed by electro-deposition have been developed. However, this solution is costly.

[0038] The described embodiments provide for a conditioned chip device comprising; - at least one connection pad on a first surface of the chip; - at least one pillar extending from, and in contact with, said block; said pillar being made of an alloy of a first element and a second element, a melting temperature of said alloy which is greater than a melting temperature of at least one of the first and second elements and greater than 260 °C, in other words greater than the remelting profile defined by JEDEC.

[0039] This allows for a lower manufacturing cost, for example, compared to copper pillars formed by electroplating. Furthermore, the resulting interconnections will not melt in the event of reflow soldering, which makes the device more robust.

[0040] Depending on the chip structure and the intended use of the final product, this solution may also provide for interconnections with flanks that can be wetted. by soldering without additional finishing and without risk of melting during final circuit assembly.

[0041] Fig. 1 represents a conditioned chip assembly 100 according to one embodiment.

[0042] The packaged chip assembly 100 includes a packaged chip device 102. The packaged chip device 102, which is, for example, a flip-chip device, a wafer-based chip encapsulation device (WLCSP), a module device, or a lead-free device, includes, for example, a semiconductor circuit 114, an integrated circuit chip 114, a passive circuit, or a microelectromechanical system. In the illustrated example, two external pads 110 of the packaged chip device are arranged on the underside of the chip 114. In one example, the number of pads can range from one to hundreds or even thousands. Pillars 108 extend from, and in contact with, the pads 110. The pillars 108 are, for example, formed by transient liquid sintering (TLPS) into an intermetallic alloy of a first element and a second element. In the text, the terms alloy and intermetallic alloy are similar.The first element is chosen, for example, from Sn or In, and the second element is chosen, for example, from Cu, Ag, or Au. The resulting alloy is, for example, an intermetallic alloy, such as an SnCu alloy or an AuSn alloy. The melting temperature of the intermetallic alloy is higher than the melting temperature of at least one of the first and second elements and is greater than 260 °C or greater than the remelting profile defined by JEDEC. In one example, the melting temperature of the alloy is greater than 350 °C.

[0043] In one example, the alloy is formed while the chip is oriented at 180° to the orientation of [Fig. 1], i.e., with the pads 110 facing upwards. The alloy is obtained by melting a mixture of the first and second elements at a temperature above 210 °C and below 260 °C, depending on the composition of the mixture and the particle size, for example, approximately 219 °C for a mixture comprising Sn and Cu. This mixture may also contain a refining agent for reduction. In the mixture, the first and second elements are, for example, in the form of micro- or nanoparticles, having, for example, an overall spherical shape.

[0044] The mixture can be deposited on the pads 110 by screen printing, or by spreading, for example before the melting step.

[0045] Once the melting step is complete, since the alloy has been formed, it will not melt again, even if a second melting step is applied to the chip. The alloy formed will also advantageously retain its shape without deforming into a spherical form, compared to conventional solder alloys, thus providing a suitable support for another deposition / melting treatment cycle of the mixture on top of the previously obtained alloy. This allows for several stacked layers of the alloy which together form the 108 pillars.

[0046] The final height of the resulting pillars 108 is, for example, tens of microns or even hundreds of microns. In one example, the height-to-width ratio of a longitudinal extension of the pillar, i.e., its height, to its width is greater than 0.4, for example, greater than 1, preferably greater than 2. This height-to-width ratio is greater than a height-to-width ratio that can be obtained with a conventional weld boss in a SnAgCu (SAC) alloy. This solution provides a precisely controllable safety distance, i.e., the distance between the conditioned chip device and the substrate 111.

[0047] In the example shown, the chip 114 is covered on each of its external surfaces with an optional insulating or protective material 112, which is, for example, a resin, a molding resin, or a polymer. In the example shown, the material 112 does not cover the pillars 108.

[0048] In the example of [Fig. 1], the pillars 108 are connected to the pads 106 of a substrate 111, which is, for example, a printed circuit board. A solder material 104 connects a region of the pillars to the respective pad 106. In one example, the melting temperature of the solder material 104 is strictly less than 260 °C, for example, 217 °C or a temperature as defined by JEDEC standards. The solder material 104 is, for example, a SnAgCu (SAC) alloy.

[0049] In one example, the surface footprint of the pads 106, in top view, is larger than the chip. This facilitates optical inspection.

[0050] Figure [Fig. 2] represents a method for manufacturing a device with a packaged chip according to an embodiment.

[0051] In a first step, chips similar to chip 114 are manufactured for example in a silicon wafer 214. The connection pads 110 of the chips are oriented upwards.

[0052] In a step 202, a first quantity 218 of the alloy is formed at the top of each of the pads. To do this, a resin (not shown) or a mask having openings aligned with the pads is deposited on the upper surface of the substrate. In one example, a layer of the mixture comprising the first and second elements is deposited on the mask, and a squeegee slides over the surface of the mask to remove the excess mixture. Screen printing, spreading, or spraying processes can also be used. After the mixture has been deposited, the mask is removed. Then, a first heat treatment, for example, between 230 °C and 250 °C, or in accordance with JEDEC remelting profiles, is applied to obtain the alloy. In one example, the first heat treatment is applied after the removal of the mask or before mask removal. Once the first quantity of alloy is formed, it retains its shape, which is for example the shape of the mask openings, thanks to the material having low sagging properties.

[0053] In a step 204, which follows step 202, another mask 220, for example made of the same material as the mask used in step 202 but with a greater thickness, is deposited on top of the substrate 214 and provided with openings aligned with the first quantities of alloy 218 obtained in step 202. A second quantity of the mixture of the first and second elements is deposited in each of the openings of the mask using, for example, a stencil as shown. A second heat treatment, for example similar to the first heat treatment, is carried out before or after the removal of the mask 220. Since the first quantity of alloy does not melt below 260 °C, it constitutes a stable base for the second quantity formed on top of it. During the second heat treatment, the first and second quantities of alloy become electrically connected, for example, by diffusion or by welding.The second quantity of alloy obtained retains its shape, which is, for example, the shape of the openings of mask 220.

[0054] In a subsequent step 206, the mask 220 is removed, for example, mechanically or chemically. In another example, a stencil may be used and, in this case, it must be removed before reflowing.

[0055] In a subsequent step 208, a third quantity of alloy is formed, for example in the same way as the second quantity, on top of the second quantity. The second and third quantities of alloy become electrically connected during the third heat treatment. The first, second, and third quantities of alloy form the pillars 108. In the example of [Fig. 2], only three quantities are stacked, but the number of stacked alloy quantities can be from one to ten, for example.

[0056] The openings of the different masks may have similar or different shapes. In one example, the openings of the first mask are larger than the openings of the second mask, and the openings of the second mask are larger than the openings of the third mask.

[0057] In a subsequent step 210, the individual chips 114 are individualized. A pick-and-place process can then be implemented.

[0058] In a step not shown, an insulating material, for example a resin, a polymer or a molding material, is formed around the chip 114 and in the gap between the pillars 108.

[0059] Figure [Fig. 3] represents a method for manufacturing a device with a packaged chip according to an embodiment.

[0060] The example in [Fig.3] includes a first step similar to step 202 in the example in [Fig.2].

[0061] In a step 304, subsequent to step 202, an insulating layer 320 of resin, polymer or molding material is formed on the wafer with a thickness greater than or equal to the height of the first quantity of alloy.

[0062] In a subsequent step 306, the thickness of the layer 320 is ground or polished until, for example, it is flush with the upper surface of the first quantities of alloy.

[0063] In a subsequent step 307, second quantities of alloy 324 are formed, for example in the same way as in step 204, for example not aligned with the first quantities of alloy, but offset horizontally in such a way that the first and second quantities of alloy are in electrical contact.

[0064] In a subsequent step 308, a second layer, for example of the same material as the material of layer 320, is formed on the first layer 320 and brought to a surface flush with the upper surface of the second quantities of alloy 324. Third quantities of alloy 334 are then formed, for example in the same way as in step 204, for example not aligned with the second quantities of alloy, but offset horizontally such that the second and third quantities of alloy are in electrical contact. Then, a third layer, for example of the same material as the material of layer 320, is formed on the second layer and brought to a surface flush with the upper surface of the third quantities of alloy 334.This process makes it possible to obtain pillars composed of the first, second, and third quantities whose longitudinal extension describes an angle between 15° and 80°, or between 100° and 165°, for example, relative to the surface of the chip or the pillars 110. In another example, a flat redistribution layer (RDL) can be obtained. In other words, the pillars describe an oblique or inclined orientation relative to the upper surface of the chip or the pillar. A redistribution layer is thus formed and can be used to connect the packaged chip device to a substrate that has connection pads with a different pitch compared to the pitch of the connection pads 110 of the chip 114.

[0065] In a step not shown, the insulating material 320 surrounding the pillars 108 can be removed entirely or completely.

[0066] In a subsequent step 310, the chips 114 are individualized.

[0067] Figure 4 represents a method for manufacturing a device with a packaged chip according to one embodiment.

[0068] In a step 402, a substrate comprising chips with their connection pads oriented upwards is treated to obtain trenches 416 between each chip. The trenches 416 originate from the upper surface of the substrate and are formed through a part of the substrate thickness but are neither dug nor cut through the entire thickness of the substrate.

[0069] In a subsequent step 404, pillars 108 are formed on the connecting pads, for example in the same way as in steps 202 to 210. In one example, step 402 is implemented after step 404.

[0070] In a subsequent step 406, an insulating material, such as a resin, a polymer or a molding material, 420 is deposited on the upper surface of the substrate so that the trenches 416 are filled as well as the spaces 421 between the pillars 108.

[0071] In a subsequent step 408, the material 420 is planarized, for example by grinding or polishing its upper surface, until its surface is flush with the top of the pillars.

[0072] In a subsequent step 409, the insulating material 420 is removed, by any mechanical or chemical or etching process, from all or part of the lateral surfaces 422 of the respective pillars, of each chip, which are turned outwards.

[0073] In one example, the outward-facing lateral surfaces 422 of the respective pillars for each chip are partially ground or sawn. In this case, the insulating material is still present in the region 421 between the pillars of each chip, but it is removed from the outward-facing lateral surfaces 422 of the pillars of each chip. In one example, part of the outward-facing surfaces is removed until the respective connecting studs are exposed. In another example, part of the outward-facing surfaces 422 is removed, but the respective connecting studs 110 are not exposed.

[0074] Step 409 allows the creation of flanks in the pillars which are, for example, more or less vertical. These flanks facilitate the formation of a solder meniscus when the chips are flipped over and soldered to a substrate.

[0075] In an optional step 410, the downward-facing surface 424 of the substrate, also called the rear face, is ground down until the trenches 416, which are filled with an insulating material, become accessible from its rear face 424.

[0076] In an optional step following 412, an insulating material, for example the same material or a different material as material 420, is formed on the back face 424, for example by rolling.

[0077] In a subsequent step 414, the chips are individualized at the trenches 416, by dividing the insulating material filling the trenches such that the insulating material surrounds each side of the individualized chips except for the outward-facing lateral sides of the pillars, which are arranged outward for each chip. The resulting individualized chips 440 are then optionally soldered to another circuit by means of a plug-and-transfer process.

[0078] Figure [Fig. 5] represents an assembly of a device with a conditioned chip according to one embodiment.

[0079] In the example shown, the chips 440, for example obtained as in step 414 of the previous [Fig.4], are returned for example with a take-and-transfer step and soldered to the connection pads 106 of a circuit for example similar to the circuit 111. The pads 106 extend for example more widely than the chip 424 to facilitate the formation of a solder meniscus 502.

[0080] In [Fig. 5], the top and the sawn, or hollowed, surfaces 422 of the pillars 108 are soldered to the respective connecting pads 106 with solder 104, which, when the temperature is above its melting point, forms a meniscus 502 between the connecting pads 106 and the lateral surface 422. The resulting meniscus shape extends, in top view, beyond the width of the chip 440. An automated optical inspection can then be performed from the top, or at an angle, to verify the presence of the meniscus 502 by reflecting light. The presence of the meniscus indicates that the packaged chip device, for example, a flip-chip or lead-free package, is then soldered to the pads 106 of the printed circuit board 111.

[0081] Figure 6 shows a graph of heat flux as a function of temperature. In the example shown, the heat flux is normalized.

[0082] More specifically, the example in [Fig. 6] shows how the alloy can be formed from a mixture, for example, of Sn and Cu particles in a carrier-forming refining agent. At room temperature, the mixture is pasty.

[0083] In step a), a temperature ramp, for example from 10 to 50 °C / min, preferably 37.5 °C / min, is applied to the mixture until it reaches, for example, 235 °C. In the example shown, the heat flow is stable at approximately -0.6 up to approximately 218.4 °C. Then, the heat flow drops to -2, which corresponds to the melting point of the first element, here Sn, which wets the second element, here Cu. This drop is then followed by a rapid increase to 2, and again by a less abrupt drop until it reaches 235 °C. This behavior is characteristic of interdiffusion between the first and second elements, leading to the formation of the intermetallic alloy.

[0084] In a subsequent step b), the temperature is kept stable for example for 5 minutes in order to improve the crystallinity of the alloy.

[0085] In a subsequent step c), the temperature is lowered at a rate between -5 and 50 °C / min, for example at least -40 °C / min, until it reaches ambient temperature. During step c), the heat flux remains stable at approximately 0.5. At this stage, the alloy is already formed. As it is in a solid state, its shape also remains sufficiently robust to withstand pick-and-place operations or to allow storage of the packaged chip device.

[0086] In a subsequent step (d), the temperature ramp, for example from 10 to 50 °C / min, for example 40 °C / min, is applied to the mixture until it reaches 300 °C, for example. In this example, the heat flux remains stable at approximately -0.6 up to the temperature of 300 °C. This demonstrates that no structural changes occur over time, that the alloy formed does not melt, and that inter-diffusion no longer occurs. The alloy and its overall shape remain stable even at temperatures typically used for welding, such as the conditions defined by JEDEC.

[0087] In a subsequent step e), the temperature is lowered at a rate between -5 and -50 °C / min, for example at -40 °C / min, until it reaches ambient temperature. During step e), the heat flux remains stable at approximately 0.5.

[0088] The packaged chip devices described above can be applied in all fields where flip-chip, LCSP, module, or lead-free devices are conventionally used. For example, the packaged chip devices described here are used for the Internet of Things (IoT), the automotive sector, or, for example, smartphones.

[0089] The device is intended, for example, for the automotive industry. The electrification of motor vehicles is generating an increasingly high level of electronic content in vehicles. The device includes, for example, thyristors, rectifiers, high-voltage transient suppression diodes, modules, etc., which must be incorporated into said vehicles. Automated driving is also generating an increasingly high level of electronic content in vehicles.

[0090] The device can, for example, be used in the industrial sector. More specifically, the device is intended, for example, to be used for developing green energy or for the electrification of infrastructure, for example, for charging stations or for incorporating solar energy. The device can also be used in the field of the Internet of Things and smart homes. The device is intended, for example, to be implemented in the power and supply circuits of equipment components.

[0091] The device can also be used in the implementation of cloud computing, 5G networks, data centers and servers.

[0092] The device is intended, for example, to be used in personal electronic equipment, for example to augment radio frequency content, in a 5G connection device or more generally in connected devices. The device is, for example, a smartphone or part of an Internet of Things network. The device is, for example, connected via 5G, WiFi or ultra-wideband. The device includes, for example, high-speed interfaces throughput, for example with advanced filtering and protection against electromagnetic discharges.

[0093] The described packaged chip devices are intended, for example, for use in communication equipment, or in computers or peripherals. For example, the device can be used in 5G infrastructure and dedicated data centers. The devices can also be used in satellites, including, for example, integrated passive devices for radio frequency applications.

[0094] The devices described can typically be used in high-frequency, high-power applications such as satellite communications, radar systems, and microwave amplifiers. They can also be used in certain specialized personal electronic devices such as high-end audio amplifiers or radio frequency (RF) transceivers.

[0095] The devices described are, for example, intended for use in LED (Light Emitting Diode) lighting systems designed to control current and voltage or to help improve the efficiency and performance of LED lighting systems.

[0096] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art. In particular, a person skilled in the art will be able, for example, to combine the examples in Figures 4 and 5. Also, even though in the figures described the pillars have a base larger than the width of their top, the base of the pillars could be designed to have a base smaller than the width of their top.

[0097] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional specifications given above. In particular, with regard to the formation temperatures of the intermetallic alloy of the pillars, a person skilled in the art will be able to adapt the heat treatment profiles according to their knowledge.

Claims

Demands

1. A device with a packaged chip (100) comprising: - at least one connection pad (110) on a first surface of the chip; - at least one pillar (108) extending from, and in contact with, said pad (110); said pillar being made of an alloy of a first element and a second element, a melting temperature of said alloy being greater than a melting temperature of at least one of the first and second elements and greater than 260 °C.

2. Device according to claim 1, wherein a ratio between the longitudinal extension of the pillar (108) and its width is greater than 0.

4.

3. Device according to claim 2, wherein said ratio is greater than 1, preferably greater than 2.

4. Device according to any one of claims 1 to 3, wherein the longitudinal extension of the pillar describes an angle having an absolute value between 15° and 80° or between 100° and 165° with respect to a surface of the block (108).

5. Device according to any one of claims 1 to 4, wherein the formation of said pillar comprises: - a first step comprising a deposition of a first quantity (218) of a first material, consisting of particles of the first element and particles of the second element, in contact with the block; - a second step comprising a processing temperature configured to form said alloy.

6. Device according to claim 5, wherein the formation of said pillar comprises: - a third step comprising a deposition of a second quantity of the first material, in contact with an entire upper surface of the first material having undergone heat treatment (218) or parts thereof; - a fourth step comprising a heat treatment configured to form said alloy; the third and fourth steps being repeatable.

7. Device according to claim 5 or 6, wherein at least the first and second steps are implemented on the scale of a wafer.

8. Device according to any one of claims 1 to 7, wherein the first element is Sn and the second element is selected from Cu, Ag or Au.

9. Device according to any one of claims 1 to 8, wherein an insulating material (320, 420) is arranged around all the lateral surfaces of the pillar (108) or parts thereof.

10. Device according to claim 9, wherein the insulating material surrounds the entire conditioned chip device.

11. Device according to claim 9, wherein the insulating material is absent from the outward-facing lateral surfaces (422) of the pillar.

12. Device according to claim 11, wherein said outwardly facing lateral surfaces (422) of the pillar are ground or cut.

13. Device according to any one of claims 1 to 12, wherein the melting temperature of said alloy is greater than a remelting temperature profile defined by JEDEC.

14. A method for manufacturing a conditioned chip device (100) according to any one of claims 1 to 13, comprising: - forming the chip (114) of the conditioned chip device; - forming said at least one pillar (108) so that it extends from, and in contact with, said pillar, and that it is made of said alloy of the first element and the second element, the melting temperature of said alloy being higher than the melting temperature of at least one of the first and second elements and higher than 260 °C.

15. Circuit assembly comprising: - the device with chip packaged according to any one of claims 11 to 13; - a printed circuit board (111) comprising at least one connection pad (106) having a top-view surface footprint larger than the chip; and - a solder material, having a melting temperature below 260 °C and the formation of a meniscus between the outward-facing lateral surface (422) of the pillar and said pad (106) of the printed circuit board.

16. A method for using a device with a conditioned chip according to any one of claims 1 to 13, comprising: the soldering of the pillar (108) to at least one connecting pillar (106) of a printed circuit board (111) using a soldering material having a melting temperature below 260 °C.

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