IMPROVED METHOD FOR CONFIGURING AN ELECTRONIC DEVICE COMPRISING A LOW POWER RADIO INTERFACE, ELECTRONIC DEVICE, AND COMPUTER PROGRAM PRODUCT.

Abstract

The invention relates to an electronic device (1) configured to perform wireless communications via a low-power communication interface (RI 145) when the electronic device (1) is operating in a deep sleep mode, and to an improved method for configuring said electronic device (1) during deep sleep. Figure to be published with the abstract: Fig. 1

Description

Title of the invention: IMPROVED METHOD OF CONFIGURATION OF AN ELECTRONIC DEVICE COMPRISING A LOW POWER RADIO INTERFACE, ELECTRONIC DEVICE, AND COMPUTER PROGRAM PRODUCT. technical field

[0001] The present invention relates to the field of electronic devices and equipment, particularly for household use, such as communication network gateways, for example, configured to operate in very low-power modes. More specifically, the invention relates to an improved method for configuring such a device or equipment to operate in a deep sleep mode, and comprising a short-range, low-power wireless communication interface, which interface enables communication modes to operate in the deep sleep configuration of the electronic device or equipment. STATE OF PRIOR ART

[0002] Electronic devices comprise several electronic circuits, each of which is conditionally supplied with electrical energy depending on whether one or more functions are activated at any given time. For example, a communication interface can be deactivated when it is not in use. It is thus possible to define different operating modes resulting in different levels of electrical energy consumption. In order to substantially reduce the electrical energy consumption of devices, and in particular household electronic devices, a so-called "deep sleep" mode is often defined as the operating mode in which the device in question consumes the least possible electrical energy.Only minimal electronic circuitry, resulting in the lowest possible energy consumption, remains active in such a deep sleep mode, in order to guarantee a minimum level of interoperability with a user or with third-party devices. For example, a user of an electronic device must be able to "wake up" it when it is configured in deep sleep, either by pressing a button on the device itself, or, for example, via a third-party device such as a remote control, or even via an electronic device acting as a remote control, that is, by performing a remote control function. Thus, many current electronic devices... include a main electronic circuitry which includes a main processor sized to handle many functions (for example, managing a fiber optic communication interface with a broadband network) as well as a secondary, or auxiliary, electronic circuitry, which is responsible for ensuring a minimum of interoperability with the environment of the electronic device when the main electronic circuitry is totally disabled for energy saving purposes.The evolution of integrated circuits dedicated to specific functions, such as the functions inherent in a home network gateway or a television receiver-decoder, as non-limiting examples, is such that this type of architecture generally features a main processor in charge of performing common tasks specific to a main circuitry, as well as a secondary or auxiliary processor operating within a second electronic circuitry, secondary or auxiliary, in charge of ensuring minimum operability, with the lowest possible power consumption.According to these known architectures, the secondary processor, often of the microcontroller type, generally includes a short-range wireless communication interface allowing the electronic device to communicate with remote equipment in the immediate or nearby environment, notably for the purpose of allowing the electronic device to exit a deep sleep mode.

[0003] It should be noted that, to achieve this, the secondary processor is then capable of controlling a power supply interface circuit able to switch one or more non-permanent power supply lines to provide conditional power to the main electronic circuitry. Thus, the secondary processor of the secondary electronic circuitry is intended to control the power supply to the main electronic circuitry.

[0004] In the case of embedded wireless communication systems using coprocessors, this type of architecture frequently operates according to specific communication modes, called "RCP mode" (for "Radio CoProcessor") and "NCP mode" (for "Network CoProcessor"). These modes are defined according to the respective functionalities offered by the primary and secondary processors. According to the so-called "RCP mode," the secondary processor only manages the wireless communication aspects (functions) related to the physical and MAC layers, while the primary processor handles the higher network layers and the application part of the software.According to the so-called "NCP mode", the secondary processor manages both the wireless communication aspects (functions) related to the physical and MAC layers, as well as a large part of the network stack implementation, leaving only the application layer or others to be managed by the main processor. Specific functions. While the described RCP and NCP operating modes offer the advantage of simplifying the development of electronic devices based on the described architecture, and simplifying their software maintenance, these implementations do not allow for communication using recent short-range communication protocols such as, for example, Matter over Thread when such an electronic device is configured in deep sleep mode. Furthermore, the inability to perform such communication when the electronic device is configured in deep sleep mode hinders modifications to the device's global configuration parameters, which must be considered when implementing, in active mode and under the control of the main electronic circuitry, certain functionalities offered by the electronic device.

[0005] The situation can be improved. Description of the invention

[0006] An object of the present invention is to provide an electronic device and a method for configuring this device operating in deep sleep mode, enabling the integration of radio management of the physical and MAC layers and the entire network stack, as well as application functions, within the capabilities of a single processor operating as a secondary or auxiliary processor of a secondary or auxiliary electronic circuitry that remains active in deep sleep mode. Advantageously, this also allows for the configuration or reconfiguration of the electronic device operating in deep sleep mode.

[0007] To this end, an electronic device is proposed comprising at least a first electronic circuit and a second electronic circuit, the first electronic circuit comprising a first processor, called the "main processor" connected to a first memory called the "main memory", and the second electronic circuit comprising a second processor, called the "secondary processor", connected to a second memory called the "secondary memory", the secondary processor comprising a wireless communication interface, called the "low-power radio interface", and the secondary processor being configured to communicate via a communication link with the main processor when the first electronic circuit is powered electrically,the first electronic circuit being configured to be conditionally powered via a power interface circuit controlled by the secondary processor and the second electronic circuit being continuously powered when the electrical device is connected to a primary power supply,

[0008] the electronic device being configured such that:

[0009] - the low-power radio interface is configured to cooperate with a configuration data memory writable by the main processor via a communication link between the main processor and the secondary processor,

[0010] - the low-power radio interface is capable of operating communications bidirectional autonomously with at least one remote device, according to a communication configuration determined from information stored in the configuration data memory, when the first circuitry is not powered, and,

[0011] - the secondary processor is capable of storing in the secondary memory of second configuration information of the electronic device when the first circuitry is not supplied with electrical power.

[0012] The device according to the invention may further comprise the following optional features, considered alone or in combination:

[0013] - The low-power radio interface is capable of operating communications according to a standard and / or short-range communication protocols.

[0014] - The low-power radio interface is capable of operating communications according to a standard and / or predetermined communication protocols from among: Bluetooth, Zigbee, and Thread.

[0015] - The secondary memory includes a non-volatile memory type memory area.

[0016] Another object of the invention is a method for configuring an electronic device as described above, the method being carried out in the second electronic circuit and comprising:

[0017] - obtain, from the main processor, in the data memory of configuration, initial configuration information representative of an operating mode to be used by the low-power radio interface,

[0018] - perform an initial check of the power interface circuit to disable the power supply to the first electronic circuitry, so as to configure the electronic device in deep sleep mode,

[0019] - to memorize, in secondary memory, second pieces of information configuration of the electronic device obtained via wireless communications through the low-power radio interface, according to an operating mode of the low-power radio interface determined by all or part of the initial configuration information obtained, when the electronic device is configured in deep sleep, and,

[0020] - perform a second check of the power interface circuit to activate the power supply of the first electronic circuitry, so as to configure the electronic device in active mode, then transmit all or part of the second configuration information to said main processor.

[0021] The method according to the invention may further have the following optional characteristics, considered alone or in combination:

[0022] - The configuration data memory is dedicated to the operation of a module low power radio interface control and is configured to understand configuration information to be used with reference to an application-level software layer of the low power radio interface control module.

[0023] - The method further comprises, prior to the first circuit check power interface: obtain secondary configuration information, representative of hardware and / or software configuration parameters of said electronic device.

[0024] - The communication mode to be operated by the radio interface is defined according to a communication standard among Bluetooth, Zigbee, and Thread.

[0025] - The method further comprises, during communications conducted in deep sleep mode, a detection of an event previously defined as a condition for exiting deep sleep, then a control, by the secondary processor, of the power interface module to activate the power supply to the first electronic circuitry, so as to configure the electronic device in active mode.

[0026] - The previously defined event is the presence of a third-party device within range electromagnetic low-voltage communication interface.

[0027] Another object of the invention is a computer program product comprising program code instructions to execute steps of a configuration process as previously described, when this program is executed by a processor of an electronic device.

[0028] The invention finally relates to a storage device comprising a computer program product as mentioned above. Brief description of the drawings

[0029] The features of the invention mentioned above, as well as others, will become clearer upon reading the following description of at least one exemplary embodiment, said description being made in relation to the accompanying drawings, among which:

[0030] [Fig-1] illustrates a home network gateway type electronic device according to a method of implementation;

[0031] [Fig.2] is a flowchart schematically illustrating the steps of a process improved configuration of an electronic device running in a secondary circuit of the electronic device already shown in [Fig.1], according to one embodiment;

[0032] [Fig.3] schematically illustrates the electronic device already shown in [Fig.1] in the environment of which is present in particular a third electronic device of the smartphone type allowing to operate a configuration of the electronic device operating a deep sleep mode;

[0033] [Fig.4] is a diagram illustrating details of protocol exchanges between the devices already represented on [Fig.3] and in particular a deep sleep configuration of the electronic device already represented on [Fig.1];

[0034] [Fig. 5] is a diagram illustrating an example of the internal architecture of a main processor of the electronic device already shown in [Fig. 1]; and,

[0035] [Fig.6] is a diagram illustrating an example of the internal architecture of a secondary processor of the electronic device already shown in [Fig.1].

[0036] DETAILED DESCRIPTION OF IMPROVEMENTS

[0037] Fig. 1 illustrates an electronic device GW 1, here of the network communication gateway type, also called "network gateway" GW 1 in this description, and of a type sometimes commonly called "gateway", from English.

[0038] The GW 1 network gateway is configured to operate primarily, but not exclusively, as a link and communication interface between a first network, of the wide area network (WAN) type, connected to an OL input of a primary communication interface MCI 15 of the GW 1 network gateway, and a second, local area network (LAN) type, connected to a LAN interface of a primary processor MP 13 of the GW 1 network gateway. The GW 1 network gateway also includes wireless communication means to be capable of establishing one or more wireless networks, of the WLAN (Wireless Local Area Network) type, for example using the 802.11 technology or standard in one of its versions, such as 802.11-2012, 802.11-2016 or 802.11-2020, with one or more of these amendments such as 802.11n-2009, 802.1 lac-2013, 802.11ax-2021, or the provisional version of Amendment P802.1 Ibe in its edition D7.00. This or these WLAN networks are managed primarily by the MP 13 main processor.

[0039] The network gateway GW 1 includes a first electronic circuit MC 11 which is conditionally powered from a power supply module PSU 2, via a power supply interface module (or circuit) PI 19, also commonly referred to as the "power interface". The power supply module PSU 2 is connected to a single-phase electrical distribution network 3, commonly referred to as the "mains supply". The first electronic circuit MC 11 includes a main processor MP 13 arranged to implement many of the usual functions of a home network gateway. The main processor MP 13 is connected to a first memory MM 15, referred to as "memory". main » MM 15 which includes RAM type memory areas and non-volatile memory (or ROM) type memory areas.

[0040] The main processor MP 13, cooperating with the main memory MM 15, performs most of the functions supported and offered by the network gateway GW 1, or even most of the main functions available.

[0041] By way of non-limiting examples, the main processor MP 13 manages and controls the main communication interface MCI 15 of the first electronic circuitry to which it is connected via a communication link 135b, as well as a plurality of communication interfaces to a local network, similar to the LAN interface of the first electronic circuitry.

[0042] The network gateway GW 1 further includes a second electronic circuit SC 12, which is always powered by the power supply module PSU 2 when the latter is connected to the electrical distribution network 3, referred to as the "mains." The second electronic circuit SC 12 is intended to operate as a secondary, or auxiliary, electronic circuit and includes a second processor AP 14, adapted for operation with very low power consumption (for example, less than 0.5 W). The secondary processor AP 14 of the second electronic circuit SC 12 is connected to the main processor of the first electronic circuit MC 11 via a communication link 132b. In one embodiment, the communication link 132b is a bidirectional wired communication link. For example, the communication link 132b is a serial link between two UART modules or an SPI bus.

[0043] Advantageously, the secondary processor AP 14 is connected to a second memory AM 16, referred to as "secondary memory" AM 16, which comprises at least one or more RAM-type memory areas and optionally one or more non-volatile memory (or ROM)-type memory areas. The secondary memory AM 16 is the working memory of the secondary processor AP 14.

[0044] Furthermore, the secondary processor AP 14 includes a low-power communication interface RI 145 connected to an antenna system A 145a. In one embodiment, this communication interface is compatible with the Bluetooth Low Energy (“BLE”) standard and is short-range. In another example, this communication interface is compatible with a LoWPAN-type protocol, such as Thread, and offers a communication range equivalent to or greater than that offered by 802.11 technology in the 2.4 GHz band.

[0045] Thanks to this communication interface, the GW 1 network gateway is able to communicate with any remote device present in its environment and within its electromagnetic range, provided that this remote device is compatible with the communication protocol(s) and / or standard(s) supported by the interface. RI 145 communication. In one embodiment, the RI 145 communication interface is a low-power, short-range interface. In non-limiting examples, the RI 145 interface is compatible with one or more of the following protocols or sets of protocols: Bluetooth, Zigbee, Thread, UWB (registered trademarks). Naturally, the communication interface can implement other existing communication protocols and / or standards. Thread is a mesh wireless communication protocol (based on IPv6). Matter is an open, IP-based connectivity standard designed for the Internet of Things and, for example, smart home technology. The Thread protocol is particularly well-suited for carrying control and / or data messaging from the Matter connectivity standard.

[0046] With regard to the operating and power consumption modes respectively defined as an "active mode" and a "deep sleep mode", the secondary processor AP 14 is configured to control a control line 194 (via an output port of the secondary processor AP 14), which control line is capable of turning on or off a power switch SWC 192 included in the power interface circuit PI 19. Thus, when the secondary processor AP 14 controls a closing of the power switch SWC 192, the electrical energy supplied to the output 191 of the power supply module PSU 2 is available on a power link 190 which connects the output of the power interface module PI 19 to the first electronic circuitry MC 11, and the network gateway GW 1 then operates in active mode.Conversely, when the secondary processor AP 14 controls the opening of the power switch SWC 192, the electrical power delivered by the power supply module PSU 2 is no longer supplied to output 190 of the power supply module PSU 2, which connects the output of the power interface module PI 19 to the first circuit board MC 11. As a result, the first circuit board MC 11 is no longer powered. The network gateway GW 1 then operates in deep sleep mode, and only the second circuit board SC 12 remains powered via the power link 191 connected upstream of the power interface module PI 19.Therefore, it is the secondary processor AP 14, which remains continuously supplied with electrical power when the GW 1 network gateway electronic device is connected to the mains, that controls the transitions between active mode and deep sleep mode, according to predetermined transition conditions.

[0047] According to one embodiment, a third RIM 145m memory dedicated to parameterizing the radio communication stack of the RI 145 communication interface is cleverly and advantageously integrated into or associated with the latter, so as to allow an internal controller module of the interface to The RIM 145m communication memory provides all the necessary elements for implementing short-range wireless communications with third-party communication devices, according to recent communication protocols and / or standards, when the GW 1 network gateway is operating in deep sleep mode. In one embodiment, the RIM 145m memory is implemented externally to the RI 145 communication interface but is connected to it, either directly or via the AP 14 secondary processor.

[0048] The RIM 145m memory is herein referred to as the "radio stack memory". According to one embodiment, the third RIM 145m memory, dedicated to parameterizing the radio communication stack of the RI 145 communication interface, is included in the AM 16 secondary memory. According to another variant, the third RIM 145m memory is implemented in a separate component independent of the AM 16 secondary memory.

[0049] The third RIM 145m memory, or radio stack memory, dedicated to the communication stack of the RI 145 communication interface, is configured to store operating parameters of the RI 145 communication interface, in particular operating parameters of an application-level software layer of the RI 145 communication interface stack. Cleverly, this dedicated memory of the RI 145 communication interface stack is directly accessible by the main processor MP 13 or optionally via the secondary processor AP 14, through defined protocol exchanges between the main processor MP 13 and the secondary processor AP 14.It is then advantageously possible for a remote third-party device to communicate with the GW 1 network gateway, according to recent communication protocols and / or standards, including in compliance with application-level communication specifications, via the short-range, low-power communication interface RI 145. Laboratory tests have shown that a network gateway device based on the described hardware and software architecture, consuming up to 30 W in active mode, is advantageously capable of operating communications according to a standard commonly called "Bluetooth" or "Matter on Thread" when the same device consumes no more than 500 mW in deep sleep mode.

[0050] In deep sleep mode, the secondary processor AP 14 autonomously manages the RI 145 communication interface, which acts as an alternative wireless communication interface within the GW 1 network gateway, thanks to the complete integration of a network stack and a minimal application software layer (or application-level software layer), thus ensuring continuous operation of the RI 145 wireless communication interface in the GW 1 network gateway's deep sleep mode. including when its main MP 13 processor is completely inactive because it is not receiving electrical power.

[0051] According to one embodiment, the internal control module of the RI 145 wireless communication interface implements and supports Bluetooth Low Energy technology as well as the 2.4G IEEE 802.15.4 radio platform (Thread and Zigbee) and all network layers useful for BLE and Thread technologies are implemented in the network stacks (also commonly called Network Stacks) of the RI 145 wireless communication interface.

[0052] According to one embodiment, a module called the "Lightweight Co-processor Application," executed by the secondary processor AP 14, manages the power supply of the network gateway GW 1 in combination with applications executed by the main processor MP 13 when the network gateway GW 1 is operating in active mode. This module obtains specific information related to managing the communication protocols of the wireless communication interface RI 145, which is to be operated when the network gateway is in deep sleep mode. Thus, the wireless communication interface RI 145 is capable of operating wireless communications independently when the network gateway GW 1 is in deep sleep, while maintaining, for example, communications using a communication protocol such as BLE or Matter over Thread.

[0053] According to one embodiment, communication between the main processor MP 13 and the secondary processor AP 14, possible in active mode, is achieved by sending protocol messages via the communication link 132b, and is ensured by a module called herein “communication handler”.

[0054] According to one embodiment, when the GW 1 network gateway is operating in active mode, the MP 13 main processor manages the communication protocol implemented by the RI 145 communication interface via the RI 145 internal control module operating in NCP mode. Thus, during a Bluetooth connection, for example, the MP 13 main processor operates as an NCP BLE host, handling the initialization and configuration of the Bluetooth stack as well as the associated BLE services. It also transmits, via the dedicated RIM 145m memory, one or more configurations to the AP 14 secondary processor performing the aforementioned "Lightweight Co-processor Application" function, which are useful and necessary for managing the communication protocol(s) and / or standards implemented when the GW 1 network gateway is operating in deep sleep mode.

[0055] According to another embodiment, and in the context of a Thread-based connection, the MP 13 main processor operates the role of NCP Thread Host and also acts as the Matter over Thread controller. The MP 13 main processor is then responsible for and guarantees the initialization and configuration of the Thread stack as well as the "commissioning Matter". In addition, it communicates, here too, via the dedicated RIM 145m memory, one or more configurations to the secondary processor AP 14 operating the aforementioned function of "Lightweight Co-processor Application", essential for managing and operating the Matter over Thread communication protocol when the GW 1 network gateway is operating in deep sleep.

[0056] The architecture again allows the main processor MP 13 to share the execution of certain prerogatives of the application layer with the secondary processor AP 14, particularly with regard to wireless communications.

[0057] Indeed, when the network gateway GW 1 operates in active mode, the main processor controls the communication interface RI 145 in NCP mode and transmits, via the dedicated memory RIM 145m, one or more specific configurations, including so-called "user" configurations, to the secondary processor AP 14, for managing wireless communications to be operated in deep sleep mode. In deep sleep mode, the secondary processor AP 14 then uses the configuration information (data) previously transmitted in active mode by the main processor MP 13, such as, for example, the definition of an event that should trigger the network gateway GW 1 to exit deep sleep mode, such as a change of state of a remote third-party device connected via Matter over Thread or via a Bluetooth connection. Such a remote device is, for example, a user's connected smartphone.

[0058] Thus, advantageously, when the network gateway GW 1 operates in deep sleep mode, the secondary processor AP 14 is also capable of receiving, via the wireless communication interface RI 145, and from a remote third-party device, second configuration information, useful for configuring or reconfiguring operating parameters of the network gateway GW 1, and of storing this second configuration information in its working memory AM 16. Such second configuration information comes, for example, from a user.

[0059] Advantageously, the secondary processor AP 14 can transmit this information in a delayed manner to the main processor MP 13 of the network gateway GW 1, when the latter is again operating in active mode. Thus, the second electronic circuitry can act as a cache memory for the transmission of configuration information between a remote third-party device connected to the wireless communication interface RI 145 and the main processor MP 13 and its working memory, the main memory MM 15.

[0060] Figure 2 schematically illustrates steps in a configuration process for network gateway GW 1 executed in network gateway GW 1, under the control of the secondary processor AP 14 operating in combination with its working memory, secondary memory AM 16.

[0061] An S0 step is an initialization step following the power-up of the network gateway GW 1, at the end of which all circuits useful for the described processes are normally powered, initialized, and operational. During an SI step, the main processor MP 13 and the secondary processor AP 14 both perform their respective main functions, including the functions of a home network gateway between the wide area network connected to the OL communication link and the local area network connected to the LAN communication link, in addition to other usual interconnection functions. Furthermore, during the SI step, the main processor transmits configuration information (or data), including initial application-level configuration information, to the secondary processor AP 14, via the dedicated RIM 145m memory of the RI 145 communication interface.Communication information is transmitted via the 132b communication link established between the two processors MP 13 and AP 14. For example, the main processor operating a role and functions of BLE NCP Host manages the RI 145 communication interface and configures a communication stack according to the Bluetooth communication protocol / standard from a user-customized BLE data model and transmits to the secondary processor all or part of the parameters, including Bluetooth configuration parameters to be considered for deep sleep operation.It should be noted that in active mode of the GW 1 network gateway, one or more users can interact with applications running on the MP 13 main processor, for example via a web UI or a mobile application running on a smartphone connected to the RI 145 communication interface, to adjust configuration parameters to be subsequently applied by the AP 14 secondary processor in deep sleep mode. One such parameter might be the ability of the GW 1 network gateway to wake from deep sleep mode upon the first Bluetooth connection of a user's smartphone.

[0062] Cleverly and advantageously, when operating in active mode, the main processor MP 13 also transmits global configuration information from the network gateway GW 1 to the secondary processor AP 14, which stores it in the secondary memory AM 16 for backup purposes during future deep sleep operation. Indeed, since the AM 16 memory is implemented and deployed in the second electronic circuit SC 12, it is continuously powered when the network gateway GW 1 is connected to the mains power supply via its power supply module PSU 2.

[0063] During step S2, the secondary processor AP 14 configures the network gateway GW 1 into standby mode by controlling the control link 194, which opens the power switch 192 and isolates the power line 190 from the first electronic circuit MC 11 (and thus from the main processor MP 13) of the power supply module PSU 2. This standby mode configuration can be triggered by observing a particular context or by the occurrence of a predetermined event from a list of predefined events. For example, the secondary processor AP 14 can detect that no activity has been observed for a specified period. For example, no communication flow related to the use of the network gateway GW 1 or via a device connected to the gateway has been detected for 10 minutes, or 15 minutes, etc.Based on this example and in this context, it appears that operating the gateway in active mode is not useful and that a deep sleep mode configuration is therefore beneficial in terms of energy savings. In another example, the secondary processor can configure the deep sleep mode of the GW 1 network gateway according to a schedule previously defined by a user, for example, based on users' home presence habits.

[0064] During an S3 step, the network gateway GW 1 is configured in deep sleep mode, and only the second electronic circuit SC 12, comprising the secondary processor AP 14 connected to its working memory, is operational, out of the two electronic circuits MC 11 and SC 12. The secondary processor AP 14 then performs reduced functions but has the capacity to manage short-range, low-power communications via its communication interface RI 145 and according to configuration data previously obtained from the main processor MP 13 and stored in the dedicated RIM 145m memory. The secondary processor can also store, notably in the secondary memory AM 16, information or data received via the communication interface RI 145.In particular, the AP 14 secondary processor has the ability to manage application-level functions based on wireless communications operated via the RI 145 communication interface, such as the ability to temporarily store global configuration parameters in its AM 16 memory during an S4 step to subsequently configure the GW 1 network gateway in active mode (i.e., "wake up" the gateway) and update these configuration parameters in the MM 15 main memory. Indeed, in deep sleep, a remote third-party device from a user can therefore communicate with the secondary processor via the RI 145 communication interface, in BLE or Thread mode, for example, to transmit new configuration parameters to the GW 1 network gateway or even read current configuration parameters, via the AM 16 secondary memory. Thus, a new . The transmitted configuration can, for example, via the secondary processor AP 14, request control of the power supply interface module PI 19 to establish power to the first electronic circuit MC 11 by means of the power switch SWC 192. When the secondary processor AP 14 performs such control, the network gateway GW 1 operates again in active mode. It is then possible for the secondary processor AP 14 to transmit to the main processor MP 13 information previously stored in the secondary memory AM 16. The secondary memory AM 16 then acts as a cache memory useful for the delayed transmission of global configuration parameters of the network gateway GW 1 from a remote third-party device connected via the communication interface RI 145.

[0065] Advantageously, it is thus possible to configure or preconfigure the GW 1 network gateway during a wake-up phase (transition between deep sleep and active mode), which wake-up phase can last several seconds, or even several tens of seconds.

[0066] Figure 3 schematically illustrates an environment and configuration for using the network gateway GW 1, interconnecting a wide area network (WAN) connected to its communication link OL and a local area network (LAN) to which a laptop computer L is connected. According to the described use case, a smartphone S is active within electromagnetic range of the antenna system A of the network gateway GW 1 and can communicate with the secondary processor AP 14, via the IR communication interface 145, when the network gateway GW 1 is operating in standby mode. A wireless communication link BL is then established between the network gateway GW 1 and the smartphone S. According to the example described here, the communication link is configured to operate using a Bluetooth communication protocol.

[0067] Figure 4 describes a sequence of information exchanges between the various elements of the illustrated environment in relation to Figure 3, illustrating a deep sleep of the network gateway GW1 followed by configuration from the smartphone S during deep sleep. For the sake of simplicity, the sending or transmission of data or information of any kind (for example, a modified electrical signal) is referred to here as "a message".

[0068] According to the example described, the main processor MP 13, which must be configured in deep sleep mode (for example, following a long period of application-level inactivity), addresses to the secondary processor AP 14, during a CS1 step, a configuration message ml for the communication interface RI 145, including configuration information for a complete network stack, including application-level configuration information, as well as global configuration information, That is, a table of current global configuration parameters (or "data model") for the GW 1 network gateway, for backup purposes, and possibly for updating through reconfiguration. This backup of global parameters is, in a way, a context backup for deep monitoring.

[0069] During a CS2 step, the secondary processor AP 14 stores the information specific to the communication interface RI 145 in the RIM 145m memory and the context information (or current global parameters in the form of a "data model") in the secondary memory AM 16 in a message m2. The secondary processor AP 14 then acknowledges receipt of this information to the main processor MP 13, via a message m3, during a CS3 step, as well as the need to control the network gateway GW 1 in deep sleep mode. The secondary processor AP 14 then performs control in deep sleep mode via a message m4, during a CS4 step, addressed as a signal to the power supply interface module PI 19, which deactivates the power supply to the first electronic circuit MC 11.The GW 1 network gateway is currently configured in deep sleep mode and can therefore only communicate with remote third-party devices via its RI 145 communication interface.

[0070] Then, during a CS5 step, the smartphone S approaches the network gateway GW 1, for example, due to a user returning home to consult configuration parameters, and sends a connection message m5 to the secondary processor AP 14, via the communication interface RI 145. The secondary processor AP 14 operates during a CS6 step and via a message m6 a control of the power supply interface module PI 19 in order to wake up the gateway GW 1, that is to say, to control an active mode by restoring the power supply to the first electronic circuit MC 11. This is, in a way, an advance wake-up command since in this context it is quite possible and conceivable that a user will want to use the network gateway GW 1 or consult its configuration.During a CS7 ​​step, the secondary processor accesses the AM 16 secondary memory via an m7 message and obtains all or part of the global configuration parameters previously saved in AM 16 memory during a CS8 step, via an m8 message. The AP 14 secondary processor is then able to respond to the information request from the smartphone S and sends it a response message m9 during a CS9 step to do so. According to the example described, the smartphone S (or at least a user using the smartphone S) wants to modify one or more global configuration parameters of the gateway GW 1 (i.e., of the "data model") and sends the AP 14 secondary processor, via the RI 145 communication interface, an mlO message to that effect during a CS10 step.

[0071] According to the example described, the main processor MP 13, having become active again after a wake-up period, notifies the secondary processor AP 14, during a CS11 step and via a mil message, of its availability to resume control of the main functions of the network gateway GW 1. The secondary processor, in turn, updates the contents of its global parameters (the "data model" memory area in the AM 16 secondary memory) during CS12 and CS13 steps, using the (re)configuration information obtained from the smartphone S in the mlO message. This update of the local configuration in the AM 16 memory is performed via the ml2 and ml3 messages, which correspond to the execution of memory accesses to the AM 16 memory by the AP 14 secondary processor.

[0072] The secondary processor AP 14, having received the availability notification from the main processor MP 13, sends the latter, during a CS14 step and via an ml4 message, a complete updated version of the global parameters (i.e., a copy of the "data model"), thus operating as a cache memory controller. The main processor MP 13 then updates its main memory MM 15 via an ml5 message during a CS15 step, and then acknowledges receipt of this configuration information to the secondary processor AP 14 via an ml6 message during a CS16 step.

[0073] Advantageously, and thanks to the communication capability of the RI 145 wireless communication interface, which is then self-contained, configuration or reconfiguration of one or more global operating parameters of the GW 1 network gateway is possible, even when it is operating in deep sleep mode. This is made possible in particular by the dedicated RIM 145 memory, which allows for the implementation of a complete radio stack to operate wireless communications autonomously in deep sleep, as well as by the presence of the AM 16 secondary memory, coupled with the AP 14 secondary processor, which operates as a cache memory during deep sleep phases.

[0074] According to one embodiment, all or part of the secondary memory AM 16 is implemented as non-volatile memory, for example as so-called "flash" memory, which allows the information obtained to be retained in the event of a mains power failure. Indeed, in such a case, and in the absence of a backup battery, neither the first circuit MC 11 nor the second circuit SC 12 remains powered by electricity.

[0075] After power is restored and following an accidental power interruption, it is possible to retrieve the last global configuration parameters from secondary memory AM 16 and to notify a user of the current configuration parameters following the incident. It is also possible to to request a user, via one or more user interfaces, to adjust or bring the current configuration into compliance with their needs.

[0076] Advantageously, these mechanisms allow the GW 1 network gateway to be configured both via a LAN to which it is connected and via a dedicated application running on a smartphone, including when the GW 1 network gateway is operating in deep sleep mode, and without having to wait for the completion of a restart process in active mode. An advantageous use case is, for example, being able to configure the GW 1 network gateway while it is operating in deep sleep mode, without having to first wake it from deep sleep, then configure it when it has become operational again in active mode, and finally restart the GW 1 network gateway for the new configuration to take effect.

[0077] The example sequence described here is obviously not limiting and is only intended to illustrate the protocol exchanges of messages made possible between the different elements or devices present thanks to the communication capabilities made accessible in deep sleep mode of the GW 1 network gateway. Other configuration message sequences could be implemented, in particular using other short-range and low-power communication protocols and / or standards.

[0078] Figure 5 schematically illustrates an example of the internal architecture of the main processor MP 13 of the network gateway GW1. It should be noted that Figure 5 could also represent an internal architecture of the first electronic circuitry MC 11. According to the example of hardware architecture shown in Figure 5,5], the main processor MP 13 then comprises, connected by a communication bus 130: a processor or CPU (Central Processing Unit) 131; a random access memory (RAM) 132; a read-only memory (ROM) 133; a storage unit such as a flash hard disk drive (or an interface to a storage media reader, such as an SD card reader (Secure Digital) 134; at least one communication interface 135 allowing the main processor MP 13 to communicate with other devices to which it is connected, such as the MCI communication interface 15 or the secondary processor AP 14, for example.

[0079] The processor 131 is capable of executing instructions loaded into RAM 132 from ROM 133, external memory (not shown), storage media (such as an SD card), or a communication network. When the main processor MP 13 of the network gateway GW 1 is powered on, the processor 131 is capable of reading instructions from RAM 132 and executing them. These instructions form a computer program causing the implementation, by the processor 131, of all or part of a process described in relation to [Fig.3] and [Fig.4] or described variants of these processes.

[0080] All or part of the process described in relation to [Fig. 3] and [Fig. 4] or their described variants can be implemented in software form by executing a set of instructions by a programmable machine, for example a DSP (Digital Signal Processor) or a microcontroller, or implemented in hardware form by a dedicated machine or component, for example a FPGA (Field-Programmable Gate Array) or an ASIC (Application-Specific Integrated Circuit). In general, the environment of the MP 13 main processor includes electronic circuitry configured to implement the described processes in relation to itself.Of course, the MP 13 main processor environment also includes all the elements usually present in a system comprising a control unit and its peripherals, such as a power supply circuit, a power monitoring circuit, one or more clock circuits, a reset circuit, input / output ports, interrupt inputs, bus drivers, this list being non-exhaustive.

[0081] Figure 6 schematically illustrates an example of the internal architecture of the AP 14 secondary processor of the GW1 network gateway. It should be noted that Figure 6 could also represent an internal architecture of the second electronic circuitry SC 12. According to the example of hardware architecture shown in Figure 6, the AP 14 secondary processor then comprises, connected by a communication bus 140: a processor core or CPU core (Central Processing Unit) 141; a RAM (Random Access Memory) 142; a ROM (Read Only Memory) 143; a storage unit such as a flash hard drive (or an interface to a storage media reader, such as an SD (Secure Digital) card reader) 144; at least the RI communication interface 145 allowing the AP 14 secondary processor to communicate with other devices to which it is connected.

[0082] The processor core 141 is capable of executing instructions loaded into RAM 132 from ROM 133, external memory (not shown), storage media (such as an SD card), or a communication network. When the secondary processor AP 14 of the network gateway GW 1 is powered on, the processor core 141 is capable of reading instructions from RAM 142 and executing them. These instructions form a computer program causing the processor core 141, and therefore the AP processor 14, to implement all or part of a process described in relation to [Fig. 3] and [Fig. 4] or described variants of these processes.

[0083] All or part of the process described in relation to [Fig. 3] and [Fig. 4] or their described variants can be implemented in software form by executing a set of instructions by a programmable machine, for example a DSP (Digital Signal Processor) or a microcontroller, or implemented in hardware form by a dedicated machine or component, for example a FPGA (Field-Programmable Gate Array) or an ASIC (Application-Specific Integrated Circuit). In general, the environment of the AP 14 secondary processor includes electronic circuitry configured to implement the described processes in relation to itself.Of course, the AP 14 secondary processor environment also includes all the elements usually present in a system comprising a control unit and its peripherals, such as a power supply circuit, a power monitoring circuit, one or more clock circuits, a reset circuit, input / output ports, interrupt inputs, bus drivers, this list being non-exhaustive.

[0084] According to one embodiment, each of the MP 13 and AP 14 processors can be implemented as a single component or module or as a plurality of cooperating components or modules.

[0085] The invention is not limited to the embodiments and examples described but more generally to any type of electronic device comprising two electronic circuits, one of which, the main electronic circuit, can be deactivated under the control of the other, the second electronic circuit, and the other, the second electronic circuit, comprises a secondary or auxiliary processor with a low-power wireless communication interface associated on the one hand with a secondary memory for information and configuration parameters, and on the other hand with a memory dedicated to storing a network communication stack of the communication interface, in particular for storing application-level configuration information when the first electronic circuit is deactivated and the electronic device is operating in deep sleep.

Claims

1. Demands Electronic device (GW 1) comprising at least a first electronic circuit (MC 11) and a second electronic circuit (SC 12), the first electronic circuit (MC 11) comprising a first processor (MP 13), referred to as the "main processor" connected to a first memory (MM 15) referred to as the "main memory", and the second electronic circuit (SC 12) comprising a second processor (AP 14), referred to as the "secondary processor", connected to a second memory (AM 16) referred to as the "secondary memory", said secondary processor (AP 14) comprising a wireless communication interface (RI 145), referred to as the "low-power radio interface", and said secondary processor (AP 14) being configured to communicate via a communication link (132b) with said main processor (MP 13) when said first electronic circuit (MC 11) is supplied with electrical energy,said first electronic circuitry (MC 11) being configured to be conditionally supplied with electrical energy via a power supply interface circuit (PI 19) controlled by said secondary processor (AP 14) and said second electronic circuitry (SC 12) being continuously supplied with electrical energy when the electrical device (1) is connected to a main power supply source (3), said electronic device (GW 1) being characterized in that: - said low-power radio interface (RI 145) is capable of cooperating with a configuration data memory (RIM 145m) writable by said main processor (MP 13) via a communication link (132b) between said main processor (MP 13) and said secondary processor (AP 14), - said low-power radio interface (RI 145) is capable of operating bidirectional communications autonomously with at least one remote device (S),according to a communication configuration determined from information recorded in said configuration data memory (RIM 145m), when said first circuitry (MC 11) is not supplied with electrical energy, and, - said secondary processor is capable of storing in said secondary memory (AM 16) second pieces of information, configuration of said electronic device (GW 1) when said first circuitry (MC 11) is not supplied with electrical energy.

2. Electronic device (GW 1) according to claim 1, wherein said low power radio interface (RI 145) is capable of operating communications according to a standard and / or short-range communication protocols.

3. Electronic device (GW 1) according to any one of claims 1 and 2, wherein said low power radio interface (RI 145) is capable of operating communications according to a predetermined communication standard and / or protocols from among: Bluetooth, Zigbee, Thread.

4. Electronic device (GW 1) according to any one of claims 1 to 3, wherein said secondary memory (AM 16) comprises a non-volatile memory type area.

5. Method for configuring an electronic device (GW 1), said electronic device being configured according to claim 1, the method being carried out in said second electronic circuitry (SC 12) and comprising: - obtaining (S1), from said main processor (MP 13), in said configuration data memory (RIM 145m), initial configuration information representative of an operating mode to be operated by said low-power radio interface, - performing a first check (S2) of said power supply interface module (PI 19) to deactivate the power supply to said first electronic circuitry (MC 11), so as to configure said electronic device (GW 1) in deep sleep,- to store (S3) in said secondary memory (AM 16) second configuration information of the electronic device GW (1) obtained via wireless communications through said low-power radio interface (RI 145), according to an operating mode of said low-power radio interface (RI 145) determined by all or part of said first configuration information, obtained, when said electronic device (GW 1) is configured in deep sleep, and, - operate a second control (S4) of said power interface module (PI 19) to activate the power supply of said first electronic circuitry (MC 11), so as to configure said electronic device (GW 1) in active mode, and then transmit all or part of said second configuration information to said main processor (MP 13).

6. A configuration method according to claim 5, wherein said configuration data memory (RIM 145m) is dedicated to the operation of a control module of said low-power radio interface (RI 145) and is configured to include information to be used with reference to an application-level software layer of said control module of said low-power radio interface (RI 145).

7. A configuration method according to any one of claims 5 and 6, the method further comprising, prior to said first check (S2) of said power supply interface module (PI 19): - obtaining (Slb) second information, representative of a hardware and / or software configuration of said electronic device (GW1)

8. A configuration method according to any one of claims 5 to 7, wherein said communication mode to be operated by said radio interface is defined according to a communication standard among Bluetooth, Zigbee, Thread.

9. A configuration method according to any one of claims 5 to 8 further comprising, during communications operated in said deep sleep, a detection of an event previously defined as being a condition for exiting said deep sleep, and then a control, by said secondary processor (AP 14), of said power supply interface module (PI 19) to activate the power supply of said first electronic circuitry (MC 11), so as to configure said electronic device (GW 1) in active mode.

10. A configuration method according to claim 9, wherein said previously defined event is the presence of a third-party device (S) within electromagnetic range of said low voltage communication interface (RI 145).

11. Product computer program comprising program code instructions to execute steps of the configuration process according to any one of claims 5 to 10, when this program is executed by a processor (AP 14) of an electronic device (GW 1).

12. Storage device comprising a computer program product according to claim 11.

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