ESD protection circuit
The described ESD protection circuit addresses the limitations of BiMOS transistors in SOI and FD-SOI by using symmetrically connected MOS devices with deactivation signals, achieving efficient ESD dissipation and reduced leakage currents.
Patent Information
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- STMICROELECTRONICS INT NV
- Filing Date
- 2024-10-28
- Publication Date
- 2026-05-01
AI Technical Summary
Existing ESD protection circuits, such as those using BiMOS transistors, face challenges in technologies like SOI and FD-SOI where channel region contact is unavailable, requiring a symmetrical response to ESD on both terminals, deactivation during circuit energization, and a lower tripping threshold without increased current leakage.
A circuit design comprising identical devices with PN junctions or MOS transistors connected symmetrically to emulate BiMOS functionality, with control terminals and deactivation signals to prevent triggering during overvoltage, and optimized for reduced leakage currents.
The proposed circuit provides faster ESD dissipation, symmetrical response, and deactivation capability, overcoming limitations of BiMOS transistors in SOI and FD-SOI technologies while minimizing current leakage.
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Abstract
Description
Title of the invention: ESD protection circuit technical field
[0001] This description relates generally to integrated electronic circuits, and more particularly to circuits for protection against electrostatic discharge (ESD from the English "ElectroStatic Discharge"). Previous technique
[0002] Fig. 1 represents an example of a Cesd component used as an ESD protection circuit.
[0003] The Cesd component includes a BiMOS 100 transistor, a first conduction terminal Al, a second conduction terminal A2, and a control terminal C for a conduction state of the Cesd component between its terminals Al and A2.
[0004] A BiMOS transistor is a MOS transistor having its front gate electrode, also called the gate or control terminal of the MOS transistor in the remainder of this description, connected to its channel-forming region. The channel-forming region of the MOS transistor, also called the channel region of the MOS transistor in the remainder of this description, corresponds to the region of the MOS transistor that extends between the source and the drain of the MOS transistor, and where the MOS transistor channel is formed.
[0005] The gate of the BiMOS transistor 100 is connected to the control terminal of the Cesd component. The first and second conduction terminals of the BiMOS transistor 100, corresponding to the source and drain of the BiMOS transistor 100, are connected to the respective terminals A1 and A2. As an example, the BiMOS transistor 100 is an N-channel transistor.
[0006] The Cesd component is commonly used to dissipate an ESD occurring at either of its terminals A1 and A2. In other words, the Cesd component is an ESD dissipation component. Put another way, the Cesd component is triggered when it receives an ESD exceeding a threshold at either of its terminals A1 and A2, this triggering resulting in the Cesd component establishing a conductive electrical path between its terminals A1 and A2, so that the ESD is discharged to the other terminal, A2 and A1.
[0007] However, the Cesd component has some drawbacks. Summary of the invention
[0008] There is a need for an ESD protection circuit that overcomes all or part of the disadvantages of an ESD protection component of the type described in relation to [Fig.1].
[0009] It would be desirable, for example, to have an ESD protection circuit having a symmetrical response for ESD occurring on its terminal A1 and for ESD occurring on its terminal A2.
[0010] It would be desirable, for example, to have an ESD protection circuit without a BiMOS transistor but implementing a BiMOS transistor between its terminals Al, A2 and C. In other words, it would be desirable to have an ESD protection circuit without a BiMOS transistor but being functionally identical to a BiMOS transistor between its terminals Al, A2 and C, that is to say that the protection circuit emulates the operation of a BiMOS transistor between its terminals Al, A2 and C. Indeed, in certain technologies such as SOI (Silicon On Insulator), FD-SOI (Fully Depleted SOI) and hybrid bulk substrate technologies, there is not always an electrical contact to the channel region of a transistor, which makes it impossible to implement a BiMOS transistor.
[0011] It would be desirable, for example, to have an ESD protection circuit that can receive a deactivation signal. Indeed, an ESD here refers to an electrical discharge occurring on either terminal A1 or A2 of the protection circuit while the electronic circuit containing the protection circuit is not energized. Providing for the deactivation of the protection circuit when the electronic circuit containing the protection circuit is energized prevents an electrical overvoltage (EOS) occurring on either terminal A1 or A2 of the protection circuit from triggering the protection circuit.
[0012] It would be desirable, for example, to have an ESD protection circuit which has a different tripping threshold than that of the Cesd component, for example a lower threshold than that of the Cesd component but, preferably, without this increasing current leakage between terminals Al and A2 when the electronic circuit which includes the protection circuit is energized.
[0013] One embodiment overcomes all or part of the disadvantages of ESD protection components of the type described in relation to [Fig.1].
[0014] One embodiment provides a circuit for protection against electrostatic discharge comprising: - an electrostatic discharge dissipation component comprising a first conduction terminal, a second conduction terminal, and a control terminal for a conduction state of the component between its first and second terminals, the component being one of: a MOS transistor, a BiMOS transistor, and a circuit functionally equivalent to a BiMOS transistor; and first and second identical devices each comprising first and second conduction terminals, the respective first terminals of the first and second devices being connected to the control terminal of the component, the respective second terminals of the first and second devices being connected respectively to the first terminal of the component and to the second terminal of the component.
[0015] According to one embodiment, each of the first and second devices includes at least one PN junction.
[0016] According to one embodiment, each of the first and second devices is implemented by one of the following: a MOS transistor, a BiMOS transistor, and a circuit functionally equivalent to a BiMOS transistor.
[0017] According to one embodiment: Each of the first and second devices further includes a control terminal for a conduction state of the device between its first and second terminals; Each of the first and second devices is implemented by one of the following: a MOS transistor, a BiMOS transistor, and a circuit functionally equivalent to a BiMOS transistor; the protection circuit includes a first MOS transistor having a first conduction terminal connected to the first component terminal, a second conduction terminal connected to the control terminal of the second device, and a gate configured to receive a deactivation signal from the protection circuit; The protection circuit includes a second MOS transistor having a first conduction terminal connected to the control terminal of the first device, a second conduction terminal connected to the second terminal of the component, and a gate configured to receive the protection circuit's deactivation signal.
[0018] According to one embodiment: the protection circuit includes a third device comprising a first conduction terminal connected to the first terminal of the component, a second conduction terminal connected to the control terminal of the component, and a control terminal; the protection circuit includes a fourth device identical to the third device, the first terminal of the fourth device being connected to the second terminal of the component, and the second terminal of the fourth device being connected to the second terminal of the third device; Each of the third and fourth devices is implemented by one of the following: a MOS transistor, a BiMOS transistor, and a circuit functionally equivalent to a BiMOS transistor; the protection circuit includes first and second MOS transistors; The first MOS transistor has a first conduction terminal connected to the first terminal of the component, a second conduction terminal connected to the control terminal of the fourth device, and a gate configured to receive a turn-off signal from the protection circuit; and The second MOS transistor has a second conduction terminal connected to the second terminal of the component, a first conduction terminal connected to the control terminal of the third device, and a gate configured to receive the protection circuit's off signal.
[0019] According to one embodiment: The component is a MOS transistor; and the first and second devices are devoid of BiMOS transistors and are configured so that the protection circuit is functionally equivalent to a BiMOS transistor; The first and second terminals of the component are functionally equivalent respectively to the first and second conduction terminals of said BiMOS transistor, and the control terminal of the component is functionally equivalent to a gate of said BiMOS transistor.
[0020] According to one embodiment, each of the first and second devices comprises: a control gate diode having a first electrode connected to the first terminal of said device, a second electrode connected to the second terminal of said device, and its gate connected to its second electrode.
[0021] According to one embodiment, each of the first and second devices comprises: a MOS transistor having a conduction terminal connected to the first terminal of said device, another conduction terminal connected to the second terminal of said device, and a gate connected to the first terminal of said device.
[0022] According to one embodiment, each of the first and second devices comprises: a first MOS transistor having a gate, a first conduction terminal connected to the first terminal of said device, a second conduction terminal connected to the second terminal of said device; and a second MOS transistor having a first conduction terminal connected to the second terminal of said device, a second conduction terminal connected to the gate of the first transistor, and a gate connected to the second terminal of said device.
[0023] According to one embodiment, each of the first and second devices comprises: a first MOS transistor having a gate, a first conduction terminal connected to the first terminal of said device, a second conduction terminal connected to the second terminal of said device; and a second MOS transistor having a first conduction terminal connected to the second terminal of said device, a second conduction terminal connected to the gate of the first transistor, and a gate connected to the first terminal of said device.
[0024] According to one embodiment, the gate of the first transistor of the second device is configured to receive a circuit turn-off signal.
[0025] According to one embodiment, each of the first and second devices comprises: a MOS transistor having a conduction terminal connected to the first terminal of said device, another conduction terminal connected to the second terminal of said device and a gate connected to the second terminal of said device.
[0026] Another embodiment provides a device for protection against electrostatic discharge comprising: of the first and second electrostatic discharge protection circuits as defined above, the control terminal of the component of the first circuit being connected to the control terminal of the component of the second circuit; a first MOS transistor having its gate connected to the control terminals of the components of the first and second circuits, a first conduction terminal connected to the first terminal of the component of the first circuit, and a second conduction terminal connected to the first terminal of the component of the second circuit; and a second MOS transistor having its gate connected to the control terminals of the components of the first and second circuits, a first conduction terminal connected to the second terminal of the component of the first circuit, and a second conduction terminal connected to the second terminal of the component of the second circuit.
[0027] According to one embodiment, the gate of the first transistor is configured to receive a device deactivation signal. Brief description of the drawings
[0028] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:
[0029] the [Fig.1], described previously, represents a BiMOS transistor used as an ESD protection circuit;
[0030] [Fig.2] represents an example of an embodiment of an ESD protection circuit;
[0031] [Fig.3] represents an example of an embodiment of an ESD protection circuit comprising the circuit of [Fig.2];
[0032] [Fig.4] represents an example of another embodiment of an ESD protection circuit comprising the circuit of [Fig.2];
[0033] [Fig.5] represents an example of an embodiment of an ESD protection circuit functionally equivalent to a BiMOS transistor;
[0034] [Fig.6] illustrates an example of implementation of the circuit of [Fig.5];
[0035] Figure 7 represents another example of an embodiment of a circuit ESD protection functionally equivalent to a BiMOS transistor;
[0036] [Fig.8] illustrates an example of implementation of the circuit of [Fig.7];
[0037] Figure 9 represents yet another example of an embodiment of a circuit ESD protection functionally equivalent to a BiMOS transistor;
[0038] [Fig. 10] illustrates an example of implementation of the circuit of [Fig. 9];
[0039] Figure 11 represents yet another example of an embodiment of a circuit ESD protection functionally equivalent to a BiMOS transistor;
[0040] Figure 12 represents yet another example of an embodiment of an ESD protection circuit functionally equivalent to a BiMOS transistor; and
[0041] [Fig. 13] represents another embodiment of a circuit or device for protection against ESD. Description of the implementation methods
[0042] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.
[0043] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.
[0044] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without intermediate elements other than conductors, and when referring to two connected (in English "coupled") elements between them, this means that these two elements can be connected or linked via one or more other elements.
[0045] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.
[0046] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.
[0047] Unless otherwise specified, when referring to the gate of a transistor (MOS or BiMOS), this means the front gate electrode of the transistor.
[0048] Unless otherwise specified, when referring to a MOS transistor, this means a MOS transistor whose gate is not connected to the channel region of the transistor, or, put another way, it means a MOS transistor that is not a BiMOS transistor.
[0049] Unless otherwise specified, when referring to a BiMOS transistor, this means a MOS transistor whose gate is connected to the channel region of the transistor.
[0050] Fig. 2 represents an example of an embodiment of an ESD protection circuit, Cesd2.
[0051] The Cesd2 circuit includes a Cesdl component. The Cesdl component includes a conduction terminal Al, a conduction terminal A2, and a control terminal C for controlling the conduction state, for example, conducting or blocking, of the Cesdl component between its terminals Al and A2. The Cesdl component is an ESD dissipation component; that is, the Cesd component is triggered when it receives an ESD exceeding a threshold on either of its terminals Al and A2. This triggering results in the Cesd component establishing a conductive electrical path between its terminals Al and A2, so that the ESD is dissipated to the other terminal, A2 and Al.
[0052] Terminal A1 of component Cesdl corresponds to terminal A1 of circuit Cesd2, these two terminals therefore being designated by the same reference A1. For example, terminal A1 of component Cesdl constitutes terminal A1 of circuit Cesd2. Terminal A2 of component Cesdl corresponds to terminal A2 of circuit Cesd2, these two terminals therefore being designated by the same reference A2. For example, terminal A2 of component Cesdl constitutes terminal A2 of circuit Cesd2.
[0053] By way of example, the Cesd2 circuit includes a control terminal C. The control terminal C of the Cesd2 circuit controls the conduction state of the Cesd2 circuit between its terminals A1 and A2. The terminal C of the Cesdl component then corresponds to the terminal C of the Cesd2 circuit, these two terminals are therefore designated by the same reference C. For example, the terminal C of the Cesdl component constitutes the terminal C of the Cesd2 circuit.
[0054] According to one embodiment, the Cesdl component is identical to the Cesd component of [Fig.1].
[0055] The Cesd2 circuit further comprises two identical devices Devl and Dev2. Each of the two devices Devl and Dev2 comprises a conduction terminal A3 and a conduction terminal A4.
[0056] In the embodiment illustrated in [Fig.2], each of the devices Devl and Dev2 further includes a control terminal C0 controlling the conduction state of the device between its terminals A3 and A4.
[0057] In the embodiment of [Fig.2], the control terminal C0 of each of the devices Devl and Dev2 is floating.
[0058] In alternative embodiments, this control terminal C0 is omitted.
[0059] According to one embodiment, each of the devices Devl and Dev2 includes a PN junction.
[0060] For example, in the embodiment illustrated in [Fig. 2], each of the devices Devl and Dev2 comprises a BiMOS 200 transistor. For example, in each of the devices Devl and Dev2, one conduction terminal of the BiMOS 200 transistor is connected to terminal A4 of the device and another conduction terminal of the BiMOS 200 transistor is connected to terminal A3 of the device. The gate of the BiMOS 200 transistor constitutes the control terminal C0 of the device when present. The gate of the BiMOS 200 transistor is left floating here.
[0061] Terminal A3 of device Devl, or device Dev2 respectively, is connected to terminal C of component Cesdl. Terminal A4 of device Devl is connected to terminal A1 of component Cesdl. Terminal A4 of device Dev2 is connected to terminal A2 of component Cesdl.
[0062] In other words, devices Devl and Dev2 are connected symmetrically between terminals A1 and C of component Cesdl and between terminals A2 and C of component Cesdl. Put another way, the connection of device Devl between terminals A1 and C of component Cesdl is identical to that of device Dev2 between terminals A2 and C of component Cesdl.
[0063] An advantage of the embodiment of [Fig.2], in the case where each of the devices Devl and Dev2 is a BiMOS 200 transistor, is that the triggering of the Cesdl component, and therefore of the Cesd2 circuit, during an ESD on either of its terminals Al and A2 is faster than for the Cesd component.
[0064] Another advantage of the embodiment of [Fig.2] is that the response of the Cesd2 circuit to an ESD on its terminal Al is symmetrical to the response of the Cesd2 circuit to an ESD on its terminal A2.
[0065] As an alternative, rather than being a BiMOS transistor, the Cesdl component can be a MOS transistor. For example, when the Cesdl component is a MOS transistor, for example an N-channel MOS transistor, the gate of the MOS transistor is connected to the control terminal C of the Cesdl component, and the first and second conduction terminals of the MOS transistor, corresponding to the source and drain of the transistor, are connected to the respective terminals A1 and A2.
[0066] As another variant, rather than being a BiMOS transistor or a MOS transistor, the Cesdl component can be a circuit without a BiMOS transistor but functionally identical to a BiMOS transistor. The Cesdl component then emulates the operation of a BiMOS transistor with its gate connected to the control terminal C and its first and second conduction terminals connected to the respective terminals A1 and A2.
[0067] As other variants, which can be combined with the variants relating to the implementation of the Cesdl component, the identical Devl and Dev2 devices, connected symmetrically to the Cesdl component, can be implemented in a way other than with BiMOS 200 transistors.
[0068] For example, each device Devl, Dev2 may be a MOS transistor, for example an N-channel MOS transistor, having its first and second conduction terminals, corresponding to the source and drain of the transistor, connected to terminals A3 and A4 respectively, and its gate connected to the control terminal C0 of component Cesdl when this is present. As another example, each device Devl, Dev2 may be a circuit without a BiMOS transistor but functionally identical to a BiMOS transistor; the device then emulates the operation of a BiMOS transistor having its first and second conduction terminals connected to terminals A3 and A4 respectively and its gate connected to the control terminal C0 when this is present.
[0069] In the case where each device Devl, Dev2 is a BiMOS transistor, a circuit emulating the operation of a BiMOS transistor, or a MOS transistor, during an ESD, the Cesd2 circuit triggers more quickly compared to the case where these devices are absent.
[0070] In the case where each device Devl, Dev2 is a BiMOS transistor or a circuit emulating the operation of a BiMOS transistor, the trigger threshold of the Cesd2 circuit during an ESD will be lower than when each device Devl, Dev2 is a MOS transistor.
[0071] Furthermore, in the embodiments and variants described above in relation to [Fig.2], the provision of the two identical devices Devl and Dev2 connected symmetrically to the component Cesdl allows that the response of the Cesd2 circuit to an ESD on its terminal Al is symmetrical to its response to an ESD on its terminal A2.
[0072] Figure 3 shows an example of an embodiment of a protection circuit against ESD, Cesd3, comprising the Cesd2 circuit described previously. Terminals A1 and A2 of the Cesd2 circuit, and therefore of the Cesd1 component, constitute two terminals A1 and A2 of the Cesd3 circuit.
[0073] In the embodiment of [Fig.3], the devices Devl and Dev2 each include the control terminal C0.
[0074] The Cesd3 circuit further comprises a MOS transistor T1 and a MOS transistor T2, for example identical. The transistors T1 and T2 are, for example, N-channel.
[0075] Transistor T1 has a conduction terminal 300 connected to the control terminal C0 of device Dev2, another conduction terminal 302 connected to terminal A1 of component Cesdl, and therefore of circuit Cesd2, and its gate 304 is configured to receive a Ko signal to disable circuit Cesd3. Symmetrically, transistor T2 has a conduction terminal 306 connected to the control terminal C0 of device Devl, another conduction terminal 308 connected to terminal A2 of component Cesdl, and therefore of circuit Cesd2, and its gate 310 is configured to receive the Ko signal.
[0076] When the electronic circuit including the Cesd3 circuit is not powered, the Ko signal is floating (or inactive). Transistors T1 and T2 are then blocked, and the operation of the Cesd2 circuit is the same as that described in relation to [Fig. 2]. The Cesd3 circuit is then active and allows for the dissipation of an ESD occurring on either of its terminals A1 and A2.
[0077] Conversely, when the electronic circuit including the Cesd3 circuit is powered, this electronic circuit is configured to provide the Ko signal at a level that enables transistors T1 and T2 to conduct, meaning that the Ko signal is active. For example, the Ko signal then corresponds to a non-zero, positive voltage. This ensures that the Cesd3 component remains in the off state between its terminals A1 and A2, even in the presence of an overvoltage on either of its terminals A1 and A2. The Cesd3 circuit is then deactivated and does not trigger.
[0078] For example, when the Cesd3 circuit is deactivated and an overvoltage occurs on terminal A1, i.e., when the potential of terminal A1 increases relative to that of terminal A2 (positive overvoltage), because transistors T1 and T2 are conducting, the Dev2 device is switched on. Terminal C of the Cesdl component is then pulled to the potential of terminal A2, and the Cesdl component therefore remains in the off state. Conversely, when the Cesd3 circuit is deactivated and an overvoltage occurs on terminal A2, i.e., when the potential of terminal A2 decreases relative to that of terminal A1 (negative overvoltage), because transistors T1 and T2 are conducting, the Devl device is switched on. Terminal C of the Cesdl component is then pulled to the potential of terminal A1, and the Cesdl component therefore remains in the off state.
[0079] The Cesd3 circuit, in addition to benefiting from the advantages of the Cesd2 circuit with regard to the evacuation of an ESD on either of the terminals Al and A2 when the Cesd3 circuit is active, can therefore be deactivated by the Ko signal, so that the Cesd3 circuit does not trigger in the presence of an overvoltage on either of the terminals Al and A2.
[0080] Preferably, when the electronic circuit including the Cesd3 circuit is energized and the voltage between terminals Al and A2, referenced to terminal A2, is greater than the conduction threshold of a PN diode, i.e., for example, greater than 0.6 V, the devices Devl and Dev2 are preferably implemented with a MOS transistor rather than a BiMOS transistor or a circuit equivalent to a BiMOS transistor. This is because it reduces the leakage currents through transistor Tl and device Dev2 compared to the case where devices Devl and Dev2 were each a BiMOS transistor or a circuit equivalent to a BiMOS transistor. When the voltage between terminals Al and A2 is less than the conduction threshold of a PN diode, devices Devl and Dev2 can each be a MOS transistor, a BiMOS transistor, or a circuit equivalent to a BiMOS transistor without affecting the leakage currents.
[0081] Figure 4 shows an example of another embodiment of an ESD protection circuit, Cesd4, comprising the Cesd2 circuit described above. Terminals A1 and A2 of the Cesd2 circuit, and therefore of the Cesd1 component, constitute two terminals A1 and A2 of the Cesd4 circuit.
[0082] The Cesd4 circuit comprises four MOS transistors T3, T4, T5 and T6, for example N-channel.
[0083] The transistor, or device, T3 has a conduction terminal A5 connected to the terminal A1 of the Cesd2 circuit, another conduction terminal A6 connected to the control terminal of the Cesd2 circuit, and a control terminal (or gate) CL
[0084] The transistor, or device T4, is identical to the transistor T3. The transistor T4 has its conduction terminal A5 connected to the terminal A2 of the Cesd2 circuit, its conduction terminal A6 connected to the terminal C of the Cesd2 component.
[0085] Devices T3 and T4 are therefore connected to the Cesd2 circuit symmetrically with respect to each other.
[0086] Transistor T5 has a conduction terminal 400 connected to terminal A1 of the Cesd2 circuit, another conduction terminal 402 connected to the control terminal C1 of device T4, and its gate 404 is configured to receive a K0 turn-off signal from the Cesd4 circuit. Symmetrically, transistor T6 has a conduction terminal 406 connected to the control terminal C1 of device T3, another conduction terminal 408 connected to terminal A2 of the Cesd2 circuit, and its gate 410 is configured to receive the K0 signal.
[0087] When the electronic circuit including the Cesd4 circuit is not powered, the Ko signal is floating (or inactive). Transistors T3, T4, T5, and T6 are cut off, and the operation of the Cesd2 circuit is then the same as that described in relation to [Fig. 2]. The Cesd4 circuit is then active and allows for the dissipation of an ESD occurring on either of its terminals A1 and A2.
[0088] Conversely, when the electronic circuit including the Cesd4 circuit is powered, this electronic circuit is configured to provide the Ko signal at a level that enables transistors T5 and T6 to conduct, meaning that the Ko signal is active. For example, the Ko signal then corresponds to a non-zero, positive voltage. This ensures that the Cesd2 circuit, and therefore the Cesd4 circuit, remains in the blocked state between its terminals A1 and A2, even in the presence of an overvoltage on either of its terminals A1 and A2. The Cesd4 circuit is then deactivated and does not trigger.
[0089] For example, when the Cesd4 circuit is deactivated and an overvoltage occurs on terminal A1, i.e., when the potential of terminal A1 increases relative to that of terminal A2 (positive overvoltage), because transistors T5 and T6 are conducting, device T4 is switched on. Terminal C of the Cesd2 circuit is then pulled to the potential of terminal A2, and the Cesd2 circuit therefore remains in the off state. Conversely, when the Cesd4 circuit is deactivated and an overvoltage occurs on terminal A2, i.e., when the potential of terminal A2 decreases relative to that of terminal A1 (negative overvoltage), because transistors T5 and T6 are conducting, device T3 is switched on. Terminal C of the Cesd2 circuit is then pulled to the potential of terminal A1, and the Cesd1 component therefore remains in the off state.
[0090] The Cesd4 circuit, in addition to benefiting from the advantages of the Cesd2 circuit with regard to the evacuation of an ESD on either of the terminals Al and A2 when the Cesd4 circuit is active, can therefore be deactivated by the Ko signal, so that the Cesd4 circuit does not trigger in the presence of an overvoltage on either of the terminals Al and A2.
[0091] In the embodiment of [Fig.4], each of the devices T3 and T4 is a MOS transistor. In alternative embodiments, each device T3, T4 is replaced by a BiMOS transistor having conduction terminals A5 and A6 and a control terminal Cl, or by a circuit equivalent to a BiMOS transistor, this circuit comprising two conduction terminals A5 and A6 and a control terminal.
[0092] Preferably, when the electronic circuit including the Cesd4 circuit is powered on and the voltage between terminals A1 and A2, referenced to terminal A2, is greater than the conduction threshold of a PN diode, devices T3 and T4 are preferably MOS transistors rather than BiMOS transistors or circuits equivalent to each a BiMOS transistor. This is because it reduces the leakage currents through transistor T5 and device T4 compared to the case where the devices T3 and T4 would each be a BiMOS transistor or a circuit equivalent to a BiMOS transistor. If the voltage between terminals A1 and A2 is below the conduction threshold of a PN diode, devices T3 and T4 can each be a MOS transistor, a BiMOS transistor, or a circuit equivalent to a BiMOS transistor without affecting the leakage currents.
[0093] Circuits equivalent to BiMOS transistors but implemented without BiMOS transistors have been mentioned several times previously. Examples of embodiments of such circuits will now be described.
[0094] Fig. 5 represents an example of an embodiment of a Cesd5 circuit functionally equivalent to a BiMOS transistor, the Cesd5 circuit being an ESD protection circuit.
[0095] The Cesd5 circuit comprises two conduction terminals Al' and A2' and a control terminal C', corresponding to the respective terminals Al, A2 and C of the BiMOS transistor 100 of [Fig.1],
[0096] The Cesd5 circuit includes an ESD dissipation component, Cesdl'. More specifically, the Cesdl' component is a MOS transistor, for example an N-channel MOS transistor. The Cesdl' MOS transistor includes a conduction terminal corresponding to terminal Al' of the Cesdl' circuit, these two terminals therefore being designated by the same reference Al'. The Cesdl' MOS transistor includes another conduction terminal corresponding to terminal A2' of the Cesdl' circuit, these two terminals therefore being designated by the same reference A2'. The Cesdl' MOS transistor includes a gate corresponding to terminal C of the Cesdl' circuit, these two terminals therefore being designated by the same reference C.
[0097] The Cesd5 circuit further comprises two identical devices Devl' and Dev2'. Each of the two devices Devl' and Dev2' comprises a conduction terminal A3' and a conduction terminal A4'.
[0098] According to one embodiment, each of the devices Devl' and Dev2' includes a PN junction.
[0099] In the embodiment illustrated in [Fig.5], each of the devices Devl' and Dev2' includes a gated diode 500. For example, in each of the devices Devl' and Dev2', a first electrode, for example the anode, of the diode 500 is connected to the terminal A3' of the device and a second electrode, for example the cathode, of the diode 500 is connected to the terminal A4' of the device, and the gate of the diode 500 is connected to its second electrode.
[0100] Terminal A3' of device Devl', or device Dev2' respectively, is connected to terminal C of component Cesdl'. Terminal A4' of device Devl' is connected to terminal A1' of component Cesdl'. Terminal A4' of device Dev2' is connected to terminal A2' of component Cesdl'.
[0101] In other words, devices Devl' and Dev2' are connected symmetrically between terminals A1' and C of component Cesdl' and between terminals A2' and C of component Cesdl. Put another way, the connection of device Devl' between terminals A1' and C of component Cesdl' is identical to that of device Dev2' between terminals A2' and C of component Cesdl'.
[0102] One advantage of the Cesd5 circuit is that it is equivalent to a BiMOS transistor but does not contain one. Thus, the Cesd5 circuit can be implemented with components (MOS transistor and gated diode) that do not require contact with a channel region of a transistor.
[0103] In particular, in the embodiments and variants previously described in relation to Figures 2 to 4, the Cesdl component can be implemented with the Cesd5 circuit of [Fig.5], the terminals Al', A2' and C of the Cesd5 circuit then corresponding to the respective terminals Al, A2 and C of the Cesdl component.
[0104] Furthermore, in the embodiments and variants previously described in relation to Figures 2 to 4, each of the devices Dev1 and Dev2 can be implemented by a Cesd5 circuit, the terminals A3, A4 and C0 of the device then corresponding to the respective terminals Al', A2' and C of the Cesd5 circuit.
[0105] Furthermore, in the embodiments and variants described in relation to [Fig.4], each of the devices T3 and T4 can be implemented by a Cesd5 circuit, the terminals A5, A6 and Cl of the device then corresponding to the respective terminals Al', A2' and C of the Cesd5 circuit.
[0106] Moreover, as shown in [Fig.6], the hardware implementation of the Cesd5 circuit can be very compact.
[0107] [Fig.6] illustrates, by a schematic top view, an example of a compact implementation of the Cesd5 circuit of [Fig.5].
[0108] The Cesd5 circuit comprises successively, and in contact two by two, a 600 region doped with a first type of conductivity, for example of type P, a region doped with the first type of conductivity (not visible in [Fig.6]) arranged under a grid 606A, a 604A region doped with a second type of conductivity, for example of type N, a region doped with the first type of conductivity (not visible in [Fig.6]) arranged under a grid 608, a 604B region doped with the second type of conductivity, a region doped with the first type of conductivity (not visible in [Fig.6]) arranged under a grid 606B, and a 602 region doped with the first type of conductivity. The region of the first type of conductivity arranged under the 606A grid and the 604A region doped with the second type of conductivity form the PN junction of the 500 diode of one of the devices Dev1' and Dev2', the 606A grid forming the grid of this 500 diode.The region of the first type of conductivity arranged under the 606B gate and the 604A region doped with the second type of conductivity form the PN junction of the 500 diode, with the 606B gate forming the gate. of this diode 500. The doped region of the first type of conductivity located under the gate 608 forms the channel region of the Cesdl' transistor, with the gate 608 corresponding to the gate of this transistor. As an example, the doped regions of the first type of conductivity located under the gates 606A, 606B, and 608 have a lower doping level than the 600 and 602 regions doped with the first type of conductivity.
[0109] In [Fig.6], the terminals A3' and A4' of the devices Devl' and Dev2' are represented by solid squares, the terminals Al', A2' and C of the transistor Cesdl' by squares, and the connections between these terminals by dotted lines.
[0110] Fig. 7 represents another example of an embodiment of a Cesd7 circuit equivalent to a BiMOS transistor, the Cesd7 circuit being an ESD protection circuit.
[0111] The Cesd7 circuit shares many features with the Cesd5 circuit, and only the differences between these two circuits are detailed here. Thus, unless otherwise stated, everything described for the Cesd5 circuit, particularly its advantages and uses, applies to the Cesd7 circuit.
[0112] In particular, the Cesd7 circuit differs from the Cesd5 circuit only in the implementation of its Devl' and Dev2' devices.
[0113] In each device Devl', Dev2' of the Cesd7 circuit, the diode 500 is replaced by a MOS transistor 700, for example an N-channel one. For example, in each of the devices Devl' and Dev2', a first conduction terminal of the transistor 700 is connected to the terminal A3' of the device, a second conduction terminal of the transistor 700 is connected to the terminal A4' of the device, and the gate of the transistor 700 is connected to its first conduction terminal.
[0114] [Fig.8] illustrates, by a schematic top view, an example of a compact implementation of the Cesd7 circuit of [Fig.7].
[0115] The Cesd7 circuit comprises three grids 800, 802 and 804 corresponding to the The respective gates of transistor 700 of device Devl', transistor Cesdl', and transistor 700 of device Dev2', with gate 802 positioned between gates 800 and 804. Each of gates 800, 802, and 804 is located on a corresponding channel region doped with a first type of conductivity, for example, P. The channel region located under gate 800 is bordered on either side by two respective regions 806 and 808 doped with a second type of conductivity, for example, N, and corresponding respectively to terminals A3' and A4' of device Devl'. Region 808 also borders the channel region located under gate 802 and therefore also corresponds to the conduction terminal A1' of transistor Cesdl'. Symmetrically, the channel region located under the grid 804 is bordered on either side by two respective regions 810 and 812 doped with the second type of conductivity, and corresponding respectively to terminals A4' and A3' of device Dev2'. Region 810 also borders the channel region located under gate 802 and therefore also corresponds to conduction terminal A2' of transistor Cesdl'.
[0116] In [Fig.8], the terminals A3' and A4' of the devices Devl' and Dev2' are represented by solid squares, the terminals Al', A2' and C of the transistor Cesdl' by solid squares, the gate contacts of the transistors 700 by solid squares and the connections between these terminals and contact by dashed lines.
[0117] Fig. 9 represents yet another example of an embodiment of a Cesd9 circuit equivalent to a BiMOS transistor, the Cesd9 circuit being an ESD protection circuit.
[0118] The Cesd9 circuit shares many features with the Cesd5 circuit, and only the differences between these two circuits are detailed here. Thus, unless otherwise stated, everything described for the Cesd5 circuit, particularly its advantages and uses, applies to the Cesd9 circuit.
[0119] In particular, the Cesd9 circuit differs from the Cesd5 circuit only in the implementation of its Devl' and Dev2' devices.
[0120] In each device Devl', Dev2' of the Cesd9 circuit, the diode 500 is replaced by a MOS transistor 900, for example an N-channel one. For example, in each of the devices Devl' and Dev2', a first conduction terminal of the transistor 900 is connected to the terminal A3' of the device, a second conduction terminal of the transistor 900 is connected to the terminal A4' of the device, and the gate of the transistor 900 is connected to its second conduction terminal.
[0121] Fig. 10 illustrates, by a schematic top view, an example of a compact implementation of the Cesd9 circuit of Fig. 9.
[0122] The Cesd9 circuit comprises three gates 1000, 1002 and 1004 corresponding to the respective gates of transistor 1000 of device Devl', of transistor Cesdl' and of transistor 1000 of device Dev2', the gate 1002 being disposed between the gates 1000 and 1004. Each of the gates 1000, 1002 and 1004 is disposed on a corresponding channel region, doped with a first type of conductivity, for example P. The channel region disposed under the gate 1000 is bordered, on either side, by two respective regions 1006 and 1008 doped with a second type of conductivity, for example N, and corresponding respectively to the terminals A3' and A4' of device Devl'. Region 1008 also borders the channel region arranged under gate 1002 and therefore also corresponds to the conduction terminal Al' of transistor Cesdl'.Symmetrically, the channel region arranged under the grid 1004 is bordered on both sides by two respective regions 1010 and 1012 doped with the second type of conductivity, and corresponding respectively to terminals A4' and A3' of the device. Dev2'. The 1010 region also borders the channel region arranged under the 1002 gate and therefore also corresponds to the conduction terminal A2' of the Cesdl' transistor.
[0123] In [Fig. 10], the terminals A3' and A4' of the devices Devl' and Dev2' are represented by solid squares, the terminals Al', A2' and C' of the transistor Cesdl' by solid squares, the gate contacts of the transistors 900 by solid squares and the connections between these terminals and contact by dashed lines.
[0124] Fig. 11 represents yet another example of an embodiment of a Cesdl 1 circuit equivalent to a BiMOS transistor, the Cesdl 1 circuit being an ESD protection circuit.
[0125] The Cesdl 1 circuit shares many features with the Cesd5 circuit, and only the differences between these two circuits are detailed here. Thus, unless otherwise stated, everything described for the Cesd5 circuit, particularly its advantages and uses, applies to the Cesdl 1 circuit.
[0126] In particular, the Cesdl 1 circuit differs from the Cesd5 circuit only in the implementation of its Devl' and Dev2' devices.
[0127] In each device Devl', Dev2' of the Cesdl 1 circuit, the diode 500 is replaced by two MOS transistors 1100 and 1102, for example N-channel. For example, in each of the devices Devl' and Dev2', a first conduction terminal of the transistor 1100 is connected to the A3' terminal of the device, a second conduction terminal of the transistor 1100 is connected to the A4' terminal of the device, the gate of the transistor 1100 is connected to a first conduction terminal of the transistor 1102, a second conduction terminal of the transistor 1102 is connected to the A4' terminal of the device, and the gate of the transistor 1102 is also connected to the A4' terminal of the device.
[0128] Compared to devices Devl' and Dev2' of circuits Cesd5, Cesd7, and Cesd9, devices Devl' and Dev2' of circuit Cesdl 1 allow Cesdl 1 to be deactivated when the electronic circuit containing Cesdl 1 is powered. This is achieved by applying a deactivation signal Ko to the gate of transistor 1100 of device 1100. This signal Ko is floating when the circuit containing Cesdl 1 is not powered, resulting in Cesdl 1 behaving like a BiMOS transistor. Conversely, this signal Ko is at a voltage level that enables transistor 1100 of device Dev2' to conduct when the circuit containing Cesdl 1 is powered. Consequently, the gate C of transistor Cesdl' is pulled to terminal A2', and this Cesdl transistor is held in the off state, thus deactivating Cesdl 1.
[0129] Fig. 12 represents yet another example of an embodiment of a Cesdl2 circuit equivalent to a BiMOS transistor, the Cesdl2 circuit being an ESD protection circuit.
[0130] The Cesdl2 circuit shares many features with the Cesdll circuit, and only the differences between these two circuits are detailed here. Thus, unless otherwise stated, everything described for the Cesdl 1 circuit, particularly its advantages and uses, applies to the Cesdl2 circuit.
[0131] In particular, the Cesdl2 circuit differs from the Cesdl 1 circuit only in the implementation of its Devl' and Dev2' devices.
[0132] In each of the devices Devl' and Dev2' of the Cesdl2 circuit, the gate of transistor 1102 is connected to terminal A3' of the device, instead of terminal A4' as was the case in [Fig. 11].
[0133] As in [Fig. 11], the devices Devl' and Dev2' of the Cesdl2 circuit allow the Cesdl2 circuit to be deactivated by providing the Ko signal to the gate of the transistor 1100 of the Dev2' device.
[0134] Fig. 13 illustrates another embodiment of an ESD protection circuit, Cesdl3.
[0135] The circuit, or device, Cesdl3 comprises two circuits Cesd7 having their control terminals C' connected to each other.
[0136] The Cesdl3 circuit further includes two MOS transistors 1300 and 1302, for example N-channel. The transistors 1300 and 1302 are preferably identical to the Cesdl' MOS transistors of the Cesd7 circuits.
[0137] The transistor 1300 has a first conduction terminal connected to the Al' terminal of one of the two Cesd7 circuits, a second conduction terminal connected to the Al' terminal of the other of the two Cesd7 circuits, and its gate connected to the control terminals C of the Cesd7 circuits.
[0138] Symmetrically, the transistor 1302 has a first conduction terminal connected to the A2' terminal of one of the two Cesd7 circuits, a second conduction terminal connected to the A2' terminal of the other of the two Cesd7 circuits, and its gate connected to the control terminals C of the Cesd7 circuits.
[0139] The Cesdl3 device allows for the dissipation of an ESD occurring on any of the terminals Al' and A2' of any of the Cesd7 circuits. Indeed, the Cesdl3 device behaves as a BiMOS transistor between the terminals Al' and A2' of one of the two Cesd7 circuits, as a BiMOS transistor between the terminals Al' and A2' of a second of the two Cesd7 circuits, but also as a BiMOS transistor between the terminals Al' of the two Cesd7 circuits, and as a BiMOS transistor between the terminals Al' of the two Cesd7 circuits.
[0140] Furthermore, according to one embodiment, the Cesdl3 circuit is configured to receive the deactivation signal on the gate C of the Cesdl' transistor of each of the Cesd7 circuits, therefore also on the gates of transistors 1300 and 1302. When the Cesdl3 device receives this Ko signal, it can then be deactivated.
[0141] Embodiments and variants of ESD protection circuits have been described. In the examples described, all transistors, whether MOS or BiMOS, are N-channel. Indeed, for an equivalent area, an N-channel MOS or BiMOS transistor has better current properties. However, those skilled in the art will be able to adapt this description to the case where all N-channel MOS transistors and all N-channel BiMOS transistors are replaced respectively by P-channel MOS transistors and P-channel BiMOS transistors.
[0142] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, the implementations of the Cesd5, Cesd7, and Cesd9 circuits described in relation to Figures 6, 8, and 10, respectively, although they have the advantage of being compact, are not the only possible implementations, and those skilled in the art will be able to foresee others from this description.
[0143] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.
Claims
Demands
1. Electrostatic discharge protection circuit (Cesd2; Cesd3; Cesd4; Cesd5; Cesd7; Cesd9; Cesdll; Cesdl2) comprising: - an electrostatic discharge dissipation component (Cesdl; Cesdl') having a first conduction terminal (Al; Al'), a second conduction terminal (A2; A2'), and a control terminal (C; C') of a conduction state of the component between its first and second terminals, the component being one of: a MOS transistor, a BiMOS transistor, and a circuit (Cesd5; Cesd7; Cesd9; Cesdll; Cesdl2) functionally equivalent to a BiMOS transistor; and identical first and second devices (Devl, Dev2; Devl', Dev2') each comprising first (A3; A3') and second (A4; A4') conduction terminals, the respective first terminals (A3; A3') of the first and second devices (Devl, Dev2; Devl', Dev2') being connected to the control terminal (C; C) of the component, the second terminals (A4;A4') respective of the first and second devices (Devl, Dev2 ; Devl', Dev2') being connected respectively to the first terminal (Al ; Al') of the component and to the second terminal (A2 ; A2') of the component.;
2. Circuit according to claim 1, wherein each of the first and second devices (Devl, Dev2; Devl', Dev2') comprises at least one PN junction.
3. Circuit (Cesd2) according to claim 1 or 2, wherein each of the first and second devices (Devl, Dev2) is implemented by one of: a MOS transistor, a BiMOS transistor, and a circuit (Cesd5; Cesd7; Cesd9; Cesdll; Cesdl2) functionally equivalent to a BiMOS transistor.
4. Circuit (Cesd3) according to claim 1 or 2, wherein: each of the first and second devices (Dev1, Dev2) further comprises a control terminal (CO) of a conduction state of the device between its first and second terminals (A3, A4);Each of the first and second devices is implemented by one of: a MOS transistor, a BiMOS transistor, and a circuit (Cesd5; Cesd7; Cesd9; Cesdll; Cesdl2) functionally equivalent to a BiMOS transistor; the protection circuit (Cesd3) includes a first MOS transistor (Tl) having a first conduction terminal (302) connected to the first terminal (Al) of component (Cesdl), a second conduction terminal (300) connected to the control terminal (CO) of the second device (Dev2), and a gate (304) configured to receive a signal (Ko) to disable the protection circuit (Cesd3);the protection circuit (Cesd3) includes a second MOS transistor (T2) having a first conduction terminal (306) connected to the control terminal (C0) of the first device (Devl), a second conduction terminal (308) connected to the second terminal (A2) of the component (Cesdl), and a gate (310) configured to receive the deactivation signal (Ko) of the protection circuit (Cesd3).
5. Circuit according to claim 1 or 2, wherein: the protection circuit (Cesd4) comprises a third device (T3) comprising a first conduction terminal (A5) connected to the first terminal (A1) of the component (Cesdl), a second conduction terminal (A6) connected to the control terminal (C) of the component (Cesdl), and a control terminal (C1); the protection circuit (Cesd4) comprises a fourth (T4) device identical to the third device (T3), the first terminal (A5) of the fourth device (T4) being connected to the second terminal (A2) of the component (Cesdl), and the second terminal (A6) of the fourth device (T4) being connected to the second terminal (A6) of the third device (T3); Each of the third and fourth devices (T3, T4) is implemented by one of: a MOS transistor, a BiMOS transistor, and a circuit (Cesd5; Cesd7; Cesd9; Cesdll; Cesdl2) functionally equivalent to a BiMOS transistor; The protection circuit (Cesd4) includes first and second MOS transistors (T5, T6); the first MOS transistor (T5) has a first conduction terminal (400) connected to the first terminal (A1) of the component (Cesdl), a second conduction terminal (402) connected to the control terminal (C1) of the fourth device (T3) and a gate (404) configured to receive a signal (K0) to disable the protection circuit (Cesd4); and the second MOS transistor (T6) has a second conduction terminal (408) connected to the second terminal (A2) of the component (Cesdl), a first conduction terminal (406) connected to the control terminal (C0) of the third device (T3) and a gate (410) configured to receive the signal (K0) to disable the protection circuit (Cesd4).
6. Circuit (Cesd5, Cesd7, Cesd9, Cesdl1, Cesdl2) according to claim 1 or 2, wherein: the component (Cesdl1) is a MOS transistor; and the first and second devices (Devl1, Dev2') are devoid of BiMOS transistors and are configured so that the protection circuit (Cesd5, Cesd7, Cesd9, Cesdl1, Cesdl2) is functionally equivalent to a BiMOS transistor; the first and second terminals (Al1, A2') of the component (Cesdl1) are functionally equivalent respectively to first and second conduction terminals (Al1, A2') of said BiMOS transistor, and the control terminal (C) of the component (Cesdl1) is functionally equivalent to a gate (C) of said BiMOS transistor.
7. Circuit (Cesd5) according to claim 6, wherein each of the first and second devices (Devl1, Dev2') comprises: a control gate diode (500) having a first electrode connected to the first terminal (A31) of said device (Devl1, Dev2'), a second electrode connected to the second terminal (A41) of said device (Devl1, Dev2'), and its gate connected to its second electrode.
8. Circuit (Cesd7) according to claim 6, wherein each of the first and second devices (Dev1, Dev2') comprises: a MOS transistor (700) having a conduction terminal connected to the first terminal (A31) of said device, another terminal of conduction connected to the second terminal (A41) of said device, and a grid connected to the first terminal (A31) of said device.
9. Circuit (Cesdl 1) according to claim 6, wherein each of the first and second devices (Devl1, Dev2') comprises: a first MOS transistor (1100) having a gate, a first conduction terminal connected to the first terminal (A31) of said device, a second conduction terminal connected to the second terminal (A4') of said device; and a second MOS transistor (1102) having a first conduction terminal connected to the second terminal (A41) of said device, a second conduction terminal connected to the gate of the first transistor (1100), and a gate connected to the second terminal (A41) of said device.
10. Circuit (Cesdl2) according to claim 6, wherein each of the first and second devices (Devl1, Dev2') comprises: a first MOS transistor (1100) having a gate, a first conduction terminal connected to the first terminal (A31) of said device, a second conduction terminal connected to the second terminal (A4') of said device; and a second MOS transistor (1102) having a first conduction terminal connected to the second terminal (A41) of said device, a second conduction terminal connected to the gate of the first transistor (1100), and a gate connected to the first terminal (A31) of said device.
11. Circuit (Cesdl 1, Cesdl2) according to claim 9 or 10, wherein the gate of the first transistor (1100) of the second device (Dev2') is configured to receive a circuit off signal (Ko).
12. Circuit (Cesd9) according to claim 6, wherein each of the first and second devices (Devl1, Dev2') comprises: a MOS transistor (900) having a conduction terminal connected to the first terminal (A31) of said device, another conduction terminal connected to the second terminal (A21) of said device and a gate connected to the second terminal (A41) of said device.
13. Device (Cesdl3) for protection against electrostatic discharge comprising: a first circuit (Cesd9) according to claim 12 and a second circuit (Cesd9) according to claim 12, the control terminal (C')
14. of the component (Cesdl1) of the first circuit (Cesd9) being connected to the control terminal (C') of the component (Cesdl1) of the second circuit (Cesd9); a first MOS transistor (1300) having its gate connected to the control terminals (C) of the components (Cesdl1) of the first and second circuits (Cesd9), a first conduction terminal connected to the first terminal (Al1) of the component (Cesdl) of the first circuit (Cesd9), and a second conduction terminal connected to the first terminal (Al1) of the component (Cesdl1) of the second circuit (Cesd9); and a second MOS transistor (1302) having its gate connected to the control terminals (C) of the components (Cesdl1) of the first and second circuits (Cesd9), a first conduction terminal connected to the second terminal (A21) of the component (Cesdl1) of the first circuit (Cesd9), and a second conduction terminal connected to the second terminal (A21) of the component (Cesdl1) of the second circuit (Cesd9). Device (Cesdl3) according to claim 13, wherein the gate of the first transistor (1300) is configured to receive a device deactivation signal (Ko).
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