Fabrication of a quantum dot array

Abstract

Quantum electronic device comprising: - an active area (20) for hosting quantum dots and, - flush on one face of the device: a) a plurality of grid lines (G11, G12, G13, G14), electrically isolated from each other and each covering a part of the active area (20), and b) re-establishment facilitation islands (I4-I7, I4a-I7a) at a rate of at least one island per grid line, the re-establishment facilitation islands being separated from each other by a distance (D1, D2, D3), each re-establishment facilitation island comprising a flank along which a lateral part (P4-P7) of a grid line extends, the device further comprising at least one electrical contact (P4-P7) for contacting at least one given grid line (G11, G12, G13, G14),at least one electrical contact being located at least on the lateral part of the given grid line extending along the flank of a contact re-establishment facilitation island (I4-I7, I4a-I7a). Figure for the abbreviation: 14,

Description

Title of the invention: Fabrication of a quantum dot array Technical context

[0001] The field of the invention is quantum computing and more specifically the storage of quantum information. In the approach considered, qubits or quantum bits are implemented in quantum dots that confine elementary charges, which are electrons or holes, within structures made of semiconductor materials such as silicon. These quantum dots are coupled to each other via tunneling barriers. Quantum information is, for example, encoded on the spin of electrons or the spin of holes. The silicon-based approach takes advantage of CMOS (Complementary Metal Oxide Semiconductor) technologies and allows operation at accessible temperatures on the order of 1 K.

[0002] To define and properly control a network of quantum dots, it is necessary to have electrodes called gates (or grids in English) allowing a local adjustment of the electrostatic potential.

[0003] Typically, some grids are dedicated to controlling the potential of quantum dots. And other grids are used to control the tunneling barriers between the dots.

[0004] In practice, charged defects are present in materials (for example, along a Si-SiO2 interface between a silicon layer and a silicon dioxide layer), and locally perturb the potential, creating electrostatic disorder that is superimposed on the potential generated by the gate voltages. Naturally, efforts are made to optimize materials and interfaces to reduce the densities of defects present, but this is not easy, and defects are always present.

[0005] When the amplitude of the potential disorder caused by the charged defects is significant, a grid pitch that approaches or is less than the characteristic length of the disorder can be used to improve the definition of quantum dots and tunneling barriers.

[0006] One response to this problem therefore consists of creating the densest possible grid arrangements. For example, a manufacturer has reduced the grid pitch to 50 nm via an integration of self-aligned grids called nested gates (US10741664, Zverwer et al., Nat. Elec. 2022, 5, 184) or via the use of extreme ultraviolet EUV lithography (Neyens et al., Nature 2024, 629, 80).

[0007] On so-called SiMOS technologies (MOS: Metal Oxide Semiconductor), where quantum dots are formed at a Si / SiO2 interface, these step sizes are sometimes still insufficient to guarantee excellent control of the quantum structures formed. It would therefore be interesting to be able to create even denser SiMOS quantum bit structures.

[0008] An additional problem arises at the contact resumption level when the dimensions and grid pitch are small: to prevent a contact from connecting several grids at once, it must be smaller than the grid pitch and perfectly aligned.

[0009] To alleviate these constraints, one solution is to extend the grids away from the electronic component towards regions of larger available size to facilitate contact re-establishment. The geometry of extended grids involves creating lines with different orientations, which is more complex than simply parallel lines. US 10741664 proposed L-shaped geometries with parallel sides of the L, but decreasing in size from the center of one side of the component towards its outer edge. However, contact re-establishment remains challenging, hence the risk of bridging. Zverwer et al. (mentioned above) also proposed angular sector geometries that use proportionally more surface area around the component.

[0010] When the grids approach the dimensions at the limit of lithographic resolution, the realization of such patterns can, however, prove complex.

[0011] For structures with extremely small grid pitches, it is therefore interesting to seek to facilitate the re-establishment of contact, by any means that would be easy to industrialize.

[0012] A particularly advantageous substrate is the SOI (silicon on insulator) substrate. It is presented in the form of circular wafers. Features of the invention and advantages

[0013] We therefore wish to obtain a very fine grid pitch for fine control of the potential and compensation of electrostatic disorder, while facilitating contact re-establishment for grid pitches smaller than the dimensions of the contacts.

[0014] To this end, a quantum electronic device is proposed comprising: - an active region to accommodate quantum dots and, - flush with one face of the device: a) a plurality of grid lines, electrically insulated from each other and each covering a portion of the active area, (b) re-establishment facilitation islands, at least one island per grid line, the re-establishment facilitation islands being spaced a distance apart, each re-establishment facilitation island comprising a flank along which a lateral portion of a grid line extends, the device further comprising at least one electrical contact for contacting at least one given grid line, the at least one electrical contact being located at least on the lateral part of the given grid line which extends along the side of a contact resumption facilitation island.

[0015] Isolated surfaces – the islands – are chosen, with dimensions in the plane greater than the width of the grid lines. These conduct the current from their part that covers the active zone to a re-establishment of contact, which is facilitated during manufacturing by the presence of the re-establishment facilitation islands.

[0016] This strategy enables the realization of a network of quantum dots with reduced pitch, since, despite the reduced pitch, re-establishment of contact is facilitated by the tolerance afforded by an isolated area—the island—towards which the tolerance is applied during the re-establishment of contact. The islands can alternate with the portions extending along the flank—the latter forming branches, each branch benefiting from a dedicated contact area with a specific tolerance.

[0017] For this, we propose an arrangement of quantum dots with control grids defined by several spacers, the widths of the spacers being defined by the resolution of the deposit thicknesses, which ultimately allows very small dimensions for the grid pitch put in place.

[0018] Several design proposals are associated with these principles, and all make it easier to re-establish contact.

[0019] According to optional and advantageous features:

[0020] - the islands facilitating the resumption of contact can be surrounded by an alternating dielectric spacers and conductive spacers in numbers that increase with the distance from the active area.

[0021] - the spacing between two neighboring contact resumption facilitation islands can increase with distance from the active area.

[0022] - the electrical contacts can all be placed between two facilitation islands of resumption of contact with neighbors but getting closer to the neighboring islet (or the two neighboring islets) or spilling over more onto the neighboring islet (or the two neighboring islets) for contacts closer to the active zone than for contacts further from the active zone.

[0023] The device may comprise a bulk silicon substrate or a silicon-on-insulator substrate.

[0024] - the active area may include a nanowire.

[0025] - the active zone may have two ends, at least one of the ends forming a reservoir of load carriers.

[0026] - the contact re-establishment facilitation islands may have a surface made of material electrically insulating, or made of electrically conductive material.

[0027] - the grids allow local adjustment of the electrostatic potential in the area active.

[0028] -an electrical contact may be placed straddling a contact re-establishment facilitation island, at least one dielectric spacer and a branch-forming lateral part, or straddling a branch-forming lateral part and a dielectric spacer without having contact with a contact re-establishment facilitation island, or straddling a branch-forming lateral part, two adjacent contact re-establishment facilitation islands and at least two dielectric spacers.

[0029] -an electrical contact can join a lateral branch between two islands of re-establishment of contact arranged with respect to each other in a direction essentially parallel to a direction of elongation of the active zone.

[0030] - an electrical contact can join a lateral part forming a branch between two islands facilitating re-establishment of contact arranged relative to each other in a direction transverse to a direction of elongation of the active zone.

[0031] - quantum dots can be quantum dots for qubit.

[0032] The arrangement extends along one dimension, with the possibility of integrating a second network of quantum dots opposite each other to allow the reading of qubits.

[0033] The invention can in particular be implemented with the following manufacturing process:

[0034] a method for manufacturing a quantum electronic device, for example for storing quantum information, comprising placing on a substrate an active area, and a plurality of grid lines, electrically insulated from each other, and between the grid lines and the active area, a layer of dielectric material, the method comprising trenching steps by etching in a conductive material placed on the substrate, then successive conformal depositions of dielectric spacers and conductive spacers, with trench widths increasing away from the active area, the conductive spacers, the method further comprising placing at least one electrical contact to contact at least one given grid line, the at least one electrical contact being located at least on a lateral part of the given grid line extending along a flank of a contact re-establishment facilitation island.

[0035] This manufacturing process is particularly effective for forming grid lines and isolated surfaces.

[0036] And according to again optional and advantageous features,

[0037] Each conformal deposition can be followed by an anisotropic etching before the next deposition

[0038] or alternatively the deposition of dielectric spacers and conductive spacers can be carried out before anisotropic etching of the conductive material and then of the dielectric material.

[0039] the trenches may include mesh trenches, a trench transverse to the elongated conductor widening as it moves away from the elongated conductor at each crossing of a trench parallel to the elongated conductor.

[0040] The proposed design allows for misalignment of contacts with respect to the patterns previously made on the substrate without risk of short-circuiting the different grids of the device.

[0041] Scaling up this type of structure is possible by interconnecting different nodes, for example via superconducting resonators. List of figures

[0042] Figures 1 to 13 relate to a first embodiment.

[0043] Fig. 1 shows a first process step relating to the preparation of a starting substrate.

[0044] Fig. 2 shows a second step of the process, relating to the engraving of a wire.

[0045] Figure 3 shows a third step of the process, relating to the deposition of the elements of base to form the grid.

[0046] Fig. 4 shows a fourth process step, relating to an engraving carried out on these elements.

[0047] Fig. 5 shows a fifth process step, relating to a deposition / etching of a first dielectric spacer.

[0048] Fig. 6 shows a sixth process step, relating to a deposition / etching of a first conductive spacer.

[0049] Figures 6B and 6C show two variants of the process.

[0050] Fig. 7 shows a seventh process step, relating to a deposition / etching of a 2nd dielectric spacer followed by a deposition / etching of a 2nd conductive spacer.

[0051] Fig. 8 shows an eighth process step, relating to a deposition / etching of a 3rd dielectric spacer followed by a deposition / etching of a 3rd conductive spacer.

[0052] Fig. 9 shows a ninth process step, relating to a deposition / etching of an Nth dielectric spacer followed by a deposition / etching of a 3rd conductive spacer.

[0053] Fig. 10 shows a tenth process step, relating to an optional CMP chemical-mechanical polishing.

[0054] Fig. 11 shows an eleventh process step, relating to the placement of a lithography mask and the subsequent engraving on the grid material, to form the grids.

[0055] Fig. 12 shows the result of the engraving.

[0056] Fig. 13 shows a twelfth step of the process, relating to the re-establishment of contact.

[0057] Figure 14 explains the resumption of contact.

[0058] Fig. 15 shows a first variant including successive deposition of spacers, un-short-circuiting and placement of individual contacts.

[0059] Fig. 16 shows a second variant including the same steps. Description related to the figures

[0060] Figures 1 to 13 relate to a first embodiment of the fabrication of a quantum electronic device and a corresponding embodiment of the quantum electronic device itself. On the left of each figure, a top view is shown, while on the right, a side view, in cross-section, is shown.

[0061] [Fig.1] In [Fig.1], a portion of the starting substrate 10 is shown. This portion of the substrate, shown here as rectangular (the substrate extends arbitrarily far in the plane, its physical limit being the edge of the plate - in fact, it is therefore generally circular), has a flat working surface 11, namely a crystalline silicon surface, with a depth for example of about 20 nm.

[0062] The starting substrate 10 was, for example, produced by obtaining silicon-on-insulator (SOI), which has a thin layer of silicon, approximately 10 nm (generally 12 to 16 nm) thick, on an insulating sublayer 12 of silicon dioxide (SiO2), and (optionally) by performing epitaxy on the flat silicon surface of this starting substrate, so as to grow a silicon layer to the desired height, which can be 20 nm – advantageous range of values: 5-30 nm. This layer will form the electrical conduction element required on the surface of the substrate, on a preferably insulating support – the SiO2 of the substrate.

[0063] In variants, the SOI is replaced by bulk silicon (bulk silicon, not shown) placed or not on an insulating layer (for example silicon dioxide SiO2).

[0064] [Fig.2] In [Fig.2], the result of an etching step, in the upper silicon layer prepared in the previous step, of two nanowires 20 (nanowire), parallel to each other and interrupted at the right side of each other at each of their two ends, is shown in the embodiment shown.

[0065] The nanowires 20 extend for example parallel to one side of the rectangle forming the substrate, but without reaching the edges on one side or the other.

[0066] At least one nanowire 20 is required to implement the invention. The nanowire constitutes an active zone for hosting quantum dots, this active zone having two ends, at least one of which forms a charge carrier reservoir. The presence of two nanowires 20 is advantageous because it allows for the simultaneous preparation of two independent quantum dot arrays on the same substrate and using the same process steps. The two nanowires 20 are, for example, placed parallel to the shorter sides of the rectangle, on either side of the perpendicular bisector of the longer sides, so that the same amount of space is available on one side of one array as on the opposite side of the other.

[0067] To delimit these nanowires, a mask (not shown) was placed on the surface to protect the material that would form the nanowires, and an etching was performed to remove the silicon around the protected material. The etching is interrupted at the level of the underlying insulating sublayer 12, such that each of the two nanowires 20 is electrically isolated from the other. The mask is removed once the etching is complete. Thus, over most of the substrate surface, the insulator is exposed, except in the region defining each of the nanowires, where the silicon remains.

[0068] Different types of engraving, including dry engraving, can be used.

[0069] Optionally, but advantageously, the space cleared around the silicon nanowires is then filled with insulator 21 (for example, silicon dioxide) in a filling process followed by oxide planarization. Optionally, a shallow trench insulation (STI) process is used, in which case, on SOI, the etching of the nanowires can be continued until the buried oxide and some of the bulk silicon are removed. The surface is then essentially flat, with the nanowires flush with the surface but having their sides surrounded by insulator 21 added during this filling step.

[0070] Instead of a nanowire, a fin (fin in English) can be etched.

[0071] The role of this structure, thin along its transverse direction parallel to the plane of the substrate, is to confine the charges in one dimension.

[0072] [Fig.3] In [Fig.3], the result of a deposition step on the surface is shown. carrying the nanowires - flattened by filling, or not - of a 30 stack for grid formation.

[0073] This stacking provided includes, starting from the part of the substrate where the nanowires are exposed, a layer of dielectric (one or more different materials - silicon dioxide, hafnium dioxide, or aluminium trioxide, for example, or a stacking of these materials) of about 5 to 15 nm, to form what is subsequently called the gate dielectric 31.

[0074] The stack then comprises a layer of electrically conductive material 32, polysilicon or conductive metal, of a greater height, approximately 100 nm or more (depending on the final number of grids planned), followed by a hard mask 33 (of silicon nitride SiN, or silicon dioxide SiO2 in particular). It is this hard mask 33 that is now on the surface of the structure.

[0075] In one embodiment, the initial stack does not contain any conductive material. Its primary role is to serve as a support for the fabrication of the spacers in the subsequent part of the embodiment. For this purpose, a dielectric material would also be suitable.

[0076] The second role of the stack, when it includes a conductive material, is to form access gates for the source and the drain. It would be possible to to do without it, by adapting the engraved pattern to the [Fig.l 1] to extend the source and the drain to the first spacers 61-62.

[0077] Using a conductive material is therefore advantageous because it allows the formation of additional grids in the structure, but it is not mandatory.

[0078] [Fig.4] In [Fig.4], the result of an E0 etching step (preceded of a lithograph to define a mask), for example a dry etching, of the previous stacking of materials, with stopping the etching at the height of the grid dielectric 31. Thus, the hard outer part, which serves to mask the protected parts and conversely was removed before the etching on the parts to be etched, and the thick layer of conductor disappeared on the etched areas.

[0079] For the purposes of this etching step, the substrate was masked, defining a network of trenches of varying widths, some parallel to the longer sides of the rectangle, and others to the shorter sides. The design is symmetrical with respect to the xx plane of symmetry of the two nanowires 20.

[0080] These trenches are for a nanowire (there are two in [Fig. 4], numbering - three parallels to the long sides of the rectangle, denoted T1, T2, T3, one of which, placed in a central position, T2, crosses the substrate from one edge to the opposite edge, - and four parallels to the short sides, labeled T4, T5, T6 and T7, all crossing the rectangle from one edge to the opposite edge. - This section describes the specific case of a device with 2x4 grids per nanowire, as shown in the figures. However, this number of grids can vary (from 2x1 to 2xN grids, with N potentially reaching ten or even several dozen). The trenches define islands, which facilitate re-establishment of contact. For example, beyond trench T4, moving away from the nanowire, there are four islands between trenches T1 and T2. These four islands form a line of four islands placed at increasing distances from the nanowire. There are the same number of islands on the other side of trench T2. There are also islands opposite these islands with respect to trenches T1 and T3, for a total of 16 islands to facilitate eight different re-establishment points.

[0081] An odd number of grids can also be used, in the case where the last space of the trench T2 is filled by a layer of conductive material. They thus define two central islands II and 12 above the nanowire (and common to both nanowires), and 16 lateral islands on each side of the plane xx.

[0082] The two lateral trenches T1 and T3, perpendicular to the nanowire, widen as they move away from the nanowire towards the shorter side of the substrate parallel to it. Their widening is not continuous but occurs in steps, since they widen each time they cross a perpendicular trench, while remaining of constant width between two crossings.

[0083] The central trench T2 parallel to the long sides of the substrate is of constant width.

[0084] The four trenches parallel to the short sides of the rectangle, T4 to T7, are each of constant width, but from one to the next, the width increases as one moves away from the nanowire. Thus, T4 is narrower than T5, which is itself narrower than T6, which is itself narrower than T7.

[0085] A rectangular frame is also engraved on the edge of the substrate (it is visible on the left side of the figure, but is not shown on the right side). It helps to delimit the islands and islets laterally.

[0086] A re-deposition of grid dielectric 31 is implemented in certain variants at the bottom of the trenches, for example trench T which can be any of the trenches (even though in the drawing it is trench T2), for example by atomic layer deposition (ALD).

[0087] [Fig. 5] In [Fig. 5], the result of a deposition step E1 (not shown, but comparable to a conformal deposition, for example by atomic layer deposition ALD) followed by anisotropic etching E2 of a first pair of spacers made of dielectric material, for example silicon dioxide SiO2, is shown. After these two substeps, this material forms a layer 5 to 10 nm thick, only on the vertical parts of the structure, namely the flanks of the thick layer of conductive material in each of the trenches T. In each trench, it occupies a first part at one end of the trench, constituting an insulating spacer 51, and another first part of the trench at the opposite end, constituting a second insulating spacer 52. The insulating spacers 51 and 52 form an insulating continuity with the gate dielectric 31. If the initial stack does not contain conductive material, as considered as an alternative, steps E1 and E2 of [Fig. 5] are unnecessary, and one can proceed directly to the subsequent steps of deposition of conductive spacers. Nevertheless, several cycles are carried out in any case, as shown below, and the subsequent cycles include steps E1 and E2 of deposition of insulating spacers. These alternate with conductive spacers.

[0088] [Fig. 6] In [Fig. 6], the result of a deposition step E3 (not shown, but comparable to a conformal deposition, for example by ALD atomic layer deposition) followed by anisotropic etching E4 of a first pair of conductors (or conductive spacers) is shown. They each have a thickness of 5 to 15 nm, only on the vertical parts of the structure, namely the sides of the thick layer of conductive material in each of the trenches T, already covered with insulating spacers. They occupy a second part at the first end of the trench, covering the dielectric (covering the insulating spacer 51), and another second part of the trench at the opposite end, also covering the dielectric (covering the insulating spacer 52). The conductive spacers 61 and 62 are insulated from the nanowire 20 by the grid dielectric 31. Each of the conductive spacers 61 and 62 forms the material from which a grid line is made, which acts as a grid with respect to the active area - in the example shown, a nanowire, and which extends along a trench, thus in the form of a line.

[0089] Thus, a sequence of steps has been described.

[0090] [Fig. 6B] In [Fig. 6B] this sequence of steps is repeated. First, there is a step of deposition of dielectric material El, as mentioned in relation to [Fig. 5], then an anisotropic etching step of the dielectric material E2, also mentioned in relation to [Fig. 5]. In [Fig. 6B], the two steps are separated for ease of reading.

[0091] Then there is a step of deposition of the conductive material E3, as mentioned in relation to [Fig. 6], and finally an anisotropic etching step of the conductive material E4, as also mentioned in relation to [Fig. 6]. In [Fig. 6B], the two steps are separated for ease of reading.

[0092] Since the dielectric etching step is carried out before the conductive material deposition step, the conductive spacers 61 and 62 are, at their lower ends, in contact with the grid dielectric 31.

[0093] We will now describe an alternative sequence of steps.

[0094] [Fig.6C] In an alternative embodiment shown in [Fig.6C], the cycle described above is replaced by a sequence of steps of dielectric deposition (E'1), then conductive material deposition (E'2), anisotropic etching of the conductive material (E'3), and finally anisotropic etching of the dielectric material (E'4).

[0095] There is therefore finally the presence of two portions 5la and 52a of additional dielectric under the spacers in conductive material, separating them from the grid dielectric 31.

[0096] This method makes it possible to overcome imperfections in the selectivity of the engravings with respect to the grid dielectric 31. The excess thickness of dielectric resulting from the reversal of the process steps then compensates for a progressive erosion of the latter.

[0097] [Fig.7] In [Fig.7], the result of a has been represented, according to the same principle (in following the sequence of [Fig.6B], but it is also of course possible to continue with the principles of [Fig.6C]), - El deposition step (not shown, but comparable to conformal deposition) followed by anisotropic E2 etching of a second spacer made of dielectric material, again with a thickness of 5 to 10 nm. It covers the conductive material surface that had This was established in the previous step. Part of the trench is still occupied on one side, and another part on the other. If the trench is very narrow, it is already full. However, wider trenches are not full at this stage—they will be at a later stage. - followed by a deposition step E3 (not shown, but comparable to conformal deposition) then anisotropic etching E4 of a second conductor (or conductive spacer) with a thickness of 5 to 15 nm. This second conductive spacer is electrically isolated from the first conductive spacer by the second dielectric spacer. If the trench is narrow, it is already full. However, wider trenches are not full at this stage – they will be in a later step.

[0098] [Fig.8] In [Fig.8], the result of a new double step of setting up insulating spacers and conductive spacers has been shown.

[0099] The successive steps are carried out using the same methods.

[0100] By design, the height of the spacers is likely to become smaller and smaller over the cycles (as shown in the figures), due to the limitations of the techniques used, but this is an effect without consequence on the functional character of the system.

[0101] In terms of dimensioning, the initial stacking must be high (in the direction vertically or perpendicular to the substrate), at least of the same order of magnitude as the space in which the grids are to be defined, horizontally in the plane of the substrate is wide, for the widest of the trenches.

[0102] The last material deposited is either a dielectric spacer or a conductor depending on the width of the trench - the result actually depends on the width of the trench.

[0103] The space is filled horizontally earlier in successive cycles, after fewer cycles of insulation and conductor deposition, if it is narrow (typically in trench T4 in [Fig.4]), and later in successive cycles, after more cycles of insulation and conductor deposition, if it is wide (typically in trench T2 or trench T7 in [Fig.4]).

[0104] The outer flanks of the islets are similarly deposited with spacers, except that, for these flanks, there is no opposite flank on the other side of a trench, in the absence of such a trench. The islands and islets are thus surrounded, on their respective circumferences, by continuous perimeters, each consisting of a spacer, the successive perimeters of an islet widening during the different stages.

[0105] The islands furthest from the nanowire are surrounded by several, for example three, perimeter conductive surfaces, each isolated from the other conductive elements of the device. These perimeter conductive surfaces result from the manufacturing process presented and are each isolated on both sides (inner side and outer side) by insulating spacers, over their entire perimeter.

[0106] [Fig.9] In [Fig.9], the end of the deposits is shown, the last deposit being in the case represented a dielectric deposit.

[0107] [Fig. 10] In [Fig. 10], the result of an optional chemical-mechanical polishing (CMP) is shown, designed to flatten the upper surface of the structure and, in particular, to eliminate the existing slope in the spacer-filled trenches. The polishing is carried out to obtain a flat surface, most of which is made of electrically conductive material 32. In the trenches, which are all completely filled, spacers are exposed, forming an alternating pattern 90 of conductive and insulating spacers. The conductive spacers have a flush polished surface that constitutes a conductive track on the surface of the electronic device. These tracks are grid lines, since they are essentially linear in shape, and they act as a grid with respect to the active area, namely the nanowire, at their end facing it and at least partially covering it to locally modulate the electrostatic potential in the active area.They are electrically isolated from each other due to the alternation of electrical spacers and conductive spacers.

[0108] On one side of trench T2, the following arrangements are consequently present:

[0109] Starting from the nanowire and moving away towards the small side of the substrate: - The island, first of all, is above the nanowire. - Next, the islands closest to the nanowire are surrounded by a conductive perimeter that is extended, via a branch in the conductive material, by a specific spacer in trench T2, on its edge, up to the top of the nanowire. - The subsequent islands, beyond the first trench parallel to the nanowire, are surrounded by a conductive perimeter isolated from the other conductive elements of the device. This isolated perimeter is unique. It is surrounded by another conductive perimeter extended, via a branch in the conductive material, by a specific spacer in trench T2, up to the top of the nanowire. - The following islands, after the second trench parallel to the nanowire, are surrounded by two conductive perimeters, each isolated from the other and from the other conductive elements of the device, and of increasing size. They are surrounded by another conductive perimeter extended via a branch in the conductive material, by a specific spacer in trench T2, up to above the nanowire. The islands furthest from the nanowire, beyond the third trench parallel to the nanowire, are surrounded by three conductive perimeters, each isolated from the other conductive elements of the device, and of increasing size. They are surrounded by another conductive perimeter extended via a branching point in the material. conductive, by a specific spacer in the T2 trench, up to above the nanowire. The islands have a polished surface flush with the face of the quantum electronic device. This surface is made of electrically insulating material, or electrically conductive material, depending on the choice of material used during the step of [Fig.3].

[0110] At this stage, the nanowire has been prepared and connected, and taking into account both sides of the T2 trench - 2x1 = 2 lateral access points for the source and the drain respectively (the two islands) - 2x4 = 8 access points for intermediate grids, to define 4 quantum dots.

[0111] They still need to be individualized and connected.

[0112] [Fig.11] In [Fig.11], a lithography and engraving step has been shown for - expose the source S and the drain D at the end of the nanowire (or both sources S and both drains D at the end of the two nanowires if two nanowires have been prepared, as is the case in the figure) of the active area, - short-circuit the opposite grids in the case where two nanowires are defined (as shown in the figure), - and create openings in the grid material.

[0113] In the upper part of [Fig. 11], top view, the structure during lithography is shown, and in particular the mask 1100 is visualized. It is planned to form a trench through and through between the two nanowires. It is also planned that the islands and islets will be cut by etching along the long sides of the substrate so that the conductive and insulating perimeters are all interrupted.

[0114] In the lower part of the figure, seen in cross-section, the structure is shown after the etching step. In the etched parts, the nanowire 20, the insulator 21 surrounding it or the underlying insulator is exposed.

[0115] [Fig. 12] In [Fig. 12], the result of the grid etching is shown from above. The process enabled the placement, by nanowire, of - 8 remote central contact re-establishment facilitation islands PCI to PC8, each associated with the nanowire area by a specific conductive spacer, a lateral portion of which follows the island's flank and extends into the central trench to form a grid line; the contact re-establishment facilitation islands are surrounded by alternating dielectric and conductive spacers in increasing numbers with distance from the active area and - two lateral pads called access gates PLI and PL2, which remain on the left and right parts of the nanowire and which are already connected to the nanowire area. The lateral pads can be considered islands, and the central contact pads can be considered islands. They form isolated surfaces at least larger than the width of the tracks formed by the grid lines, and even more than five times wider. An island has a dimension on the order of 100 nm, whereas a track formed by a grid line has a width on the order of 5 to 10 nm. The islands facilitate re-establishment of contact for the grid lines associated with them. Each re-establishment island includes a flank along which a lateral portion of a grid line extends.

[0116] Each conductive spacer is, at the right of the nanowire, separated from the nanowire by and only by the gate dielectric layer.

[0117] Incidentally, these 10 grid-forming connection pads were constructed for each of the two nanowires, in a double mirror geometry, since the embodiment represented relates to a two-nanowire system, and there are, on [Fig. 12], 2x10 = 20 grids.

[0118] [Fig. 13] In [Fig. 13], the upper part shows the re-establishment of contact, which occurs on the left lateral branches 1100 for four contacts, and on the right lateral branches 1110 for four other contacts. Electrical contacts are arranged to contact the grid lines, line by line, the electrical contacts being located on the lateral part of the given grid line that extends along the flank of a re-establishment facilitation island. This allows for a tolerance in the contact positioning. In the design of [Fig. 13], an electrical contact joins a lateral part of one of the grid lines between two islands, and these two islands are arranged relative to each other in a direction parallel to an elongation direction of the nanowire forming the active zone.

[0119] Contacts 1300, each in the form of a cylinder, a block, or a track, with a footprint, viewed from above, essentially rectangular (as shown) or oblong (in an alternative not shown), are used to ensure the common polarization of groups of adjacent lines—the flush portion of the conductive spacers—by contact, establishing contact above the interposed insulating spacer, or interposed insulating spaces. This approach makes it possible to equalize the potential of the islands and the associated conductive perimeter, which is extended above the nanowire in the trench T2.

[0120] The contacts have a sufficient width to facilitate re-establishment of contact without significant alignment constraints. They are dispersed over a surface area much larger than that of the nanowire.

[0121] The resulting isopotential regions are identified in the lower part of the figure (potentials are transmitted to the islands only if their surface is conductive, naturally).

[0122] This design with 8 side grids and two access grids allows for the implementation of 4 quantum dots. Every other grid is dedicated to controlling the potential of the quantum dots. The other is used to control the tunneling barrier between two adjacent dots.

[0123] [Fig.14] In [Fig.14], the left half of the structure of [Fig.13] is shown, so as not to overload the image. Blocks 14 and I4a separate trenches T4 and T5, blocks 15 and I5a separate trenches T5 and T6, blocks 16 and I6a separate trenches T6 and T7 and blocks 17 and I7a extend beyond trench T7.

[0124] The distance D1, D2, D3 between two successive islands is shown in the figure. This distance between two successive islands increases as the islands move further away from the active zone. The further an island is from the active zone, the further it is from the preceding island and also from the following island.

[0125] Trench Tl separates block 14 from block I4a, block 15 from block I5a, block 16 from block I6a and block 17 from block I7a.

[0126] The section of the trench Tl between islands 14 and I4a is narrow and therefore contains a single conductive spacer, for the leftmost grid on the nanowire in the figure, referenced Gll. This single conductive spacer is formed by the joining of a pair of spacers since both the circumferential part of a spacer going around island 14 and the circumferential part of a spacer going around island I4a are in contact at the center of the trench, the latter electrically contacting the spacer defining the grid Gll.

[0127] The section of trench Tl between islands 15 and I5a is wider, and contains three conductive spacers (two spacers of a mirrored pair, and a central spacer formed by the joining of a pair of spacers), in the following order: - an isolated conductive spacer - it is a circumferential conductive spacer around island 15. - a conductive spacer for the next grid on the nanowire, namely the second one from the left on the nanowire, referenced G12 - and another isolated conductive spacer - it is a circumferential conductive spacer around island I5a.

[0128] The section of trench T1 between islands 16 and I6a is even wider, and contains five conductive spacers (four spacers of two mirrored pairs, and a central spacer formed by the joining of a pair of spacers), in the following order: - two circumferential conductive spacers isolated around island 16 - one conductive spacer for the third grid from the left on the nanowire in the figure, G13 - two isolated circumferential conductive spacers around island I6a.

[0129] The section of trench Tl between islands 17 and I7a is even wider, and contains seven conductive spacers (six spacers of three mirrored pairs, and a central spacer formed by the joining of a pair of spacers), in the following order: - three isolated circumferential conductive spacers around island 17 - a conductive spacer for the fourth grid from the left on the nanowire in the figure, G14 - three isolated circumferential conductive spacers around island I7a.

[0130] At the level of trench Tl, it is easy to form a contact connecting a single grid, many portions being electrically isolated from the other grids of the device.

[0131] Thus, the contact point P4 for the grid G11 can be positioned above the trench T1, taking advantage of the adjacent insulated surfaces formed by the islands 14 and I4a. P4, as long as it contacts the spacer of G11, can be freely positioned on the side of island 14 or island I4a without causing a short circuit.

[0132] The contact resumption pad P5 for the grid G12 can be positioned above the trench T1 by taking advantage of the adjacent insulated surfaces formed by the islands 15 and I5a. P5, as long as it contacts the spacer of G12, can be freely positioned on the side of island 15 or island I5a without causing a short circuit.

[0133] The contact point P6 for the grid G13 can be positioned above the trench T1, taking advantage of the adjacent insulated surfaces formed by the islands 16 and I6a. As long as P6 is in contact with the spacer of G13, it can be freely positioned on the side of island 16 or island I6a without causing a short circuit.

[0134] Finally, the contact resumption pad P7 for the grid G14 can be positioned above the trench T1 by taking advantage of the adjacent insulated surfaces formed by the islands 17 and I7a. P7, as long as it contacts the spacer of G14, can be freely positioned on the side of island 17 or island I7a without causing a short circuit.

[0135] Thus, a contact can be placed straddling a lateral part of one of the grid lines, two adjacent contact re-establishment facilitation islands, and at least two dielectric spacers. This is the case for each of the pads P4 to P7.

[0136] [Fig. 15] In [Fig. 15] a design variant is shown, not using a two-dimensional network of trenches, but only a succession of trenches (here three in number) parallel to the nanowire 20, increasing in size with distance from the nanowire, which facilitates re-establishment of contact. The trenches are separated by islands. In this design, an electrical contact joins a lateral part of one of the grid lines between two islands, and these two islands are arranged relative to each other in a transverse direction, in this case perpendicular, to the nanowire and therefore to a direction of elongation of the active zone. There is an island facilitating contact re-establishment via the grid line.

[0137] Island II 1 separates trenches T1 1 and T12, island 112 separates trenches T12 and T13, and island 113 extends beyond trench T13. Again, the islands are contact re-establishment facilitation islands and include a flank along which a lateral portion of a grid line extends, in this case in the form of a conductive spacer in a trench. The distance between two adjacent contact re-establishment facilitation islands increases with the distance from the active zone.

[0138] Here, the Tl 1 trench is narrow and therefore contains only one conductive spacer, for the leftmost grid on the nanowire in the figure, referenced G11.

[0139] Trench T1 1 is followed, moving away from nanowire 20, by trench T12, which is wider and contains three conductive spacers, - a conductive spacer for the leftmost grid on the nanowire in the figure, G11 - a second conductive spacer for the next grid on the nanowire, namely the second from the left on the nanowire, referenced G12 - and a third conductive spacer, which is isolated - it is a circumferential conductive spacer around island 112, referenced C12.

[0140] Trench T12 is followed, still moving away from nanowire 20, by trench T13, which is even wider, and which contains five conductive spacers - one of which is isolated, namely the circumferential conductive spacer around island 112, mentioned above, C12 - the second one for the second grid from the left on the nanowire in the figure, G12 a third one for the next grid on the nanowire, namely the third grid from the left on the nanowire, referenced G13 - a fourth isolated and a fifth isolated, these are both circumferential conductive spacers around island 113, referenced C13 and C14.

[0141] At the level of the trenches, it is easy to form a contact connecting a single grid, many portions being electrically isolated from the other grids of the device.

[0142] Thus, the contact resumption point PI 1 for the grid G11 can be positioned above the trench T1 1, taking advantage of the adjacent insulated surface formed by the island II 1. PI 1, as long as it contacts the spacer of G11, can be freely positioned on the side of the island II 1 without causing a short circuit. Therefore, an electrical contact can be placed across a contact resumption facilitation island, a dielectric spacer, and a lateral portion of one of the grid lines. This is the case for both the PI 1 and the P12 point.

[0143] The contact resumption pad P12 for the grid G12 can be positioned above the trench T12 by taking advantage of the adjacent insulated surface formed by the island 112. P12, as long as it contacts the spacer of G12, can be positioned freely on the side of the island 112 without causing a short circuit.

[0144] Finally, the contact resumption pad P13 for the grid G13 can be positioned above the trench T13 by taking advantage of the adjacent insulated surface formed by the island 113. P13, as long as it contacts the spacer of G13, can be positioned freely on the side of the island 113 without causing a short circuit.

[0145] This variant does not impose any constraints on the size of the contacts.

[0146] To minimize the resistance of the contact points, it is possible to place several of them above the same trench or to extend them along the direction of the trench.

[0147] As in [Fig. 14] we observe that the further an island is from the active zone, the further Pilot is from the preceding Pilot and also from the following Pilot.

[0148] [Fig.16] In [Fig.16], another variant is shown, with a succession of trenches of generally increasing width when moving away from nanofil 20, but in the succession, a greater trench width is adopted only after two successive trenches have had the same width.

[0149] Thus, we see a succession of trenches (here five in number) parallel to the nanowire 20. The trenches are separated by islands. Again, the islands are contact re-establishment facilitation islands and comprise a flank along which a lateral portion of a grid line extends, in this case in the form of a conductive spacer in a trench. There are two contact re-establishment facilitation islands per grid line.

[0150] Block 121 separates trenches T21 and T21a, block 12la separates trenches T21a and T22, block 122 separates trenches T22 and T22a, block I22a separates trenches T22a and T23, block 123 separates trenches T23 and T23a, and block I23a extends beyond trench T23a.

[0151] Here, the trenches T21 and T21a are of the same width and narrow and therefore contain a single conductive spacer, for the leftmost grid on the nanowire in the figure, referenced Gll.

[0152] Trench T21a is followed, moving away from nanowire 20, by trench T22 and trench T22a, which are of the same width and wider than the previous ones, and which each contain three conductive spacers,

[0153] For T22 - a conductive spacer for the leftmost grid on the nanowire in the figure, G11 - a second conductive spacer for the next grid on the nanowire, namely the second from the left on the nanowire, referenced G12 - and a third conductive spacer, which is isolated - it is a circumferential conductive spacer around island 122, referenced C22.

[0154] For T22a - the conductive spacer, isolated - circumferential around island 122, referenced C22 - again the second conductive spacer for the next grid on the nanowire, namely the second from the left on the nanowire, referenced G12 - and a third conductive spacer, which is isolated - it is a circumferential conductive spacer around island I22a, referenced C22a.

[0155] Trench T22a is followed, moving further away from nanowire 20, by trenches T23 and T23a, which are of the same width and even wider than the previous ones, and which each contain five conductive spacers,

[0156] For T23 - one isolated, it is the circumferential conductive spacer around the island I22a, mentioned above, C22a - the second one for the second grid from the left on the nanowire in the figure, G12 - a third one for the next grid on the nanowire, namely the third grid from the left on the nanowire, reference G13 - a fourth isolated and a fifth isolated, these are both circumferential conductive spacers around island 123, referenced C23 and C24.

[0157] For T23a - the two spacers C23 and C24, both isolated - a third spacer for the next grid on the nanowire, namely the third grid from the left on the nanowire, reference G13 - a fourth isolated and a fifth isolated, these are both circumferential conductive spacers around island I23a, referenced C23a and C24a.

[0158] At the level of the trenches, it is easy to form a contact connecting a single grid, many portions being electrically isolated from the other grids of the device.

[0159] Thus, the contact resumption pad P21 for the grid G11 can be positioned above the trench T21a by taking advantage of the two adjacent insulated surfaces formed by the islands 121 and 121a. As long as it contacts the spacer of G11, it can be freely positioned on the side of island 121 or island 12a without causing a short circuit.

[0160] The contact point P22 for grid G12 can be positioned above trench T22a, taking advantage of the adjacent isolated surfaces formed by islands I22 and I22a. P22, as long as it contacts the spacer of G12, can be positioned freely on the side of island 122 or on the side of island I22a without causing a short circuit.

[0161] Finally, the contact resumption pad P23 for the grid G13 can be positioned above the trench T23a by taking advantage of the adjacent insulated surfaces formed by the islands 123 and I23a. P23, as long as it contacts the spacer of G13, can be freely positioned on the side of island 123 or island I23a without causing a short circuit.

[0162] Thus, a contact is placed straddling a lateral part of one of the grid lines and a dielectric spacer without having contact with a contact re-establishment facilitation island. This is the case for pad P24.

[0163] Or a contact may be placed straddling a lateral part of one of the grid lines, two adjacent re-establishment facilitation islands and at least two dielectric spacers. This is the case for pads P21, P22 and P23.

[0164] In this variant, contacts can be re-established without difficulty. These contacts can be extended along the direction of the trenches to minimize the resistance of the re-established contacts and / or along the transverse direction to minimize alignment constraints.

[0165] As can be seen in [Fig. 14] and [Fig. 15], the further an island is from the active zone, the further the island is from the preceding island and also from the following island.

Claims

Demands

1. A quantum electronic device comprising: - an active region (20) for hosting quantum dots and, - flush on one face of the device: a) a plurality of grid lines (G11, G12, G13, G14), electrically insulated from one another and each covering a portion of the active region (20), and b) reconnection facilitation islands (14-17, 14a-17a; 11-113; 121-123a) at a ratio of at least one island per grid line, the reconnection facilitation islands being separated from one another by a distance (D1, D2, D3), each reconnection facilitation island comprising a flank along which a lateral portion (P4-P7; P11-P13; P21-P23) of a grid line extends, the device further comprising at least one electrical contact (P4-P7; P11-P13;P21-P23) to contact at least one given grid line (G11,G12, G13,G14), at least one electrical contact being located at least on the lateral part of the given grid line which extends along the side of a re-establishment facilitation island (14-17,14a-17a; 11-113; 121-123a).;

2. Quantum electronic device according to claim 1, characterized in that the contact re-establishment facilitation islands (14-17, I4a-I7a; I1-I13; I21-I23a) are surrounded by an alternation of dielectric spacers and conductive spacers in numbers that increase with the distance from the active area (20).

3. Quantum electronic device according to claim 1 or claim 2, characterized in that the distance (D1, D2, D3) between two neighboring re-establishment contact facilitation islands increases with the distance from the active area (20).

4. Quantum electronic device according to any one of claims 1 to 3, characterized in that the device comprises a substrate (10) of bulk silicon or silicon on insulator.

5. Quantum electronic device according to any one of claims 1 to 4, characterized in that the active area comprises a nanowire, in particular made of silicon.

6. A quantum electronic device according to any one of claims 1 to 5, characterized in that the active area has two ends, at least one of the ends forming a reservoir of load carriers.

7. Quantum electronic device according to any one of claims 1 to 6, characterized in that the contact re-establishment facilitation islands have a surface made of electrically insulating material, or of electrically conductive material.

8. Quantum electronic device according to any one of claims 1 to 7, characterized in that the grid lines form grids for local adjustment of the electrostatic potential in the active area.

9. Quantum electronic device according to any one of claims 1 to 8, characterized in that an electrical contact is placed straddling a re-establishment facilitation island, at least one dielectric spacer and a lateral part of one of the grid lines, or straddling a lateral part of one of the grid lines and a dielectric spacer without having contact with a re-establishment facilitation island, or straddling a lateral part of one of the grid lines, two adjacent re-establishment facilitation islands and at least two dielectric spacers.

10. Quantum electronic device according to any one of claims 1 to 9, characterized in that an electrical contact joins a lateral part of one of the grid lines between two islands arranged relative to each other in a direction essentially parallel to a direction of elongation of the active area.

11. Quantum electronic device according to any one of claims 1 to 9, characterized in that an electrical contact joins a lateral part of one of the grid lines between two islands arranged relative to each other in a direction transverse to a direction of elongation of the active area.

12. A method for manufacturing a quantum electronic device comprising placing, on a substrate (10), an active region (20), and a plurality of grid lines (G11, G12, G13, G14), electrically insulated from each other, and between the grid lines and the active region (20), a layer of dielectric material (31), the method comprising trenching steps (T4-T7) by etching in a conductive material placed on the substrate, then successive conformal depositions of dielectric spacers (E1; E'1) and conductive spacers (E3; E'2), with trench widths increasing with distance from the active region (20), the

13.

14. conductive spacers forming the plurality of grid lines, the method further comprising the provision of at least one electrical contact to contact at least one given grid line, the at least one electrical contact being located at least on a lateral part of the given grid line extending along a flank of a contact resumption facilitation island. Method of manufacturing a quantum electronic device according to claim 12, characterized in that each conformal deposit (E1, E3) is followed by an anisotropic etching (E2, E4) before the next deposit or the deposits of dielectric spacers (E'1) and conductive spacers (E'2) are carried out before anisotropic etchings of the conductive material (E'3) and then of the dielectric material (E'4). Method of manufacturing a quantum electronic device according to claim 12 or claim 13, characterized in that the trenches comprise mesh trenches, a transverse trench (T1, T3) to the elongated conductor (20) widening away from the elongated conductor (20) at each crossing of a parallel trench (T4-T7) to the elongated conductor (20).

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