A modular and scalable power semiconductor module arrangement

Abstract

Power semiconductor module for a hybrid electric vehicle (EV), comprising a multilayer substrate. The layers comprise first insulating layer 20, and first, second and third conductive tracks 201, 202,

Description

Technical Field The present disclosure relates to a power semiconductor module and a method for manufacturing the same. More particularly, but not exclusively, the present disclosure relates to a power semiconductor system which integrates two or more semiconductor modules for use in applications such as Electric Vehicles or Hybrid Electric Vehicles. Background Power semiconductor modules have been considered as one of the most delicate components in electric drive systems, such as those for electric vehicles (EVs) and hybrid electric vehicles (HEVs). For such applications, there has been an increasing demand for power semiconductor modules with increased power density, improved electrical performance and thermal performance, high reliability and reduced costs. Wideband gap (WBG) power semiconductor devices, such as silicon carbide (SiC) and gallium nitride (GaN) transistors have become increasingly commercially available over recent years, and have been demonstrated to achieve improved switching performance over silicon transistors in high-frequency, high-power and high-temperature applications. Therefore, they are generally attractive for use as switching devices to construct e.g. power semiconductor modules applications with varying voltages, such as converting direct current (DC) to three-phase alternating currents (ACs) and converting single-phase or three-phase ACs to DC in the on-board charging (OBC), or electric control systems of HEVs and EVs. However, when WBG power semiconductor devices are integrated into power semiconductor modules using known packaging structures, switching or otherwise operating the devices at higher frequencies can result in large levels of voltage overshoot during the turn-off stages, as well as increases in electromagnetic interference (EMI) noise and CM noise currents. This is due, at least in part, to parasitic inductance, generally high current and voltage slew rates, and parasitic capacitances (e.g. to heat sinks which are typically grounded for safety). There may exist unbalanced currents distributed between the paralleled power semiconductor devices, therefore the even distribution of currents between the paralleled power semiconductor devices may be further improved. The Applicant has therefore recognised a need to further improve the power density, the electrical and thermal performances as well as the reliability of power semiconductor modules in EV and HEV electric drive applications while also reducing the associated manufacturing and assembly costs. It is an object of the present disclosure, among others, to provide such an improved power semiconductor module. Documents with relevance to the field of the disclosure include the following: - US 2020 / 0244164 A1; - US 2014 / 0152373 A1; - US 2019 / 0172772 A1; - US 10,032,732 B1; - Low inductive full ceramic SiC power module for high-temperature automotive applications (PCIM Europe digital days 2020; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 07-08 July 2020, Klein et al); and - Wide band gap packaging (ECPC Tutorial on Power Electronics Packaging, 21 September 2022, Feix et al). Summary According to a first aspect of the present disclosure, there is provided a power semiconductor module, comprising: a substrate comprising a plurality of layers, the plurality of layers comprising: a first insulating layer; and a first conductive layer arranged on a surface of the first insulating layer, the first conductive layer comprising first, second and third conductive tracks spaced apart from one another; a plurality of second insulating layers arranged on the first and second conductive tracks of the first conductive layer; a plurality second conductive layers each arranged on one of the plurality of second insulating layers a first power terminal operatively connected to the first conductive track of the first conductive layer; a second power terminal operatively connected to the second conductive track of the first conductive layer; an output terminal operatively connected to the plurality of second conductive layers; a first semiconductor die the first semiconductor die arranged on the first conductive track of the first conductive layer; and a second semiconductor die, the second semiconductor die arranged on the second conductive track of the first conductive layer, wherein a gate terminal or electrode of the second semiconductor die is operatively connected to the third conductive track of the first conductive layer; and wherein a source terminal or electrode of the first semiconductor die and a drain terminal or electrode of the second semiconductor die are operatively connected to the plurality of second conductive layers. Advantageously, in the power semiconductor module the special layouts of conductive tracks and electrical connections lead to the formation of local anti-parallel current flows and branches of current flow and thus effectively reduce the parasitic inductances of the commutation loops. They in combination with the layout of the electrical connections can also facilitate balanced parasitic inductance values between the first power terminal and output terminal and the second power terminal and output terminal, and balanced parasitic capacitance values between the one associated with the first power terminal, and the one associated with the second power terminal to the back of the first insulating layer. All these can assist in effectively suppressing the EMI noise and CM noise currents at high switching frequencies. Further, under many manufacturing techniques, a number of layers with smaller individual surface areas can be produced with a reduced manufacturing cost in comparison with larger single layer substrates with a same total area. The wire bonding technology in combination with a number of insulated layers bonded onto a first insulated layer can also help to reduce the manufacturing cost to assemble the power semiconductor module. Therefore, the power semiconductor module can be produced with low cost. The arrangement of smaller layers bonded on a common insulated layer can further reduce the bending / warpage of the packaging structure due to mismatched coefficients of thermal expansion (CTE) between the different layers, e.g. via suitable selection of materials for the layers of the substrate, and reduce the thermo-mechanical stress and strain developments in the solder joints or sintered joints which may be used to bond the layers and / or bond the power semiconductor module onto a thermal management device, such as a cold plate or heat sink. Also, the insulating layers in the power semiconductor module may be provided with no metal-filled vias. This reduces or, ideally, eliminates the thermo-mechanically weak points associated with such vias, which often lead to cracking and fracturing of the insulating layers due to the different thermal expansion and contraction of the filled metal and ceramic when they are subjected to varied temperatures. Therefore, the power semiconductor modules can also have high reliability when they are subjected to the varied temperatures in the application environments. It would be understood that any suitable method may be used to operatively connect and / or mechanically attach the layers, attach the terminals of the first and second semiconductor dies to the conductive tracks of the conductive layers and the terminals to the conductive tracks of the conductive layers. For example, the various layers and components of the module may be connected or attached via sintering, soldering, Direct Bonding Copper (DBC), or any other suitable means or method. The term “operatively connected” used in the present disclosure encompasses both direct connections and indirect connections (where further element(s) are placed between the two connected elements), suitable for their intended use. For example, for components requiring an electrical connection, the term “operatively connected” may comprise any suitable electrically conductive connection or attachment, while for components requiring a connection to facilitate heat transfer the term may comprise any suitable thermally conductive connection or attachment. It would be further understood that the power semiconductor module may alternatively / additionally comprise a plurality of substrates, each comprising an insulating layer and at least one conductive layer without changing the scope of the present invention. For example, the plurality of layers of the substrate may form a plurality of auxiliary substrates, such that the substrate comprises respective first, second, third, etc. auxiliary substrates formed by the plurality of layers of the substrate. The substrate may further comprise: a third insulating layer arranged on the first conductive track of the first conductive layer; and a third conductive layer arranged on the surface of the third insulating layer, the third conductive layer may comprise a plurality (e.g. first, second, third...) conductive tracks spaced apart from one another; wherein the source terminal or electrode of the first semiconductor die is operatively connected to conductive tracks of the third conductive layer and the gate terminal or electrode of the first semiconductor die is operatively connected to a (different) conductive track of the third conductive layer, for e.g. providing control signals to the first semiconductor die. The power semiconductor module may comprise further control terminals operatively connected to the second and third conductive tracks of the first conductive layer, for e.g. providing control signals for the second semiconductor die. The power semiconductor module may further comprise a plurality of control terminals operatively connected to at least one of the conductive tracks of the third conductive layer and the second and third conductive tracks of the first conductive layer. The control terminals may form respective external source and gate terminals for the semiconductor dies. At least one of the plurality of control terminals, the first and second power terminals and the output terminal may extend in a substantially perpendicular direction with respect to the first insulating layer of the substrate. For example, all of the plurality of control terminals, the first and second power terminals and the output terminal may extend in a substantially perpendicular direction with respect to the first insulating layer of the substrate. Advantageously, by placing the control, output and / or power terminals ‘vertically’ (i.e. extending in a direction substantially perpendicular to the substrate surfaces the footprint of the power semiconductor module can be significantly reduced compared to the conventional ‘horizontal’ terminals. At least one of the plurality of control terminals, the first and second power terminals and the output terminal may be made of or otherwise comprise a material with a coefficient of thermal expansion which matches the coefficients of thermal expansion of a material forming or comprising the plurality of layers. Advantageously, matching coefficients of thermal expansion mitigate or eliminate the stress and strain developments in the joints between terminals and the layers to which they are bonded / attached. Accordingly, the thermo-mechanical reliability of the power semiconductor module is improved. The power semiconductor module may further comprise a plurality of wire bonds operatively connecting the source terminal of the first semiconductor die and a drain terminal of the second semiconductor die to the plurality of second conductive layers. The plurality of wire bonds connected to the source side or drain side of each power semiconductor die may form local anti-parallel current flows and branches of current flow and thus effectively improve the ability of carrying high currents and reliability of the wire bonds. The wire bonds are thus in some implementations made of or comprise aluminium wires which can be ultrasonically bonded on the die with the metallisation system, to provide bonding parameters which are better developed and established than those for bonding silver and copper wires while having sufficient ability of carrying high currents. One or more wires can be bonded on or to each die. The power semiconductor module may further comprise a capacitor operatively connected in series between the first and second conductive tracks of the first conductive layer. The inclusion of an (integrated) decoupling capacitor or capacitors, along with the configuration of the conductive tracks and / or wire bonds, may assist in the formation of local anti-parallel current flows and branches of current flow, and thus effectively further reduce the parasitic inductances of the commutation loops. The power semiconductor module may further comprise a diode operatively connected in an anti-parallel configuration with at least one of the first and second semiconductor die. The anti-parallel configuration of the diodes may reduce a reverse recovery loss. The power semiconductor module may further comprise: a conductive spacer operatively connected between a source terminal of the second semiconductor die and the second conductive track of the first conductive layer; and a printed circuit board operatively connected between the gate terminal of the second semiconductor die and the third conductive track of the first conductive layer. The thickness of the conductive spacer and the printed circuit board may be approximately or substantially the same, or otherwise equal. Advantageously, using a printed circuit board (PCB) to electrically connect the flipped low side device to the first conductive layer of the substrate facilitates the design of the conductive layer on one side of the PCB to match the dimensions of the gate terminal, and the conductive layer on the other side to be designed to match the dimensions of the conductive track of the first conductive layer to which it is affixed. The matched thickness conductive spacer simplifies construction ensuring that the low side device sits substantially horizontally on the first conductive layer. At least one of the layers may be made of an electrically insulating and thermally conductive material. For example, some or all of the insulating layers of the plurality of layers forming the substrate may be electrically insulating layers. The power semiconductor module may be configured as a half-bridge switch operatively connected in series between the first and second power terminals. The power semiconductor module may further comprise an encapsulant encapsulating the first and second semiconductor die. The encapsulant may additionally / alternatively encapsulate one or more other ‘elements’ of the power semiconductor module. Encapsulating these elements provides both good insulation and additional mechanical support to the elements improving the strength and thermo-mechanical reliability of the power semiconductor module. Accordingly, the encapsulant must be sufficiently hard to provide the necessary support and thermo-mechanical reliability i.e. not comprise a soft silicone gel. Furthermore, potting compound in combination with plastic frame housing is used as the encapsulation and is designed with special surface grooves to thin the modules while maintaining sufficient creepage distances between the terminals. Therefore, the modules can be constructed with low volume and thus high power density. The encapsulant may comprise a moulding compound. The moulding compound may comprise thermally conductive fillers. As compared to a conventional technique which uses a plastic housing and silicone gel as the encapsulant, using the moulding compound as the encapsulant reduces the volume of the power semiconductor module and ensures sufficient insulating and creepage distances between the conductive tracks and between the terminals of the power semiconductor module with smaller or similar dimensions or volumes. Further, the moulding compound provides additional mechanical support to the power semiconductor module, and hence improves the structural strength and thermomechanical reliability of the power semiconductor module. The power semiconductor module may further comprise a fourth conductive layer arranged on a further side of the first insulating layer, such as a (conductive) back plate. The fourth conductive layer may be configured to be (electrically) connected to a baseplate or heat sink. The power semiconductor module may further comprise a thermal management device, such as a heat-sink or cold plate, wherein the first insulating layer is operatively connected to the heat-sink or cold plate. According to a second aspect of the present disclosure, there is provided a power semiconductor system comprising a plurality of power semiconductor modules according to the first aspect. The power semiconductor system is constructed with a plurality of semiconductor modules. For example, a plurality of half bridge switches may be combined to form single phase or multiple phase half bridge switches for handling high currents and can hence have currents evenly distributed between the paralleled power semiconductor device die because each die or each pair of die are assembled in the same packaging structure and hence have conducting path or loop exactly the same as each other. The plurality of power semiconductor modules may comprise one or more of a common first insulating layer, a common baseplate or common heatsink or cold plate. In implementations comprising a common insulating layer or baseplate, the common insulating layer or baseplate may be attached to a common heat sink or cold plate. According to a third aspect of the present disclosure, there is provided an electric vehicle comprising a power semiconductor system according to the second aspect. According to a fourth aspect of the present disclosure, there is provided a hybrid electric vehicle comprising a power semiconductor system according to the second aspect. According to a fifth aspect of the present disclosure, there is provided a method of manufacturing a power semiconductor module, comprising: providing a substrate, wherein providing the substrate comprises: forming a first insulating layer; forming a first conductive layer on a surface of the first insulating layer, the first conductive layer comprising first, second and third conductive tracks spaced apart from one another; forming a plurality of second insulating layers on the first and second conductive tracks of the first conductive layer; forming a plurality second conductive layers on one of the plurality of second insulating layers; attaching a first power terminal to the first conductive track of the first conductive layer; attaching a second power terminal to the second conductive track of the first conductive layer; attaching an output terminal to the plurality of second conductive layers; attaching a first semiconductor die to the first conductive track of the first conductive layer; and attaching a second semiconductor die to the second conductive track of the first conductive layer and a gate terminal of the second semiconductor die to the third conductive track of the first conductive layer electrically connecting a source terminal of the first semiconductor die and a drain terminal of the second semiconductor die to the plurality of second conductive layers. Providing the substrate may further comprise forming a third insulating layer on the first conductive track of the first conductive layer; and forming a third conductive layer on the surface of the third insulating layer, the third conductive layer comprising a plurality of conductive tracks spaced apart from one another. The method may further comprise electrically connecting the source terminal of the first semiconductor die to the first and third conductive tracks of the third conductive layer, and electrically connecting the gate terminal of the first semiconductor die to the second conductive track of the third conductive layer. The method may further comprise encapsulating the first and second semiconductor die with an encapsulant. According to a sixth aspect of the present disclosure, there is provided a power semiconductor module, comprising: a substrate comprising a plurality of layers, the plurality of layers comprising: a first insulating layer; a first conductive layer arranged on a surface of the first insulating layer, the first conductive layer comprising first, second and third conductive tracks spaced apart from one another; a plurality of second insulating layers arranged on the first and second conductive tracks of the first conductive layer; a plurality second conductive layers each arranged on one of the plurality of second insulating layers a first power terminal operatively connected to the first conductive track of the first conductive layer; a second power terminal operatively connected to the second conductive track of the first conductive layer; and an output terminal operatively connected to the plurality of second conductive layers; wherein the first and second power terminals and the output terminal extend in a substantially perpendicular direction with respect to the first insulating layer of the substrate. Advantageously, by placing the output and / or power terminals ‘vertically’ (i.e. extending in a direction substantially perpendicular to the substrate surfaces the footprint of the power semiconductor module can be significantly reduced compared to the conventional ‘horizontal’ terminals commonly used in the art. Where appropriate any of the features described above in relation to one aspect of the present disclosure may be applied to any other aspect of the disclosure. It would also be understood that the terms “first”, “second”,... , ’’sixth” are used in the present disclosure to label the relevant elements for the ease of description, and are not intended to limit or imply any limitations to the sequence or locations of the relevant elements. Brief Description of the Drawings In order that the disclosure may be more fully understood, a number of embodiments of the disclosure will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 schematically illustrates a circuit diagram of a power semiconductor module according to an embodiment of the present disclosure; Figure 2 schematically illustrates a top perspective view of a power semiconductor module according to an embodiment of the present disclosure which implements the circuit diagram of Figure 1; Figure 3 schematically illustrates a bottom perspective view of the power semiconductor module of Figure 2; Figure 4 schematically illustrates a top plan view of the power semiconductor module of Figure 2; Figure 5 schematically illustrates a side view of the power semiconductor module of Figure 2; Figure 6 schematically illustrates a top perspective view of the power semiconductor module of Figure 2 with AC terminal 13 being invisible; Figure 7 schematically illustrates a top perspective view of the power semiconductor module of Figure 2 with all terminals and wire bonds being invisible; Figure 8 schematically illustrates a top perspective view of the power semiconductor module of Figure 2 with all terminals, wire bonds and second to fourth substrates being invisible; Figure 9 schematically illustrates a cross-sectional view of the power semiconductor module of Figure 2 along dash line AB of Figure 8; Figure 10a schematically illustrates a bottom perspective view of the low side device of the power semiconductor module of Figure 2; Figure 10b schematically illustrates a bottom perspective view of the low side device of the power semiconductor module of Figure 2 with the PCB and conductive spacer present; Figure 11 schematically illustrates a top perspective view of the first substrate of the power semiconductor module of Figure 2; Figure 12 schematically illustrates a bottom perspective view of the first substrate of the power semiconductor module of Figure 2; Figure 13 schematically illustrates a top perspective view of the PCB of the power semiconductor module of Figure 2; Figure 14 schematically illustrates a bottom perspective view of the PCB of the power semiconductor module of Figure 2; Figure 15 schematically illustrates a top perspective view of the second or third substrate of the power semiconductor module of Figure 2; Figure 16 schematically illustrates a bottom perspective view of the second or third substrate of the power semiconductor module of Figure 2; Figure 17 schematically illustrates a top perspective view of the fourth substrate of the power semiconductor module of Figure 2; Figure 18 schematically illustrates a bottom perspective view of the fourth substrate of the power semiconductor module of Figure 2; Figure 19 schematically illustrates a circuit diagram of an H-bridge module according to a further embodiment of the present disclosure, including two of the power semiconductor modules of Figure 1; Figure 20 schematically illustrates a top perspective view of an H-bridge module according to a further embodiment of the present disclosure which implements the circuit diagram of Figure 19; Figure 21 schematically illustrates a bottom perspective view of the H-bridge module of Figure 20; Figure 22 schematically illustrates a top plan view of the H-bridge module of Figure 20; Figure 23 schematically illustrates a side view of the H-bridge module of Figure 20; Figure 24 schematically illustrates a top perspective view of the H-bridge module of Figure 20 with plastic frame 82 being invisible; Figure 25 schematically illustrates a top perspective view of the H-bridge module of Figure 20 with plastic frame 82 and potting compound encapsulant 92 being invisible; Figure 26 schematically illustrates a side view of the H-bridge module of Figure 20 with plastic frame 82 and potting compound encapsulant 92 being invisible; Figure 27 schematically illustrates a top perspective view of a three-phase half bridge module according to a yet further embodiment of the present disclosure, including nine of the power semiconductor modules of Figure 1; Figure 28 schematically illustrates a top perspective view of the three-phase half bridge module of Figure 27; Figure 29 schematically illustrates a bottom perspective view of the three-phase half bridge module of Figure 27; Figure 30 schematically illustrates a side view of the three-phase half bridge module of Figure 27; Figure 31 schematically illustrates a top perspective view of the three-phase half bridge module of Figure 27 with plastic frame 83 being invisible; Figure 32 schematically illustrates a top perspective view of the three-phase half bridge module of Figure 27 with plastic frame 83 and potting compound encapsulant 93 being invisible; Figure 33 schematically illustrates a side view of the three-phase half bridge module of Figure 27 with plastic frame 83 and potting compound encapsulant 93 being invisible; Figure 34 shows process steps of a method for manufacturing a power semiconductor module according to an embodiment of the present disclosure. In the figures, like parts are denoted by like reference numerals. It will be appreciated that the drawings are for illustration purposes only and are not drawn to scale. Detailed Description of the Preferred Embodiments Figure 1 shows a circuit diagram of a power semiconductor module 100 according to an embodiment of the present disclosure. The power semiconductor module 100 comprises half bridge switch comprising a high side device M1 and a low side device M2 electrically connected in series between a DC+ (power) terminal 11 and a DC-(power) terminal 12, and an AC output terminal 13 electrically connected there between. The high side device M1 comprises three control terminals G1 (15), S11 (14) and S12(16). The low side device M2 comprises three further control terminals G2 (18), S21 (17) and S22(19). The half-bridge switch 100 further comprises a decoupling capacitor Cd electrically connected in series between the DC+ terminal 11 and a DC-terminal 12. Figure 1 further shows a number of typical parasitic parameters. In the parasitic inductance parameters, Lc+ represents the effective parasitic inductance between the positive electrode of the decoupling capacitor Cd and the middle interconnecting point of high and low side devices M1 and M2. Lc- represents the effective parasitic inductance between the negative electrode of the decoupling capacitor Cd and the middle interconnecting point of high and low side devices M1 and M2. Lt+ stands for the effective parasitic inductance between the DC+ terminal and the positive electrode of the decoupling capacitor CD. Lt- represents the effective parasitic inductance between the DC- terminal and the negative electrode of the decoupling capacitor Cd. Lac represents the effective parasitic inductance between the AC terminal and the middle interconnecting point of high and low side devices M1 and M2. Lgi stands for the effective parasitic inductance from the G1 terminal 15 to the paralleled S11 14 and S12 16 terminals via the high side device M1. Lg2 stands for the effective parasitic inductance from the G2 terminal 18 to the paralleled S21 17 and S22 19 terminals via the low side device M2. In the parasitic capacitance parameters, C+ represents the effective parasitic capacitance between the drain electrode of the high side device M1 and ground. C-represents the effective parasitic capacitance between the source electrode of the low side device M2 and ground. Cac represents the effective parasitic capacitance between the source electrode of the high side device M1 or the drain electrode of the low side device M2 and ground. The body diode of each of the high and low side devices M1 and M2 is employed as the freewheeling diode. In case where the body diodes lead to high reverse recovery loss, diodes may be connected to high and low side devices M1 and M2 in anti-parallel. In the example of Figure 1 the high and low side devices M1 and M2 are SiC MOSFET chips. However, the high and low side devices M1 and M2 may be replaced with other wide bandgap semiconductor power chips such as GaN transistor chips. Figures 2 to 17 schematically illustrate a power semiconductor module 100 according to a first embodiment of the present disclosure which implements the circuit diagram of Figure 1. Elements of the power semiconductor module 100 which implement elements of the circuit diagram of Figure 1 are identified using the same labels. As can be seen from Figures 2 to 10, the high side device M1, is attached with a joint A1, on the conductive track 201, of a ceramic-insulated substrate consisting of conductive tracks 201 to 203, an insulating ceramic layer 20, and a back conductive plate 21. The low side device M2, is flipped where its source pads are connected to the conductive track 202 via a metallic spacer 61, and two joints A21 and A22; and its gate pad is connected to the conductive track 203 via a small flexible PCB and two joints A23 and A24. In other words, device M2 is a flip chip semiconductor device or die. As shown in Figures 13 and 14, the small flexible PCB comprises a conductive layer 601, on one side, insulating layer 60, in the middle, and another conductive layer 602, on the other side. The conductive layers 601 and 602, are electrically connected with a via 603, through the insulating layer 60. One decoupling capacitor Cd, is also attached on the two conductive tracks 201 and 202, with two joints A3 and A4. Three smaller insulated substrates are further bonded on the conductive tracks 201 and 202, of the ceramic-insulated substrate. As shown in Figures 15 and 16, two of the three smaller insulated substrates are the same as each other. They each comprise a conductive track 301 or 401 on the top side, insulating layer 30 or 40, in the middle, and conductive tracks 31 and 32 or 41 and 42, on the other side. As shown in Figures 16 and 17, another smaller insulated substrate comprises conductive tracks 501 to 503, on the top side, insulating layer 50, in the middle, and conductive track 51, on the other side. The two conductive tracks 31 and 32, of one smaller insulated substrate are bonded on the two conductive tracks 201 and 202, with two joints A5 and A6, respectively. The two conductive tracks 41 and 42, of the second smaller insulated substrate are bonded on the two conductive tracks 201 and 202, with two joints A7 and A8 (shown in Figure 5), respectively. The conductive track 51, of another smaller insulated substrate is bonded on the conductive track 201, with one joint A9 (shown in Figure 5). It will be understood that the main substrate 20 and smaller substrates 30, 40, 50 may formed by various layers of a single substrate, or may be provided as separate substrates stacked, connected or attached together to form the module 100. In alternative configurations, one pair of stacked substrates may be used to replace the four (main and smaller) substrates, or two pairs of stacked substrates may be placed at the two sides of the power semiconductor chips M1, M2, to provide similar benefits of reduced parasitic inductances, suppressed EMI noise and CM noise currents. In this case, the costs of such modules may be higher than the module 100. Nevertheless, such modules can still provide evenly distributed currents between paralleled power semiconductor chips, high power density, reduced cost and high reliability of the WBG power semiconductor modules in comparison with the existing corresponding modules with larger single layer stacked substrates. Two groups of wire bonds, 1 and 2, are used to connect the source pad of M1 to conductive tracks, 301 and 401, of the two smaller insulated substrates. Another two groups of wire bonds, 3 and 4, are used to connect the drain side of M2 to the same two conductive tracks, 301 and 401, and thus the source side of M1 and drain side of M2 are connected together with the two conductive tracks, 301 and 401. Wire bonds, 5 to 7, are used to connect the gate and auxiliary source pads of M1 to three conductive tracks, 501 to 503, of another smaller insulated substrate. The two DC terminals, 11 and 12, are respectively bonded on the two conductive tracks, 201 and 202, of the ceramic-insulated substrate, and near the two electrodes of the decoupling capacitor, Cd. AC terminal, 13, is bonded in the middle of the two conductive tracks, 301 and 401, of the two smaller insulated substrates. The three terminals, 14 to 16, are bonded on the three conductive tracks, 501 to 503, of another smaller insulated substrate. The three terminals, 17 to 19, are bonded on the three ends of the two conductive tracks, 202 and 203, of the ceramic-insulated substrate. In the above described power semiconductor module 100, the two groups of wire bonds, 1 and 2, which are connected to the source side of M1, and the two groups of wire bonds, 3 and 4, which are connected to the drain side of M2, are designed to form local anti-parallel current flows and branches of current flow and thus effectively improve the ability of carrying high currents and reliability of the wire bonds. The four groups of wire bonds, 1 to 4, in combination with the two conductive tracks, 301 and 401, of the two smaller insulated substrates, to form the local anti-parallel current flows and branches of current flow can be further used to effectively reduce the parasitic inductance of the commutation loop. It will be understood that the parasitic inductances of the commutation loops in power modules depend on the size of the semiconductor power device chips. Larger chips require larger and wider conductive tracks to accommodate them. In the present example power semiconductor module 100 the size of high and low side devices M1 and M2 is approximately 5 mm by 4 mm. Therefore the parasitic inductances may be less than 7nH for the commutation loop which is formed by: the DC+ terminal 11, conductive track 201, high side device M1, groups of wire bonds 1 and 2, paralleled conductive tracks 301 and 401, groups of wire bonds 3 and 4, low side device M2, conductive track 202, DC- terminal 12; and may be less than 3nH for the commutation loop which is formed by: the positive electrode of the decoupling capacitor, Cd, conductive track 201, high side device M1, groups of wire bonds 1 and 2, paralleled conductive tracks 301 and 401, groups of wire bonds 3 and 4, low side device M2, conductive track 202, and the negative electrode of the decoupling capacitor, Cd. Similarly, to achieve low parasitic inductances between the gate and auxiliary source terminals, two wire bonds 5 and 7, and two auxiliary source terminals 14 and 16, are used to connect to the auxiliary source pad of M1, and two ends of one conductive track 202, and two auxiliary source terminals 17 and 19, are used to connect to the source side of M2. Then the parasitic inductances may both be less than 4.6nH for the gate loops from the gate terminal 15, conductive track 502, wire bond 6, high side device M1, wire bonds 5 and 7 and auxiliary terminals 14 and 16, and from the gate terminal 18, conductive track 203, low side device M2, conductive track 202 and auxiliary terminals 17 and 19. In addition to the reduced parasitic inductances, one decoupling capacitor Cd, is connected in series with and between high and low side devices M1 and M2 of the example power semiconductor module 100 to ‘absorb’ and ‘offer’ energy during the device switching on / off, and hence achieve significant reduction in the voltage overshoot during the switching-off stage. Alternatively, two or more decoupling capacitors Cd may be connected in series or in parallel to replace the one capacitor. In this case, the conductive tracks of the ceramic-insulated substrate may be adjusted accordingly. However, one decoupling capacitor Cd is preferably employed to simplify the structure and reduce the footprint of the ceramic-insulated substrate. The decoupling capacitor(s) Cd may comprise one type of the surface mount device (SMD) capacitors, and preferred to comprise one of ceramic SMD capacitors due to their compact sizes and high temperature stability and reliability. However, any suitable decoupling capacitor(s) Cd may be used. The flipped low side device M2, plus the three smaller insulated substrates bonded on the ceramic-insulated substrate are used to take the parasitic capacitance of the source side of M1 and the drain side of M2, i.e., the parasitic capacitance associated with the AC terminal 13, Cac shown in Figure 1, away from the insulating ceramic layer 20, against the back plate 21, of the ceramic-insulated substrate which is in general electrically connected to a baseplate and / or heat sink. Furthermore, they in combination with the four groups of wire bonds 1 to 4, can be used to readily achieve balanced parasitic inductance values between the one from the DC+ terminal 11 to the AC terminal 13, and the one from the AC terminal 13 to DC- terminal 12; and balanced parasitic capacitance values between the one of the drain side of M1 from the insulating ceramic layer 20, against the conductive back plate 21, i.e. the parasitic capacitance associated with the DC+ terminal, and the one of the source side of M2 from the insulating ceramic layer 20, against the conductive back plate 21, i.e. the parasitic capacitance associated with the DC- terminal. All these can effectively suppress the EMI noise and CM noise currents (l=C(dV / dt)) due to parasitic capacitance (e.g. to heat sinks which are typically grounded for safety) and high slew rate, dV / dt. In addition, all of the power and control terminals 11 to 19 in the power semiconductor module 100 have portions which extend in a direction substantially perpendicular with respect to the main plane of the stacked substrates. Such an arrangement of the terminals 11 to 19 can reduce the footprint of the power semiconductor module 100 and consequentially any power converter constructed with a plurality of the power semiconductor module 100 to form single phase or multiple phase half bridge switches for handling higher or similar currents. Optionally, some or all of the terminals may be placed horizontally with respect to the main plane of the module. For example, the gate and auxiliary source terminals of the two chips M1, M2 may be extended from two opposite sides, and all the power terminals may be extended from a third side of the module. In this case, the footprint of the module may somewhat enlarged relative to a module with perpendicular terminals, but its thickness or height may be reduced. The modules may therefore be more suitable for stacking in alternating layers with heat sinks, rather than placing the modules side by side as depicted in e.g. Fig. 25. Nevertheless, each module can be provided with integrated decoupling capacitor(s) and the special layouts of conductive tracks and wire bonds, as in module 100, to achieve low parasitic inductances of the commutation loops, and the flipped low side power device chip connected to the ceramic-insulated substrate via a small flexible PCB to form the desirable parasitic inductances and capacitances. In the power semiconductor module 100, the ceramic-insulated substrate is preferably chosen from the standard / conventional direct bonded copper (DBC), directed bonded aluminium (DBA) or active brazed metal (ABM) substrates. In one of these DBC, DBA or ABM substrates, the insulating layer 20, is 0.2 to 1 mm thick Aluminium Oxide (AI2O3), AIN or silicon nitride (Si3N4) ceramic tile, and the conductive layers on both sides of the ceramic tile are 0.1 to 1 mm thick pure copper, pure aluminium, coppermolybdenum alloy, copper-tungsten alloy, or other pure metals or alloys with similar thermal, electrical and thermo-mechanical properties. The pure metal or alloy layer on the top side of the substrate is configured to form the conductive tracks 201 to 203, to support the high and low side devices M1 and M2, accommodate the decoupling capacitor Cd, bond the three smaller insulated substrates, and hold three terminals 17 to 19. The gate pads of the high and low side devices M1 and M2 are somewhat smaller than the narrowest conductive track (typically 0.8 mm) which can be achieved on the DBC, DBA and AMB substrates. The small flexible PCB (shown in Figures 13 and 14) consisting of conductive layer 601, on one side, insulating layer 60, in the middle, and another conductive layer 602, on the other side, is used to interconnect the gate pad of the low side MOSFET chip M2, to the conductive track 203, of the ceramic-insulated substrate. The size of the conductive layer 601, typically 0.3 to 0.7 mm by 0.4 to 1.0 mm, is similar to the size of the gate pad of M2, and the size of the conductive layer 602, is matched to that of the conductive track 203, of the ceramic-insulated substrate. The conductive via 603 electrically connecting the conductive layers 601 and 602, may be 0.1 to 0.4 mm in diameter. The conductive layers 601 and 602, are normally made of 0.035 to 0.1 mm thick copper, and the insulating layer 60 may be made of 0.015 to 0.1 mm thick polyimide or other polymer which has high insulating strength and can withstand the processing temperatures to assemble the power semiconductor modules. Such a small flexible PCB can be readily and cost-effectively produced with known well-established and mature PCB manufacturing technology. In addition, the metallic spacer 61, should have a thickness equal to or very close to the total thickness of the three layers 601, 60 and 602, of the small flexible PCB. This metallic spacer may be made of pure copper, pure aluminium, copper- molybdenum alloy, copper-tungsten alloy, or other pure metals or alloys with similar thermal, electrical and thermomechanical properties. The three smaller insulated substrates consisting of conductive tracks 301, 31 and 32 or 401, 41 and 42 and insulating layer 30 or 40, or conductive tracks 501 to 503 and 51 and insulating layer 50 may also be standard / conventional DBC, DBA or ABM substrates with similar thicknesses of the different layers as those in the above ceramic-insulated substrates. Alternatively, these three substrates may be standard / conventional insulated metal substrates (IMSs). In this case, the insulating layers 30, 40 or 50, may be 0.05 to 0.25 mm thick resin compound, or other organic-based materials with high insulating strength and high thermal conductivity. The conductive layers on the two sides of the insulating layers are in general pure copper, pure aluminium, copper alloy, aluminium alloy, or other pure metals or alloys with similar thermal, electrical and thermomechanical properties, may have the same or different thicknesses in the range of 0.05 mm to several mm. All of the joints, A1 and A3 to A9, used to bond the high side device M1, the decoupling capacitor Cd, and the three smaller insulated substrates on the conductive tracks 201 and 202, of the ceramic-insulated substrate, and A21 to A24, used to bond the small flexible PCB and metallic spacer 61, between the low side device M2, and the conductive tracks 203 and 202, of the ceramic-insulated substrate may be formed with lead-free solder alloys, such as tin-silver, tin-copper, tin-silver-copper, tin-antimony, bismuth-silver solder alloys. Alternatively, they can be formed with sintering technologies, such as silver sintering and copper sintering technologies. Their thicknesses are typically 0.05 to 0.2 mm. The four groups of wire bonds 1 to 4, and three wire bonds 5 to 7, used to achieve the interconnections between the high and low side devices M1 and M2, and the corresponding conductive tracks of the three smaller insulated substrates may be made of ultrasonically bonded aluminium wires, silver wires and copper wires with diameters of 0.1 to 0.5 mm. They are preferably made of aluminium wires which can ultrasonically bonded on the chips with the metallization system and bonding parameters which are better developed and established than those for bonding the silver and copper wires while having sufficient ability of carrying high currents because two groups of wire bonds are bonded on each SiC MOSFET chip. The wire bonds may be replaced with or otherwise comprise conductive clips or conductive spacers, along with an additional a top layer substrate to provide the topside interconnections of the power semiconductor chips and / or double sided cooling of the module. In this case, the costs of the modules may be higher than that of module 100, but the cooling performance of the modules may be improved. All the power terminals 11 to 13, and control terminals 14 to 19, may be made of pure metal such as pure copper and pure aluminium, or alloy such as copper-molybdenum alloy and copper-tungsten alloy, or metal-matrix composite such as copper-graphite composite and aluminium-carbon fibre composite, or other materials with high thermal conductivity and high electrical conductivity. Preferably, the terminals are made of the materials with coefficients of thermal expansion (CTEs) matched or close to those of the substrates and / or semiconductor power chips. They can be bonded on the corresponding conductive tracks of the ceramic-insulated substrate and the three smaller insulated substrates with solder alloys or sintering technologies the same as those to form the aforementioned joints A1, A3 to A9 and A21 to A24. Alternatively, they can be bonded on the conductive tracks of the substrates with ultrasonic welding technology or laser welding technology. In the case of using ultrasonic welding technology, they are preferably made of metals or alloys such as pure copper, pure aluminium, copper alloy or aluminium alloy with sufficient strength and good ductility, and the footprint of the substrates may need to be somewhat increased for having sufficiently large conductive tracks to facilitate the ultrasonic welding process. The lead-free solder joints to bond the high and low side devices M1 and M2, the decoupling capacitor Cd, the small flexible PCB, the three smaller insulated substrates, and all the terminals 11 to 19 are preferred for low cost applications where the junction temperatures of the semiconductor chips are in general lower than 150 °C. The sintered silver or copper joints to bond the high and low side devices M1 and M2, the decoupling capacitor Cd, the small flexible PCB, the three smaller insulated substrates, and all the terminals 11 to 19 are preferred for high temperature and high reliability applications where the junction temperatures of the semiconductor chips may be higher than 150 °C. It will be understood that all these joints can be made with the same solder alloy or several solder alloys with different melting points, or combined sintering technology and solder alloys. The power semiconductor module 100 described above and shown in Figures 1 to 5 can be used as the basic building brick to construct single phase and multiple phase half bridge switches for handling similar or higher currents. Figure 19 shows a circuit diagram two power semiconductor modules 100 which are placed together to construct an exemplary H-bridge module, where the two DC+ terminals 11 and the two DC- terminals 12 of the two power semiconductor modules 100 can be connected together via external connections. Figures 20 to 26 schematically illustrate an exemplary H-bridge module constructed with two power semiconductor modules 100 as shown in Figures 1 to 5. In this H-bridge module, each of the two half bridges consists of only one power semiconductor module 100. In the H-bridge module shown in Figures 20 to 23, the conductive back plates 21, of the ceramic-insulated substrates of the two power semiconductor modules 100 are bonded on a common cold plate 72, with two joints B21 (not shown in any figure) and B22 (shown in Figure 26), which may be made using solder alloys or sintering technologies as described above with reference to bonding the high and low side devices M1 and M2, the decoupling capacitor Cd, the small flexible PCB, the three smaller insulated substrates, and all the terminals 11 to 19. The cold plate 72, is integrated with cooling-enhanced pin fins 720s, four holes 721 to 724, which are used to install the coolant manifold with screws / nuts and sealing rings for forming coolant channels and inlet / outlet connectors, and two holes 725 and 726, which are used to mount the plastic frame 82, with screws 921 and 922, and sealing adhesive applied between the frame 82 and the cold plate 72. The cold plate may be replaced with any other thermal management device, such as a heat sink. The plastic frame 82, is mounted on the cold plate 72, where the two extrudes 821 and 822 are used to hold the two screws 921 and 922. Another two extrudes with holes 823 and 824 of the plastic frame 82 can be used to support and install power PCB and drive / control PCB of the H-bridge module. The plastic frame 82, can also be used as a housing / fixture for potting compound encapsulant 92. One of the two holes 825 and 826 on the plastic frame 82, can be used as the inlet for potting the compound encapsulant 92, and the other hole can be used as the outlet for releasing air. A cut-out 827, and nine grooves G21 to G29, on the plastic frame are preferably formed to increase the creepage distances between the different power and control terminals of the H-bridge module. The cut-out 827 and grooves G21 to G29 may be 1 to 10 mm in width and 0.5 to 3 mm in depth. Potting compound is used as the encapsulant 92 to provide both good insulation and additional mechanical support to all of the high and low side devices M1 and M2, the decoupling capacitor Cd and all the terminals 11 to 19 and thus improve the strength and thermo-mechanical reliability of the H-bridge module. In particular, it is important to use sufficiently hard potting compound, rather than soft silicone gel, as the encapsulant 92 to ensure sufficient thermo-mechanical reliability of the H-bridge module where all the power and control terminals 11 to 19 are bonded on the conductive tracks with solder alloys or sintering technologies. The potting compound may be epoxy, other polymer based materials, or inorganic materials with high insulating strength and curing temperatures at least 20°C lower than the lowest melting point of the solder alloys used to bond the semiconductor chips, decoupling capacitors, substrates and terminals. Preferably, a polymer-based potting compound may contain fillers such as silica, aluminium nitride or boron nitride fillers having high thermal conductivity and low CTEs to improve the thermal conductivity and constrain the GTE of the potting compound. In devices comprising a plurality of the semiconductor modules, the potting compound encapsulant may be applied to all of the modules together, or may be applied on each module independently, i.e. such that each module is encapsulated separately. In this case, the modules may not be bonded on a cold plate or heat sink with solder alloys or sintering technologies, but instead mounted on the cold plate or the heat sink with via a layer of thermal interface material (TIM). Alternatively, the exposed surfaces of the substrates in the modules may be used as the cooling surfaces, and the modules may be mounted with sealing rings on the cold plate or heat sinks which can deliver the coolant to the cooling surfaces directly. Figures 27 to 33 schematically illustrate an exemplary three-phase half bridge module constructed with nine power semiconductor modules 100 as shown in Figures 1 to 5. In this three-phase half bridge module, each of the two half bridges consists of three power semiconductor modules 100. In the three-phase half bridge module shown in Figures 27 to 30, the conductive back plates 21, of the nine ceramic-insulated substrates of the nine power semiconductor modules 100 are bonded on a common cold plate 73, with nine joints B31 to B39 (only B39 is shown in Figure 33), which may be made using solder alloys or sintering technologies as described above with reference to bonding the high and low side devices M1 and M2, the decoupling capacitor Cd, the small flexible PCB, the three smaller insulated substrates, and all the terminals 11 to 19. The cold plate 73, is integrated with cooling-enhanced pin fins 730s, six holes 731 to 736, which are used to install coolant manifold with screws / nuts and sealing ring for forming coolant channels and inlet / outlet connectors, and two holes 737 and 738, which are used to mount the plastic frame 83, with screws 931 and 932, and sealing adhesive applied between the frame 83 and the cold plate 73. The plastic frame 83, is mounted on the cold plate 73, where the two extrudes 831 and 832 are used to hold the two screws 931 and 932. Another six extrudes with holes 833 to 838, of the plastic frame 83 can be used to support and install power PCB and drive / control PCB of the three-phase half bridge module. The plastic frame 83, can also be used as a housing / fixture for potting compound encapsulant 93. One of the two holes 839 and 840, on the plastic frame 83, can be used as the inlet for potting the compound encapsulant 93, and the other hole can be used as the outlet for releasing air. A cut-out 841, and ten grooves G31 to G40, on the plastic frame 83 are preferably formed to increase the creepage distances between the different power and control terminals of the three-phase half bridge module. The cut-out 841 and grooves G31 to G40 may be 1 to 10 mm in width and 0.5 to 3 mm in depth. As in the previously described exemplary H-bridge module, potting compound, is used as the encapsulant 93 to provide both good insulation and additional mechanical support to all of the high and low side devices M1 and M2, the decoupling capacitor Cd and all the terminals 11 to 19 and thus improve the strength and thermo-mechanical reliability of the three-phase half bridge module. The potting compound may also be epoxy, other polymer based materials, or inorganic materials with high insulating strength and curing temperatures at least 20°C lower than the lowest melting point of the solder alloys used to bond the semiconductor chips, decoupling capacitors, substrates and terminals. Preferably, a polymer-based potting compound may contain fillers such as silica, aluminium nitride or boron nitride fillers having high thermal conductivity and low CTEs to improve the thermal conductivity and constrain the CTE of the potting compound. In both the exemplary H-bridge module and three-phase half bridge module, all the power terminals can be connected to a power PCB, and all the control terminals can be connected to a drive / control PCB with soldering or welding technologies. All the necessary connections between the paralleled power terminals and control terminals for implementing the topology of the H-bridge switch or the three-phase half bridge switches can be realized with the conductive traces in the power and drive / control PCBs, and these PCBs can be made with the mature and cost-effective PCB materials and manufacturing processes / technologies. In both the exemplary H-bridge module and three-phase half bridge module, the pin fin cold plates 72 and 73, are preferably made of pure aluminium or aluminium alloy with light weight and low cost. They can also be made of other pure metal such as pure copper, or alloy such as copper-molybdenum alloy and copper-tungsten alloy, or metalmatrix composite such as copper-graphite composite, aluminium-silicon carbide composite and aluminium-carbon fibre composite, or other materials with high thermal conductivity. The pin fins in the cold plates may be replaced by other cooling-enhanced features. It will be understood that the cold plates may be replaced by heat sinks or coolers with integrated cold plates, cooling-enhance features, coolant channels, and inlet / outlet connectors. Additionally, it will be understood that the conductive back plates 21, of the ceramic-insulated substrates in all the power semiconductor modules 100 can be used as the cooling surface of the modules. In this case, the joints B21 and B22 or B31 to B39, used to bond all the conductive back plates 21 on the common cold plates 72 or 73, can be eliminated. The cold plates 72 or 73, may be replaced by frames or other heat sinks or coolers which can offer the direct cooling to the conductive back plates. Figure 34 schematically illustrates processing steps of a method for manufacturing a power module (e.g., the power semiconductor module 100). At step S1, a multi-layer substrate is provided. The multi-layer substrate comprises a first insulating layer (e.g. 20), a first conductive layer arranged on a surface of the first insulating layer, the first conductive layer comprising first, second and third conductive tracks (e.g. 201, 202, 203) spaced apart from one another. The multi-layer substrate further comprises a plurality of second insulating layers (e.g. 30, 40) arranged on the first and second conductive tracks of the first conductive layer. The multi-layer substrate further comprises a plurality of second conductive layers (e.g. 301, 401) each arranged on one of the plurality of second insulating layers. At step S2, a first and second semiconductor die (e.g. M1, M2) is attached to the first conductive layer of the substrate. In particular, the first second semiconductor die is attached to the first conductive track of the first conductive layer and the second semiconductor die is attached to the second track of the first conductive layer. At step S3 first and second power terminals (e.g. 11, 12) are attached to the first conductive layer of the substrate. In particular, the first power terminal is attached to the first conductive track of the first conductive layer and second power terminal is attached to the second conductive track of the first conductive layer. At step S4 an output terminal (e.g. 13) is attached to the plurality of second conductive layers of the substrate. At step S5 the first and second semiconductor die are electrically connected to the plurality of second conductive layers of the substrate. In particular, a source terminal of the first semiconductor die and a drain terminal of the second semiconductor die are attached to the plurality of second conductive layers of the substrate. It would be appreciated that the steps S2 to S4 may be performed in a temporal order that is different from the order of description. For example, steps S3 and S4 may be performed earlier than or simultaneously with step S2. The terms “having”, “containing”, “including”, “comprising” and the like are open and the terms indicate the presence of stated structures, elements or features but not preclude the presence of additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘top’, ‘bottom’, ‘left’, ‘right’ etc. are made with reference to conceptual illustrations of a power semiconductor module, such as those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a power semiconductor module when in an orientation as shown in the accompanying drawings. Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

1. A power semiconductor module, comprising:a substrate comprising a plurality of layers, the plurality of layers comprising:5 a first insulating layer;a first conductive layer arranged on a surface of the first insulating layer, the first conductive layer comprising first, second and third conductive tracks spaced apart from one another;a plurality of second insulating layers arranged on both the first and 10 second conductive tracks of the first conductive layer; anda plurality of second conductive layers each arranged on a respective one of the plurality of second insulating layers;a first power terminal operatively connected to the first conductive track of the first conductive layer;15 a second power terminal operatively connected to the second conductive trackC\l of the first conductive layer;an output terminal operatively connected to the plurality of second conductive layers; andQQ a half bridge switch comprising:20 a high side device, the high side device arranged on the first conductivetrack of the first conductive layer, wherein a drain terminal of the high side device is operatively connected to the first conductive track of the first conductive layer; anda low side device, the low side device arranged on the second 25 conductive track of the first conductive layer, wherein a gate terminal of the lowside device is operatively connected to the third conductive track of the first conductive layer and a source terminal of the low side device is operatively connected to the second conductive track of the first conductive layer; and wherein:30 a source terminal of the high side device and a drain terminal of the low sidedevice are operatively connected to the plurality of second conductive layers.

2. The power semiconductor module of claim 1 wherein the substrate further comprises:a third insulating layer arranged on the first conductive track of the first conductive layer; anda third conductive layer arranged on the surface of the third insulating layer, the third conductive layer comprising a plurality of conductive tracks spaced apart from one another;wherein the source terminal and a gate terminal of the high side device are operatively connected to the plurality of conductive tracks of the third conductive layer.1015203. The power semiconductor module of claim 2 further comprising a plurality of control terminals operatively connected to the conductive tracks of the third conductive layer.

4. The power semiconductor module of claim 3 wherein at least one of the plurality of control terminals, the first and second power terminals and the output terminal extend in a substantially perpendicular direction with respect to the first insulating layer of the substrate.

5. The power semiconductor module of claim 4 wherein the plurality of control terminals, the first and second power terminals and the output terminal extend in a substantially perpendicular direction with respect to the first insulating layer of the substrate.

6. The power semiconductor module of claim 4 or claim 5 wherein at least one of the plurality of control terminals, the first and second power terminals and the output 25 terminal comprise a material with a coefficient of thermal expansion which matches the coefficients of thermal expansion of a material forming the plurality of layers.

7. The power semiconductor module of any preceding claim further comprising a plurality of wire bonds operatively connecting the source terminal of the high side 30 device and the drain terminal of the low side device to the plurality of second conductive layers.

8. The power semiconductor module of any preceding claim further comprising a capacitor operatively connected in series between the first and second conductive 35 tracks of the first conductive layer.

9. The power semiconductor module of any preceding claim further comprising a diode operatively connected in an anti-parallel configuration with at least one of the high side device and the low side device.

510. The power semiconductor module of any preceding claim further comprising:a conductive spacer operatively connected between a source terminal of the low side device and the second conductive track of the first conductive layer; and10 a printed circuit board operatively connected between the gate terminalof the low side device and the third conductive track of the first conductive layer; wherein a thickness of the conductive spacer and a thickness of the printed circuit board are substantially equal.15 11. The power semiconductor module of any preceding claim wherein at least oneof the layers comprises an electrically insulating and thermally conductive material.

12. The power semiconductor module of any preceding claim, further comprising an20 encapsulant encapsulating the high side device and the low side device.

13. The power semiconductor module of claim 12 wherein the encapsulant comprises a moulding compound.25 14. The power semiconductor module of claim 13 wherein the moulding compoundcomprises thermally conductive fillers.

15. The power semiconductor module of any preceding claim further comprising a fourth conductive layer arranged on a further surface of the first insulating layer.3016. The power semiconductor module of claim 15 wherein the further surface is anopposite surface to the surface on which the first conductive layer is arranged.

17. The power semiconductor module of any preceding claim further comprising a thermal management device, wherein the first insulating layer is operatively connected to the thermal management device.5 18. The power semiconductor module of claim 15 wherein the thermal managementdevice is a heat sink or a cold plate.

19. A power semiconductor system comprising a plurality of power semiconductor modules as defined in any one of claims 1 to 18.1020. The power semiconductor system of claim 19 wherein the plurality of power semiconductor modules comprise a common baseplate attached to their respective first insulating layers.15 21. An electric vehicle comprising the power semiconductor system of claim 19 orclaim 20.CMCM 22. A hybrid electric vehicle comprising a power semiconductor system of claim 19or claim 20.CO 2023. A method of manufacturing the power semiconductor module comprising: providing a substrate, wherein providing the substrate comprises:forming a first insulating layer;forming a first conductive layer on a surface of the first insulating layer, 25 the first conductive layer comprising first, second and third conductive tracks spaced apart from one another;forming a plurality of second insulating layers on both the first and second conductive tracks of the first conductive layer;forming a plurality second conductive layers each arranged on a 30 respective one of the plurality of second insulating layers;attaching a first power terminal to the first conductive track of the first conductive layer;attaching a second power terminal to the second conductive track of the first conductive layer;35 attaching an output terminal to the plurality of second conductive layers;03 12 24attaching a drain terminal of a high side device to the first conductive track of the first conductive layer;attaching a source terminal of a low side device to the second conductive track of the first conductive layer and a gate terminal of the low side device to the third 5 conductive track of the first conductive layer; andelectrically connecting a source terminal of the high side device and a drain terminal of the low side device to the plurality of second conductive layers, wherein the high side device and the low side device form a half bridge switch.10 24. The method of claim 23 wherein providing the substrate further comprises:forming a third insulating layer on the first conductive track of the first conductive layer; andforming a third conductive layer on the surface of the third insulating layer, the third conductive layer comprising a plurality of conductive tracks spaced apart from one 15 another;wherein the method further comprises electrically connecting the drain terminal of the high side device and a gate terminal of the high side device to the plurality of conductive tracks of the third conductive layer.20 25. The method of claim 23 or claim 24 further comprising encapsulating the highside device and the low side device with an encapsulant.

Images