Wiring substrate, backplane and electronic apparatus

Abstract

The present disclosure relates to the technical field of display, in particular to a wiring substrate, a backplane and an electronic apparatus. In order to provide more electronic element fixing modes

Description

Wiring substrate, backplane and electronic device

[0001] This application claims priority to Chinese patent application No. 202210663553.X filed on June 13, 2022, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a wiring substrate, a backplane, and an electronic device. Background Art

[0003] Mini Light-Emitting Diode (Mini LED), whose size is approximately less than 500μm, has a significant increase in its use in the display field due to its smaller size, ultra-high brightness, and long life.

[0004] Invention Disclosure

[0005] In one aspect, a wiring substrate is provided, comprising: a substrate, a plurality of connecting traces disposed on one side of the substrate, and a pad group. Among the plurality of connecting traces disposed on one side of the substrate, at least one of the plurality of connecting traces includes a first connecting end, and at least another connecting trace includes a second connecting end, with the first connecting end and the second connecting end being disposed opposite each other. The pad group is located in the region where the first connecting end and the second connecting end are located, and the pad group includes at least one first sub-pad and at least two second sub-pads; the at least one first sub-pad is located in the region where the first connecting end is located, and the at least two second sub-pads are located in the region where the second connecting end is located, and the at least one first sub-pad and the at least two second sub-pads are disposed spaced apart from each other.

[0006] One of the at least one first sub-pad is adjacent to one of the at least two second sub-pads along the first direction, and the first sub-pad is adjacent to another of the at least two second sub-pads in the second direction; the first direction intersects the second direction.

[0007] In some embodiments, each of the at least one first sub-pad is adjacent to two of the at least two second sub-pads in the first direction and the second direction, respectively.

[0008] In some embodiments, the first sub-pad and the second sub-pad adjacently disposed in the first direction are separated by a first distance, and the first sub-pad and the second sub-pad adjacently disposed in the second direction are separated by a second distance, and the first distance is 0.9 to 1.1 times the second distance.

[0009] In some embodiments, the number of the at least one first sub-pad is N, the number of the at least two second sub-pads is M, N and M are positive integers, N≥1, N=M-1.

[0010] In some embodiments, the substrate is a parallelogram, and the first direction is parallel to a longer side of the substrate.

[0011] In some embodiments, edges of the first connection end and the second connection end adjacent to each other have the same shape.

[0012] In some embodiments, edges of the first connection end and the second connection end adjacent to each other have a stepped structure.

[0013] In some embodiments, any first sub-pad among the at least one first sub-pad is not adjacent to any other first sub-pad among the at least one first sub-pad in the first direction and / or the second direction.

[0014] In some embodiments, any second sub-pad among the at least two second sub-pads is not adjacent to any other second sub-pad among the at least two second sub-pads in the first direction and / or the second direction.

[0015] In some embodiments, each of the multiple connecting lines includes a main body, and among the two connecting lines with the first connecting end and the second connecting end arranged opposite to each other, the main body of one connecting line extends along the first direction, and the main body of the other connecting line extends along the second direction.

[0016] In some embodiments, a passivation layer is provided on the side of the multiple pad groups away from the substrate, and a plurality of openings are provided on the passivation layer, and the orthographic projection of each of the multiple openings on the substrate overlaps with the orthographic projection of a first sub-pad or a second sub-pad in the pad group on the substrate.

[0017] In another aspect, a backplane is provided, comprising: a wiring substrate according to any of the above embodiments; and a plurality of electronic components. The plurality of electronic components are disposed on one side of a pad group of the wiring substrate, and the electronic components are connected to at least one first sub-pad and one second sub-pad of the pad group that are adjacently disposed along a first direction or a second direction.

[0018] In some embodiments, the plurality of electronic components includes at least two electronic components, one of the at least two electronic components is electrically connected to a first sub-pad and a second sub-pad in the pad group arranged along a first direction, and the other of the at least two electronic components is electrically connected to a first sub-pad and a second sub-pad in the pad group arranged along a second direction.

[0019] In some embodiments, among the multiple electronic components, the number of electronic components electrically connected to the first sub-pad and the second sub-pad arranged along the second direction in the pad group is greater than the number of electronic components electrically connected to the first sub-pad and the second sub-pad arranged along the first direction in the pad group.

[0020] In some embodiments, the plurality of pad groups include a passivation layer having a plurality of openings disposed therein, the plurality of electronic components being disposed on a side of the passivation layer away from the substrate, and the electrodes of each electronic component being electrically connected to the pad group through the openings. The backplane further includes a protective adhesive layer disposed on a side of the plurality of electronic components away from the wiring substrate. The protective adhesive layer fills gaps between adjacent electronic components and any openings not covered by the electronic components.

[0021] In yet another aspect, an electronic device includes the back panel according to any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0023] FIG1 is a structural diagram of a display device provided by some embodiments of the present disclosure;

[0024] FIG2 is a structural diagram of a backplane provided by some embodiments of the present disclosure;

[0025] FIG3 is a cross-sectional view taken along the AA direction in FIG2 ;

[0026] FIG4 is a diagram illustrating an arrangement of a wiring substrate on a motherboard according to some embodiments of the present disclosure;

[0027] FIG5 is another arrangement diagram of a wiring substrate on a motherboard provided by some embodiments of the present disclosure;

[0028] FIG6 is a structural diagram of a wiring substrate provided by some embodiments of the present disclosure;

[0029] FIG7 is an enlarged view of area C in FIG6 ;

[0030] FIG8 is a structural diagram of a local area of ​​a circuit layer provided by some embodiments of the present disclosure;

[0031] FIG9 is a structural diagram of another wiring substrate provided by some embodiments of the present disclosure;

[0032] FIG10 is an enlarged view of area D in FIG9 ;

[0033] FIG11 is a structural diagram of a local area of ​​another circuit layer provided by some embodiments of the present disclosure;

[0034] FIG12 is a structural diagram of a local area of ​​another circuit layer provided by some embodiments of the present disclosure;

[0035] FIG13 is a structural diagram of a first connection end and a second connection end provided by some embodiments of the present disclosure;

[0036] FIG14 is a structural diagram of another first connection end and a second connection end provided in some embodiments of the present disclosure;

[0037] FIG15 is a structural diagram of another first connection end and a second connection end provided by some embodiments of the present disclosure;

[0038] FIG16 is a structural diagram of another electronic device provided by some embodiments of the present disclosure;

[0039] FIG17 is an enlarged view of the chip area G in FIG16 ;

[0040] FIG18 is a structural diagram of a connection wiring of a functional area provided by some embodiments of the present disclosure;

[0041] FIG19 is a structural diagram of another connection wiring of functional areas provided by some embodiments of the present disclosure;

[0042] FIG20 is a structural diagram of another backplane provided by some embodiments of the present disclosure;

[0043] FIG21 is a cross-sectional view taken along the EE direction in FIG20 ;

[0044] FIG22 is a structural diagram of another backplane provided by some embodiments of the present disclosure;

[0045] FIG23 is a structural diagram of another backplane provided by some embodiments of the present disclosure;

[0046] FIG24 is a structural diagram of another backplane provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0047] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0048] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0049] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0050] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0051] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0052] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0053] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0054] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0055] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0056] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0057] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0058] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0059] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0060] Some embodiments of the present disclosure provide an electronic device, which is an electronic device including a wiring substrate and a plurality of electronic components, wherein the electronic components are electrically connected and fixed to the wiring substrate by soldering.

[0061] In some examples, the electronic device may be a display device using a liquid crystal display, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, or any other product or component with a display function. For example, the electronic device 2000 shown in FIG1 is a mobile phone using a liquid crystal display 1000.

[0062] In some embodiments, the electronic device may include a backplane and a housing fixed to the backplane. As shown in FIG2 , the backplane 1100 includes a wiring substrate 100 and a plurality of electronic components 200 disposed on the wiring substrate 100 .

[0063] As shown in Figures 2 and 3, where Figure 3 is a cross-sectional view taken along line AA in Figure 2, the backplane 1100 includes a wiring substrate 100 and electronic components 200 such as an integrated circuit (IC) chip, capacitors, resistors, inductors, sensors, and micro-LEDs mounted on the wiring substrate 100.

[0064] In some embodiments, as shown in FIG3 , the wiring substrate 100 includes a substrate 10, a circuit layer 20, and an insulating layer 30 stacked in sequence. The substrate 10 may be any one of a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a semiconductor substrate such as a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate such as silicon germanium, or an SOI (Silicon On Insulator) substrate. The substrate 10 may also include an organic resin material such as epoxy, triazine, silicone, or polyimide. In some examples, the substrate 10 may be an FR4-type printed circuit board (PCB), or may be a flexible PCB that is easily deformable. In some examples, the substrate 10 may include a ceramic material such as silicon nitride, AlN, or Al2O3, or a metal or metal compound, or a metal core printed circuit board (MCPCB) or a metal copper clad laminate (MCCL). The circuit layer 20 includes traces for transmitting electrical signals. An opening 40 is provided on the insulating layer 30. The opening 40 exposes at least part of the end of the trace to serve as a solder pad to be bound and connected to the electronic component 200. The insulating layer 30 is used to isolate the traces in the circuit layer 20 that have no electrical connection relationship, and to protect the surface of the traces located away from the substrate 10.

[0065] In some examples, the wiring substrate 100 may have a quadrilateral structure, with a plurality of electronic components 200 arranged in an array on the wiring substrate 100, wherein the electronic components 200 may be micro-light-emitting diodes. The wiring layer of the wiring substrate 100 includes a plurality of connecting traces L. As shown in FIG8 , any of the plurality of connecting traces L includes a main body 21 and a connecting end D. The main body 21 is used to ensure that the electrical performance of the connecting trace L, such as signal transmission speed and power consumption, meets design requirements. The line width of the main body 21 is substantially the same throughout. The connecting end D may be the end region of the connecting trace L, and its line width is no greater than that of the main body.

[0066] Among the multiple connecting lines L, there are two connecting lines L that are close to each other, that is, the two connecting lines L respectively include two connecting ends D that are close to each other. Exemplarily, at least one connecting line L among the multiple connecting lines L includes a first connecting end D1, and at least another connecting line L includes a second connecting end D2. The first connecting end D1 and the second connecting end D2 are close to each other, for example, arranged relative to each other.

[0067] Exemplarily, an opening 40 is provided on the insulating layer 30, and the opening 40 exposes at least part of the end of the trace to serve as a pad. The material of the insulating layer 30 includes at least one of silicon oxide, silicon nitride and silicon oxynitride. For example, of two connecting traces L adjacent to each other, one connecting trace L includes a first connecting end D1, and the other connecting trace L includes a second connecting end D2. A portion of the first connecting end D1 is exposed by an opening 40 of the insulating layer 30 to form a first sub-pad 51, and a portion of the second connecting end D2 is exposed by another opening 40 of the insulating layer 30 to form a second sub-pad 52. Accordingly, the orthographic projection of each opening 40 in the plurality of openings 40 on the substrate 10 overlaps with the orthographic projection of a first sub-pad 51 or a second sub-pad 52 in the pad group 50 on the substrate 10. The first sub-pad 51 and the second sub-pad 52 exposed by the adjacent first connecting end D1 and the second connecting end D2 constitute a pad group 50.

[0068] In some embodiments, as shown in FIG. 2 and FIG. 3 , the micro light emitting diode includes a first pin and a second pin, wherein the first pin is electrically connected to the first sub-pad 51 , and the second pin is electrically connected to the second sub-pad 52 .

[0069] In some embodiments, as shown in Figures 4 and 5, a wiring substrate 100 to be connected to multiple micro-LEDs is cut from a motherboard 300. For example, to reduce production costs and improve production efficiency, one implementation method is to provide a motherboard, which can be, for example, a substrate made of glass, quartz, sapphire, or ceramic, or a wafer made of silicon or silicon carbide, or a printed circuit board, a flexible printed circuit board, or a substrate made of metal or a metal compound. Material film formation and patterning are performed on the motherboard, thereby forming a wiring pattern and an insulating layer covering the wiring pattern in each of the multiple regions to be cut to form the multiple wiring substrates.

[0070] Next, the motherboard 300 is cut into multiple wiring substrates 100. Each wiring substrate 100 undergoes a nickel-gold solder pad process, a white oil coating process, and an electronic component bonding process. The wiring substrate 100 with the electronic components bonded thereto is then cut a second time and edge-grinded to form a single-panel SP. For example, as shown in FIG4 , a motherboard 300 can be cut into six wiring substrates 100, each of which can be cut into two single-panel SPs. Alternatively, as shown in FIG5 , a motherboard 300 can be cut into eight wiring substrates 100, each of which can be cut into one single-panel SP. The more single-panel SPs each wiring substrate 100 contains, the higher the efficiency and lower the cost of subsequent processes.

[0071] As shown in Figures 4 and 5 , to highlight the orientation and arrangement of the various structures, only one pad group 50 is enlarged and schematically illustrated. Pad group 50 includes a first sub-pad 51 and a second sub-pad 52 spaced apart from each other. Taking the electronic component as an example, the arrangement and orientation of the micro-LEDs on each single-panel board (SP) are identical. Since the micro-LEDs are die-bonded after the motherboard is cut into a wiring substrate, all pad groups 50 on a wiring substrate 100, including the first sub-pads 51 and second sub-pads 52 arranged in the same orientation, have the same arrangement and orientation. As shown in Figures 4 and 5 , the first sub-pad 51 and the second sub-pad 52 in each pad group 50 are spaced apart along the long side of the wiring substrate 100. Therefore, the long side of the micro-LED to be connected to a pad group 50 extends parallel to the long side of the wiring substrate 100 on which the micro-LED is located.

[0072] During the die bonding process of the wiring substrate 100 using equipment, multiple micro-LEDs are typically bonded at once to improve efficiency. For example, the equipment may include a strip-shaped gantry, which can be used to bond multiple micro-LEDs arranged along a specific direction at a time. Therefore, when the wiring substrate 100 includes multiple micro-LEDs arranged in an array, the gantry must be moved multiple times to bond all of the micro-LEDs. However, this movement inevitably results in errors. Increased movement reduces the accuracy of the micro-LED bonding, hindering product quality and leading to a decrease in production efficiency.

[0073] In contrast, the most efficient die-bonding method for micro-LEDs on wiring substrate 100 is to arrange the two pins of the micro-LEDs in the same direction as the long side of the wiring substrate 100, and to use a bracket to bond multiple micro-LEDs arranged in a direction parallel to the long side of the wiring substrate 100 (hereinafter referred to as the optimal die-bonding direction T). Die-bonding on wiring substrate 100 along the optimal die-bonding direction T offers the advantages of high die-bonding efficiency and precision.

[0074] In some related technologies, during the film preparation process, the motherboard 300 shown in Figure 4 and the motherboard 300 shown in Figure 5 can share a set of masks to expose various areas, and the arrangement of the wiring substrate 100 and the single-sided board SP needs to be arranged according to the actual distribution of the traces and pads on the motherboard.

[0075] It should be noted that due to the shared mask, the arrangement direction of the first and second sub-pads in the pad group may not be consistent with the long side direction of the wiring substrate 100. In other words, the die-bonding direction of the micro-LEDs during die-bonding may differ from the optimal die-bonding direction T. For example, the arrangement direction of the first and second sub-pads 51 and 52 in the pad group may be parallel to the short side direction of the wiring substrate 100. In this case, each time the bracket is used to bond multiple micro-LEDs arranged in a direction parallel to the short side of the wiring substrate 100, the bracket needs to be moved more times, resulting in reduced efficiency. At the same time, the accumulation of process errors may further lead to a decrease in yield.

[0076] Based on this, on the one hand, some embodiments of the present disclosure provide a wiring substrate, which includes a substrate, a circuit layer and an insulating layer, wherein the arrangement structure of the substrate, the circuit layer and the insulating layer is described in detail in the above embodiments and will not be repeated here.

[0077] As shown in Figures 6, 7, and 8, where Figure 7 is an enlarged view of area C in Figure 6 and Figure 8 is a structural diagram of a portion of the circuit layer 20, the wiring substrate 100 further includes a pad group 50, which includes at least one first sub-pad 51 and at least two second sub-pads 52. The at least one first sub-pad 51 is located in the area where the first connection terminal D1 is located, and the at least two second sub-pads 52 are located in the area where the second connection terminal D2 is located. The at least one first sub-pad 51 and the at least two second sub-pads 52 are spaced apart from each other.

[0078] As shown in Figures 7 and 8, in a pad group 50, one first sub-pad 51 of at least one first sub-pad 51 is adjacent to one second sub-pad 52 of at least two second sub-pads 52 along the first direction X, and the first sub-pad 51 is adjacent to another second sub-pad 52 of the at least two second sub-pads 52 in the second direction Y, wherein the first direction X intersects the second direction Y.

[0079] In some examples, a plurality of pad groups 50 are arranged in an array on the wiring substrate 100. Each pad group 50 may include at least one first sub-pad 51 and at least two second sub-pads 52. The at least one first sub-pad 51 is located in the region where the first connection terminal D1 is located. That is, the region where the insulating layer 30 covers the first connection terminal D1 is provided with at least one opening 40. The portion of the first connection terminal D1 exposed by each opening 40 constitutes a first sub-pad 51. The at least two second sub-pads 52 are located in the region where the second connection terminal D2 is located. That is, the region where the insulating layer 30 covers the second connection terminal D2 is provided with at least two openings 40. The portion of the second connection terminal D2 exposed by each opening constitutes a second sub-pad 52. Any first sub-pad 51 of the at least one first sub-pad 51 has one of the at least two second sub-pads 52 arranged in the first direction X, and the other of the at least two second sub-pads 52 arranged in the second direction Y.

[0080] It should be noted that "covering" in this disclosure means that the orthographic projections of two components on the substrate overlap. The two components may be in direct contact or isolated from each other. For example, "covering" in the context of the insulating layer 30 covering the first connection terminal D1 means that the orthographic projection of the insulating layer 30 on the substrate overlaps with the orthographic projection of the first connection terminal D1 on the substrate.

[0081] The first sub-pad 51 and the second sub-pad 52 are arranged in the first direction X, and the first sub-pad 51 and the other second sub-pad 52 are arranged in the second direction Y. Therefore, an electronic component with two pins provided on the wiring substrate can be electrically connected to the first sub-pad 51 and the second sub-pad 52 arranged in the first direction X, or can be electrically connected to the first sub-pad 51 and the second sub-pad 52 arranged in the second direction Y. In this way, one of the two directions can be selected for arranging electronic components. The first direction X and the second direction Y intersect.

[0082] 8 , a pad group 50 includes a first sub-pad 51 located in the region where the first connection terminal D1 is located, and two second sub-pads 52 located in the region where the second connection terminal D2 is located. The first sub-pad 51 and the one second sub-pad 52 are arranged in the first direction X, and the first sub-pad 51 and the other second sub-pad 52 are arranged in the second direction Y.

[0083] For example, a micro-LED is an electronic component with two pins disposed on a wiring substrate. The first pin of the micro-LED is electrically connected to a first sub-pad 51, and the second pin of the micro-LED is electrically connected to a second sub-pad 52. Thus, the micro-LEDs are arranged along a first direction X, i.e., the die-bonding direction of the micro-LEDs is the same as the first direction X. The second pin of the micro-LED is electrically connected to another second sub-pad 52. Thus, the micro-LEDs are arranged along a second direction Y, i.e., the die-bonding direction of the micro-LEDs is the same as the second direction Y. The first direction X and the second direction Y may be orthogonal.

[0084] In some embodiments, as shown in FIG. 8 and FIG. 11 , each of the at least one first sub-pad 51 and two of the at least two second sub-pads 52 are adjacently disposed in the first direction X and the second direction Y, respectively.

[0085] For example, if a first sub-pad 51 or a second sub-pad 52 in a pad group 50 is damaged or falls off, it is impossible to form an electrical connection with the corresponding electronic component. Therefore, a pad group 50 may also include two or more first sub-pads 51, and two or more second sub-pads 52. For example, each first sub-pad 51 is arranged adjacent to a second sub-pad 52 in the first direction X, and is arranged adjacent to another second sub-pad 52 in the second direction Y. For example, a pad group 50 shown in Figure 11 includes two first sub-pads 51. The first first sub-pad 51' is arranged with a second sub-pad 52 in the first direction X and the second direction Y, and the second first sub-pad 51" is arranged with a second sub-pad 52 in the first direction X and the second direction Y.

[0086] 8 , 11 and 12 , the number of the at least one first sub-pad 51 is N, the number of the at least two second sub-pads 52 is M, N and M are positive integers, N≥1. In some embodiments, N=M−1.

[0087] In some examples, the number of at least one first sub-pad 51 in a pad group 50 can be 1, 2, or 3. FIG8 shows one first sub-pad 51 and two second sub-pads 52: a first second sub-pad 52' and a second second sub-pad 52", wherein the first sub-pad 51 and the second second sub-pad 52" are arranged in the first direction X, and the first sub-pad 51 and the first second sub-pad 52' are arranged in the second direction Y.

[0088] In other examples, as shown in Figure 11, when there are two first sub-pads 51, the two first sub-pads 51 are: a first first sub-pad 51' and a second first sub-pad 51", and accordingly, there are three second sub-pads 52: a first second sub-pad 52', a second second sub-pad 52", and a third second sub-pad 52'". The first first sub-pad 51' and the first second sub-pad 52' are arranged in the second direction Y, and the first first sub-pad 51' and the second second sub-pad 52" are arranged in the first direction X; the second first sub-pad 51" and the third second sub-pad 52' are arranged in the first direction X, and the second first sub-pad 51" and the second second sub-pad 52" are arranged in the second direction Y.

[0089] In some other examples, as shown in FIG12 , when there are three first sub-pads 51, the three first sub-pads 51 are: a first first sub-pad 51', a second first sub-pad 51", and a third first sub-pad 51'"; accordingly, there are four second sub-pads 52: a first second sub-pad 52', a second second sub-pad 52", a third second sub-pad 52'" and a fourth second sub-pad 52". Among them, the first first sub-pad 51' and the first second sub-pad 52' are arranged in the second direction Y, and the first first sub-pad 51' and the second second sub-pad 52" are arranged in the first direction X; the second first sub-pad 51" and the third second sub-pad 52"' are arranged in the first direction X, and the second first sub-pad 51" and the second second sub-pad 52" are arranged in the second direction Y; the third first sub-pad 51"' and the fourth second sub-pad 52"" are arranged in the first direction X, and the third first sub-pad 51"' and the third second sub-pad 52"' are arranged in the second direction Y.

[0090] In some embodiments, as shown in Figures 7, 9, and 10, the first sub-pad 51 and the second sub-pad 52 adjacently disposed in the first direction X are separated by a first distance X1, and the first sub-pad 51 and the second sub-pad 52 adjacently disposed in the second direction Y are separated by a second distance X2, and the first distance X1 is 0.9 to 1.1 times the second distance X2. The first distance X1 refers to the closest distance between the edges of the first sub-pad 51 and the second sub-pad, in the first direction X, of the adjacent first sub-pad 51 and the second sub-pad 52. The second distance X2 refers to the closest distance between the edges of the first sub-pad 51 and the second sub-pad, in the second direction Y, of the adjacent first sub-pad 51 and the second sub-pad 52.

[0091] In some examples, the electrodes of the electronic components are electrically connected to the first sub-pad 51 and the second sub-pad 52 in the first direction X, or to the first sub-pad 51 and the second sub-pad 52 in the second direction Y. The first sub-pad 51 and the second sub-pad 52 in the first direction X and the first sub-pad 51 and the second sub-pad 52 in the second direction Y are connected to the same type of electronic components. When the distance between the electrodes of the electronic components remains stable, the first distance X1 and the second distance X2 should remain the same or substantially the same to ensure that the electrodes of the same type of electronic components are accurately connected to the corresponding pads when the arrangement direction is changed. In actual processes, there is a certain deviation in the positions of the first sub-pad 51 and the second sub-pad 52, that is, the first distance X1 is 0.9 to 1.1 times the second distance X2, for example, the first distance X1 is 0.9 times the second distance X2, the first distance X1 is 1.0 times the second distance X2, or the first distance X1 is 1.1 times the second distance X2.

[0092] It should be noted that when there is a deviation of 0.9 to 1.1 times between the first distance X1 and the second distance X2 , the electrodes of the electronic components provided on the pad group 50 are electrically connected to the corresponding first sub-pads 51 and second sub-pads 52 .

[0093] In some embodiments, as shown in FIG. 13 , FIG. 14 , or FIG. 15 , the edges of the first connection end D1 and the second connection end D2 that are close to each other have the same shape.

[0094] In some examples, the edges of the first connection end D1 and the second connection end D2 that are adjacent to each other have a stepped structure. The edge of the first connection end D1 that is adjacent to the second connection end D2 is a first edge 23. The first edge 23 includes at least one first sub-edge 231 arranged along the first direction X and at least one second sub-edge 232 arranged along the second direction Y. The at least one first sub-edge 231 and the at least one second sub-edge 232 are alternately arranged and sequentially connected.

[0095] The edge of the second connection end D2 adjacent to the first connection end D1 is a second edge 24. The second edge 24 includes at least one third sub-edge 241 arranged along the first direction X and at least one fourth sub-edge 242 arranged along the second direction Y. The at least one third sub-edge 241 and the at least one fourth sub-edge 242 are alternately arranged and connected in sequence.

[0096] In some embodiments, as shown in FIG. 13 , FIG. 14 or FIG. 15 , any first sub-pad 51 of the at least one first sub-pad 51 is not adjacent to other first sub-pads 51 of the at least one first sub-pad 51 in the first direction X and / or the second direction Y.

[0097] Exemplarily, as shown in Figures 11 and 14, the first connection end D1 includes two first sub-pads 51, and the first edge 23 includes two first sub-edges 231 and two second sub-edges 232. The two first sub-edges 231 and the two second sub-edges 232 are alternately arranged in sequence and connected in sequence to form a stepped structure, wherein each first sub-edge 231 and a second sub-edge 232 intersect to form a first corner area Ar1, that is, the two first sub-edges 231 and the two second sub-edges 232 form two first corner areas Ar1, and the two first corner areas Ar1 are arranged along the third direction Z. A first sub-pad 51 is arranged on each first corner area Ar1, that is, the two first sub-pads 51 are arranged along the third direction Z. Therefore, one of the two first sub-pads 51 is not adjacent to the other first sub-pad 51 in the first direction X and / or the second direction Y, wherein the third direction Z intersects with the first direction X and the second direction Y.

[0098] In some embodiments, any second sub-pad 52 of the at least two second sub-pads 52 is not adjacent to the other second sub-pads 52 of the at least two second sub-pads 52 in the first direction X and / or the second direction Y.

[0099] Exemplarily, as shown in Figures 11 and 14, the first connection end D1 includes two first sub-pads 51, and accordingly, the second connection end D2 includes three second sub-pads 52, and the second edge 24 includes three third sub-edges 241 and three fourth sub-edges 242. The three third sub-edges 241 and the three fourth sub-edges 242 are alternately arranged in sequence and connected in sequence to form a stepped structure, wherein a second sub-pad 52 is arranged on the second corner area Ar2 formed by the intersection of each third sub-edge 241 and the fourth sub-edge 242, that is, the three third sub-edges 241 and the three fourth sub-edges 242 form three second corner areas Ar2, and the three second corner areas Ar2 are arranged along the third direction Z. A second sub-pad 52 is arranged on each second corner area Ar2, that is, the three second sub-pads 52 are arranged along the third direction Z. Therefore, one of the three second sub-pads 52 is not adjacent to the other two second sub-pads 52 in the first direction X and / or the second direction Y.

[0100] The first sub-pads 51 and the second sub-pads 52 are arranged along the third direction Z, so that one second sub-pad 52 is arranged with one first sub-pad 51 in the first direction X, and simultaneously arranged with another adjacent first sub-pad 51 in the second direction Y. In other words, one first sub-pad 51 and two second sub-pads 52 allow electronic components to be arranged in either one first direction X or one second direction Y; two first sub-pads 51 and three second sub-pads 52 allow electronic components to be arranged in either one first direction X or two second directions Y; and so on. For every additional first sub-pad 51 and second sub-pad 52, one more position for electronic components to be arranged in the first direction X and one more position for electronic components to be arranged in the second direction Y are added. This arrangement of the first sub-pad 51 and the second sub-pad 52 can achieve that at least one sub-pad in a pad group is shared, so that when the number of sub-pads is constant, the number of first sub-pads 51 and second sub-pads 52 in the pad group arranged in pairs in the first direction X or the second direction Y can be increased as much as possible, which can reduce the complexity of the process and improve the flexibility of the arrangement of electronic components on the wiring substrate.

[0101] In some examples, as shown in FIG23 , a plurality of electronic components 200 are arranged on the wiring substrate 100 along the first direction X or the second direction Y, and the orientation of the plurality of electronic components 200 on the wiring substrate 100 is consistent. If it is necessary to replace one of the electronic components 200, then in the pad group corresponding to the electronic component 200, the first sub-pad and / or the second sub-pad electrically connected to the replaced electronic component 200 are different from the first sub-pad and / or the second sub-pad electrically connected to the electronic component before the replacement. In a pad group, there are at least two first sub-pads and second sub-pads arranged in pairs in the first direction X or the second direction Y. Therefore, the orientation of the electronic component after replacement can be consistent with the orientation of the electronic component before replacement. For example, as shown in FIG12 , the first pin of the electronic component before replacement can be electrically connected to the first first sub-pad 51 ', and the second pin can be electrically connected to the first second sub-pad 52 '. The first pin of the replaced electronic component can be electrically connected to the second first sub-pad 51 ″, and the second pin can be electrically connected to the second second sub-pad 52 ″, so that the replaced electronic component has the same orientation as the electronic component before replacement.

[0102] It is understood that the electronic components before replacement are arranged in equal spacing with other electronic components along the row or column direction, and the electronic components after replacement are slightly offset relative to the row or column in which the electronic components before replacement were located. For example, as shown in FIG23 , multiple electronic components 200B are arranged in a column along the second direction Y. Any one of the multiple electronic components 200B is replaced with an electronic component 200C. The orientation of the replaced electronic component 200C is consistent with the orientation of electronic component 200B, and the replaced electronic component 200C is relatively offset relative to the column formed by the multiple electronic components 200B.

[0103] It should be noted that the orientation of the newly fixed electronic component 200C is consistent with the orientation of the electronic component 200B, which means that among the electronic components of the same type, a certain edge of all the electronic components is arranged along a fixed direction.

[0104] In some examples, the electronic components may be micro-LEDs. An array of multiple micro-LEDs is arranged on a wiring substrate and can serve as a light-emitting backplane for a liquid crystal display. The replaced micro-LEDs are relatively staggered within a row of micro-LEDs. The staggered arrangement is acceptable because the offset is minor and does not affect the normal display of the LCD.

[0105] In some embodiments, as shown in FIG13 , FIG14 , or FIG15 , each of the plurality of connecting traces L includes a main body 21 . Among the two connecting traces L having a first connecting end D1 and a second connecting end D2 disposed opposite each other, the main body 21 of one connecting trace L extends along the first direction X, and the main body 21 of the other connecting trace L extends along the second direction Y. It will be appreciated that, in some embodiments, the main body 21 of a connecting trace L extends in a different direction from the first connecting end D1 and the second connecting end D2 of the connecting trace L.

[0106] In some embodiments, as shown in Figures 16, 18, and 19, a wiring substrate 100 includes a plurality of functional areas H, chip areas G, and a plurality of signal lines arranged in an array, with a chip area G arranged on one side of each functional area H. The functional area H includes at least one pad group, each of which can be electrically connected to an electronic component. As shown in Figure 17, each chip area G includes a plurality of chip pads 53, which may include a first chip pad 54, a second chip pad 55, a third chip pad 56, and a fourth chip pad 57. The chip pads 53 in each chip area G are electrically connected to a driver chip, wherein several of the plurality of driver chips provided on the wiring substrate are cascaded. The plurality of signal lines may, for example, include a first power supply voltage line VLED, a second power supply voltage line GND, a third power supply voltage signal line PWR, an addressing signal line Addr, and a feedback signal line FB.

[0107] As shown in Figures 16 and 17 , each functional area H is electrically connected to the first power supply voltage trace VLED. Each functional area H is also electrically connected to the second die pad 55 of the chip area G corresponding to that functional area H. Several of the multiple chip areas G located on the wiring substrate 100 are electrically connected in sequence, i.e., the second die pad 55 of the previous chip area G is electrically connected to the first die pad 54 of the next chip area G. The first die pad 54 of the first chip area G among the multiple sequentially electrically connected chip areas G is electrically connected to the addressing signal line Addr, and the second die pad 55 of the last chip area G is electrically connected to the feedback signal line FB. The third die pad 56 of each chip area G is electrically connected to the third power supply voltage signal line PWR, and the fourth die pad 57 of each chip area G is electrically connected to the second power supply voltage trace GND.

[0108] Among them, the first power supply voltage line VLED is configured to transmit a first level signal to the functional area H, the second power supply voltage line GND is configured to transmit a second level signal to the chip area G, the third power supply voltage signal line PWR is configured to transmit a third level signal to the chip area G, the addressing signal line Addr is configured to transmit an addressing signal, and the feedback signal line FB is configured to receive the feedback signal output by the chip area G and transmit it to the upper chip.

[0109] The first level signal and the third level signal can be high level signals with different or equal voltages, and the second level signal can be a low level signal. In the present disclosure, a "high level signal" refers to the potential of an electrical signal received or output by a node, a terminal, or an output terminal in a circuit. For example, a high level signal can be 3.3V or 5V. A "low level signal" refers to the potential of an electrical signal received or output by a node, a terminal, or an output terminal in a circuit. For example, a low level signal can refer to a ground signal. Specifically, a low level signal can be 0V.

[0110] A plurality of electronic components are disposed on a wiring substrate, wherein Q of the plurality of electronic components are sequentially connected in series, where Q is a positive integer greater than 1. In some embodiments, as shown in FIG18 as a structural diagram of a functional area H, in a pad group 50, the first sub-pad 51 and the second sub-pad 52 are arranged in only one direction, for example, the first sub-pad 51 and the second sub-pad 52 are arranged in only the first direction X, or the first sub-pad 51 and the second sub-pad 52 are arranged in only the second direction Y. To ensure that the arrangement direction of the Q electronic components in series is the first direction X or the second direction Y, and the Q electronic components are arranged in an array on the array substrate, the main portion of each connecting trace extends along the first direction X or along the second direction Y. For example, of two connecting traces L with a first connecting end D1 and a second connecting end D2 disposed opposite each other, the main portion of one connecting trace L is arranged along the first direction X, and the main portion of the other connecting trace L is arranged along the second direction Y; or, the main portion of one connecting trace L is arranged along the second direction Y, and the main portion of the other connecting trace L is arranged along the first direction X. In Figure 18, each pad group 50 includes only a first sub-pad 51 and a second sub-pad 52, and the first sub-pad 51 and the second sub-pad 52 of each pad group 50 are arranged in the same direction, that is, only a single bonding direction is retained in the wiring substrate shown in Figure 18. For example, this bonding direction is the optimal bonding direction, and in some cases (for example, there is no need to change the bonding direction during the bonding process) it can match the optimal bonding efficiency.

[0111] In other embodiments, as shown in FIG19 , a structure diagram of another functional area H is shown. In a pad group 50, a first sub-pad 51 and two second sub-pads 52 are included. The first sub-pad 51 and the second sub-pad 52 are arranged in the first direction X, and the other second sub-pad 52 is arranged in the second direction Y. The electronic components corresponding to the pad group 50 can be arranged in the first direction X or the second direction Y. The main portion of the connecting trace L extends along the first direction X or the second direction Y. Specifically, of the two connecting traces L with the first connecting end D1 and the second connecting end D2 arranged opposite to each other, the main portion of one connecting trace L is arranged along the first direction X, and the main portion of the other connecting trace L is arranged along the second direction Y; alternatively, the main portion of one connecting trace L is arranged along the second direction Y, and the main portion of the other connecting trace L is arranged along the first direction X. In this solution, a pad group 50 includes a first sub-pad 51 and two second sub-pads 52. By reserving and adding sub-pads required for bonding in another direction, the actual bonding direction requirements can be taken into account to choose to change the bonding direction of the electronic components, so as to maximize the bonding efficiency of the electronic components in the actual bonding process.

[0112] The change in the number and arrangement position of the first sub-pads or the second sub-pads in the pad group 50 does not affect the extension direction of the main body of the two connecting traces L oppositely arranged at the first connecting end D1 and the second connecting end D2.

[0113] Exemplarily, as shown in Figures 18 and 19, in a wiring substrate, a plurality of connecting traces L are divided into a plurality of groups, each group includes N connecting traces, and the N connecting traces are arranged in sequence, and the connection end of the previous connecting trace is arranged opposite to the connection end of the next trace. For example, a group of connecting traces includes 5 connecting traces, one end of the first connecting trace L1 is the first connection end, one end of the second connecting trace L2 is the second connection end, and the first connection end of the first connecting trace L and the second connection end of the second connecting trace L are arranged opposite to each other; the other end of the second connecting trace L2 is the first connection end, and one end of the third connecting trace L3 is the second connection end, and the first connection end of the second connecting trace L2 and the second connection end of the third connecting trace L3 are arranged opposite to each other, and so on. The other end of the fourth connecting trace L4 is the second connection end, and one end of the fifth connecting trace L5 is the first connection end, and the first connection end of the fifth connecting trace L5 and the second connection end of the fourth connecting trace L4 are arranged opposite to each other. It should be noted that the other end of the first connection line L1 is electrically connected to the first power voltage line VLED, and the other end of the fifth connection line L5 is electrically connected to the chip region G.

[0114] The first sub-pad 51 in each pad group 50 is located in the area where the first connection end D1 is located, and the second sub-pad 52 is located in the area where the second connection end D2 is located. Each pad group 50 is located in the area where the first connection end and the second connection end are located, which are oppositely arranged between two connecting lines L. Five connecting lines correspond to four pad groups.

[0115] In the four pad groups 50 shown in Figures 18 and 19, the four electronic components corresponding to each of the four pad groups 50 are connected in series. In the four pad groups 50, the connection trace L where the first sub-pad 51 in the first pad group 50 is located is electrically connected to the first power supply voltage trace VLED, forming an integrated structure. The connection trace L electrically connected to the second sub-pad in the last pad group 50 is electrically connected to the middle trace LL between the chip areas G, forming an integrated structure. Each pad group 50 is provided with an electronic component, so that Q electronic components are connected in series.

[0116] As shown in FIG19 , the main body of each connecting line extends generally along the first direction or along the second direction. For example, taking the third connecting line L3 and the fourth connecting line L4 shown in FIG19 as an example, the first connection end D1 of the third connecting line L3 and the second connection end D2 of the fourth connecting line L4 are arranged relative to each other, the main body of the third connecting line L3 is arranged generally along the first direction X (for example, it may have a bent portion), and the main body of the fourth connecting line L4 is arranged generally along the second direction Y (for example, it may have a bent portion). Alternatively, taking the second connecting line L2 and the third connecting line L3 shown in FIG19 as an example, the first connection end D1 of the second connecting line L2 and the second connection end D2 of the third connecting line L3 are arranged relative to each other, the main body of the second connecting line L2 is arranged along the second direction Y, and the main body of the third connecting line L3 is arranged generally along the first direction X (for example, it may have a bent portion). That is to say, when the pad group 50 includes at least one first sub-pad and at least one second sub-pad, the extension direction of the main body of the connecting trace remains unchanged relative to the design in which the first sub-pad 51 and the second sub-pad 52 are arranged in only one direction in Figure 18. While changing the arrangement direction of the electronic components, the changes to the overall design of the trace layer of the wiring substrate can be reduced, and the impact on the production process can be minimized.

[0117] On the other hand, some embodiments of the present disclosure further provide a backplane 1100, as shown in Figures 20 and 21, wherein Figure 21 is a cross-sectional view taken along the EE direction in Figure 20. The backplane 1100 includes the wiring substrate 100 provided in any of the above embodiments and a plurality of electronic components, the plurality of electronic components being disposed on one side of the pad group of the wiring substrate 100, and the electronic components being connected to at least one first sub-pad and one second sub-pad adjacently disposed in the first direction X or the second direction Y in the pad group.

[0118] In some examples, the backplane 1100 includes a wiring substrate and a plurality of electronic components disposed on the wiring substrate 100. The wiring substrate 100 includes a plurality of pad groups, each pad group including at least one first sub-pad and at least two second sub-pads disposed along a first direction X and a second direction Y. The electrodes of each electrical component are electrically connected to a corresponding pad group through an opening in the wiring substrate 100. That is, the electronic component can be electrically connected to the first sub-pad and the second sub-pad disposed along the first direction X, or the electronic component can be electrically connected to the first sub-pad and the second sub-pad disposed along the second direction Y.

[0119] Exemplarily, the electronic component may be a micro light emitting diode, and a reflective layer 60 is further provided on the side of the insulating layer 30 away from the substrate. The reflective layer 60 reflects light. For example, the material of the reflective layer 60 includes photosensitive white ink or thermosetting white ink.

[0120] The reflective layer 60 is provided with a reflective layer opening 70 that can expose at least a portion of the first sub-pad 51 and the second sub-pad 52. In other words, the orthographic projection of the reflective layer opening 70 on the substrate 10 overlaps with the orthographic projection of the opening 40 of the insulating layer 30 on the substrate 10. For the first sub-pads 51 and the second sub-pads 52 that are not connected to the pins of the electronic component, the corresponding openings 40 in the insulating layer 30 can be covered by the reflective layer 60, preventing the exposed sub-pads from becoming an entrance for water and oxygen to corrode the wiring substrate.

[0121] For example, as shown in FIG20 or FIG22, the electronic component 200 can be a micro-light emitting diode, which includes a first pin and a second pin, and each micro-light emitting diode is electrically connected to a pad group. During the die bonding process of the micro-light emitting diode, in order to reduce the number of line changes of the die bonding bracket and improve the die bonding efficiency, the micro-light emitting diode adopts the optimal die bonding direction T. For example, the first pin of the micro-light emitting diode shown in FIG22 is electrically connected to a first sub-pad of the pad group, and the second pin is electrically connected to the second sub-pad of the first sub-pad arranged in the first direction X. Accordingly, on the wiring substrate 100, the long side extension direction of the plurality of micro-light emitting diodes is arranged along the first direction X, that is, the micro-light emitting diodes are bonded using the optimal die bonding direction T.

[0122] In some embodiments, due to sharing a common set of mask plates, the arrangement direction of the first sub-pads and the second sub-pads on the wiring substrate is inconsistent with the optimal die-bonding direction T, and the die-bonding direction of the micro-LEDs is inconsistent with the optimal die-bonding direction T. For example, the first pin of the micro-LED shown in FIG22 is electrically connected to a first sub-pad of a pad group, and the second pin is electrically connected to a second sub-pad of the first sub-pad arranged in the second direction Y. Accordingly, on the wiring substrate, the long sides of the multiple micro-LEDs are arranged along the second direction Y.

[0123] The second sub-pad arranged in the second direction Y with the first sub-pad can provide a second arrangement direction for the electronic component, for example, a second arrangement direction can be provided for the micro light-emitting diode, so that the actual bonding direction requirements can be taken into account. In some processes that require changing the bonding direction of the micro light-emitting diode, a suitable pad group is selected to adapt to the actual bonding direction to improve efficiency.

[0124] In some embodiments, as shown in FIG23 , the plurality of electronic components include at least two electronic components 200, wherein one electronic component 200A of the at least two electronic components 200 is electrically connected to a first sub-pad and a second sub-pad in the pad group arranged along a first direction X. Another electronic component 200B of the at least two electronic components 200 is electrically connected to a first sub-pad and a second sub-pad in the pad group arranged along a second direction Y.

[0125] In some examples, the wiring substrate 100 includes multiple pad groups, each pad group is provided with an electronic component 200, and in some pad groups, the electrodes of the electronic component 200 are electrically connected to the first sub-pad and the second sub-pad arranged along the first direction X; in another part of the pad groups, the electrodes of the electronic component 200 are electrically connected to the first sub-pad and the second sub-pad arranged along the second direction Y.

[0126] By way of example, the electronic component 200 may be a micro-LED. The micro-LED includes a first pin and a second pin, each of which is electrically connected to a pad group. For example, a first pin of a first type of micro-LED among the plurality of micro-LEDs is electrically connected to a first sub-pad of the pad group, and a second pin is electrically connected to a second sub-pad of the first sub-pad arranged in a first direction X. Accordingly, on the wiring substrate, the long sides of the first type of micro-LEDs are arranged along the first direction X. A first pin of a second type of micro-LED among the plurality of micro-LEDs is electrically connected to a first sub-pad of the pad group, and a second pin is electrically connected to a second sub-pad of the first sub-pad arranged in a second direction Y. Accordingly, on the wiring substrate, the long sides of the plurality of micro-LEDs are arranged along the second direction Y.

[0127] In some embodiments, as shown in Figure 23, among the multiple electronic components 200, the number of electronic components 200 electrically connected to the first sub-pads and the second sub-pads arranged in the pad group along the second direction Y is greater than the number of electronic components electrically connected to the first sub-pads and the second sub-pads arranged in the pad group along the first direction X.

[0128] In some examples, the electronic component 200 is a micro-LED. To reduce the number of times the die-bonding bracket needs to be rewound during the die-bonding process and improve die-bonding efficiency, the micro-LEDs are die-bonded in an optimal die-bonding direction. Specifically, on the wiring substrate 100, the long side of the wiring substrate 100 is in a first direction X, and the long sides of the multiple micro-LEDs extend in the same direction. Alternatively, the long side of the wiring substrate 100 is in a second direction Y, and the long sides of the multiple micro-LEDs extend in the same direction Y.

[0129] If there is a defect such as a cold solder joint, a short circuit, or a connection position offset between the electronic component and the sub-pad, it is necessary to apply a lateral shear force to remove the electronic component and re-connect it firmly in the correct position. In the process of removing the electronic component, the sub-pad may be damaged, resulting in the sub-pad being unable to achieve a reliable connection with the electronic component again. Using the embodiment provided by the present disclosure, since a pad group includes multiple groups of first sub-pads and second sub-pads arranged in pairs, when resetting the electronic component, a first sub-pad and / or second sub-pad different from the previous one can be selected to complete the solidification. In some cases, the orientation of the reset electronic component may be different from the arrangement orientation of the original electronic component, for example, perpendicular to each other. It can be understood that the number of electronic components on the entire backplane that have the above-mentioned defective problems accounts for a very low proportion. Therefore, the number of electronic components arranged in a certain direction on the backplane should be much larger than the number of electronic components arranged in another direction.

[0130] That is, two or more first sub-pads and second sub-pads can be used as spare pads in the repair process when poor die bonding occurs in the electronic component, making it convenient to reliably bond the electronic component again and greatly improving the yield rate.

[0131] In some embodiments, as shown in FIG24 , the back plate 1100 further includes a protective adhesive layer 400 , which is disposed on a side of the plurality of electronic components 200 away from the wiring substrate 100 . The protective adhesive layer 400 covers the electronic components 200 to provide protection.

[0132] In some examples, a protective adhesive layer 400 is disposed on a side of the plurality of electronic components 200 away from the substrate. The protective adhesive layer 400 can cover the plurality of electronic components 200 and fill the gaps between adjacent electronic components 200 .

[0133] The protective adhesive layer 400 can protect the electronic component 200 and prevent water and oxygen from corroding the back plate 1100 through the pins of the electronic component 200 .

[0134] For example, taking the electronic component 200 as a micro-LED, the protective adhesive layer 400 may be a transparent protective adhesive that covers the micro-LEDs on the wiring substrate 100 and fills the gaps between the micro-LEDs.

[0135] On another aspect, some embodiments of the present disclosure further provide an electronic device, comprising the backplane according to any one of the embodiments in the other aspect above.

[0136] The electronic device provided in this embodiment adopts the backplane provided in the above embodiment and has the same functions and advantages as the backplane described in the above embodiment, which will not be described in detail here.

[0137] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A wiring substrate, wherein: include: substrate; a plurality of connection traces disposed on one side of the substrate, wherein at least one of the plurality of connection traces includes a first connection end, and at least another connection trace includes a second connection end, and the first connection end and the second connection end are disposed opposite to each other; a pad group located in the region where the first connection end and the second connection end are located, the pad group including at least one first sub-pad and at least two second sub-pads; the at least one first sub-pad is located in the region where the first connection end is located, and the at least two second sub-pads are located in the region where the second connection end is located; the at least one first sub-pad and the at least two second sub-pads are spaced apart from each other; One of the at least one first sub-pad is adjacent to one of the at least two second sub-pads along a first direction, and the first sub-pad is adjacent to another of the at least two second sub-pads in a second direction; the first direction intersects with the second direction.

2. The wiring substrate according to claim 1, wherein Each of the at least one first sub-pad is adjacent to two of the at least two second sub-pads in the first direction and the second direction, respectively.

3. The wiring substrate according to claim 1 or 2, wherein: The first sub-pad and the second sub-pad adjacent to each other in the first direction are separated by a first distance, and the first sub-pad and the second sub-pad adjacent to each other in the second direction are separated by a second distance, wherein the first distance is 0.9 to 1.1 times the second distance.

4. The wiring substrate according to any one of claims 1 to 3, wherein The number of the at least one first sub-pad is N, and the number of the at least two second sub-pads is M, where N and M are positive integers, N≥1, and N=M-1.

5. The wiring substrate according to any one of claims 1 to 4, wherein The substrate is a parallelogram, and the first direction is parallel to a longer side of the substrate.

6. The wiring substrate according to any one of claims 1 to 5, wherein: The edges of the first connection end and the second connection end adjacent to each other have the same shape.

7. The wiring substrate according to claim 6, wherein The edges of the first connection end and the second connection end close to each other have a stepped structure.

8. The wiring substrate according to claim 7, wherein Any first sub-pad among the at least one first sub-pad is not disposed adjacent to any other first sub-pad among the at least one first sub-pad in the first direction and / or the second direction.

9. The wiring substrate according to claim 8, wherein Any second sub-pad among the at least two second sub-pads is not disposed adjacent to other second sub-pads among the at least two second sub-pads in the first direction and / or the second direction.

10. The wiring substrate according to claim 9, wherein Each of the multiple connecting lines includes a main body. Among the two connecting lines with the first connecting end and the second connecting end arranged opposite to each other, the main body of one connecting line extends along the first direction, and the main body of the other connecting line extends along the second direction.

11. The wiring substrate according to any one of claims 1 to 10, wherein: A passivation layer is provided on the side of the multiple pad groups away from the substrate, and a plurality of openings are provided on the passivation layer. The orthographic projection of each of the multiple openings on the substrate overlaps with the orthographic projection of a first sub-pad or a second sub-pad in the pad group on the substrate.

12. A backplane, wherein: The backplane comprises: The wiring substrate according to any one of claims 1 to 11, A plurality of electronic components are arranged on one side of the pad group of the wiring substrate, and the electronic components are connected to at least a first sub-pad and a second sub-pad in the pad group that are adjacently arranged along the first direction or the second direction.

13. The back plate according to claim 12, wherein: The plurality of electronic components include at least two electronic components, one of the at least two electronic components is electrically connected to the first sub-pad and the second sub-pad in the pad group arranged along the first direction; Another electronic component of the at least two electronic components is electrically connected to the first sub-pad and the second sub-pad in the pad group that are arranged along the second direction.

14. The back plate according to claim 13, wherein Among the multiple electronic components, the number of electronic components electrically connected to the first sub-pad and the second sub-pad arranged along the second direction in the pad group is greater than the number of electronic components electrically connected to the first sub-pad and the second sub-pad arranged along the first direction in the pad group.

15. The back plate according to claim 14, wherein The plurality of pad groups include a passivation layer having a plurality of openings, the plurality of electronic components are disposed on a side of the passivation layer away from the substrate, and an electrode of each electronic component is electrically connected to the pad group through the opening; The back plate further comprises a protective adhesive layer, and the protective adhesive layer is arranged on a side of the plurality of electronic components away from the wiring substrate; The protective adhesive layer fills the gaps between adjacent electronic components and the openings among the plurality of openings that are not covered by the electronic components.

16. An electronic device, wherein: Comprising the backing plate according to any one of claims 12 to 15 above.

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