Semiconductor structures

Abstract

A semiconductor structure comprises a substrate 110; a buffer layer 120 over the substrate; a back-barrier region 470 over the buffer layer; a channel layer 130 over the back-barrier region; and a bar

Description

Technical field The present application relates to semiconductor structures. The present application also relates to a semiconductor device, a power management device, a radio frequency module and an electronic device. Background Forming semiconductor devices from lll-N semiconductor materials is becoming increasingly desirable. Si has dominated the semiconductor industry for many decades. However, lll-N semiconductor materials, such as GaN, possess desirable electronic and photonic properties, outperforming Si in many aspects. The high electron mobility transistor (HEMT) is a semiconductor device commonly formed from lll-N materials. The HEMT has found use in many applications. lll-N HEMTs typically exhibit a higher breakdown voltage and greater electron mobility than Si MOSFETs. The use of lll-N HEMTs has therefore found use in power and radio frequency (RF) communications applications. lll-N HEMT fabrication involves epitaxially growing layers of lll-N semiconductor material on a substrate. Figure 1 illustrates an example of a HEMT epitaxial semiconductor structure 100. Semiconductor structure 100 comprises a substrate 110, which can comprise SiC, Sapphire or Si. Structure 100 further includes a nucleation layer 115, which provides an improved surface for the growth of the lll-N layers thereon. The nucleation layer 115 can comprise a thin layer of AIN or GaN. The structure further includes a buffer layer 120, which is designed to eliminate defects and provide isolation between the substrate 110 and the channel layer 130 above the buffer layer 120. The buffer layer 130 can also be doped to aid in the isolation properties. Semiconductor structure 100 further includes the channel layer 130. Channel layer 130 provides the channel in the HEMT for charge carriers to flow. A 2-dimensional electron gas (2DEG) is formed in the channel, which confines the electrons and results in the HEMT exhibiting high electron mobility properties. The semiconductor structure 100 further comprises a spacer layer 140 and a barrier layer 150. Barrier layer 150 creates a polarization discontinuity between itself and the channel layer 130, resulting in the formation of the 2DEG in the channel layer 130. Spacer layer 140 provides isolation between the channel layer 130 and the barrier layer 150 to improve the channel layer 130 electrical properties. The semiconductor structure 100 further comprises a cap layer 160, which passivates surface defects of the barrier layer 150 to improve electrical performance of the structure 100. In order to provide appropriate defect elimination and isolation effects, the buffer layer 120 can be grown relatively thick and have a thickness of, for example, 800-1800 nm. At these thicknesses, the buffer layer provides suitable defect elimination and isolation properties. However, thick buffer layers also provide sites for electron traps, which increase drain lag of the HEMT. Increasingly, there is a trend to reduce the thickness of the buffer layer 120 to less than 500 nm, in order to reduce the potential effects of drain lag. Furthermore, it is increasingly desirable to leave the buffer layer 120 undoped, which further reduces the likelihood of forming electron traps. Reducing the thickness of the buffer layer 130 and leaving the buffer layer 120 undoped reduces the likelihood of forming traps, but reduces the ability of the buffer layer 120 to provide suitable isolation effects between the channel layer 130 and the substrate 110. Thinner buffer layers further result in less defect annihilation and more defective films. Furthermore, an undoped buffer layer 120 does not confine carriers into the channel layer 130, resulting in carrier migration outside of the 2DEG thereby reducing mobility. Poor confinement allows carriers to interact with defects present in the buffer layer 120, nucleation layer 115 and substrate 110, which reduces device performance. In order to combat the negative effects associated with thin and undoped buffer layers, HEMT designs have developed, which include a back barrier. The back barrier is typically situated between the channel layer 130 and the buffer layer 120, and acts to improve the confinement of carriers in the channel layer 130. However, the confinement provided by some back barrier designs is poor and carriers can still migrate out of the channel layer 130 and into the buffer layer 120. Summary It is an object of the disclosure to obviate or eliminate at least some of the abovedescribed disadvantages associated with existing techniques. According to a first aspect there is provided a semiconductor structure that comprises: a substrate; a buffer layer over the substrate; a back-barrier region over the buffer layer; a channel layer over the back-barrier region; and a barrier layer over the channel layer. The back barrier region comprises: a first semiconductor layer configured to form a first potential barrier; and a second semiconductor layer configured to form a second potential barrier in the second semiconductor layer, wherein the second potential barrier is greater than the first potential barrier. According to a second aspect there is provided a semiconductor structure that comprises: a substrate; a buffer layer over the substrate; a back barrier region over the buffer layer; a channel layer over the back-barrier region; and a barrier layer over the channel layer. The back barrier region comprises: a first semiconductor layer comprising AIGaN; a second semiconductor layer over the first semiconductor layer comprising Al and N; a third semiconductor layer over the second semiconductor layer comprising GaN; and a fourth semiconductor layer over the third semiconductor layer comprising InGaN. According to a third aspect there is provided a semiconductor device comprising the semiconductor structure according to the first aspect or the second aspect. According to a fourth aspect there is provided a power management device comprising the semiconductor device according to the third aspect. According to a fifth aspect there is provided a radio frequency module comprising the semiconductor device according to the third aspect. According to a sixth aspect there is provided an electronic device comprising the power management device according to the fourth aspect or the radio frequency module according to fifth aspect. Brief description of the drawings For a better understanding of the techniques, and to show how it may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 is an example of a semiconductor structure; Figure 2 is another example of a semiconductor structure; Figures 3a-c are examples of energy band diagrams; Figure 4 is another example of a semiconductor structure; Figure 5 is another example of an energy band diagram; Figure 6 is another example of a semiconductor structure; Figure 7 is another example of an energy band diagram; Figure 8 is another example of an energy band diagram; Figure 9 is another example of an energy band diagram. Detailed Description Epitaxy or epitaxial means crystalline growth of material, usually via high temperature deposition. Epitaxy can be effected in a molecular beam epitaxy (MBE) tool in which layers are grown on a heated substrate in an ultra-high vacuum environment. Elemental sources are heated in a furnace and directed towards the substrate without carrier gases. The elemental constituents react at the substrate surface to create a deposited layer. Each layer is allowed to reach its lowest energy state before the next layer is grown so that bonds are formed between the layers. Epitaxy can also be performed in a metal organic vapour phase epitaxy (MOVPE) tool, also known as a metal-organic chemical vapour deposition (MOCVD) tool. Compound metal-organic and hydride sources are flowed over a heated surface using a carrier gas, typically hydrogen. Epitaxial deposition occurs at much higher pressure than in an MBE tool. The compound constituents are cracked in the gas phase and then reacted at the surface to grow layers of desired composition. Deposition means the depositing of a layer on another layer or substrate. It encompasses epitaxy, chemical vapour deposition (CVD), powder bed deposition and other known techniques to deposit material in a layer. A compound material comprising one or more materials from group III of the periodic table with one or more materials from group V is known as a lll-V material. The compounds have a 1:1 combination of group III and group V regardless of the number of elements from each group. Subscripts in chemical symbols of compounds refer to the proportion of that element within that group. Thus Alo.2sGaAs means the group III part comprises 25% Al, and thus 75% Ga, whilst the group V part comprises 100% As. Crystalline means a material or layer with a single crystal orientation. In epitaxial growth or deposition subsequent layers with the same or similar lattice constant follow the registry of the previous crystalline layer and therefore grow with the same crystal orientation. In-plane is used herein to mean parallel to the surface of the substrate; out-of-plane is used to mean perpendicular to the surface of the substrate. Substrate means a planar wafer on which subsequent layers may be deposited or grown. A substrate may be formed of a single element or a compound material, and may be doped or undoped. For example, common substrates include silicon (Si), gallium arsenide (GaAs), silicon germanium (SiGe), silicon germanium tin (SiGeSn), indium phosphide (InP), and gallium antimonide (GaSb). A substrate may be on-axis, that is where the growth surface aligns with a crystal plane. For example it has <100 crystal orientation. References herein to a substrate in a given orientation also encompass a substrate which is miscut by up to 20° towards another crystallographic direction, for example a (100) substrate miscut towards the (111) plane. Vertical or out of plane means in the growth direction; lateral or in-plane means parallel to the substrate surface and perpendicular to the growth direction. Doping means that a layer or material contains a small impurity concentration of another element (dopant) which donates (donor) or extracts (acceptor) charge carriers from the parent material and therefore alters the conductivity. Charge carriers may be electrons or holes. A doped material with extra electrons is called n-type whilst a doped material with extra holes (fewer electrons) is called p-type. A layer may be monolithic, that is comprising bulk material throughout. Alternatively it may be porous for some or all of its thickness. A porous layer includes air or vacuum pores, with the porosity defined as the proportion of the area which is occupied by the pores rather than the bulk material. The porosity can vary through the thickness of the layer. For example, the layer may be porous in one or more sublayer. The layer may include an upper portion which is porous with a lower portion that is non-porous. Alternatively the layer may include one or more discrete, non-continuous portions (domains) that are porous with the remainder being non-porous (with bulk material properties). The portions may be non-continuous within the plane of a sublayer and / or through the thickness of the layer (horizontally and / or vertically in the sense of the growth direction). The portions may be distributed in a regular array or irregular pattern across the layer, and / or through it. The porosity may be constant or variable within the porous regions. Where the porosity is variable it may be linearly varied through the thickness, or may be varied according to a different function such as quadratic, logarithmic or a step function. Where a device is described it should be understood that it will typically be formed on a circular substrate wafer of 4” (100mm), 6” (150mm), 8” (200mm), 12” (300mm) or greater diameter. After growth, deposition, bonding and other fabrication steps the devices are separated by dicing the wafer and layers into devices (chips) of appropriate dimensions. Typically tens, hundreds or thousands of devices are cut from a single wafer. To provide additional context to the description of the examples according to the present disclosure, there now follows a further discussion of the drawbacks, which conventional techniques suffer from. Figure 2 is an example of a semiconductor structure 200. Semiconductor structure 200 comprises elements in common to semiconductor structure 100 described above. Said common elements are labelled with common reference numerals and may comprise corresponding features and may operate with substantially the same functionality to that described above. Semiconductor structure 200 comprises a back barrier 270. As described above back barrier 270 can provide some carrier confinement to prevent carriers in the channel layer 130 from migrating to the buffer layer 120. In some examples, channel layer 130 comprises GaN and buffer layer 120 also comprises GaN. In such examples, the back barrier 270 can comprise InGaN or AIGaN, which can provide some confinement for carriers into the channel layer 130. However, the confinement provided by an InGaN or AIGaN back barrier is relatively weak. Figures 3a and 3b are energy band diagrams illustrating the carrier confinement provided by an InGaN and AIGaN back barrier, respectively. Figure 3a illustrates an energy band diagram 300a for a HEMT comprising an InGaN back barrier 270. The band diagram 300a illustrates the conduction band 310 of the HEMT relative to the fermi level 320. The band diagram 300a further illustrates the valence band 330 relative to the fermi level 320. Energy band diagram 300a illustrates that a 2DEG 311 is formed in the GaN channel layer 130. The 2DEG 311 forms due to the discontinuity of the polarization fields between the AIGaN barrier layer 150 and the GaN channel layer 130. The formation of the 2DEG 311 is further improved by the presence of the AIN spacer layer 140. The InGaN back barrier 270 forms a small potential well 312 in the conduction band 310 followed by a potential barrier 313 at the interface with the GaN buffer layer 120. As illustrated in band diagram 300a, a first electron 314 may migrate towards the GaN buffer 120. However, the energy of the electron may be sufficiently low such that the well 312 and barrier 313 formed by the InGaN back barrier 270 prevents the first electron 314 from entering the GaN buffer layer 120. However, the potential barrier 313 is relatively small and is only about 1eV above the fermi level 320. In some examples, a second electron 315 may possess a higher energy than the potential barrier 313 and enter the GaN buffer layer 120. For example, a sufficient voltage may be applied to the HEMT, which promotes an electron from the valence band 330 to the conduction band 310 with enough excess energy to pass over the potential barrier 313. In such examples, the carrier confinement provided by the InGaN back barrier 270 is thus relatively weak and may allow a number of electrons to enter the GaN buffer 120. Figure 3b illustrates an energy band diagram 300b for a HEMT comprising an AIGaN back barrier 270. The band diagram 300b again illustrates the conduction band 310, fermi level 320 and valence band 330. The AIGaN back barrier 270 forms a potential barrier 313 between the GaN channel layer 130 and the GaN buffer layer 120. The potential barrier 313 can again prevent a first electron 314 from entering the GaN buffer layer 120 from the channel layer 130. However, again, the potential barrier 313 is relatively small and may be about 1.8 eV above the fermi level 320. The potential barrier 313 may not prevent a second electron 315 possessing a higher energy from passing from the channel layer 130 and into the GaN buffer layer 120. The AIGaN back barrier 270 thus also provides relatively weak carrier confinement. Furthermore, although the AIGaN back barrier 270 can provide improved confinement over the InGaN back barrier 270, the use of an AIGaN 270, over a GaN buffer layer 130 suffers from drawbacks. For example, due to the polarization discontinuity between the AIGaN back barrier 270 and the GaN buffer layer 120, a two-dimensional electron gas (2DEG) can form in the GaN buffer layer 120. This creates an additional conduction channel in the GaN buffer 120, which is undesirable. Thus, more commonly, the back barrier is removed and the GaN buffer 120 is replaced by a AIGaN buffer layer 120’. Figure 3c illustrates an energy band diagram 300c for a HEMT comprising an AIGaN buffer layer 120’. The band diagram 300c again illustrates the conduction band 310, fermi level 320 and valence band 330. The AIGaN buffer layer 120’ forms a potential barrier 313 between the GaN channel layer 130 and the nucleation layer 115 (not illustrated). The potential barrier 313 can again prevent a first electron 314 from entering the AIGaN buffer layer 120’ from the channel layer 130. However, again, the potential barrier 313 is relatively small and may be about 1 eV above the fermi level 320. The potential barrier 313 may not prevent a second electron 315 possessing a higher energy from passing from the channel layer 130 and into the GaN buffer layer 120. The AIGaN buffer layer 120’ also comprises electron traps. Thus electron 315 passing over the potential barrier 313 and into the AIGaN buffer layer 120’ can increase the drain lag. The weak confinement provided by the potential barrier 313 is thus again problematic. Examples according to the present disclosure provide a semiconductor structure for forming a HEMT, which comprises a back barrier region providing improved carrier confinement to prevent carriers migrating from the channel layer to the buffer layer. The back barrier region according to examples of the present disclosure includes a first semiconductor layer configured to form a first potential barrier; and a second semiconductor layer configured to form a second potential barrier in the second semiconductor layer, wherein the second potential barrier is greater than the first potential barrier. In some examples, the first semiconductor layer may comprise InGaN and the second semiconductor layer may comprise AI(Ga)N. It has been observed that the back barrier region according to examples of the present disclosure results in a significant increase in the height of the potential barriers to provide improved carrier confinement. In particular, the second semiconductor layer forms a large potential barrier, which lifts the energy of the first potential barrier to provide improved carrier confinement. In some examples, the back barrier region according to examples of the present disclosure may further include a third semiconductor layer configured to form an intermediate energy level between the first potential barrier and the second potential barrier. In some examples, the third semiconductor layer may comprise GaN. The third semiconductor layer can provide a relatively thick high energy region that can prevent carriers from tunneling through the first potential barrier. In some examples, the back barrier region according to examples of the present disclosure may further include a fourth semiconductor layer configured to form a second intermediate energy level above a fermi level and maintain a valence band below the fermi level. In some examples, the fourth semiconductor layer may comprise AIGaN. The fourth semiconductor layer can prevent a secondary channel from forming in the GaN buffer layer 120, which may be formed if the fourth semiconductor layer were not present. Figure 4 illustrates a semiconductor structure 400 according to examples of the present disclosure. Semiconductor structure 400 comprises elements in common with semiconductor structures 100, 200 described above. Said common elements are labelled with common reference numerals and may comprise corresponding features and may operate with substantially the same functionality to that described above. Semiconductor structure comprises a GaN buffer layer 120. In some examples the GaN buffer layer 120 may comprise a thickness of less than or equal to 500 nm. Semiconductor structure 400 comprises a back barrier region 470 configured to confine carriers into the channel layer 130. Back barrier region 470 comprises an AIGaN layer 472. In some examples, the AIGaN layer 472 may comprise a thickness of 2-20 nm. In other examples, the AIGaN layer 472 may comprise a thickness of up to 50 nm. In some examples, a thickness above, for example, 50 nm may result in the AIGaN layer 472 undergoing relaxation. In some examples, the AIGaN layer 472 may comprise a Al concentration of 2-10% of the group III materials. As will be described in more detail below, AIGaN layer 472 may prevent the formation of a 2-dimensional hole gas in the valence band of a HEMT, which may be formed between the AIN layer 474 and the GaN buffer layer 120 if the AIGaN layer 472 were not present. Back barrier region 470 further comprises an AIN layer 474. In some examples, the AIN layer 474 may comprise a thickness of 0.5-2 nm. In some examples, a thickness above, for example, 2 nm may result in relaxation of the AIN layer 474. As will be described in more detail below, the AIN layer 474 is configured to form a potential barrier between the GaN channel layer 130 and the GaN buffer layer 120. Back barrier region 470 further comprises a GaN layer 476. In some examples, the GaN layer 476 may comprise a thickness of 2-20 nm. As will be described in more detail below, the GaN layer 476 may provide a relatively thick high energy region that can prevent carriers from tunneling through the potential barriers formed in the back barrier region 470. Back barrier region 470 further comprises InGaN layer 478. In some examples, the InGaN layer 478 may comprise a thickness of 0.5-2 nm. In some examples, a thickness above, for example, 2 nm may result in relaxation of the InGaN layer 478. In some examples, the InGaN layer 478 may comprise a In concentration of 5-15% of the group III materials. As will be described in more detail below, the InGaN layer 478 is configured to form a potential barrier between the GaN channel layer 130 and the GaN buffer layer 120. Semiconductor structure 400 further comprises a GaN channel layer 130. In some examples, the GaN channel layer 130 may comprise a thickness of 10-50 nm. Semiconductor structure 400 further comprises an AIN spacer layer 140. In some examples, the AIN spacer layer may comprise a thickness of 0-1 nm. Thus, in some examples, AIN spacer may not be present and the GaN channel layer may interface with the AIGaN barrier layer 150. Semiconductor structure 400 thus further comprises an AIGaN barrier layer 150. In some examples, the AIGaN barrier layer 150 may comprise a thickness of 5-30 nm. In some examples, the AIGaN barrier layer 150 may comprise an Al concentration of 10-50% of the group III materials. Semiconductor structure 400 further comprises cap layer 400. In some examples, the cap layer 160 may comprise GaN, SiN or SiO2. Figure 5 illustrates an example of an energy band diagram 500. Energy band diagram 500 represents the energy band diagram of the semiconductor structure 400 described above. Energy band diagram 500 comprises corresponding elements to band diagrams 300a and 300b described above, where said corresponding elements are labeled with corresponding reference numerals. Energy band diagram again illustrates that a 2DEG 311 is formed in the GaN channel layer 130 due to the polarization field of the AIGaN barrier layer 150. Energy band diagram further illustrates that a potential well 312 and first potential barrier 313 is formed by the InGaN layer 478 of the back barrier region 470. Thus, first electron 314 is blocked from entering the GaN buffer layer 120 by the first potential barrier 313. Energy band diagram 500 further illustrates that a second potential barrier 316 is formed in the AIN layer 474 of the back barrier region 470. Thus, a second electron 315 with a higher energy is also blocked from entering the GaN buffer layer 120 by the second potential barrier 316. The back barrier region 470 thus provides improved carrier confinement to prevent carriers from migrating from the GaN channel layer 130 to the GaN buffer layer 120. It will be noted that the back barrier region 470 forms two high energy potential barriers. The first potential barrier 313 is about 2 eV greater than the fermi level 320 and the second potential barrier 316 is about 4.5 eV greater than the fermi level 320. The first and second potential barriers 313, 316 thus greatly reduce the likelihood of an electron migrating from the GaN channel layer 130 to the GaN buffer layer 120. Energy band diagram 500 further illustrates that an intermediate energy level 317 is formed between the first and second potential barriers 313, 316 by the GaN layer 476 of the back barrier region 470. The intermediate energy level 317 is also high energy having an energy of at least 2 eV above the fermi level 320. The intermediate energy level 317 formed by the GaN layer 476 acts to prevent electrons tunneling through the relatively thin first potential barrier 313, which may occur if the GaN layer 476 were not present. The intermediate energy level 317 is greater than the first potential barrier 313 across all or a major thickness of the GaN layer 476. The second potential barrier 316 formed in the AIN layer 474 is greater than the intermediate energy level 317 across all or a major thickness of the AIN layer 474. Energy band diagram 500 further illustrates a second intermediate energy level 318 formed between the second potential barrier 316 and the GaN buffer layer 120. The AIGaN layer 472 of the back barrier region 470 is configured to form the second intermediate energy level 318. The second intermediate energy level 318 is configured to maintain the energy of the valence band 330 below the fermi level 320 at the interface with the AIN layer 474. If the AIGaN layer 472 were not present, the valence band 330 may be pulled above the fermi level 320 and form a 2 dimensional hole gas in the GaN buffer layer 120. This would create a conductive channel in the GaN buffer layer 120, which would be undesirable in the formation of a HEMT. Back barrier region 470 is thus configured to improve carrier confinement of carriers to the channel layer 130. Figure 6 illustrates a semiconductor structure 600 according to examples of the present disclosure. Semiconductor structure 600 comprises elements in common with semiconductor structures 100, 200, 600 described above. Said common elements are labelled with common reference numerals and may comprise corresponding features and may operate with substantially the same functionality to that described above. Semiconductor structure 600 comprises a back barrier region 670. Back barrier region 670 comprises corresponding layers to back barrier region 470 described above, but where the AIN layer 474 has been replaced by AIGaN layer 674. In some examples, AIGaN layer 674 may again be configured to form a second potential barrier between the GaN channel layer 130 and the GaN buffer layer 120. In some examples, the AIGaN layer 674 may comprise an Al concentration of 25-75% of the group 111 materials. In some examples, the AIGaN layer 674 may comprise a thickness of 0.5-2 nm. Figure 7 illustrates an example of an energy band diagram 700. Energy band diagram 700 represents the energy band diagram of the semiconductor structure 600 described above wherein the AIGaN layer 674 comprises an Al concentration of 75%. Energy band diagram 700 comprises corresponding elements to band diagrams 300a, 300b and 500 described above, where said corresponding elements are labeled with corresponding reference numerals. Energy band diagram 700 illustrates that a second potential barrier 716 is formed in the AIGaN layer 674. The second potential barrier 716 is 4 eV above the fermi level 320. This is smaller compared to the second potential barrier 316 described above, which is 4.5 eV above the fermi level 320. The reduced concentration of Al in the AIGaN (75% Al) layer 674 compared to the AIN layer 474 reduces the height of the second potential barrier 716. However, the second potential barrier 716 still presents a significant potential barrier, which prevents second electron 315 from migrating from the GaN channel layer 130 to the GaN buffer layer 120. Second potential barrier 716 thus improves the carrier confinement for carriers in the GaN channel layer 130. Figure 8 illustrates an example of an energy band diagram 800. Energy band diagram 800 represents the energy band diagram of the semiconductor structure 600 described above wherein the AIGaN layer 674 comprises an Al concentration of 50%. Energy band diagram 800 comprises corresponding elements to band diagrams 300a, 300b, 500 and 700 described above, where said corresponding elements are labeled with corresponding reference numerals. Energy band diagram 800 illustrates that a second potential barrier 816 is formed by the AIGaN layer 674. The second potential barrier 816 is 3.5 eV above the fermi level 320. This is smaller compared to the second potential barriers 316, 716 described above. The reduced concentration of Al in the AIGaN (50% Al) layer 674 again reduces the height of the second potential barrier 816. Furthermore, the reduction in the height of the second potential barrier 816 also affects the height of the first potential barrier 813, which reduces to 1.9 eV above the fermi level 320. Despite the reduction in the height of the first potential barrier 813 and the second potential barrier 816, the barriers still present a significant potential barrier, which prevents first electron 314 and second electron 315 from migrating from the GaN channel layer 130 to the GaN buffer layer 120. The first and second potential barriers 813, 816 thus improve the carrier confinement for carriers in the GaN channel layer 130. Figure 9 illustrates an example of an energy band diagram 900. Energy band diagram 900 represents the energy band diagram of the semiconductor structure 600 described above wherein the AIGaN layer 674 comprises an Al concentration of 25%. Energy band diagram 900 comprises corresponding elements to band diagrams 300a, 300b, 500, 700 and 800 described above, where said corresponding elements are labeled with corresponding reference numerals. Energy band diagram 900 illustrates that a second potential barrier 916 is formed by the AIGaN layer 674. The second potential barrier 916 is 2.7 eV above the fermi level 320. This is smaller compared to the second potential barriers 316, 716, 816 described above. The reduced concentration of Al in the AIGaN (25% Al) layer 674 again reduces the height of the second potential barrier 916. Furthermore, the reduction in the height of the second potential barrier 916 also affects the height of the first potential barrier 913, which reduces to 1.8 eV above the fermi level 320. Despite the reduction in the height of the first potential barrier 913 and the second potential barrier 916, the barriers still present a significant potential barrier, which prevents first electron 314 and second electron 315 from migrating from the GaN channel layer 130 to the GaN buffer layer 120. The first and second potential barriers 913, 916 thus improve the carrier confinement for carriers in the GaN channel layer 130. Examples according to the present disclosure provide a back barrier region that can provide carrier confinement between a channel layer and a buffer layer of a HEMT. The carrier confinement is useful for semiconductor structures comprising a relatively thin buffer layer of less than or equal to 500 nm. However, in other examples, the buffer layer may comprise a thickness of greater than 500 nm. Similarly, the back barrier region that can provide carrier confinement between a channel layer and a buffer layer of a HEMT, where the buffer layer is undoped. However, in other examples, the buffer layer may be doped n-type or p-type or doped to be semi-insulating with an element such as Fe. Examples of the present disclosure present epitaxial semiconductor structures where layers are interfaced with one another. It will be appreciated that one or more layers may be inserted between any of the semiconductor layers described in the above described examples. Examples according to the present disclosure have described a back barrier region comprising AIGaN, AI(Ga)N, GaN and InGaN. However, in other examples, the back barrier region may comprise two semiconductor layers, for example, AI(Ga)N and InGaN, resulting in the formation of two high energy potential barriers to improve the confinement of carriers into the channel layer. The present disclosure further provides a semiconductor device comprising a semiconductor structure according to examples of the present disclosure. In some examples the semiconductor device may comprise a semiconductor device for managing or transferring power. In some examples, the semiconductor device may comprise a semiconductor device for wireless radio frequency (RF) communication. In some examples the semiconductor device may comprise a high electron mobility transistor (HEMT). The present disclosure further provides power management device comprising a semiconductor device according to examples of the present disclosure. In some examples the power management device may manage or transfer power for an electronic device for user operation, for example a mobile phone, cell phone, smart phone, tablet computer, wearable computer such as a watch, or similar. In some examples the power management device may comprise a charging device such as a charger, an adapter, a wireless charger, or similar for charging a battery or on-board power source of an electronic device. In some examples the power management device may comprise a power supply housed in an electronic device for user operation, such as a power converter, for example a DC-DC converter, an AC-DC converter, a DC-AC converter or similar. The present disclosure further provides an RF module comprising a semiconductor device according to examples of the present disclosure. In some examples the RF module may comprise one of: a switch module, a power amplifier module, a transmitter module, a receiver module and a transceiver module. The present disclosure further provides an electronic device comprising a power management device according to examples of the present disclosure and / or a RF module according to examples of the present disclosure. In some examples the electronic device may comprise an electronic device for user operation. In some examples the electronic device may comprise a communication device such as a mobile telephone, smartphone or similar. In some examples the electronic device may comprise handheld computing device, such as a tablet or similar. In some examples the electronic device may comprise a visual display device, such as a television, a monitor or similar. In some examples the electronic device may comprise a wearable device, such as a smartwatch, smart glasses, or similar. In some examples the electronic device may comprise a gaming device such as a games console, or similar. In some examples the electronic device may comprise a headset such as a virtual reality (VR) headset, an augmented reality (AR) headset, or similar. In some examples the electronic device may comprise an audio accessory device, such as headphones, earphones, wireless headphones, true wireless headphones, earbuds, or similar. In some examples the electronic device may comprise an appliance such as a household appliance, for example a refrigerator or a washing machine, or similar. In some examples, the electronic device may comprise a communications infrastructure device, such as a communication infrastructure device for a base station, a cell tower or similar. In some examples the electronic device may comprise a communication hub, such as a Wi-Fi router or switch. In some examples the electronic device may comprise a communications device for a radar device, such as a radar transmitter, radar receiver, radar transceiver or similar. It should be noted that the above-mentioned embodiments illustrate rather than limit the idea, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or 5 “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

1. A semiconductor structure comprising:a substrate;a buffer layer over the substrate;a back-barrier region over the buffer layer;a channel layer over the back-barrier region; anda barrier layer over the channel layer;wherein the back barrier region comprises:a first semiconductor layer configured to form a first potential barrier; anda second semiconductor layer configured to form a second potential barrier in the second semiconductor layer, wherein the second potential barrier is greater than the first potential barrier.

2. A semiconductor structure according to any of claims 1 wherein the second potential is greater than an energy level of the buffer layer.

3. A semiconductor structure according to any preceding claim wherein the second potential barrier is 0.9 eV larger than the first potential barrier.

4. A semiconductor structure according to any preceding claim wherein the second potential barrier is 1.6 eV larger than the first potential barrier.

5. A semiconductor structure according to any preceding claim wherein the second potential barrier is 2 eV larger than the first potential barrier.

6. A semiconductor structure according to any preceding claim wherein the first semiconductor layer comprises InGaN.

7. A semiconductor structure according to claim 6 wherein the first semiconductor layer comprises lnzGai.zN, wherein 0.05 <z <0.15.

8. A semiconductor structure according to any preceding claim wherein the second semiconductor layer comprises Al and N.

9. A semiconductor structure according to claim 8 wherein the second semiconductor layer further comprises Ga.

10. A semiconductor structure according to claim 9 wherein the second semiconductor layer comprises AlyGai.yN, wherein 0.25 <y <1.

11. A semiconductor structure according to claim 10 wherein y >0.75.

12. A semiconductor structure according to any preceding claim wherein the back barrier region further comprises a third semiconductor layer configured to form an intermediate energy level between the first potential barrier and the second potential barrier; wherein an energy of the second potential barrier nearest the third semiconductor layer is larger than the intermediate energy level.

13. A semiconductor structure according to claim 12 wherein the energy of the second potential barrier is greater than the intermediate energy level across a major thickness of the second semiconductor layer.

14. A semiconductor structure according to claim 12 or 13 wherein the third semiconductor layer comprises GaN.

15. A semiconductor structure according to any preceding claim wherein the back barrier region further comprises a fourth semiconductor layer configured to form a second intermediate energy level above a fermi level and maintain a valence band below the fermi level.

16. A semiconductor structure according to claim 15, wherein the second intermediate energy level is less than or equal to the first intermediate energy level.

17. A semiconductor structure according to claim 15 or 16 wherein the fourth semiconductor layer comprises AIGaN,18. A semiconductor structure according to claim 16 or 17 wherein the fourth semiconductor layer comprises AlxGai.xN, wherein 0.02 <x <0.1.

19. A semiconductor structure according to any preceding claim wherein the buffer layer comprises a thickness of less than 500 nm.

20. A semiconductor structure according to any preceding claim wherein the buffer layer is undoped.

21. A semiconductor structure comprising:a substrate;a buffer layer over the substrate;a back-barrier region over the buffer layer;a channel layer over the back-barrier region; anda barrier layer over the channel layer;wherein the back-barrier region comprises:a first semiconductor layer comprising AIGaN;a second semiconductor layer over the first semiconductor layer comprising Al and N;a third semiconductor layer over the second semiconductor layer comprising GaN; anda fourth semiconductor layer over the third semiconductor layer comprising InGaN.

22. A semiconductor device comprising the semiconductor structure according to any preceding claim.

23. A power management device comprising the semiconductor device according to claim 22.

24. A radio frequency module comprising the semiconductor device according to claim 22.

25. An electronic device comprising the power management device according to claim 23 or the radio frequency module according to claim 24.21

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