Thin double side cooled power semiconductor modules

Abstract

The power module package comprises a half bridge configuration of two power MOSFETS M1, M2 connected in series with antiparallel diodes D1, D2. The MOSFETS have their drains connected to conductive tr

Description

Technical Field The present disclosure relates to a power semiconductor module, a method for manufacturing the same and a jig for use in such a method. More particularly, but not exclusively, the present disclosure relates to thin power semiconductor modules with double side cooling for use in applications such as Electric Vehicles or Hybrid Electric Vehicles. Background Power semiconductor modules have been considered as one of the most delicate components in electric drive systems, such as those for electric vehicles (EVs) and hybrid electric vehicles (HEVs). For such applications, there has been an increasing demand for power semiconductor modules with increased power density, improved electrical performance and thermal performance, high reliability and reduced costs. Wideband gap (WBG) power semiconductor devices, such as silicon carbide (SiC) and gallium nitride (GaN) transistors have become increasingly commercially available over recent years, and have been demonstrated to achieve improved switching performance over silicon transistors in high-frequency, high-power and high-temperature applications. Therefore, they are generally attractive for use as switching devices to construct e.g. power semiconductor modules applications with varying voltages, such as converting direct current (DC) to three-phase alternating currents (ACs) and converting singlephase or three-phase ACs to DC in the on-board charging (OBC), or electric control systems of HEVs and EVs. It is known to use double side cooling to directly improve the cooling performance of power semiconductor modules. However, this typically requires wire bonds, conductive track and spacers (or “shims”) to provide interconnections between devices and between devices and external terminals. Currently available double side cooled modules are relatively thick and, due to the interconnection requirements necessitate multiple processing steps during manufacture, increasing the time and cost of doing so. It is an object of the present disclosure, among others, to provide a power semiconductor module, which provides improvements over known power semiconductor modules. Documents with relevance to the field of the disclosure include the following: 10 - US 2015 / 9041183 B2; Low inductive full ceramic SiC power module for high-temperature automotive applications (PCIM Europe digital days 2020; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 07-08 July 2020, Klein et al); - CN 2021 / 112736040 A; and - US 2022 / 0238413 A1 Summary According to a first aspect of the present disclosure, there is provided a power semiconductor module, comprising: a first substrate comprising a plurality of layers, the plurality of layers comprising: a first insulating layer; a first conductive layer arranged on a surface of the first insulating layer; a second substrate comprising a plurality of layers, the plurality of layers comprising: a second insulating layer; a second conductive layer arranged on a surface of the second insulating layer; a first semiconductor die, the first semiconductor die arranged between the first conductive layer and the second conductive layer, wherein a drain terminal of the first semiconductor die is operatively connected to the first conductive layer; and a gate terminal and a source terminal of the first semiconductor die are operatively connected to the second conductive layer via a first interconnection device; a second semiconductor die, the second semiconductor die arranged between the first conductive layer and the second conductive layer, wherein a drain terminal of the second semiconductor die is operatively connected to the second conductive layer; and a gate terminal and a source terminal of the second semiconductor die are operatively connected to the first conductive layer via a second interconnection device; wherein the first conductive layer and the second conductive layer are operatively connected via a plurality of conductive spacers. Advantageously, a power semiconductor module comprising a plurality of semiconductor die bonded between two substrates may be formed at a consistent desired thickness using conductive spacers and interconnection devices (e.g. interconnection boards) using a one-step bonding process e.g. a one-step reflow, soldering or sintering process. Furthermore, as no wire bonds are required, the double side cooled power semiconductor module may be formed with significantly reduced thickness and weight, in part due to the reduction in the thickness of the spacers. The module may also be produced at reduced cost, in part due to the thinner spacer materials and reduced processing time and steps. The reduction in thickness of the module may have other beneficial effects such as reduced parasitic inductance values due to better cancellation of electromagnetic fields in the commutation loops and reduced thermal resistance because of better heat dissipation from the double side cooling surfaces. One or more or each of the substrates may be direct bonded copper (DBG) substrates, direct bonded aluminium substrates (DBA), active metal braised substrates (AMB) or any other suitable substrate technology. The conductive spacers may be ‘thin’ conductive spacers i.e. conductive spacers of 0.1 to 0.3mm in thickness. Thin conductive spacers of 0.1 to 0.3 mm in thickness between the dies and the conductive tracks of the first or second substrates provide sufficient insulation between the different electrodes of the power semiconductor die in, for example, double side cooled modules for EV and HEV applications. It would be understood that any suitable method may be used to operatively connect and / or mechanically attach the terminals of the first and second semiconductor dies to the conductive tracks of the conductive layers, the interconnection devices and / or the conductive spacers and the conductive tracks of the conductive layers to the conductive spacers. For example, the various layers and components of the module may be connected or attached via sintering, soldering, direct copper bonding, or any other suitable means or method. The term “operatively connected” used in the present disclosure encompasses both direct connections and indirect connections (where further element(s) are placed between the two connected elements), suitable for their intended use. For example, for components requiring an electrical connection, the term “operatively connected” may comprise any suitable electrically conductive connection or attachment, while for components requiring a connection to facilitate heat transfer the term may comprise any suitable thermally conductive connection or attachment. The first conductive layer and / or the second conductive layer may comprise a plurality of conductive tracks spaced apart from one another. The first interconnection device may be or comprise a printed circuit board (PCB). The second interconnection device may be or comprise a printed circuit board. The first and / or second interconnection device may be thin. The first and / or second interconnection device may have a thickness less than 1mm for example in the range of 0.05 to 0.5mm, such as from 0.15 to 0.3mm. The first and / or second interconnection device may be a flexible interconnection device e.g. a flexible PCB. The use of a PCB as an interconnection device to match with the pad layouts on the semiconductor chip, instead of using, for example, patterned copper tracks on a conventional DBC, DBA or AMB substrate or the like, provides a cost-effective transition to interconnect the pads of power semiconductor chips, which typical comprise fine passivation gaps, to the conductive tracks of the outer substrates. Using a PCB substrate facilitates the design of the conductive layer on one side of the PCB to match the dimensions of the semiconductor die terminals, and the conductive layer on the other side to be designed to match the dimensions of the conductive track of the first conductive layer (or respective conductive spacers) to which it is affixed. Furthermore, PCBs can typically be more easily and cost effectively manufactured at reduced thicknesses, providing for an overall thinner module assembly. Additionally, using conventional ‘outer’ substrates in combination with interconnection PCBs, instead of, for example low temperature co-fired ceramic (LTCC) substrates may provide for a more cost effective module assembly. A width and / or a length of the first substrate may be different to a width and / or a length of the second substrate. Advantageously, using substrates with unequal (i.e. different) dimensions allows each of the substrates to be supported by a separate plane within a corresponding manufacturing jig. This may provide for a module assembly which has a more consistent and accurate thickness in the assembled module. Wherein a thickness of each of the plurality conductive spacers and a thickness of each of the first and second interconnection devices may be substantially equal. The power semiconductor module may comprise a diode operatively connected in an anti-parallel configuration with the first semiconductor die. The power semiconductor module may comprise a diode operatively connected in an anti-parallel configuration with the second semiconductor die. The power semiconductor module may comprise an encapsulant covering the first and second semiconductor die. The encapsulant may additionally / alternatively cover (e.g. encapsulate) one or more other ‘elements’ of the power semiconductor module. Covering or encapsulating these elements provides both good insulation and additional mechanical support to the elements improving the strength and thermo-mechanical reliability of the power semiconductor module. The encapsulant may comprise a moulding compound. The moulding compound may comprise thermally conductive fillers. Accordingly, the encapsulant must be sufficiently hard to provide the necessary support and thermo-mechanical reliability i.e. not comprise a soft silicone gel. As compared to a conventional technique which uses a plastic housing and silicone gel as the encapsulant, using the moulding compound as the encapsulant reduces the volume of the power semiconductor module (thus increasing the power density of said module) and ensures sufficient insulating and creepage distances between the conductive tracks and between the terminals of the power semiconductor module (when present) with smaller or similar dimensions or volumes. Further, the moulding compound provides additional mechanical support to the power semiconductor module, and hence improves the structural strength and thermo-mechanical reliability of the power semiconductor module. The power semiconductor module may comprise a plurality of control and / or power terminals. The plurality of control and / or power terminals may be operatively connected to at least one of the plurality of conductive tracks of the first conductive layer. The plurality of control and / or power terminals may extend in a substantially parallel direction with respect to the first insulating layer. At least one of the plurality of control and / or power terminals may be made of or otherwise comprise a material with a coefficient of thermal expansion which matches the coefficients of thermal expansion of a material forming or comprising the first and / or second substrate. Advantageously, matching coefficients of thermal expansion may mitigate or eliminate the stress and strain developments in the joints between terminals and the substrate to which they are bonded / attached. Accordingly, the thermo-mechanical reliability of the power semiconductor module is improved. The power semiconductor module may comprise a third conductive layer arranged on a further surface of the first insulating layer, wherein the further surface is an opposite surface to the surface on which the first conductive layer is arranged. The power semiconductor module may comprise a fourth conductive layer arranged on a further surface of the second insulating layer, wherein the further surface is an opposite surface to the surface on which the second conductive layer is arranged. The additional conductive layer(s) provide a beneficial means to electrically connect the outer layers of the semiconductor module to a heat sink or cold plate and or to ground the outer layer of the module (e.g. for safety reasons). The power semiconductor module may comprise comprising a thermal management device. The first and / or second insulating layer may be operatively connected to the thermal management device. The thermal management device may be a heat sink or a cold plate. The power semiconductor module may comprise a plurality of holes in the first and / or second conductive layers. The plurality of holes may be configured so as to assist with the alignment of bonding material used to bond one or more or each of the semiconductor dies, conductive spacers, terminals and / or interconnection devices to the first and / or second conductive layers during manufacture. The plurality of holes may be configured so as to absorb excessive boding materials during manufacture. According to a second aspect of the present disclosure, there is provided a power semiconductor system comprising a plurality of power semiconductor modules according to the first aspect. The power semiconductor system may be constructed with a plurality of semiconductor modules. For example, a plurality of half bridge switches may be combined to form single phase or multiple phase half bridge switches for handling high currents and can hence have currents evenly distributed between the paralleled power semiconductor die because each die or each pair of die are assembled in the same packaging structure and hence have conducting path or loop exactly the same as each other. The plurality of power semiconductor modules may comprise one or more of a common first and / or second insulating layer, a common conductive layer or layers or a common heatsink or cold plate. In implementations comprising a common insulating layer or conductive layer, the common insulating layer or conductive layer may be attached to a common heat sink or cold plate or other thermal management device. According to a third aspect of the present disclosure, there is provided an electric vehicle comprising the power semiconductor system according to the second aspect. According to a fourth aspect of the present disclosure, there is provided a hybrid electric vehicle comprising a power semiconductor system according to the second aspect. According to a fifth aspect of the present disclosure, there is provided a jig for use in the manufacture of the power semiconductor module according to the first aspect, the jig comprising: a cavity, the cavity comprising: a first plane at a first depth, the first plane configured to receive the second substrate; and a second plane at a second depth, the second plane configured to receive the first substrate, wherein the second depth is shallower than the first depth; The jig may comprise a third plane at a third depth. The third plane may comprise one or more slots extending from the cavity on the third plane. Each of the one or more slots may be configured to receive a terminal. The third depth may be shallower than the first depth and / or deeper than the second depth. The jig may comprise an object or object of weight. The object may be configured to be disposed into the first cavity. The surface area of the object may be substantially the same as the surface area of the cavity. The object may be dimensioned to fit tightly into the cavity, and as such providing a means of applying a more even distribution of pressure across the module assembly once placed into the jig. The application of the object during the bonding process (e.g. during the reflow soldering or pressure-less sintering process) in combination with height constrained by the first and second planes of the cavity of the jig will ensure that the required thickness of the assembled module is consistently and accurately achieved. A width and / or a length of the first plane may be different to a width and / or a length of the second plane. According to a sixth aspect of the present disclosure, there is provided a method of manufacturing the power semiconductor module according to the first aspect, the method comprising: providing the jig of the fifth aspect; disposing the second substrate into the cavity, onto the first plane, wherein the second conductive layer is arranged uppermost; disposing the plurality of conductive spacers, the second semiconductor die and the second interconnection device onto the second conductive layer; disposing the first interconnection device onto the second semiconductor die; disposing the first semiconductor die onto the second interconnection device; disposing the first substrate into the cavity, onto the second plane, wherein the first conductive layer is arranged lowermost; bonding the plurality of conductive spacers, the first and second semiconductor die and the first and second interconnection devices between the first and second substrate to form the power semiconductor module. The bonding may comprise a reflow soldering process. The bonding may comprise a pressure-less sintering process. The bonding may comprise a pressure assisted sintering process. Advantageously, using a jig with two or more supporting planes plus the pressure applied by an object with specified size and weight and / or a sintering press can be used to achieve the required and consistent thickness between the two substrates. The jig also enables a manufacturing method involving applying pressure in only one direction providing a much simpler manufacturing method than those employed in existing methods. The bonding may comprise a one-step process. The method may comprises disposing, before the bonding step, an object into the cavity. The method may comprise, disposing one or more terminals into one or more or each of the one or more slots. Where appropriate any of the features described above in relation to one aspect of the present disclosure may be applied to any other aspect of the disclosure. It would also be understood that the terms “first”, “second”,... , ’’sixth” are used in the present disclosure to label the relevant elements for the ease of description, and are not intended to limit or imply any limitations to the sequence or locations of the relevant elements. Brief Description of the Drawings In order that the disclosure may be more fully understood, a number of embodiments of the disclosure will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 schematically illustrates a circuit diagram of a power semiconductor module according to an embodiment of the present disclosure; Figure 2 illustrates a top perspective view of a power semiconductor module according to an embodiment of the present disclosure which implements the circuit diagram of Figure 1; Figure 3 illustrates a bottom perspective view of the power semiconductor module of Figure 2; Figure 4 illustrates a side view of the power semiconductor module of Figure 2; Figure 5 illustrates a top perspective view of the power semiconductor module of Figure 2 with the encapsulant being invisible. Figure 6 illustrates a top perspective view of the power semiconductor module of Figure 5 with the top substrate being invisible. Figure 7 illustrates a top perspective view of the power semiconductor module of Figure 6 with the terminals being invisible. Figure 8 illustrates a top perspective view of the power semiconductor module of Figure 7 with part of the bonding material layers being invisible. Figure 9 illustrates a top perspective view of the power semiconductor module of Figure 8 with the second semiconductor die, second diode, second printed circuit board and part of the conductive spacers being invisible. Figure 10 illustrates a top perspective view of the power semiconductor module of Figure 9 with a further part of the bonding material layers being invisible. Figure 11 illustrates a top perspective view of the power semiconductor module of Figure 10 with the first semiconductor die, first diode and first printed circuit board being invisible. Figure 12 illustrates a top perspective view of the first substrate of the power semiconductor module of Figure 2. Figure 13 illustrates a bottom perspective view of the second substrate of the power semiconductor module of Figure 2 with a part of the bonding materials layer present. Figure 14 illustrates a bottom perspective view of the second substrate of the power semiconductor module of Figure 2. Figure 15 illustrates a top perspective view of the second printed circuit board of the power semiconductor module of Figure 2. Figure 16 illustrates a bottom perspective view of the second printed circuit board of the power semiconductor module of Figure 2. Figure 17 illustrates a top perspective view of the first printed circuit board of the power semiconductor module of Figure 2. Figure 18 illustrates a bottom perspective view of the first printed circuit board of the power semiconductor module of Figure 2. Figure 19 illustrates a perspective view of the gate / source side of the first and second semiconductor dies of the power semiconductor module of Figure 2. Figure 20 illustrates a cross-sectional view of the power semiconductor module of Figure 2 along dash line AB of Figure 5; Figure 21 illustrates a top perspective view of a jig for manufacturing a power semiconductor module according to an embodiment of the present disclosure. Figure 22 illustrates a top perspective view of the jig of Figure 21 with the object of weight removed. Figure 23 illustrates a plan view of the jig of Figure 21 with the object of weight removed. Figure 24 illustrates an exploded view of the jig of Figure 21 and the corresponding power semiconductor module of Figure 5. Figure 25 shows process steps of a method for manufacturing a power semiconductor module according to an embodiment of the present disclosure. In the figures, like parts are denoted by like reference numerals. It will be appreciated that the drawings are for illustration purposes only and are not drawn to scale. Detailed Description of the Preferred Embodiments Figure 1 shows a circuit diagram of a power semiconductor module 100 according to an embodiment of the present disclosure. The power semiconductor module 100 comprises half bridge switch comprising a high side device M1 and a low side device M2 electrically connected in series between a DC+ (power) terminal 11 and a DC- (power) terminal 12, and an AC output terminal 13 electrically connected there between. The high side device M1 comprises three control terminals S1 (17), G1 (18), and D1(19). The low side device M2 comprises three further control terminals S2 (14), G2 (15) and D2(16). Diodes D1 and D2 are electrically connected in anti-parallel to high and low side devices M1 and M2. Figure 1 further shows a number of typical parasitic parameters. In the parasitic inductance parameters, L+ represents the effective parasitic inductance between the DC+ terminal and the middle interconnecting point of high and low side devices M1 and M2 (or diodes DI1 and DI2). L represents the effective parasitic inductance between the DC- terminal and the middle interconnecting point of high and low side devices M1 and M2 (or diodes DI1 and DI2). Lac represents the effective parasitic inductance between the AC terminal and the middle interconnecting point of high and low side devices M1 and M2 (or diodes DI1 and DI2). Lgi represents the effective parasitic inductance from the G1 terminal 18 to the S1 terminal via the high side device M1. Lg2 represents the effective parasitic inductance from the G2 terminal 15 to the S2 terminal via the low side device M2. In the parasitic capacitance parameters, C+ represents the effective parasitic capacitance between the drain electrode of the high side device M1 (or the cathode of the diode DI1) and ground. C- represents the effective parasitic capacitance between the source electrode of the low side device M2 (or the anode of the diode DI2) and ground. Cac represents the effective parasitic capacitance between the source electrode of the high side device M1, the anode of the diode D11, the drain electrode of the low side device M2, or the cathode of the diode DI2 and ground. The diodes DI1 and DI2 are employed in the case where using the body diode of each of the high and low side devices M1 and M2 as the freewheeling diode leads to high reverse recovery loss. In the case where the body diode of each of the high and low side devices M1 and M2 may be effectively employed as the freewheeling diode, the diodes DI1 and DI2 may be omitted. In the example of Figure 1 the high and low side devices M1 and M2 are SiC metal-oxide-semiconductor field-effect transistor (MOSFET) chips. However, the high and low side devices M1 and M2 may be replaced with other wide bandgap semiconductor power chips such as GaN transistor chips. Figures 2 to 20 schematically illustrate a power semiconductor module 100 according to a first embodiment of the present disclosure which implements the circuit diagram of Figure 1. Elements of the power semiconductor module 100 which implement elements of the circuit diagram of Figure 1 are identified using the same labels. As can be seen from Figures 3, 10 and 11, the drain of the high side device M1, and the cathode of the high side diode chip DI1, are attached with two joints B21 and B22, on the conductive track 312, of the bottom substrate with an insulating ceramic layer 30, and a back conductive plate 31. As can be seen from Figures 5 to 9 and 13, the source pad of M1 is connected with a conductive spacer 46, and two joints B36 and B46, to the conductive track 211, of the top substrate with an insulating ceramic layer 20, and a top conductive plate 21. The anode pad of DI1 is also connected to the conductive track 211 of the top substrate with another conductive space 45, and two joints B35 and B45. The auxiliary source and gate pads (AS and G as shown in Figure 19) of M1 are connected with a first small flexible PCB and six joints B51 to B56, to the three conductive tracks 211 to 213, of the top substrate. As shown in Figures 15 and 16, the first small flexible PCB consists of conductive pads 51 to 53 on the top side, insulating layer 50 in the middle, and conductive pads 54 to 56 on the bottom side. The conductive pads 51 to 53 are electrically connected to the conductive pads 54 to 56 with the vias 57 to 59 through the insulating layer 50 respectively. The low side device M2, and low side diode chip D2 are flipped. As can be seen from Figures. 7, 8 and 13, the source of M2 is attached with a joint B24, and the cathode of D2 is attached with a joint B23, both to the conductive track 211 of the top substrate. As can be seen from Figures 8 to 11, the source pad of M2 is connected with a conductive spacer 43, and two joints B33 and B43 on the conductive track 313 of the bottom substrate. The anode pad of DI2 is also connected to the conductive track 313 of the bottom substrate with another conductive spacer 44, and two joints B34 and B44. The auxiliary source and gate pads (AS and G as shown in Figure 19) of M2 are connected with a second small flexible PCB and six joints B61 to B66 to the three conductive tracks 315, 316 and 313 of the bottom substrate. As shown in Figures 17 and 18, the second small flexible PCB consists of conductive pads 61 to 63 on the bottom side, insulating layer 60 in the middle, and conductive pads 64 to 66 on the top side. The conductive pads 61 to 63 are electrically connected to the conductive pads 64 to 66 with the vias 67 to 69 through the insulating layer 60 respectively. As can be seen from Figures 7 to 9 and 13 the conductive spacers 41,42 and 47 to 49 are bonded on the conductive tracks 311, 314, 319, 318 and 317 respectively of the bottom substrate with joints B41, B42, B47 to B49, and are bonded to the conductive tracks 211, 211, 212, 213 and 211 respectively of the top substrate with joints B31, B32 and B37 to B39. As can be seen from Figures 6 to 8, all the nine terminals 11 to 19, are bonded on the conductive tracks 312 to 319 and 312, of the bottom substrate with joints B11 to B19. In the above physical structure implementing the topology of power module described in Figure 1, the conducting path from the DC+ to AC is formed by: terminal 11^ joint B11 -> conductive track 312 -> joint B21 -> high side device M1 -> joint B46 -> conductive spacer 46 -> joint B36 -> conductive track 211^ joint B32 -> conductive spacer 42 -> joint B42 conductive track 314 >joint B13 >terminal 13. The conductive path from the AC to DC+ is formed by: terminal 13^ joint B13 conductive track 314 joint B42 -> conductive spacer 42 -> joint B32 -> conductive track 211 -> joint B35 -> conductive spacer 45 -> joint B45 -> high side diode chip DI1 -> joint B22 -> conductive track 312 -> joint B11 -> terminal 11. The conducting path from the AC to DC- is formed by: terminal 13 joint B13 conductive track 314 joint B42 -> conductive spacer 42 -> joint B32 conductive track 211 -> joint B24 -> low side device M2 joint B33 -> conductive spacer 43 -> joint B43 -> conductive track 313 -> joint B12 -> terminal 12. The conductive path from the DC- to AC is formed by: terminal 12 joint B12 conductive track 313 >joint B44 conductive spacer 44 >joint B34 low side diode chip DI2 -4- joint B23 -> conductive track 211^ joint B32 -> conductive spacer 42 joint B42 -> conductive track 314 -> joint B13 terminal 13. The conducting path from the port D1 to drain of M1 is formed by: terminal 19 -> joint B19 conductive track 312 joint B21 -> drain of high side device M1. The conducting path from the port G1 to gate pad of M1 is formed by: terminal 18^ joint B18 conductive track 319 joint B47 -> conductive spacer 47 -> joint B37 -> conductive track 212 -> joint B52 -> conductive pad 52 -> via 58 -> conductive pad 55 -> joint B55 -> gate pad G of high side device M1. The conducting path from the port S1 to a first auxiliary source pad of M1 is formed by: terminal 17 joint B17 conductive track 318 -> joint B48 -> conductive spacer 48 —> joint B38 -> conductive track 213 -> joint B53 -> conductive pad 53 -> via 59 -> conductive pad 56 -> joint B56 -> the first auxiliary source pad AS of high side device M1. The connection of a second auxiliary source pad AS of M1 to the conductive track 211 of the top substrate is not necessary, and thus the two joints B51 and B54 or either of them may be used or ignored. The conducting path from the port D2 to drain of M2 is formed by: terminal 16^- joint B16 -> conductive track 317 -> joint B49 -> conductive spacer 49 -> joint B39 -4-conductive track 211 joint B24 -> drain side of low side device M2. The conducting path from the port G2 to gate pad of M2 is formed by: terminal 15 -> joint B15 -> conductive track 316 -> joint B62 -> conductive pad 62 -> via 68 conductive pad 65 -> joint B65 -> gate pad G of low side device M2. The conducting path from the port S2 to a first auxiliary source pad of M2 is formed by: terminal 14 >joint B14 conductive track 315 >joint B61 -4- conductive pad 61 via 67 conductive pad 64 joint B64 -> first auxiliary source pad AS of low side device M2. The connection of a second auxiliary source pad AS of M2 to the conductive track 313 of the bottom substrate is not necessary, and thus the two joints B63 and B66 or either of them may be used or ignored. In the above physical structure implementing the topology of the power module 100 described in Figure 1, both the bottom substrate and the top substrate may be chosen from the conventional DBC, DBA or ABM substrates. In these DBG, DBA or ABM substrates, the insulating layers 20 and 30 are 0.2 to 1 mm thick aluminium, aluminium nitride or silicon nitride ceramic tiles, and the conductive layers on both sides of the ceramic tiles are 0.1 to 1 mm thick pure copper, pure aluminium, copper- molybdenum alloy, copper-tungsten alloy, or other pure metals or alloys with similar thermal, electrical and thermo-mechanical properties as would be apparent to those skilled in the art. The pure metal or alloy layer on one side of each of the substrates is configured to form the conductive tracks to attach the MOSFET and diode chips, bond the conductive spacers, small flexible PCBs and terminals and / or realize the necessary interconnections. As shown in Figure 12, a slot 321 is added between the conductive tracks 311 and 312 of the bottom substrate. This is to reduce the size of the conductive track 312 and hence achieve the same or similar values between the parasitic capacitance due to the conductive track 312 and the conductive plate 31 against the insulating ceramic layer 30, and the parasitic capacitance due to the conductive track 313 and the conductive plate 31 against the insulating ceramic layer 30. If the conductive plate 31 is electrically connected to a cold plate or a heat sink which is grounded (e.g. for safety) the above two parasitic capacitance values correspond to C+ and C- shown in Figure 1. As shown in Figure 14, two slots 221 and 222 are further added in the conductive track, 211 of the top substrate. This is to guide the current flows and hence achieve the same or similar values between the parasitic inductance of the conducting paths from the DC+ terminal to the middle interconnecting point of the two MOSFET chips M1 and M2 or the two diode chips DI1 and DI2, and the parasitic inductance of the conducting path from DC- terminal to the middle interconnecting point of the two MOSFET chips M1 and M2 or the two diode chips DI1 and DI2. These two parasitic inductance values correspond to L+ and L- shown in Figure 1. Of the DBC, DBA and ABM substrates, silicon nitride based ABM substrates are particularly beneficial for high performance and high reliability applications. This is because silicon nitride based ABM substrates have high mechanical strength and can withstand high mechanical stresses for sealing or mounting the double side cold plates and / or heat sinks and also have good thermo-mechanical reliability. The narrowest conductive track and the narrowest gap between the conductive tracks which can be achieved on the DBC, DBA and substrates are both typically 0.8 mm in width while the gate pads are typical 0.3 mm x 0.6 mm in size and the passivation gaps between the gate pads and source pads may be 0.1 to 0.2 mm in width on the MOSFET chips M1 and M2. Therefore, the patterns of the conductive tracks in the bottom and top substrates cannot cost-effectively be made to match with the layout of the gate, source and auxiliary source pads on the MOSFET chips M1 and M2. This is the reason why the two small flexible PCBs shown in Figures 15 to 18 are especially used to interconnect the gate and auxiliary pads of the two MOSFET chips M1 and M2 to the corresponding conductive tracks of the two substrates. The two smaller flexible PCBs are exactly the same as each other in structure, but are placed in different orientation in the module 100. The conductive pads 51 to 56, conductive vias 57 to 59, and insulating layer 50 of one flexible PCB are exactly the same as the conductive pads 61 to 66, conductive vias 67 to 69, and insulating layer 60 of the other flexible PCB, respectively. The conductive pads 51 to 53 or 61 to 63 should be designed to have insulating gaps of at least 0.4 mm between them and can be connected to the three corresponding conductive tracks of the top or bottom substrates which have insulating gaps typically of 0.8 mm or wider. The conductive pads 54 to 56 or 64 to 66 should be designed to have insulating gaps of at least 0.4 mm between them and can be connected to the three corresponding auxiliary source and gate pads of the MOSFET chip M1 or M2 which have passivation gaps of 0.1 to 0.2 mm. The conductive vias, 57 to 59 or 67 to 69 electrically connecting the conductive pads 51 to 53 or 61 to 63 to the conductive pads 54 to 56 or 64 to 66 at the two sides of the insulating layer 50 or 60 may be 0.1 to 0.4 mm in diameter. The conductive pads 51 to 56 or 61 to 66, are normally made of 0.01 to 0.2 mm thick copper, and the insulating layer, 50 or 60 may be made of 0.01 to 0.2 mm thick polyimide or other polymer which can withstand the processing temperature to assemble the power module 100. Such small flexible PCBs can be readily and cost-effectively produced with the well-established and mature PCB manufacturing technology. As shown in Figure 20, if the gate pad G of the low side device M2 is directly bonded on the conductive track 316 of the bottom substrate without the small flexible PCB, the spreading of the bonding material, e.g. B62 or B65, on the conductive track 316 would lead to bridging and thus short circuit between the gate pad G and the adjacent auxiliary source pad AS and source pad S (source pad S is not shown in Figure 20). Therefore, the two small flexible PCBs can be used as cost-effective transition to bond the gate and auxiliary source pads to the conductive tracks of the top or bottom substrate. As in many commercially available MOSFET modules, the auxiliary source pads on the two MOSFET chips M1 and M2 may not be used, and the ports S1 and S2 may be connected to the source pads of the two MOSFET chips M1 and M2. In this case, it will be appreciated that the conductive pads 51, 53, 54 and 56 or 61, 63, 64 and 66, and the conductive vias 57 and 59 or 67 and 69 may be eliminated, and thus the two flexible PCBs may beneficially be made even smaller. Accordingly, the conductive tracks 213 and 211 of the top substrate should be merged together and the conductive tracks 315 and 313 of the bottom substrate should be merged together. The conductive spacers 43 to 46, should have a thickness of 0.05 to 0.3 mm which is equal to or very close to the total thickness of the three layers 51 to 53, 50 and 54 to 56 or 61 to 63, 60 and 64 to 66 of the two small flexible PCBs. The conductive spacers 41, 42 and 47 to 49 should have a thickness of 0.15 to 0.5 mm which is equal to or very close to the value of the thickness of the conductive spacers 43 to 46 plus the thickness of the MOSFET chip M1 or M2 or the diode chip DI1 or DI2 and the thickness of the joint B33, B34, B45 or B46. All the conductive spacers 41 to 49 may be made of pure copper, pure aluminium, copper- molybdenum alloy, copper-tungsten alloy, or other pure metals or alloys, or metal-matrix composite such as copper-graphite composite and aluminiumcarbon fibre composite, or other materials with similar thermal, electrical and thermomechanical properties. All the power terminals 11 to 13, and signal / control terminals 14 to 19, may be made of materials similar to those of the conductive spacers 41 to 49 with high thermal conductivity and high electrical conductivity. All the joints B11 to B19, B21 to B24, B31 to B39, B41 to B49, B51 to B56 and B61 to B66, used to bond all the terminals, attach all the MOSFET and diode chips, bond all the conductive spacers and bond the two flexible PCBs are typically 0.02 to 0.1 mm in thickness and can be formed using lead-free solder alloys, such as tin-silver, tin-copper, tin-silver-copper, tin-antimony, bismuth-silver solder alloys. Alternatively, they can be formed with sintering technologies, such as silver sintering and copper sintering technologies. It should be noted that all the joints can be formed with the same solder alloy or several solder alloys with different melting points, or combined sintering technology and solder alloys. The lead-free solder joints are preferred for low cost applications where the junction temperatures of the semiconductor chips are in general lower than 150 °C. The sintered silver or copper joints are preferred for high temperature and high reliability applications where the junction temperatures of the semiconductor chips may be higher than 150 °C. It will be appreciated that the conductive spacer 41 and the two joints B31 and B41 are not necessary but may be included to provide additional mechanical support to the assembled power module. Molding compound 70 is used as the encapsulant to fill all the gaps in the module after bonding all the terminals, chips, conductive spacers and flexible PCBs between the top and bottom substrates. In comparison with silicone gel, molding compound can eliminate the use of plastic housing and hence reduce the volume of the power module and / or provide better insulation with similar dimensions or volume of the power module. Furthermore, it can provide additional mechanical support to all the bonded terminals, chips, conductive spacers and flexible PCBs and thus improve the strength and thermomechanical reliability of the power module. The molding compound may be epoxy, other polymer based materials, or inorganic materials with high insulating strength and curing temperatures at least 20°C lower than the lowest melting point of the solder alloys used to bond all the terminals, chips, conductive spacers and flexible PCBs. Preferably, a polymer-based molding compound may contain fillers such as silica, aluminium nitride or boron nitride fillers having high thermal conductivity and low CTEs to improve the thermal conductivity and constrain the CTE of the molding compound. The top surface of the top conductive plate 21 of the top substrate and the bottom surface of the bottom conductive plate 31 of the bottom substrate can be used as double side cooling surfaces of the power module 100. They can be mounted with thermal interface material (TIM) and / or bonded with lead-free solder alloys or sintering technologies between double side cold plates and / or heat sinks, or be in direct contact with, or otherwise thermally coupled to, the coolant from single or double side heat sinks. The use of small flexible PCBs as interconnection devices reduces or eliminates any wire bonds in the module, and 0.05 to 0.3 mm thick conductive spacers 43 to 46 plus 0.02 to 0.1 mm thick joints B34 to B36 and B43 to B46 are sufficient to provide the insulation between the different electrodes of the power semiconductor chips with voltage ratings of 650 to 1200V (e.g. for EV and HEV applications). Therefore, the power semiconductor half bridge switch module 100 can be categorized as one thin double side cooled power semiconductor module. Figure 25 illustrates processing steps of a method 1000 for manufacturing a power module (e.g., the power semiconductor module 100) using a simple jig 80 (provided at step S1100) to bond MOSFET and diode chips, conductive spacers and small flexible PCBs between two substrates and is described with reference to Figures 21 to 24. Figure 21 is a perspective view of the top of the assembly where all the MOSFET and diode chips, conductive spacers, small flexible PCBs and terminals (plus the corresponding bonding material layers) are placed between the top and bottom substrates of the module 100 (as shown in exploded view of Figure 24). The module 100 is then placed face down into the cavity of the jig 80 and an object of weight 90 is then placed into the cavity of the jig 80 on top of the module 100. As step S1200, and as shown in Figures 21 to 24, the top substrate is placed into the jig 80 such that the large surface of the conductive plate 21 is in contact with the plane 801, and the position of the top substrate is constrained with the four planes 803 to 806 in the jig 80. At step S1300 the terminals 11 to 19 are placed into the jig 80 and respectively constrained by the slots 81 to 89 of the jig 80. The terminals 11 to 19 may be placed into the jig 80 prior to, simultaneously or following the placement of the top substrate. Alternatively the terminals may be omitted entirely and / or attached, soldered or otherwise bonded onto the substrate after the module is removed from the jig 80. The bonding materials for forming the joints B11 to B19 are then placed on the corresponding positions of the terminals 11 to 19 proximal to the top substrate. The bonding materials for forming the joints B23, B24, B31, B32, B35 to B39, and B51 to B53 are placed on the corresponding conductive tracks of the top substrate. The holes 230s with diameter typically of 0.6 mm in the conductive tracks of the top substrate (see for example Figure 14) not only provide the references to position these bonding materials, but also adsorb excessive bonding materials to reduce the possibility of causing bridging and short circuits between the different electrodes of the power semiconductor chips during the subsequent reflow soldering or sintering process used to bond the final assembly together. After placing the bonding materials for forming the joints B23, B24, B31, B32, B35 to B39, and B51 to B53, the conductive spacers 41, 42 and 45 to 49, MOSFET chip M2, diode chip DI2, and the first small flexible PCB (with the insulating layer 50) are placed on the corresponding bonding materials. From the perspective view of the top of the jig 80, the chips M2 and DI2 are placed with their source pads and anode pads on the top side, and the first small flexible PCB is placed with its conductive pads 51 to 53 on the bottom side and its conductive pads 54 to 56 on the top side. Subsequently the bonding materials for forming the joints B33 and B64 to B66 on the chip M2, for forming joint B34 on chip DI2, for forming joints B41, B42, and B45 to B49 on the conductive spacers 41, 42 and 45 to 49, and for forming the joints B54 to B56 on the conductive pads 54 to 56 of the small flexible PCB with the insulating layer 50 are placed such that they align with their respective joints. Then the MOSFET chip M1 is placed with its auxiliary source and gate pads in contact with the bonding materials for forming joints B54 to B56, and its source pad in contact with the bonding material for forming joint B46. The diode chip DI1 is placed with its anode pad in contact with the bonding material for forming the joint B45. The conductive spacers 43 and 44 are respectively placed on the bonding materials for forming the joints B33 and B34, and the second small flexible PCB (with the insulating layer 60) is placed with its conductive pads 64 to 66 on the bonding materials for forming the joints B64 to B66. Subsequently the bonding materials for forming the joints B21 and B22 on the cathode side of the chip DI1 and the drain side of the chip M1, for forming the joints B43 and B44 on the conductive spacers 43 and 44, and for forming the joints B61 to B63 on the conducive pads 61 to 63 of the small flexible PCB with the insulating layer 60 are placed such that they align with their respective joints. At step S1400, after placing the bonding materials for forming all the joints, the bottom substrate is then placed face down with its conductive tracks in contact with the bonding materials for forming the joints B11 to B19, B21, B22, B41 to B44, B47 to B49 and B61 to B63. Around the two long edges of the bottom substrate, the surfaces of the conductive tracks are also in contact with the plane 802 in the jig 80, and the position of the bottom substrate is further constrained with the four planes 803, 808, 805 and 807 in the jig 80. The holes 330s with diameter typically of 0.6 mm in the conductive tracks of the bottom substrate (see for example Figure 12) are also added to adsorb excessive bonding materials to reduce the possibility of causing bridging or short circuit between the different electrodes of the power semiconductor chips during the subsequent reflow soldering or sintering process used to bond the final assembly together. The bonding materials for forming all the joints may be in the form of preforms and / or pastes. In the cases of pastes, they may be placed by dispensing, or those bonding materials in contact with the conductive tracks of the top or the bottom substrates may be printed on the conductive tracks before placing the top or bottom substrate. All the substrates, terminals, MOSFET and diode chips, conductive spacers, flexible PCBs and bonding materials may be placed in the jig 80 manually or automatically using machines such as automatic pick up and place, dispensing and printing machines. At step S1500, after all of the elements of the assembly are placed into the jig 80, an object of weight 90, may be manually or automatically placed on the top of the conductive plate 31 of the bottom substrate before putting the assembly through a reflow soldering or sintering process. The object of weight 90 may have a size the same as that of the insulating layer 30 of the bottom substrate, and thus its position may also be constrained with the four planes 803, 808, 805 and 807 in the jig 80. This object of weight 90 may be made of copper, molybdenum and tungsten or other metals or alloys with similar weight and, for example, a thickness of 2 mm or more. A thicker and heavier object of weight 90 can also be used. If all the joints B11 to B19, B21 to B24, B31 to B39, B41 to B49, B51 to B56 and B61 to B66 are formed with lead-free solder alloys, the jig 80 may be made of a material such as graphite and / or aluminium or other materials which have similar thermal conductivity and poor wetability with the bonding materials for forming all the joints. After all the substrates, terminals, MOSFET and diode chips, conductive spacers, flexible PCBs, bonding materials and object of weight 90 are placed in the jig 80, they may be moved into a reflow oven or furnace to produce all the joints using a one-step reflow soldering process with a peak temperature in the range of, for example, 230 to 300 °C. If all the joints B11 to B19, B21 to B24, B31 to B39, B41 to B49, B51 to B56 and B61 to B66 are formed with silver or copper sintering technologies, the jig 80 may be made of a material such as aluminium or other materials which has similar or higher thermal conductivity and mechanical strength and poor wettability with the silver or copper sintering materials for forming all the joints. If a pressure-less sintering process is employed, after all the substrates, terminals, MOSFET and diode chips, conductive spacers, flexible PCBs, bonding materials and object of weight are placed in the jig 80, they may be moved into a sintering oven or furnace to produce all the joints with a peak temperature in the range of, for example, 240 to 300 °C. If a pressure-assisted sintering process is employed, after all the substrates, terminals, MOSFET and diode chips, conductive spacers, flexible PCBs, bonding materials, the object of weight 90 may still be placed or alternatively may be omitted. In any case, the assembly may be moved into a sintering press where, for example, 0.05 to 2 mm thick compliant materials such as PTFE and silicone rubber or other materials with similar Young’s modulus may be placed under the jig 80 and / or over the object of weight 90 or the conductive plate 31 of the bottom substrate. All of the joints B11 to B19, B21 to B24, B31 to B39, B41 to B49, B51 to B56 and B61 to B66 may be formed using a pressure-assisted sintering process with an average pressure of, for example, 1 to 60 MPA on all the joints and a peak temperature in the range of, for example, 200 to 300 °C. In the example power semiconductor half bridge switch module 100, the length of the bottom substrate Lb (as shown in Figure 12), is the same as the length of the top substrate Lt (as shown in Figure 14), while the width of the bottom substrate Wb (as shown in Figure 12), is wider than the width of the top substrate Wt (as shown in Figure 14). Therefore, the application of the object of weight 90 during the reflow soldering process or the pressure-less sintering process or the application of the pressure by the sintering press during the pressure-assisted sintering process in combination with height constrained by the planes 801 and 802 of the jig 80 will ensure that the required thickness of the assembled module is consistently and accurately achieved. However, as will be appreciated by those skilled in the art, for this purpose the length of the bottom substrate Lb may be shorter than the length of the top substrate Lt, while the width of the bottom substrate Wb is wider than the width of the top substrate Wt. Alternatively, the length of the bottom substrate Lb may be longer than the length of the top substrate Lt, while the width of the bottom substrate Wb may be wider than, the same as or even narrower than the width of the top substrate Wt. Various other modifications to the structure of module 100, and method 1000 of manufacturing thereof, will be apparent to those skilled in the art. For example, as long as the corresponding spaces are not obscured, all the terminals, MOSFET and diode chips, conductive spacers, flexible PCBs and bonding materials for forming all the joints may be placed in orders which are different from the placing order described above. The structure of the module 100 may be modified to include wire bonds and comparatively thick conductive spacers (for example to accommodate said wire bonds) as the interconnection devices and / or links of the semiconductor chips. In this case, the thickness and weight, thermal and electrical performance of the modules may be poorer than the thin double side cooled power modules described above. However, the modules may still be designed with substrates having different sizes in combination with a jig with two or more supporting planes in addition to the pressure applied by an object of weight or a sintering press. As such an efficient one-step reflow soldering process or sintering process and the required and consistent thickness of the assembled modules may still be achieved. The structure of the module 100 may be alternatively / additionally modified to replace the smaller PCBs and / or the conventional DBC, DBA or AMB top and / or bottom substrates with LTCC substrates and / or with conventional DBC, DBA or AMB substrates with fine conductive tracks or features added by additional manufacturing processes (for example additional electro-plating or selective sintering processes). In this case, the LTCC substrates or the alternative substrates with the added fine conductive tracks or features may be more expensive than the conventional DBC, DBA or AMB substrates plus the smaller PCBs described above. However, the modules may still be designed with substrates having different sizes in combination with a jig with two or more supporting planes in addition to the pressure applied by an object of weight or a sintering press. As such an efficient one-step reflow soldering process or sintering process and the required and consistent thickness of the assembled modules may still be achieved. The manufacturing method 1000 may be alternatively / additionally modified to replace the jig 80 with a plurality of dedicate jigs and / or the one-step reflow soldering or sintering process with a plurality of reflow soldering or sintering processes. In this case, the process to manufacture the thin double side cooled power semiconductor modules may be less efficient. However, the small flexible PCBs and thin conductive spacers in combination with the conventional DBC, DBA or AMB substrates will be considerably cheaper than the LTCC substrates or the alternative substrates with the added fine conductive tracks or features described above. The terms “having”, “containing”, “including”, “comprising” and the like are open and the terms indicate the presence of stated structures, elements or features but not preclude the presence of additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. 5 The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘top’, ‘bottom’, ‘left’, ‘right’ etc. are made with reference to conceptual illustrations of a power semiconductor module, such as those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a power 10 semiconductor module when in an orientation as shown in the accompanying drawings. Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able 15 to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

1. A power semiconductor module, comprising:a first substrate comprising a plurality of layers, the plurality of layers comprising:a first insulating layer;a first conductive layer arranged on a surface of the first insulating layer;a second substrate comprising a plurality of layers, the plurality of layers comprising:a second insulating layer;a second conductive layer arranged on a surface of the second insulating layer;a first semiconductor die, the first semiconductor die arranged between the first conductive layer and the second conductive layer, wherein a drain terminal of the first semiconductor die is operatively connected to the first conductive layer; and a gate terminal and a source terminal of the first semiconductor die are operatively connected to the second conductive layer via a first interconnection device;a second semiconductor die, the second semiconductor die arranged between the first conductive layer and the second conductive layer, wherein a drain terminal of the second semiconductor die is operatively connected to the second conductive layer; and a gate terminal and a source terminal of the second semiconductor die are operatively connected to the first conductive layer via a second interconnection device;wherein the first conductive layer and the second conductive layer are operatively connected via a plurality of conductive spacers.

2. The power semiconductor module of claim 1 wherein the first conductive layer and / or the second conductive layer comprises a plurality of conductive tracks spaced apart from one another.

3. The power semiconductor module of claim 1 or claim 2 wherein one or both of the first interconnection device and the second interconnection device is or comprises a printed circuit board.

4. The power semiconductor module of any preceding claim wherein a width and / or a length of the first substrate is different to a width and / or a length of the second substrate.

5. The power semiconductor module of any preceding claim wherein a thickness of each of the plurality conductive spacers and a thickness of each of the first and second interconnection devices are substantially equal.

6. The power semiconductor module of any preceding claim further comprising a diode operatively connected in an anti-parallel configuration with at least one of the first and second semiconductor die.

7. The power semiconductor module of any preceding claim, further comprising an encapsulant covering the first and second semiconductor die.

8. The power semiconductor module of claim 7 wherein the encapsulant comprises a moulding compound, and optionally, wherein the moulding compound comprises thermally conductive fillers.

9. The power semiconductor module of any preceding claim, further comprising a plurality of control and / or power terminals operatively connected to at least one of the plurality of conductive tracks of the first conductive layer and extending in a substantially parallel direction with respect to the first insulating layer.

10. The power semiconductor module of claim 9 wherein at least one of the plurality of control and / or power terminals is made of or otherwise comprises a material with a coefficient of thermal expansion which matches the coefficients of thermal expansion of a material forming or comprising the first and / or second substrate.

11. The power semiconductor module of any preceding claim further comprising: a third conductive layer arranged on a further surface of the first insulating layer, wherein the further surface is an opposite surface to the surface on which the first conductive layer is arranged; and / ora fourth conductive layer arranged on a further surface of the second insulating layer, wherein the further surface is an opposite surface to the surface on which the second conductive layer is arranged.

12. The power semiconductor module of any preceding claim further comprising a thermal management device, wherein the first and / or second insulating layer is operatively connected to the thermal management device, optionally wherein the thermal management device is a heat sink or a cold plate.

13. The power semiconductor module of any preceding claim further comprising a plurality of holes in the first and / or second conductive layers, wherein the plurality of holes are configured so as to:assist with the alignment of bonding material used to bond one or more or each of the semiconductor dies, conductive spacers, terminals and / or interconnection devices to the first and / or second conductive layers during manufacture; and / orabsorb excessive boding materials during manufacture.

14. A power semiconductor system comprising a plurality of power semiconductor modules as defined in any one of claims 1 to 13.

15. An electric vehicle comprising the power semiconductor system of claim 14.

16. A hybrid electric vehicle comprising a power semiconductor system of claim 14.

17. A jig for use in the manufacture of the power semiconductor module of claim 1, the jig comprising:a cavity, the cavity comprising:a first plane at a first depth, the first plane configured to receive the second substrate; anda second plane ata second depth, the second plane configured to receive the first substrate, wherein the second depth is shallower than the first depth;18. The jig of claim 17 further comprising a third plane at a third depth, the third plane comprising one or more slots extending from the cavity on the third plane, each of the one or more slots configured to receive a terminal, wherein the third depth is shallower than the first depth and deeper than the second depth.

19. The jig of claim 17 or claim 18 further comprising an object, the object configured to be disposed into the first cavity and optionally wherein the surface area of the object is substantially the same as the surface area of the cavity.

20. The jig of any one of claims 17 to 19 wherein a width and / or a length of the first plane is different to a width and / or a length of the second plane.

21. A method of manufacturing the power semiconductor module of any one of claims 1 to 13, the method comprising:providing the jig of claim 17;disposing the second substrate into the cavity, onto the first plane, wherein the second conductive layer is arranged uppermost;disposing the plurality of conductive spacers, the second semiconductor die and the second interconnection device onto the second conductive layer;disposing the first interconnection device onto the second semiconductor die;disposing the first semiconductor die onto the second interconnection device;disposing the first substrate into the cavity, onto the second plane, wherein the first conductive layer is arranged lowermost;bonding the plurality of conductive spacers, the first and second semiconductor die and the first and second interconnection device between the first and second substrate to form the power semiconductor module.

22. The method of claim 21 wherein the bonding comprises at least one of:a reflow soldering process;a pressure-less sintering process; or a pressure assisted sintering process.

23. The method of claim 21 or claim 22 wherein the bonding comprises a one-step process.

24. The method of any one of claims 21 to 23 wherein the method further comprises disposing, before the bonding step, an object into the cavity.

25. The method of any one of claims 21 to 24 wherein the jig of claim 18 is provided and the method further comprises, disposing one or more terminals into one or more or each of the one or more slots.34

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