High electron mobility transistors

Abstract

A a high electron mobility transistor (HEMT) comprises a channel layer 110 which may comprise GaN and a barrier layer 120 to induce a two-dimensional electron gas (2DEG) 130 in the channel layer 110. An interconnect layer comprising a first insulating material 176 is formed on a first surface 112 of the channel layer, which is disposed between the barrier layer 120 and the insulating layer 176. A growth substrate (Fig. 3a: 310) and buffer layer (Fig. 3a: 320) are removed to expose the first surface 112 and the insulating material 176 is subsequently deposited. Source and drain terminals 160, 150 may be formed on the channel layer and a gate terminal 140 may be formed on the barrier layer 120. A second interconnect layer 180 is formed using BEOL techniques. A handle wafer 200 comprising further semiconductor devices 220, 230 on a substrate 210 is bonded on the second interconnect layer 180. The handle wafer comprises a third interconnect layer 240. A source field plate (Fig. 4: 462) may be formed on the opposite side of the channel layer to the gate, source and drain contacts. An RF module may comprise series connected HEMT devices.

Description

Technical field The present application relates to a semiconductor structure and a method of forming a semiconductor structure. Background There is increasing interest to form semiconductor devices such as transistors from III-N semiconductor materials. Ill-N semiconductor materials, such as GaN, possess desirable electronic properties, such as a high breakdown voltage and high critical electric field. A popular semiconductor device formed from lll-N semiconductor materials, such as GaN, is the high electron mobility transistor (HEMT). A HEMT comprises a two-dimensional electron gas (2DEG) for carrier flow between the source and the drain, which is attractive due to the high electron mobility of the 2DEG. The GaN HEMT has found use in RF and power applications. Summary In particular, the GaN HEMT is an attractive semiconductor device for RF applications. However, GaN HEMTs also possess some drawbacks. The formation of a GaN HEMT involves the epitaxial growth of semiconductor layers on a substrate. Typically, one or more buffer layers are first grown on the substrate followed by the growth of a channel layer and barrier layer. The growth substrate and buffer layer(s) can cause problems for the operation of a GaN HEMT. In particular, the growth substrate and buffer layer(s) can cause non-linearity effects in a GaN HEMT. In RF applications, it is desirable for a HEMT to exhibit strong linearity performance. However, substrates used for the epitaxial growth of semiconductor layers for a HEMT are a source of 2nd and even-order harmonics, which detrimentally affect linearity. Furthermore, the buffer layer(s) of a HEMT can contain defects, which provide trapping sites for carriers. These trapping sites can introduce drain lag. The issues associated with the harmonics and trapping sites become an even bigger problem as RF applications move towards higher frequency switching operations used in 5G and 6G communications protocols. It is an object of the disclosure to obviate or eliminate at least some of the abovedescribed disadvantages associated with existing techniques. According to a first aspect there is provided a semiconductor structure comprising: a high electron mobility transistor (HEMT). The HEMT comprises: a channel layer comprising a first surface; and a barrier layer. The semiconductor structure further comprises a insulating material contacting the first surface. The channel layer is between the barrier layer and the insulating layer. According to a second aspect there is provided a radio frequency (RF) module comprising the semiconductor structure according to the first aspect. According to a third aspect there is provided an electronic device comprising the semiconductor structure according to the first aspect or the radio frequency module according to the second aspect. According to the fourth aspect there is provided a method of forming a semiconductor structure comprising: forming a HEMT. Forming the HEMT comprises: forming a channel layer comprising a first surface; and forming a barrier layer. Forming the semiconductor structure further comprises forming an insulating material contacting the first surface. The channel layer is between the barrier layer and the insulating material. Brief description of the drawings For a better understanding of the techniques, and to show how it may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 is an example of a HEMT; Figure 2 is an example of a semiconductor structure; Figures 3a-f are examples of process steps in a method of manufacturing a HEMT; Figure 4 is an example of a semiconductor structure; Figure 5 is an example of a semiconductor structure; Figure 6 is an example of a semiconductor structure; Figure 7 is a flow chart illustrating process steps in a method of manufacturing a HEMT. Detailed Description Epitaxy or epitaxial means crystalline growth of material, usually via high temperature deposition. Epitaxy can be effected in a molecular beam epitaxy (MBE) tool in which layers are grown on a heated substrate in an ultra-high vacuum environment. Elemental sources are heated in a furnace and directed towards the substrate without carrier gases. The elemental constituents react at the substrate surface to create a deposited layer. Each layer is allowed to reach its lowest energy state before the next layer is grown so that bonds are formed between the layers. Epitaxy can also be performed in a metalorganic vapour phase epitaxy (MOVPE) tool, also known as a metal-organic chemical vapour deposition (MOCVD) tool. Compound metal-organic and hydride sources are flowed over a heated surface using a carrier gas, typically hydrogen. Epitaxial deposition occurs at much higher pressure than in an MBE tool. The compound constituents are cracked in the gas phase and then reacted at the surface to grow layers of desired composition. A compound material comprising one or more materials from group III of the periodic table with one or more materials from group V is known as a lll-V material. The compounds have a 1:1 combination of group III and group V regardless of the number of elements from each group. Subscripts in chemical symbols of compounds refer to the proportion of that element within that group. Thus Alo^GaAs means the group III part comprises 25% Al, and thus 75% Ga, whilst the group V part comprises 100% As. Doping means that a layer or material contains a small impurity concentration of another element (dopant) which donates (donor) or extracts (acceptor) charge carriers from the parent material and therefore alters the conductivity. Charge carriers may be electrons or holes. A doped material with extra electrons is called n-type whilst a doped material with extra holes (fewer electrons) is called p-type. A layer may be monolithic, that is comprising bulk material throughout. Alternatively it may be porous for some or all of its thickness. A porous layer includes air or vacuum pores, with the porosity defined as the proportion of the area which is occupied by the pores rather than the bulk material. The porosity can vary through the thickness of the layer. For example, the layer may be porous in one or more sublayer. The layer may include an upper portion which is porous with a lower portion that is non-porous. A porous layer means that pores have been formed through bulk material so that voids are intentionally introduced. Porosity is expressed in percentages which refers to the volume of bulk material which has been removed so 25% porosity means that the 25% of the equivalent volume of bulk material is voided. A fully depleted porous layer means a layer in which there are no charge carriers. Where a device is described it should be understood that it will typically be formed on a circular substrate wafer of 4” (100mm), 6” (150mm), 8” (200mm), 12” (300mm) or greater diameter. After growth, deposition, bonding and other fabrication steps the devices are separated by dicing the wafer and layers into devices (chips) of appropriate dimensions. Typically tens, hundreds or thousands of devices are cut from a single wafer. Throughout the present disclosure corresponding elements in the Figures are labelled with corresponding reference numerals. Examples according to the present disclosure provide a HEMT that does not include a substrate or buffer layer(s) to thereby avoid the above-described problems. Examples according to the present disclosure can utilise a method of layer transfer, which can remove the substrate and buffer layer(s) from the HEMT. The substrate and buffer layer(s) can therefore enable the high-quality epitaxial growth of the channel and barrier layers of a HEMT, but not detrimentally impact the linearity performance of the HEMT. Examples according to the present disclosure thus provide a semiconductor structure comprising a HEMT that comprises a channel layer, comprising a first surface, and a barrier layer. The semiconductor structure further comprises insulating material contacting the first surface, where the channel layer is between the barrier layer and the insulating material. Once the substrate and buffer layer(s) have been removed from the HEMT, a first surface of the channel layer of the HEMT will be exposed. Insulating material, such as a dielectric, may thus be deposited on the first surface in later fabrication processes to provide appropriate insulation for the channel layer. Figure 1 is an example of a HEMT 100 according to examples of the present disclosure. HEMT 100 comprises a channel layer 110 and a barrier layer 120. The barrier layer 120 may comprise a material configured to induce the formation of a two-dimensional electron gas (2DEG) 130 in the channel layer 110, as one skilled in the art will readily understand. For example, the channel layer and barrier layer may comprise lll-N semiconductor material, which results in the formation of the 2DEG 130 in the channel layer 110. In one example, the channel layer comprises GaN and the barrier layer comprises AIGaN. HEMT 100 further comprises a gate contact 140, a drain contact 150 and a source contact 160. Gate contact 140 may thus be operated to modulate the 2DEG 130 and control current flow between the drain contact 150 and source contact 160. In one example, HEMT 100 may be configured for depletion mode operation (D-mode). In D-mode operation the 2DEG 130 is present between the drain contact 150 and source contact 160, and a negative bias voltage is applied to the gate contact 140 to suspend formation of the 2DEG 130, and thus suspend current flow between the drain contact 150 and source contact 160. Although source contact 160 and drain contact 150 are illustrated as being directly in contact with the channel layer 110, in some examples, one or more intermediary layers or material may be present between the source contact 160 and drain contact 150, and the channel layer 110. For example, at least a portion of barrier layer 120 may be present between the channel layer 110 and the source contact 160 and drain contact 150. In another example, one or more dielectric layers, may be present between the gate contact 140 and the barrier layer 120. Gate contact 140, drain contact 150 and source contact 160 may comprise any suitable material for forming electrical contacts for a HEMT. HEMT 100 further comprises a first surface 112. As will be described in more detail below, a semiconductor structure is formed where insulating material is deposited on the first surface 112. In conventional examples, typically one or more buffer layers contact the first surface 112, and a substrate for epitaxial growth contacts the one or more buffer layers. However, as will be described in more detail below, in examples according to the present disclosure, buffer layer(s) and the epitaxial growth substrate can be removed to expose the first surface 112. HEMT 100 may thus be referred to as a “bufferless HEMT”. Insulating material can subsequently be deposited on the first surface 112 where the buffer layer(s) would conventionally be present. In some examples, the first surface 112 may comprise the N-polar surface of the channel layer 110. As one skilled in the art will be familiar with, typically lll-N semiconductor materials, such as GaN, epitaxially forms with the group III component terminating at the upper surface of the lll-N semiconductor layer. For example, HEMT 100 further comprises a second surface 114, opposite the first surface 112. As will be described in more detail below, HEMT 100 may be formed on an epitaxial growth substrate, such that the second surface 114 may comprise the upper surface relative to the growth direction. The second surface 114 may therefore comprise a surface terminated with the group III component. For example, where the channel layer 110 comprises GaN, the second surface 114 comprise a Ga-polar surface. In such examples, where the epitaxial growth substrate and buffer layer(s) are removed from the channel layer 110, this will expose the first surface 112, which may thus comprise the N-polar surface of the lll-N channel layer 110. As illustrated in Figure 1, source contact 160 and drain contact 150 are formed on the second surface 114 of the channel layer 110, such that the source contact 160 and drain contact 150 contact the second surface 114. Gate contact 140 is formed on the barrier layer 120. However, it will be appreciated that gate contact 140 is also formed “on” the second surface 114, as will be described in more detail below. In other words, the channel layer 110 is between one or more of the gate contact 140, drain contact 150 and source contact 160, and insulating material deposited on the first surface 112. In other words, firstand second surfaces 112, 114 of the channel layer 110 are between one or more of the gate contact 140, drain contact 150 and source contact 160, and the insulating material. In such examples, the opposing surfaces 112, 114 may thus comprise the major surfaces of the channel layer 110 and the edges 116, 118 of the channel layer 110 may not comprise the major surfaces and instead comprise the minor surfaces. The channel layer 110 is thus further positioned between the barrier layer 120 and the insulating material. Figure 2 is an example of a semiconductor structure 101. Semiconductor structure 101 comprises a first semiconductor wafer 190 bonded to a handle wafer 200. First semiconductor wafer 190 comprises the HEMT 100, which comprises corresponding elements to that described above. First semiconductor wafer 190 further comprises a first interconnect layer 170. First interconnect layer 170 comprises first insulating material 176, which contacts the first surface 112 of channel layer 110. As described above, the first surface 112 may be exposed by removing buffer layer(s) and an epitaxial growth substrate from the first surface 112. First insulating material 176 may subsequently be deposited on the first surface 112, for example, in one or more layers. First interconnect layer 170 further comprises a first interconnect 172. In some examples, the first interconnect 172 may be used for connecting one or more semiconductor devices of the first semiconductor wafer 190. It will be appreciated that first semiconductor wafer 190 is an illustrative example, and first semiconductor wafer 190 may comprise many semiconductor devices, where the first interconnect 172 may be one of many interconnects for connecting the semiconductor devices of the first semiconductor wafer 190. In some examples, first interconnect layer 170 may thus be formed using back end of line (BEOL) fabrication techniques, as will be described in more detail below. First semiconductor wafer 190 further comprises a second interconnect layer 180. Second interconnect layer 180 comprises a second interconnect 182 configured to connect drain contact 150 to first contact pad 184. The first contact pad 184 connects the drain contact 150 to the second semiconductor wafer 200. Second interconnect layer 180 further comprises a third interconnect 186 configured to connect source contact 160 to second contact pad 188. The second contact pad 188 connects the source contact 160 to the second semiconductor wafer 200. Although not illustrated in Figure 2, it will be appreciated that in some examples, second interconnect layer 180 may further comprise an additional interconnect layer to connect the gate contact 140 to one or more other semiconductor devices (not illustrated). Second interconnect layer 180 further comprises second insulating material 189. In one example, one or more layers of second insulating material 189 may be deposited over the barrier layer 120 and contacts 140, 150, 160, and the second interconnect 182, first contact pad 184, third interconnect 186 and second contact pad 188 may be formed in the one or more layers of second insulating material 189. In some examples, second interconnect layer 180 may thus be formed using BEOL fabrication techniques, as will be described in more detail below. Semiconductor structure 101 further comprises a handle wafer 200. Handle wafer 200 comprises a substrate 210. In some examples, the substrate 210 may comprise a epitaxial growth substrate to permit the epitaxial growth of semiconductor material thereon. In some examples, the substrate 210 may thus comprise a semiconductor material. For example, the substrate 210 may comprise a group IV semiconductor material such as Si, Ge or SiC. In another example, the substrate 210 may comprise a group 11 l-V semiconductor material such as GaN. In other examples, the substrate 210 may not comprise a epitaxial growth substrate and may comprise a material bonded to form the handle wafer 200. For example, substrate 210 may comprise porous Si, trap rich Si, glass, sapphire, diamond, a polycrystalline substrate, such as Poly-AIN or Poly-SiC or any suitable material for integrated circuit manufacture. Handle wafer 200 further comprises a first semiconductor device 220 and a second semiconductor device 230. In one example, the first semiconductor device 220 and the second semiconductor device 230 may be formed on substrate 210. In another example, first semiconductor device 220 and the second semiconductor device 230 may be formed on an alternative substrate and bonded to the substrate 210. First semiconductor device 220 and a second semiconductor device 230 may comprise any suitable semiconductor device. In one example, the first semiconductor device 220 and / or a second semiconductor device 230 may comprise an electronic semiconductor device, such as a transistor e.g. HEMT, MOSFET, MISFET etc. In another example, the first semiconductor device 220 and / or a second semiconductor device 230 may comprise an optoelectronic device such as a photoemitter or a photodetector. Although first semiconductor device 220 and second semiconductor device 230 are illustrated as being fabricated on the substrate 210, it will be appreciated that these are illustrative examples and one or more elements of first semiconductor device 220 and second semiconductor device 230 may be formed in the substrate 210. In such examples, substrate 210 may thus comprise a semiconductor wafer comprising semiconductor layers for forming one or more semiconductor devices. In some examples, first semiconductor device 220 and second semiconductor device 230 may comprise group IV semiconductor material, such as Si. In some examples, first semiconductor device 220 and second semiconductor device 230 may comprise group I ll-V semiconductor material such as GaN, GaAs, InP etc. In some examples, the first semiconductor device 220 and second semiconductor device 230 may be formed using complementary metal-oxide semiconductor (CMOS) fabrication techniques. Handle wafer 200 further comprises third interconnect layer 240. Third interconnect layer 240 comprises a fourth interconnect 241 connecting the first semiconductor device 220 to the third contact pad 242. The third interconnect layer further comprises a first interconnect portion 243, second interconnect portion 244 and third interconnect portion 245. First interconnect portion 243, second interconnect portion 244 and third interconnect portion 245 form a fifth interconnect connecting the second semiconductor device 230 to a fourth contact pad 246. Third interconnect layer 240 further comprises third insulating material 247. In one example, one or more layers of third insulating material 247 may be deposited over substrate 210, and the fourth interconnect 241, third contact pad 242, first interconnect portion 243, second interconnect portion 244 and third interconnect portion 245 and fourth contact pad 246 may be formed in the one or more layers of third insulating material 247. In some examples, third interconnect layer 240 may thus be formed using BEOL fabrication techniques. In some examples, the first interconnect 172, second interconnect 182 first contact pad 184, third interconnect 186, second contact pad 188, fourth interconnect 241, third contact pad 242, first interconnect portion 243, second interconnect portion 244 and third interconnect portion 245 and fourth contact pad 246 may be formed from any suitable metal used for integrated circuit metallization and routing. In some examples, first insulating material 176, second insulating material 189 and third insulating material 247 may comprise a dielectric material. For example, first insulating material 176, second insulating material 189 and third insulating material 247 may comprise any suitable dielectric material used in BEOL fabrication processes. First semiconductor wafer 190 and handle wafer 200 are bonded together in such a way that the first contact pad 184 is bonded to the fourth contact pad 246 and the second contact pad 188 is bonded to the third contact pad 242. In this manner the drain contact 150 is connected to the third semiconductor device 230 and the source contact 160 is connected to the second semiconductor device 220. The bonding of the first semiconductor wafer 190 to the handle wafer 200 may thus enable the formation of a 3D integrated circuit (3DIC). It will be appreciated that first semiconductor wafer 190 and handle wafer 200 are illustrative examples, and in other examples, first semiconductor wafer 190 and handle wafer 200 may comprise many more semiconductor devices and interconnects that may be connected to form a 3DIC. Figure 3a-g illustrate process steps in a method for manufacturing the HEMT 100 and the semiconductor structure 100 described above. Figure 3a illustrate a first process step 300a, in which a buffer layer 320, the channel layer 110 and the barrier layer 120 are formed a substrate 310. In one example, the buffer layer 320, the channel layer 110 and the barrier layer 120 are epitaxially grown on the substrate 310. For example, the buffer layer 320, the channel layer 110 and the barrier layer 120 may be formed by metal organic-chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). In such examples, the buffer layer 320, the channel layer 110 and the barrier layer 120 may comprise semiconductor material, such as Ill-N semiconductor material as described above. In some examples, the substrate 310 may thus comprise a material configured to permit the epitaxial growth of semiconductor material thereon. For example, the substrate 310 may comprise Si, Sic, GaN or AIN. As illustrated in Figure 3a, the 2DEG 130 is again formed in the channel layer 110. The barrier layer 120 thus comprises a material configured to induce the formation of the 2DEG in the channel layer 110. Figure 3b illustrates a second process step 300b in which gate contact 140, drain contact 150 and source contact 160 are formed on the second surface 114 of the channel layer 110. For example, gate contact 140, drain contact 150 and source contact 160 may be formed using any suitable fabrication technique, such as, etching and lithography techniques. As illustrated in Figure 3b, drain contact 150 and source contact 160 are formed directly contacting the second surface 114 of the channel layer 110. However, in other examples, at least a portion of the barrier layer 120 may be between the second surface 114, and the drain contact 150 and source contact 160. In some examples, a gate dielectric may be present between the gate contact 140 and the barrier layer 120 Figure 3c illustrates a third step 300c in which the second interconnect layer 180 is formed. In one example, forming the second interconnect layer 180 may comprise depositing one or more layers of the second insulating material 189 and forming the second interconnect 182 and third interconnect 186 in the one or more layers of the second insulating material 189. For example, one or more vias may be formed in the one or more layers of the second insulating material 189 and metal may be formed in the vias to form the second interconnect 182 and third interconnect 186. In a similar manner, in a final layer of the second insulating material 189, the contact pads 184, 188 may be formed by etching the final layer of the second insulating material 189 to provide space to deposit metal to form the contact pads 184, 188. In such examples, second interconnect 182, third interconnect 186 and contact pads 184, 188 may thus be formed using BEOL fabrication processes. Figure 3d illustrates a fourth step 300d in which handle wafer 200 is bonded to the second interconnect layer 180. Handle wafer 200 again comprises first semiconductor device 220 and second semiconductor device 230 on substrate 210. Handle wafer 200 further comprises the third interconnect layer 240 comprising corresponding elements and functionality to that described above. Handle wafer 200 may thus be fabricated in a separate process, prior to step 300d. As illustrated in Figure 3d, the handle wafer 200 is bonded to the second interconnect layer 180 in such a way that the first contact pad 184 contacts the fourth contact pad 246 and the second contact pad 188 contacts the third contact pad 242. As such, the drain contact 150 is connected to the first semiconductor device 220 and source contact 160 is connected to the third semiconductor device 230. The bonding of handle wafer 200 to the second interconnect layer 180 may thus involve a hybrid bonding process. Figure 3e illustrates a fifth step 300e in which substrate 310 and buffer layer 320 are removed from the channel layer 110. The removal of buffer layer 320 and substrate 310 is performed to expose the first surface 112 of the channel layer 110 for further fabrication steps, as will be described in more detail below. In one example, the substrate 310 and the buffer layer 320 may be removed in a grinding process. In another example, the substrate 310 and the buffer layer 320 may be removed using a release layer. For example, a release layer may be formed between the buffer layer 320 and the channel layer 110, which can release the buffer layer 320 and substrate 310 from the channel layer 110. In another example, the buffer layer 320 may act as the release layer. In some examples, the release layer may comprise a porous layer. For example, lll-N semiconductor materials can be porosified by heavily doping the lll-N semiconductor material n-type (N+) and subjecting the N+ lll-N semiconductor material to an electrochemical etch process. The electrochemical etch process is further selective to the N+ lll-N semiconductor material meaning that other material in a lll-N layer stack can be substantially unaffected by the electrochemical etch process. After the porous layer has been formed, the porous layer can then be removed using an annealing process where the pores expand to remove the porous layer. As such, in some examples, a porous layer can be formed between the channel layer 110 and buffer layer 320. In another example, the buffer layer 320 may be porosified and comprise a porous layer. For example, during the epitaxial growth of the layers in step 300b, the buffer layer 320 may be doped N+ or an additional N+ layer may be formed between the channel layer 110 and the buffer layer 320. The N+ layer or N+ buffer layer 320 can then be porosified using an electrochemical etch process. The porosifcation process is elective to the N+ material, as described above. In one example, the porosifcitaion process may take place after the growth of the channel layer 110 and barrier layer 120. In another example, the porosifctaion may take place before the growth of the channel layer 110 and barrier layer 120, and the channel layer 110 and barrier layer 120 may be formed on the porous layer. The porous layer may remain intact during the fabrication processes described above at steps 300b-d and the porous layer may be subsequently removed at step 300e, for example, using an anneal process. Figure 3f illustrates a sixth process step 300f in which HEMT 100 and handle wafer 200 are flipped and first interconnect layer 170 is formed on the first surface 112. In one example, forming the first interconnect layer 170 may comprise depositing one or more layers of the first insulating material 176 on the first surface and forming the first interconnect 172 in the one or more layers of the first insulating material 176. For example, one or more vias may be formed in the one or more layers of the first insulating material 176 and metal may be formed in the vias to form the first interconnect 172. Although, not illustrated in Figure 3f, it will be appreciated first interconnect 172 may connect to one or more other semiconductor devices formed on first semiconductor wafer 190. In such examples, the first interconnect may thus be formed using BEOL fabrication processes. Steps 300a-300f thus illustrates process steps form forming a 3DIC semiconductor structure according to examples of the present disclosure. Figure 4 illustrates another example of a semiconductor structure 401 according to examples of the present disclosure. Semiconductor structure 401 comprises HEMT 100 and a source field plate 462 connected to the source contact 160 of HEMT 100. As one skilled in the art will be familiar with, a source field plate can grade the drain electric field between the drain contact 150 and the source contact 160. This improves the breakdown voltage of the HEMT and further provides hot carrier injection protection. However, in conventional HEMT architectures the source field plate is located on the same side of the channel layer as the gate, source and drain, which can create nonlinear capacitances, particularly in applications involving higher drain biases. Semiconductor structure 401, however, comprises a source field plate 462 on an opposite side of the channel layer 110 to the gate contact 140, drain contact 150 and source contact 160. In this architecture, the effect of the source field plate 462 on the non-linear capacitances can be reduced compared to when the source field plate 462 is located on the same side of the channel layer 110 as the gate contact 140, drain contact 150 and source contact 160. Semiconductor structure 401 thus further comprises a fourth interconnect portion 442, fifth interconnect portion 444 and sixth interconnect portion 446. The fourth interconnect portion 442, fifth interconnect portion 444 and sixth interconnect portion 446 together form a seventh interconnect configured to connect the source contact 160 to the source field plate 462. As illustrated in Figure 4, the channel layer 110 is between the source field plate 462, and the gate contact 140, drain contact 150 and source contact 160. Semiconductor structure 401 further comprises a fifth contact pad 476 connected to the sixth interconnect portion 446. In some examples, the fifth contact pad 476 may be connected e.g. bonded to another semiconductor device. Semiconductor structure 401 further comprises a first interconnect layer 470. The first interconnect layer 470 comprises the source field plate 462, third interconnect portion 446 and fifth contact pad 476 surrounded by insulating material 478. The insulating material 478 further contacts the first surface 112 of the channel layer 110. In some examples, first interconnect layer 470 may be formed using similar fabrication processes to the formation of the first interconnect layer 170 in step 300f described above. Semiconductor structure 401 further comprises a second interconnect layer 480. The second interconnect layer comprises the fourth interconnect portion 442, fifth interconnect portion 444 and sixth interconnect portion 446 surrounded by insulating material 489. In some examples, second interconnect layer 480 may be formed using similar fabrication processes to the formation of the second interconnect layer 180 described above in step 300c. In some examples, the first interconnect layer 470 and the second interconnect layer 480 may thus be formed using BEOL fabrication processes. Figure 5 is an example of a semiconductor structure 501. Semiconductor structure comprises HEMT 100 and a second HEMT 500. HEMT 100 comprises corresponding elements to that described above. Second HEMT 500 comprises second channel layer 510, second barrier layer 520, second 2DEG 530, second gate contact 540, second drain contact 550 and second source contact 560. Second channel layer 510, second barrier layer 520, second 2DEG 530, second gate contact 540, second drain contact 550 and second source contact 560 may comprise corresponding features and functionality to channel layer 110, barrier layer 120, 2DEG 130, gate contact 140, drain contact 150 and source contact 160, respectively. In some examples, the corresponding elements of HEMT 100 and HEMT 500 may thus be fabricated in a corresponding way. Semiconductor structure 501 further comprises a dividing region 590 configured to electrically isolate HEMT 100 from second HEMT 500. In some examples, dividing region 590 may comprise an implanted semiconductor portion implanted with H or N. Semiconductor structure 501 further comprises a first interconnect layer 570 comprising a first insulating material 576. In a similar manner to that described above, insulating material 576 contacts the first surface 112 of channel layer 110 and the first side 512 of the second channel layer 510. Semiconductor structure 501 further comprises a second interconnect layer 580 comprising first interconnect portion 572, second interconnect portion 574 and third interconnect portion 576, which together form a first interconnect. The second interconnect layer 580 further comprises second insulating material 587. The first interconnect formed by first interconnect portion 572, second interconnect portion 574 and third interconnect portion 576 thus connects the HEMT 100 and the second HEMT 500 in series to form a plurality of series connected HEMTs. Typically, transistors such as HEMTs and MOSFETs are connected in series to handle more power. Theoretically, by increasing the number of transistors connected in series, the voltage the series connected transistors can handle also increases. However, in some conventional examples, it is observed that beyond a critical number of transistors, the series connection of more transistors does not result in an increased voltage handling ability. This is due to electrical coupling between the device layers of the transistors and the substrate. Once the first transistor of the series connection collapses, the increased number of transistors does not result in increased voltage handling ability. This results in a non-linear voltage handling stacking of the transistors. In examples according to present disclosure, a plurality of series connected HEMTs 100, 500 may be formed where a subset or all of the series connected transistors may not comprise a substrate or buffer layer(s). As such, the electrical coupling between the substrate and the device layers of the HEMTs 100, 500 does not occur. In such examples, increasing the number of series connected HEMTs thus results in increased voltage handling beyond the critical number of transistors observed for conventional examples. Figure 6 is an example of a semiconductor structure 601 comprising a HEMT 600. HEMT 600 comprises corresponding elements to HEMT 100 described above, where said corresponding elements are labelled with corresponding reference numerals. HEMT 600 further comprises a gate contact 640. Gate contact 640 is formed on the first surface 112 of the channel layer 110, as opposed to the second surface 114 described for HEMT 100 above. The ability to expose the first surface 112 of the channel layer 110 enables the possibility to form the gate contact 640 on an opposite side of the channel layer 110 to the drain contact 150 and the source contact 160. In conventional examples, forming the gate contact, source contact and drain contact on the same side of the channel layer 110 can contribute to parasitic capacitance effects. HEMT 600, however, enables the gate contact 640 to be formed on an opposite side to the source contact 160 and drain contact 150, which can improve the parasitic effects. Furthermore, although HEMT 600 illustrates that the gate contact 640 is on opposite sides of the channel layer 110 to the drain contact 150 and source contact 160, in other examples, one of source contact 160 or drain contact 150 may be positioned on the first surface 112 alongside the gate contact 640. In some examples, such an arrangement of the gate contact 640, drain contact 150 and source contact 160 may also reduce parasitic capacitance effects. Semiconductor structure 601 further comprises first interconnect layer 670 comprising first insulating material 676. First insulating material 676 thus contacts the first surface 112 of the channel layer 110 in a similar manner to that described above. First insulating material 676 thus additionally contacts the gate contact 640. First insulating material 676 may thus contact a majority of or major area of the first surface 112. In such examples, the channel layer 110 may thus still be considered to be between the barrier layer 120 and the first insulating material 676. As described above, in some examples, the first surface 112 may comprise the N-polar side of a channel layer 112 comprising GaN. Forming the gate contact 640 on the N-polar side of the channel layer 110 can improve the gate control of the gate contact 640 and provide greater design freedom for adjusting the threshold voltage of the HEMT 100, compared to forming the gate contact 640 on the Ga-polar side of a GaN channel layer 110. Although not illustrated in Figure 6, it will be appreciated that first interconnect layer 670 may comprise interconnects and routing to, for example, connect the gate contact 640 to one or more semiconductor devices. Semiconductor structure 601 further comprises second interconnect layer 680 comprising second insulating material 686. Second insulating material 686 is thus fabricated over the barrier layer 120, source contact 150 and drain contact 160 in a similar manner to that described above. Although not illustrated in Figure 6, it will be appreciated that second interconnect layer 680 may comprise interconnects and routing to, for example, connect the drain contact 150 and source contact 160 to one or more semiconductor devices. In some examples, the gate contact 640 may thus be fabricated on the first surface in any suitable manner. For example, step 300b above may be modified such that a gate contact is not formed on the second surface 114 in the same step as the formation of the drain contact 150 and the source contact 160. In such examples, gate contact 640 may thus instead be formed on the first surface 112, for example, in a step between process steps 300e and 300f described above. Figure 7 is a flowchart illustrating process steps in a method 700 for forming a HEMT. The method 700 comprises, in a first step 710, forming a HEMT. First step 710 further comprises forming a channel layer comprising a first surface and forming a barrier layer. The method 700 further comprises, in a second step 720, forming an insulating material contacting the first surface, wherein the channel layer is between the barrier layer and the insulating material. The present disclosure further provides an RF module comprising a semiconductor structure according to examples of the present disclosure. In some examples the RF module may comprise one of: a switch module, a power amplifier module, a transmitter module, a receiver module and a transceiver module. The present disclosure further provides an electronic device comprising a semiconductor structure according to examples of the present disclosure or an RF module according to examples of the present disclosure. In some examples the electronic device may comprise an electronic device for user operation. In some examples the electronic device may comprise a communication device such as a mobile telephone, smartphone or similar. In some examples the electronic device may comprise a handheld computing device, such as a tablet or similar. In some examples the electronic device may comprise a visual display device, such as a television, a monitor or similar. In some examples the electronic device may comprise a wearable device, such as a smartwatch, smart glasses, or similar. In some examples the electronic device may comprise a gaming device such as a games console or similar. In some examples the electronic device may comprise a headset such as a virtual reality (VR) headset, an augmented reality (AR) headset, or similar. In some examples the electronic device may comprise an audio accessory device, such as headphones, earphones, wireless headphones, true wireless headphones, earbuds, or similar. In some examples the electronic device may comprise an appliance such as a household appliance, for example a refrigerator or a washing machine, or similar. It should be noted that the above-mentioned embodiments illustrate rather than limit the idea, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

16 12241. A semiconductor structure comprising:a high electron mobility transistor, HEMT, comprising:5 a channel layer comprising a first surface and a second surface; anda barrier layer; anda insulating material contacting the first surface, wherein the channel layeris between the barrier layer and the insulating layer; anda source contact and a drain contact formed on the second surface of the10 channel layer.

2. The semiconductor structure according to claim 1 wherein the channel layer comprises lll-N semiconductor material.15 3. The semiconductor structure according to claim 2 wherein the first surfacecomprises a N-polar surface.

4. The semiconductor structure according to any preceding claim wherein the HEMT comprises a source field plate coupled to the source contact.

205. The semiconductor structure according to claim 4 further comprising a gate contact and, wherein the channel layer is between the source field plate and the gate contact.25 6. The semiconductor structure according to any preceding claim comprising aplurality of series connected HEMTs comprising the HEMT.

7. The semiconductor structure according to any preceding claim further comprising a handle wafer bonded to the HEMT.

308. The semiconductor structure according to claim 7 wherein the handle wafer comprises one or more semiconductor devices connected to the HEMT.

9. The semiconductor structure according to claims 7 or 8 wherein the handle wafer35 comprises: porous Si; trap rich Si; glass or sapphire.

10. The semiconductor structure according to any preceding claim further comprising one or more interconnect layers connected to the HEMT.

11. A radio frequency, RF, module comprising the semiconductor structure according to any of claims 1-10.5 12. An electronic device comprising the semiconductor structure according to any ofclaims 1-10 or the radio frequency module according to claim 11.

13. A method of forming a semiconductor structure comprising: forming a HEMT comprising:10 forming a channel layer comprising a first surface and a secondsurface; andforming a barrier layer; andforming an insulating material contacting the first surface, wherein the channel layer is between the barrier layer and the insulating material; and15 forming a source contact and a drain contact on the second surface of the, channel layer.CM14. The method according to claim 13 comprising forming the channel layer on a substrate and removing the substrate from the channel layer.2015. The method according to claim 14 further comprising: bonding the channel layer to a handle wafer; and removing the substrate from the channel layer.25 16. The method according to claim 14 or 15 further comprising:forming a buffer layer over the substrate;forming the channel layer over the buffer layer;bonding the channel layer to the handle wafer; andremoving the substrate and the buffer layer from the channel layer.3017. The method according to any of claims 14-16 wherein forming the HEMT comprises:forming a release layer over the substrate;forming the channel layer over the release layer;35 bonding the channel layer to a handle wafer; andremoving the substrate from the channel layer comprising removing the release layer.

18. The method according to claim 17 wherein forming the release layer comprises porosifying the release layer.5 19. The method according to claim 17 or 18, when dependent on claim 14, whereinthe release layer comprises the buffer layer.

20. The method according to any of claims 15-19 wherein the handle wafer10 comprises one or more semiconductor devices; and the method furthercomprises connecting the one or more semiconductor devices to the HEMT.

21. The method according to any of claims 15-20 wherein the handle wafer comprises: porous Si; trap rich Si; glass or sapphire.1522. The method according to any of claims 14-21 wherein responsive to removing the channel layer from the substrate; forming the insulating material on the first surface of the channel layer.2023. The method according to any of claims 13-22 wherein forming the HEMT further comprises:forming a source field plate coupled to the source contact.

24. The method according to claim 23 wherein forming the HEMT further comprises25 forming a gate contact; wherein the channel layer is between the source fieldplate and the gate contact.

25. The method according to any of claims 13-24 further comprising forming a plurality of HEMTs comprising the HEMT and connecting the plurality of HEMTs 30 in series.

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