Driving circuit, driving method, and display apparatus

Abstract

A driving circuit, a driving method, and a display apparatus. The driving circuit comprises an inverter circuit (11), a first output node control circuit (12), a second output node control circuit (14) and an output circuit (15), wherein the inverter circuit (11) inverts the potential of a first output node (N1) in at least part of a display period, so as to obtain the potential of a first node (N2); the first output node control circuit (12) controls the potential of the first output node; the second output node control circuit (14) obtains the potential of a second output node (N4) on the basis of the potential of the first node (N2); and under the control of the potential of the first output node (N1) and the potential of the second output node (N4), the output circuit controls a driving output end to output a driving signal (O1).

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims a priority of the Chinese patent application No. 202310946523.4 filed on July 28, 2023, which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the field of display technology, in particular to a driving circuit, a driving method and a display device. BACKGROUND

[0003] Recently, display devices have a development tendency of high integration level and low cost, and Gate Driver on Array (GOA) is a very important technology. Through the GOA technology, a gate driving circuit is integrated on an array substrate of a display substrate, so as to omit a gate driving integrated circuit, thereby to reduce the manufacture cost in terms of materials and a manufacturing process. A gate switching circuit integrated on the array substrate using the GOA technology is also called as a GOA circuit or a shift register circuit, and each shift register unit in the gate switching circuit is also called as a GOA unit. SUMMARY

[0004] In one aspect, the present disclosure provides in some embodiments a driving circuit, including a phase inversion circuit, a first output node control circuit, a second output node control circuit and an output circuit. The phase inversion circuit is electrically coupled to a first output node and a first node, and configured to perform phase inversion on a potential at the first output node within at least a part of stages of a display cycle, to obtain a potential at the first node; the first output node control circuit is electrically coupled to the first output node, and configured to control the potential at the first output node; the second output node control circuit is electrically coupled to the first node and a second output node, and configured to obtain a potential at the second output node based on the potential at the first node; and the output circuit is electrically coupled to the first output node, the second output node and a driving output end, and configured to control the driving output end to output a driving signal under the control of the potential at the first output node and the potential at the second output node.

[0005] In a possible embodiment of the present disclosure, the driving circuit further includes a first energy storage circuit, and the first energy storage circuit is electrically coupled to the first output node and the driving output end and configured to storage electric energy.

[0006] In a possible embodiment of the present disclosure, the phase inversion circuit includes a first transistor, a second transistor, a third transistor and a storage capacitor. A gate electrode of the first transistor is electrically coupled to the first output node, a first electrode of the first transistor is electrically coupled to a second node, and a second electrode of the first transistor is electrically coupled to a first voltage end. A gate electrode of the second transistor is electrically coupled to the first output node, a first electrode of the second transistor is electrically coupled to the first node, and a second electrode of the second transistor is electrically coupled to the first voltage end. A gate electrode of the third transistor is electrically coupled to the second node, a first electrode of the third transistor is electrically coupled to a second voltage end, and a second electrode of the third transistor is electrically coupled to the first node. A first end of the storage capacitor is electrically coupled to a first clock signal end, and a second end of the storage capacitor is electrically coupled to the second node.

[0007] In a possible embodiment of the present disclosure, the phase inversion circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor. A gate electrode of the first transistor is electrically coupled to the first output node, a first electrode of the first transistor is electrically coupled to a second node, and a second electrode of the first transistor is electrically coupled to a first voltage end. A gate electrode of the second transistor is electrically coupled to the first output node, a first electrode of the second transistor is electrically coupled to the first node, and a second electrode of the second transistor is electrically coupled to the first voltage end. A gate electrode of the third transistor is electrically coupled to the second node, a first electrode of the third transistor is electrically coupled to a second voltage end, and a second electrode of the third transistor is electrically coupled to the first node. A gate electrode and a first electrode of the fourth transistor are both electrically coupled to a first control end, and a second electrode of the fourth transistor is electrically coupled to the second node.

[0008] In a possible embodiment of the present disclosure, the first control end is the second voltage end, a first clock signal end, a second clock signal end or a frame resetting end.

[0009] In a possible embodiment of the present disclosure, the driving circuit further includes a second energy storage circuit and an on / off control circuit. The on / off control circuit is electrically coupled to the first output node, a first clock signal end and a first end of the second energy storage circuit, and configured to control the first end of the second energy storage circuit to be electrically coupled to or electrically decoupled from the first clock signal end under the control of the potential at the first output node. A second end of the second energy storage circuit is electrically coupled to the first output node, and the second energy storage circuit is configured to store electric energy.

[0010] In a possible embodiment of the present disclosure, the on / off control circuit includes a fifth transistor, and the second energy storage circuit includes a second capacitor. Agate electrode of the fifth transistor is electrically coupled to the first output node, a first electrode of the fifth transistor is electrically coupled to the first clock signal end, and a second electrode of the fifth transistor is electrically coupled to a first end of the second capacitor. A second end of the second capacitor is electrically coupled to the first output node.

[0011] In a possible embodiment of the present disclosure, the first output node control circuit is further electrically coupled to an input end, the first node, a first clock signal end, a second clock signal end and a first voltage end, and configured to control the first output node to be electrically coupled to or electrically decoupled from the first voltage end under the control of a first clock signal from the first clock signal end and the potential at the first node, and control the first output node to be electrically coupled to or electrically decoupled from the input end under the control of a second clock signal from the second clock signal end.

[0012] In a possible embodiment of the present disclosure, the first output node control circuit is further electrically coupled to a third node, an input end, a second clock signal end, the first node, a first voltage end, a first clock signal end and a third voltage end, and configured to control the third node to be electrically coupled to or electrically decoupled from the input end under the control of a second clock signal from the second clock signal end, control the third node to be electrically coupled to or electrically decoupled from the first voltage end under the control of the potential at the first node and a first clock signal from the first clock signal end, and control the third node to be electrically coupled to or electrically decoupled from the first output node under the control of a third voltage signal from the third voltage end.

[0013] In a possible embodiment of the present disclosure, the driving circuit further includes a first node control circuit, and the first node control circuit is electrically coupled to the first node, a fourth voltage end and a first clock signal end, and configured to control the first node to be electrically coupled to or electrically decoupled from the fourth voltage end under the control of the potential at the first node and a first clock signal from the first clock signal end.

[0014] In a possible embodiment of the present disclosure, the second output node control circuit is further electrically coupled to the first output node, a first clock signal end and a first voltage end, and configured to control the first node to be electrically coupled to or electrically decoupled from the second output node under the control of a first clock signal from the first clock signal end, and control the second output node to be electrically coupled to or electrically decoupled from the first voltage end under the control of the potential at the first output node.

[0015] In a possible embodiment of the present disclosure, the output circuit is further electrically coupled to a first voltage end and a second voltage end, and the output circuit is configured to control the driving output end to be electrically coupled to or electrically decoupled from the second voltage end under the control of the potential at the first output node, and control the driving output end to be electrically coupled to or electrically decoupled from the first voltage end under the control of the potential at the second output node.

[0016] In a possible embodiment of the present disclosure, the first output node control circuit includes a sixth transistor, a seventh transistor and an eighth transistor; a gate electrode of the sixth transistor is electrically coupled to the first clock signal end, and a first electrode of the sixth transistor is electrically coupled to the first voltage end; a gate electrode of the seventh transistor is electrically coupled to the first node, a first electrode of the seventh transistor is electrically coupled to a second electrode of the sixth transistor, and a second electrode of the seventh transistor is electrically coupled to the first output node; and a gate electrode of the eighth transistor is electrically coupled to the second clock signal end, a first electrode of the eighth transistor is electrically coupled to the input end, and a second electrode of the eighth transistor is electrically coupled to the first output node.

[0017] In a possible embodiment of the present disclosure, the eighth transistor is a doublegate transistor.

[0018] In a possible embodiment of the present disclosure, the first output node control circuit includes a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor. A gate electrode of the sixth transistor is electrically coupled to the first clock signal end, and a first electrode of the sixth transistor is electrically coupled to the first voltage end. A gate electrode of the seventh transistor is electrically coupled to the first node, a first electrode of the seventh transistor is electrically coupled to a second electrode of the sixth transistor, and a second electrode of the seventh transistor is electrically coupled to the third node. A gate electrode of the eighth transistor is electrically coupled to the second clock signal end, a first electrode of the eighth transistor is electrically coupled to the input end, and a second electrode of the eighth transistor is electrically coupled to the third node. Agate electrode of the ninth transistor is electrically coupled to the third voltage end, a first electrode of the ninth transistor is electrically coupled to the third node, and a second electrode of the ninth transistor is electrically coupled to the first output node.

[0019] In a possible embodiment of the present disclosure, the first node control circuit includes a tenth transistor and an eleventh transistor. A gate electrode of the tenth transistor is electrically coupled to the first node, a first electrode of the tenth transistor is electrically coupled to the fourth voltage end, and a second electrode of the tenth transistor is electrically coupled to a first electrode of the eleventh transistor. A gate electrode of the eleventh transistor is electrically coupled to the first clock signal end, and a second electrode of the eleventh transistor is electrically coupled to the first node.

[0020] In a possible embodiment of the present disclosure, the second output node control circuit includes a twelfth transistor and a thirteenth transistor. A gate electrode of the twelfth transistor is electrically coupled to the first clock signal end, a first electrode of the twelfth transistor is electrically coupled to the first node, and a second electrode of the twelfth transistor is electrically coupled to the second output node. A gate electrode of the thirteenth transistor is electrically coupled to the first output node, a first electrode of the thirteenth transistor is electrically coupled to the first voltage end, and a second electrode of the thirteenth transistor is electrically coupled to the second output node.

[0021] In a possible embodiment of the present disclosure, the output circuit includes a fourteenth transistor and a fifteenth transistor. A gate electrode of the fourteenth transistor is electrically coupled to the first output node, a first electrode of the fourteenth transistor is electrically coupled to the driving output end, and a second electrode of the fourteenth transistor is electrically coupled to the second voltage end. A gate electrode of the fifteenth transistor is electrically coupled to the second output node, a first electrode of the fifteenth transistor is electrically coupled to the first voltage end, and a second electrode of the fifteenth transistor is electrically coupled to the driving output end.

[0022] In a possible embodiment of the present disclosure, the driving circuit further includes a third energy storage circuit, a first end of the third energy storage circuit is electrically coupled to the second output node, a second end of the third energy storage circuit is electrically coupled to a first voltage end, and the third energy storage circuit is configured to store electric energy.

[0023] In another aspect, the present disclosure provides in some embodiments a driving method for the above-mentioned driving circuit, including: performing, by a phase inversion circuit, phase inversion on a potential at a first output node, to obtain a potential at a first node; controlling, by a first output node control circuit, the potential at the first output node; obtaining, by a second output node control circuit, a potential at a second output node based on the potential at the first node; and controlling, by an output circuit, a driving output end to output a driving signal under the control of the potential at the first output node and the potential at the second output node.

[0024] In yet another aspect, the present disclosure provides in some embodiments a display device including the above-mentioned driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG. 1 is a schematic view showing a driving circuit according to at least one embodiment of the present disclosure;

[0026] FIG. 2 is another schematic view showing the driving circuit according to at least one embodiment of the present disclosure;

[0027] FIG. 3 is yet another schematic view showing the driving circuit according to at least one embodiment of the present disclosure;

[0028] FIG. 4 is still yet another schematic view showing the driving circuit according to at least one embodiment of the present disclosure;

[0029] FIG. 5 is still yet another schematic view showing the driving circuit according to at least one embodiment of the present disclosure;

[0030] FIG. 6 is still yet another schematic view showing the driving circuit according to at least one embodiment of the present disclosure;

[0031] FIG. 7 is still yet another schematic view showing the driving circuit according to at least one embodiment of the present disclosure;

[0032] FIG. 8 is still yet another schematic view showing the driving circuit according to at least one embodiment of the present disclosure;

[0033] FIG. 9 is still yet another schematic view showing the driving circuit according to at least one embodiment of the present disclosure;

[0034] FIG. 10 is still yet another schematic view showing the driving circuit according to at least one embodiment of the present disclosure;

[0035] FIG. 11 is still yet another schematic view showing the driving circuit according to at least one embodiment of the present disclosure;

[0036] FIG. 12 is still yet another schematic view showing the driving circuit according to at least one embodiment of the present disclosure;

[0037] FIG. 13 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0038] FIG. 14 is a sequence diagram of the driving circuit in FIG. 13;

[0039] FIG. 15 A is a schematic view showing an operating state of the driving circuit in FIG. 13 within a first stage;

[0040] FIG. 15B is a schematic view showing an operating state of the driving circuit in FIG. 13 within a second stage;

[0041] FIG. 15C is a schematic view showing an operating state of the driving circuit m FIG. 13 within a third stage;

[0042] FIG. 15D is a schematic view showing an operating state of the driving circuit in FIG. 13 within a fourth stage;

[0043] FIG. 15E is a schematic view showing an operating state of the driving circuit in FIG. 13 within a fifth stage;

[0044] FIG. 15F is a schematic view showing an operating state of the driving circuit in FIG. 13 within a sixth stage;

[0045] FIG. 16 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0046] FIG. 17 is a sequence diagram of the driving circuit in FIG. 16;

[0047] FIG. 18 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0048] FIG. 19 is a sequence diagram of the driving circuit in FIG. 18; and

[0049] FIG. 20 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] The present disclosure will be described hereinafter in a clear and complete manner in conjunction with the drawings and embodiments. Obviously, the following embodiments merely relate to a part of, rather than all of, the embodiments of the present disclosure, and based on these embodiments, a person skilled in the art may, without any creative effort, obtain the other embodiments, which also fall within the scope of the present disclosure.

[0051] All transistors adopted in the embodiments of the present disclosure may be thin film transistors, field effect transistors or any other elements having an identical characteristic. In order to differentiate two electrodes other than a gate electrode from each other, one of the two electrodes is called as first electrode and the other is called as second electrode.

[0052] In actual use, when the transistor is a thin film transistor or field effect transistor, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.

[0053] As shown in FIG. 1, the present disclosure provides in some embodiments a driving circuit, which includes a phase inversion circuit 11, a first output node control circuit 12, a second output node control circuit 14 and an output circuit 15. The phase inversion circuit 11 is electrically coupled to a first output node N1 and a first node N2, and configured to perform phase inversion on a potential at the first output node N1 within at least a part of stages of a display cycle, to obtain a potential at the first node N2. The first output node control circuit 12 is electrically coupled to the first output node Nl, and configured to control the potential at the first output nodeNl. The second output node control circuit 14 is electrically coupled to the first node N2 and a second output node N4, and configured to obtain a potential at the second output node N4 based on the potential at the first node N2. The output circuit 15 is electrically coupled to the first output node Nl, the second output node N4 and a driving output end 01, and configured to control the driving output end 01 to output a driving signal under the control of the potential at the first output node Nl and the potential at the second output node N4.

[0054] The driving circuit in the embodiments of the present disclosure adopts the phase inversion circuit 11, and the phase inversion circuit 11 performs the phase inversion on the potential at the first output node N1 within at least a part of the stages of the display cycle to obtain the potential at the first node N2. A novel structure of the driving circuit is provided in the embodiments of the present disclosure, so as to output the driving signal.

[0055] In at least one embodiment of the present disclosure, the driving circuit further includes a first energy storage circuit, and the first energy storage circuit is electrically coupled to the first output node and the driving output end and configured to storage electric energy.

[0056] During the implementation, the driving circuit further includes the first energy storage circuit, a first end of the first energy storage circuit is electrically coupled to the first output node, and a second end of the first energy storage circuit is electrically coupled to the driving output end.

[0057] As shown m FIG. 2, on the basis of the driving circuit in FIG. 1, the driving circuit in at least one embodiment of the present disclosure further includes a first energy storage circuit 21, a first end of the first energy storage circuit 21 is electrically coupled to the first output node Nl, a second end of the first energy storage circuit 21 is electrically coupled to the driving output end 01, and the first energy storage circuit 21 is configured to store electric energy.

[0058] During the operation of the driving circuit in FIG. 2, in a case that a potential of the driving signal from the driving output end 01 is pulled down from a high voltage to a low voltage, the potential at the first output node Nl is pulled down only once due to a bootstrapping effect of the first energy storage circuit 21, so there is no step for a falling edge of the driving signal from the driving output end 01.

[0059] In a possible embodiment of the present disclosure, the phase inversion circuit includes a first transistor, a second transistor, a third transistor and a storage capacitor. A gate electrode of the first transistor is electrically coupled to the first output node, a first electrode of the first transistor is electrically coupled to a second node, and a second electrode of the first transistor is electrically coupled to a first voltage end. A gate electrode of the second transistor is electrically coupled to the first output node, a first electrode of the second transistor is electrically coupled to the first node, and a second electrode of the second transistor is electrically coupled to the first voltage end. A gate electrode of the third transistor is electrically coupled to the second node, a first electrode of the third transistor is electrically coupled to a second voltage end, and a second electrode of the third transistor is electrically coupled to the first node. A first end of the storage capacitor is electrically coupled to a first clock signal end, and a second end of the storage capacitor is electrically coupled to the second node.

[0060] In a possible embodiment of the present disclosure, the phase inversion circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor. A gate electrode of the first transistor is electrically coupled to the first output node, a first electrode of the first transistor is electrically coupled to a second node, and a second electrode of the first transistor is electrically coupled to a first voltage end. A gate electrode of the second transistor is electrically coupled to the first output node, a first electrode of the second transistor is electrically coupled to the first node, and a second electrode of the second transistor is electrically coupled to the first voltage end. A gate electrode of the third transistor is electrically coupled to the second node, a first electrode of the third transistor is electrically coupled to a second voltage end, and a second electrode of the third transistor is electrically coupled to the first node. A gate electrode and a first electrode of the fourth transistor are both electrically coupled to a first control end, and a second electrode of the fourth transistor is electrically coupled to the second node.

[0061] In at least one embodiment of the present disclosure, the first control end is the second voltage end, a first clock signal end, a second clock signal end or a frame resetting end.

[0062] In a possible embodiment of the present disclosure, a frame resetting signal from the frame resetting end has a phase inverse to a start signal.

[0063] The driving circuit in at least one embodiment of the present disclosure further includes a second energy storage circuit and an on / off control circuit. The on / off control circuit is electrically coupled to the first output node, a first clock signal end and a first end of the second energy storage circuit, and configured to control the first end of the second energy storage circuit to be electrically coupled to or electrically decoupled from the first clock signal end under the control of the potential at the first output node. A second end of the second energy storage circuit is electrically coupled to the first output node, and the second energy storage circuit is configured to store electric energy.

[0064] During the implementation, the driving circuit further includes the second energy storage circuit and the on / off control circuit, the on / off control circuit controls the first end of the second energy storage circuit to be electrically coupled to or electrically decoupled from the first clock signal end under the control of the potential at the second output node, the second end of the second energy storage circuit is electrically coupled to the first output node, and the second energy storage circuit is configured to store electric energy.

[0065] As shown in FIG. 3, based on the driving circuit in FIG. 1, the driving circuit in at least one embodiment of the present disclosure further includes a second energy storage circuit 31 and an on / off control circuit 32. The on / off control circuit 32 is electrically coupled to the first output node Nl, a first clock signal end CKB and a first end of the second energy storage circuit 31, and configured to control the first end of the second energy storage circuit 31 to be electrically coupled to or electrically decoupled from the first clock signal end CKB under the control of the potential at the first output node Nl. A second end of the second energy storage circuit 31 is electrically coupled to the first output node Nl, and the second energy storage circuit 31 is configured to store electric energy.

[0066] During the operation of the driving circuit in FIG. 3, through the second energy storage circuit 31 and the on / off control circuit 32, the potential at the first output node Nl is pulled down multiple times within one frame, so as to stabilize an output of the transistor of the output circuit whose gate electrode is electrically coupled to the first output node, and reduce an influence caused by a parasitic capacitance of the transistor on a voltage of the first output node Nl, thereby to effectively improve the reliability of the driving circuit.

[0067] In a possible embodiment of the present disclosure, the on / off control circuit includes a fifth transistor, and the second energy storage circuit includes a second capacitor. Agate electrode of the fifth transistor is electrically coupled to the first output node, a first electrode of the fifth transistor is electrically coupled to the first clock signal end, and a second electrode of the fifth transistor is electrically coupled to a first end of the second capacitor. A second end of the second capacitor is electrically coupled to the first output node.

[0068] In at least one embodiment of the present disclosure, the first output node control circuit is further electrically coupled to an input end, the first node, a first clock signal end, a second clock signal end, a first voltage end and the first output node, and configured to control the first output node to be electrically coupled to or electrically decoupled from the first voltage end under the control of a first clock signal from the first clock signal end and the potential at the first node, and control the first output node to be electrically coupled to or electrically decoupled from the input end under the control of a second clock signal from the second clock signal end.

[0069] In a possible embodiment of the present disclosure, the first voltage end is, but not limited to, a high voltage end.

[0070] As shown in FIG. 4, based on the driving circuit in FIG. 2, the first output node control circuit 12 is further electrically coupled to an input end STV, the first node V2, a first clock signal end CKB, a second clock signal end CK and a first voltage end VI, and configured to control the first output node N1 to be electrically coupled to or electrically decoupled from the first voltage end V1 under the control of a first clock signal from the first clock signal end CKB and the potential at the first node N2, and control the first output node Nl to be electrically coupled to or electrically decoupled from the input end STV under the control of a second clock signal from the second clock signal end CK.

[0071] As shown in FIG. 5, based on the driving circuit in FIG. 3, the first output node control circuit 12 is further electrically coupled to an input end STV, the first node V2, a first clock signal end CKB, a second clock signal end CK and a first voltage end VI, and configured to control the first output node N1 to be electrically coupled to or electrically decoupled from the first voltage end V1 under the control of a first clock signal from the first clock signal end CKB and the potential at the first node N2, and control the first output node N1 to be electrically coupled to or electrically decoupled from the input end STV under the control of a second clock signal from the second clock signal end CK.

[0072] In at least one embodiment of the present disclosure, the first output node control circuit is further electrically coupled to a third node, an input end, a second clock signal end, the first node, a first voltage end, a first clock signal end and a third voltage end, and configured to control the third node to be electrically coupled to or electrically decoupled from the input end under the control of a second clock signal from the second clock signal end, control the third node to be electrically coupled to or electrically decoupled from the first voltage end under the control of the potential at the first node and a first clock signal from the first clock signal end, and control the third node to be electrically coupled to or electrically decoupled from the first output node under the control of a third voltage signal from the third voltage end.

[0073] As shown m FIG. 6, based on the driving circuit in FIG. 3, the first output node control circuit 12 is further electrically coupled to a third node N3, an input end STV, a second clock signal end CK, the first node N2, a first voltage end VI, a first clock signal end CKB and a third voltage end V3, and configured to control the third node N3 to be electrically coupled to or electrically decoupled from the input end STV under the control of a second clock signal from the second clock signal end CK, control the third node N3 to be electrically coupled to or electrically decoupled from the first voltage end VI under the control of the potential at the first node and a first clock signal from the first clock signal end CKB, and control the third node N3 to be electrically coupled to or electrically decoupled from the first output node N1 under the control of a third voltage signal from the third voltage end V3.

[0074] In the driving circuit in FIG. 6, the first output node control circuit 12 is directly electrically coupled to the third node N3, and configured to control the third node N3 to be electrically coupled to or electrically decoupled from the first voltage end VI under the control of the first clock signal from the first clock signal end CKB and the potential at the first node N2, and control the third node N3 to be electrically coupled to or electrically decoupled from the input end STV under the control of the second clock signal from the second clock signal end CK.

[0075] In the driving circuit in FIG 6, the first output node is electrically coupled to the third node via an always-on transistor.

[0076] In a possible embodiment of the present disclosure, the third voltage end is, but not limited to, a first low voltage end.

[0077] In at least one embodiment of the present disclosure, the driving circuit further includes a first node control circuit, and the first node control circuit is electrically coupled to the first node, a fourth voltage end and a first clock signal end, and configured to control the first node to be electrically coupled to or electrically decoupled from the fourth voltage end under the control of the potential at the first node and a first clock signal from the first clock signal end.

[0078] During the implementation, the first node control circuit further controls the first node to be electrically coupled to or electrically decoupled from the fourth voltage end under the control of the potential at the first node and the first clock signal from the first clock signal end.

[0079] In a possible embodiment of the present disclosure, the fourth voltage end is, but not limited to, a second low voltage end.

[0080] As shown in FIG. 7, based on the driving circuit in FIG. 4, the driving circuit in at least one embodiment of the present disclosure further includes a first node control circuit 13, and the first node control circuit 13 is electrically coupled to the first node N2, a fourth voltage end V4 and a first clock signal end CKB, and configured to control the first node N2 to be electrically coupled to or electrically decoupled from the fourth voltage end V4 under the control of the potential at the first node N2 and a first clock signal from the first clock signal end CKB.

[0081] As shown in FIG. 8, based on the driving circuit in FIG. 5, the driving circuit in at least one embodiment of the present disclosure further includes a first node control circuit 13, and the first node control circuit 13 is electrically coupled to the first node N2, a fourth voltage end V4 and a first clock signal end CKB, and configured to control the first node N2 to be electrically coupled to or electrically decoupled from the fourth voltage end V4 under the control of the potential at the first node N2 and a first clock signal from the first clock signal end CKB.

[0082] As shown in FIG. 9, based on the driving circuit in FIG. 6, the driving circuit in at least one embodiment of the present disclosure further includes a first node control circuit 13, and the first node control circuit 13 is electrically coupled to the first node N2, a fourth voltage end V4 and a first clock signal end CKB, and configured to control the first node N2 to be electrically coupled to or electrically decoupled from the fourth voltage end V4 under the control of the potential at the first node N2 and a first clock signal from the first clock signal end CKB.

[0083] In at least one embodiment of the present disclosure, the second output node control circuit is further electrically coupled to the first output node, a first clock signal end and a first voltage end, and configured to control the first node to be electrically coupled to or electrically decoupled from the second output node under the control of a first clock signal from the first clock signal end, and control the second output node to be electrically coupled to or electrically decoupled from the first voltage end under the control of the potential at the first output node.

[0084] During the implementation, the second output node control circuit further controls the first node to be electrically coupled to or electrically decoupled from the second output node under the control of the first clock signal, and controls the second output node to be electrically coupled to or electrically decoupled from the first voltage end under the control of the potential at the first output node.

[0085] In at least one embodiment of the present disclosure, the output circuit is further electrically coupled to a first voltage end and a second voltage end, and the output circuit is configured to control the driving output end to be electrically coupled to or electrically decoupled from the second voltage end under the control of the potential at the first output node, and control the driving output end to be electrically coupled to or electrically decoupled from the first voltage end under the control of the potential at the second output node.

[0086] In a possible embodiment of the present disclosure, the first voltage end is a high voltage end, and the second voltage end is a low voltage end.

[0087] In a possible embodiment of the present disclosure, the first output node control circuit includes a sixth transistor, a seventh transistor and an eighth transistor. A gate electrode of the sixth transistor is electrically coupled to the first clock signal end, and a first electrode of the sixth transistor is electrically coupled to the first voltage end. A gate electrode of the seventh transistor is electrically coupled to the first node, a first electrode of the seventh transistor is electrically coupled to a second electrode of the sixth transistor, and a second electrode of the seventh transistor is electrically coupled to the first output node. Agate electrode of the eighth transistor is electrically coupled to the second clock signal end, a first electrode of the eighth transistor is electrically coupled to the input end, and a second electrode of the eighth transistor is electrically coupled to the first output node.

[0088] In a possible embodiment of the present disclosure, the eighth transistor is a doublegate transistor.

[0089] In a possible embodiment of the present disclosure, the first output node control circuit includes a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor. A gate electrode of the sixth transistor is electrically coupled to the first clock signal end, and a first electrode of the sixth transistor is electrically coupled to the first voltage end. A gate electrode of the seventh transistor is electrically coupled to the first node, a first electrode of the seventh transistor is electrically coupled to a second electrode of the sixth transistor, and a second electrode of the seventh transistor is electrically coupled to the third node. A gate electrode of the eighth transistor is electrically coupled to the second clock signal end, a first electrode of the eighth transistor is electrically coupled to the input end, and a second electrode of the eighth transistor is electrically coupled to the third node. Agate electrode of the ninth transistor is electrically coupled to the third voltage end, a first electrode of the ninth transistor is electrically coupled to the third node, and a second electrode of the ninth transistor is electrically coupled to the first output node.

[0090] In a possible embodiment of the present disclosure, the first node control circuit includes a tenth transistor and an eleventh transistor. A gate electrode of the tenth transistor is electrically coupled to the first node, a first electrode of the tenth transistor is electrically coupled to the fourth voltage end, and a second electrode of the tenth transistor is electrically coupled to a first electrode of the eleventh transistor. A gate electrode of the eleventh transistor is electrically coupled to the first clock signal end, and a second electrode of the eleventh transistor is electrically coupled to the first node.

[0091] In a possible embodiment of the present disclosure, the second output node control circuit includes a twelfth transistor and a thirteenth transistor. A gate electrode of the twelfth transistor is electrically coupled to the first clock signal end, a first electrode of the twelfth transistor is electrically coupled to the first node, and a second electrode of the twelfth transistor is electrically coupled to the second output node. A gate electrode of the thirteenth transistor is electrically coupled to the first output node, a first electrode of the thirteenth transistor is electrically coupled to the first voltage end, and a second electrode of the thirteenth transistor is electrically coupled to the second output node.

[0092] In a possible embodiment of the present disclosure, the output circuit includes a fourteenth transistor and a fifteenth transistor. A gate electrode of the fourteenth transistor is electrically coupled to the first output node, a first electrode of the fourteenth transistor is electrically coupled to the driving output end, and a second electrode of the fourteenth transistor is electrically coupled to the second voltage end. A gate electrode of the fifteenth transistor is electrically coupled to the second output node, a first electrode of the fifteenth transistor is electrically coupled to the first voltage end, and a second electrode of the fifteenth transistor is electrically coupled to the driving output end.

[0093] In at least one embodiment of the present disclosure, the driving circuit further includes a third energy storage circuit, a first end of the third energy storage circuit is electrically coupled to the second output node, a second end of the third energy storage circuit is electrically coupled to a first voltage end, and the third energy storage circuit is configured to store electric energy.

[0094] During the implementation, the driving circuit further includes the third energy storage circuit configured to maintain the potential at the second output node.

[0095] As shown in FIG. 10, based on the driving circuit in FIG. 7, the driving circuit in at least one embodiment of the present disclosure further includes a third energy storage circuit 101. The second output node control circuit 14 is further electrically coupled to the first output node Nl, the first clock signal end CKB and the first voltage end VI, and configured to control the first node N2 to be electrically coupled to or electrically decoupled from the second output node N4 under the control of the first clock signal from the first clock signal end CKB, and control the second output node N4 to be electrically coupled to or electrically decoupled from the first voltage end V1 under the control of the potential at the first output node N1. The output circuit 15 is further electrically coupled to the first voltage end VI and the second voltage end V2. The output circuit 15 is configured to control the driving output end 01 to be electrically coupled to or electrically decoupled from the second voltage end V2 under the control of the potential at the first output node Nl, and control the driving output end 01 to be electrically coupled to or electrically decoupled from the first voltage end VI under the control of the potential at the second output node N4. A first end of the third energy storage circuit 101 is electrically coupled to the second output node N4, a second end of the third energy storage circuit 101 is electrically coupled to the first voltage end VI, and the third energy storage circuit 101 is configured to store electric energy.

[0096] As shown in FIG. 11, based on the driving circuit in FIG. 8, the driving circuit in at least one embodiment of the present disclosure further includes a third energy storage circuit 101. The second output node control circuit 14 is further electrically coupled to the first output node Nl, the first clock signal end CKB and the first voltage end VI, and configured to control the first node N2 to be electrically coupled to or electrically decoupled from the second output node N4 under the control of the first clock signal from the first clock signal end CKB, and control the second output node N4 to be electrically coupled to or electrically decoupled from the first voltage end V1 under the control of the potential at the first output node Nl. The output circuit 15 is further electrically coupled to the first voltage end VI and the second voltage end V2. The output circuit 15 is configured to control the driving output end 01 to be electrically coupled to or electrically decoupled from the second voltage end V2 under the control of the potential at the first output node Nl, and control the driving output end 01 to be electrically coupled to or electrically decoupled from the first voltage end VI under the control of the potential at the second output node N4. A first end of the third energy storage circuit 101 is electrically coupled to the second output node N4, a second end of the third energy storage circuit 101 is electrically coupled to the first voltage end VI, and the third energy storage circuit 101 is configured to store electric energy.

[0097] As shown in FIG. 12, based on the driving circuit in FIG. 9, the driving circuit in at least one embodiment of the present disclosure further includes a third energy storage circuit 101. The second output node control circuit 14 is further electrically coupled to the first output node Nl, the first clock signal end CKB and the first voltage end VI, and configured to control the first node N2 to be electrically coupled to or electrically decoupled from the second output node N4 under the control of the first clock signal from the first clock signal end CKB, and control the second output node N4 to be electrically coupled to or electrically decoupled from the first voltage end V1 under the control of the potential at the first output node N1. The output circuit 15 is further electrically coupled to the first voltage end VI and the second voltage end V2. The output circuit 15 is configured to control the driving output end 01 to be electrically coupled to or electrically decoupled from the second voltage end V2 under the control of the potential at the first output node Nl, and control the driving output end 01 to be electrically coupled to or electrically decoupled from the first voltage end VI under the control of the potential at the second output node N4. A first end of the third energy storage circuit 101 is electrically coupled to the second output node N4, a second end of the third energy storage circuit 101 is electrically coupled to the first voltage end VI, and the third energy storage circuit 101 is configured to store electric energy.

[0098] As shown in FIG. 13, based on the driving circuit in FIG. 10, the phase inversion circuit includes a first transistor Tl, a second transistor T2, a third transistor T3 and a storage capacitor CO. A gate electrode of the first transistor T1 is electrically coupled to the first output node Nl, a source electrode of the first transistor T1 is electrically coupled to a second node N7, and a drain electrode of the first transistor T1 is electrically coupled to a high voltage end VGH. A gate electrode of the second transistor T2 is electrically coupled to the first output node Nl, a source electrode of the second transistor T2 is electrically coupled to the first node N2, and a drain electrode of the second transistor T2 is electrically coupled to the high voltage end VGH. A gate electrode of the third transistor T3 is electrically coupled to the second node N7, a source electrode of the third transistor T3 is electrically coupled to a low voltage end VGL, and a drain electrode of the third transistor T3 is electrically coupled to the first node N2. A first end of the storage capacitor CO is electrically coupled to a first clock signal end CKB, and a second end of the storage capacitor CO is electrically coupled to the second node N7.

[0099] The first output node control circuit includes a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8. A gate electrode of the sixth transistor T6 is electrically coupled to the first clock signal end CKB, and a source electrode of the sixth transistor T6 is electrically coupled to the high voltage end VGH. Agate electrode of the seventh transistor T7 is electrically coupled to the first node N2, a source electrode of the seventh transistor T7 is electrically coupled to a drain electrode of the sixth transistor T6, and a drain electrode of the seventh transistor T7 is electrically coupled to the first output node Nl. A gate electrode of the eighth transistor T8 is electrically coupled to the second clock signal end CK, a source electrode of the eighth transistor T8 is electrically coupled to the input end STV, and a drain electrode of the eighth transistor T8 is electrically coupled to the first output node Nl.

[0100] The first node control circuit includes a tenth transistor T10 and an eleventh transistor Til. A gate electrode of the tenth transistor T10 is electrically coupled to the first node N2, a source electrode of the tenth transistor T10 is electrically coupled to a second low voltage end VGL2, and a drain electrode of the tenth transistor T10 is electrically coupled to a source electrode of the eleventh transistor Til. A gate electrode of the eleventh transistor Til is electrically coupled to the first clock signal end CKB, and a drain electrode of the eleventh transistor TH is electrically coupled to the first node N2.

[0101] The second output node control circuit includes a twelfth transistor T12 and a thirteenth transistor T13. A gate electrode of the twelfth transistor T12 is electrically coupled to the first clock signal end CKB, a source electrode of the twelfth transistor T12 is electrically coupled to the first node N2, and a drain electrode of the twelfth transistor T12 is electrically coupled to the second output node N4. A gate electrode of the thirteenth transistor T13 is electrically coupled to the first output node Nl, a source electrode of the thirteenth transistor T13 is electrically coupled to the high voltage end VGH, and a drain electrode of the thirteenth transistor T13 is electrically coupled to the second output node N4.

[0102] The output circuit includes a fourteenth transistor T14 and a fifteenth transistor T15. A gate electrode of the fourteenth transistor T14 is electrically coupled to the first output node Nl, a source electrode of the fourteenth transistor T14 is electrically coupled to the driving output end 01, and a drain electrode of the fourteenth transistor T14 is electrically coupled to a low voltage end VGL. A gate electrode of the fifteenth transistor T15 is electrically coupled to the second output node N4, a source electrode of the fifteenth transistor T15 is electrically coupled to the high voltage end VGH, and a drain electrode of the fifteenth transistor T15 is electrically coupled to the driving output end 01.

[0103] The first energy storage circuit includes a first capacitor Cl, a first end of the first capacitor Cl is electrically coupled to the first output node Nl, and a second end of the first capacitor Cl is electrically coupled to the driving output end 01.

[0104] The third energy storage circuit includes a third capacitor C3, a first end of the third capacitor C3 is electrically coupled to the second output node N4, and a second end of the third capacitor C3 is electrically coupled to the high voltage end VGH.

[0105] In at least one embodiment of the present disclosure, a voltage value of a second low voltage signal from VGL2 is greater than a voltage value of a first low voltage signal from VGL1. For example, the voltage value of the first low voltage signal is, but not limited to, -7V, and the voltage value of the second low voltage signal is, but not limited to, -9V.

[0106] In the driving circuit in FIG. 13, all the transistors are, but not limited to, p-type transistors.

[0107] In the driving circuit in FIG. 13, a fifth node N5 is arranged between T6 and T7, and a sixth node N6 is arranged between T10 and T11.

[0108] In the driving circuit in FIG. 13, T8 is a double-gate transistor, so as to reduce the occurrence of current leakage of Cl via T8.

[0109] In the driving circuit in FIG. 13, in order to prevent the current leakage of Cl via T8, an always-on transistor is added. A gate electrode of the always-on transistor is electrically coupled to a low voltage end, and the always-on transistor is arranged between Nl and the gate electrode of T14, so as to stabilize the potential at Nl, and improve the current leakage at Nl.

[0110] As shown in FIG. 14, during the operation of the driving circuit in FIG. 13, a display cycle includes a first stage SI, a second stage S2, a third stage S3, a fourth stage S4, a fifth stage S5 and a sixth stage S6 arranged one after another.

[0111] At the first stage S1, CK provides a high voltage signal, CKB provides a low voltage signal, and STV provides a low voltage signal. The potential at Nl is maintained at a low voltage. As shown in FIG. 15A, T1 and T2 are turned on, the potential at N7 is a high voltage, T3 is turned off, T12 is turned on, T15 is turned off, and T14 is turned on. At this time, 01 outputs a low voltage signal.

[0112] At the second stage S2, CK provides a low voltage signal, CKB provides a high voltage signal, and STV provides a high voltage signal. As shown in FIG. 15B, T8 is turned on, the potential at Nl is a high voltage, T4 is turned off, Tl, T2 and T3 are turned off, T12 is turned off, and T14 and T15 are turned off. At this time, 01 outputs a low voltage signal.

[0113] At the third stage S3, in a case that CK provides a high voltage signal and CKB provides a low voltage signal, STV provides a high voltage signal. As shown in FIG. 15C, the potential of the first clock signal from CKB is pulled down from a high voltage to a low voltage, so the potential at N7 is a low voltage, T3 is turned on, the potential at N2 is a low voltage, Tl 0 and Tl 1 is turned on, N2 is electrically coupled to VGL2, T12 is turned on, the potential at N4 is a low voltage, T15 is turned on, 01 outputs a high voltage signal, T8 is turned off, T6 and T7 are turned on, the potential at N1 is a high voltage, and T14 is turned off

[0114] At the fourth stage S4, in a case that CK provides a low voltage signal and CKB provides a high voltage signal, STV provides a high voltage signal. As shown in FIG. 15D, T8 is turned on, the potential at N1 is a high voltage, T14 is turned off, T1 and T2 are turned off, the potential at N7 is a high voltage, T3 is turned off, the potential at N2 is maintained as a low voltage, T10 is turned on, Til is turned off, T12 is turned off, the potential at N4 is maintained as a low voltage, T15 is turned on, and 01 outputs a high voltage signal.

[0115] At the fifth stage S5, CK provides a low voltage signal, CKB provides a high voltage signal, and STV provides a low voltage signal. As shown in FIG. 15E, T8 is turned on, the potential at N1 is a low voltage, T1 and T2 are turned on, the potential at N7 is a high voltage, T3 is turned off, the potential at N2 is a high voltage, T10 and Til are turned off, T6 and T7 are turned off, T13 are turned on, the potential at N4 is a high voltage, T15 is turned off, T14 is turned on, and 01 outputs a low voltage signal.

[0116] At the sixth stage S6, CK provides a high voltage signal, CKB provides a low voltage signal, and STV provides a low voltage signal. As shown in FIG. 15F, T8 is turned off, the potential at M is maintained as a low voltage, T1 and T2 are turned on, the potential at N7 is a high voltage, T3 is turned off, the potential at N2 is a high voltage, T10 is turned off, T11 is turned off, T12 is turned on, the potential at N4 is a high voltage, T15 is turned off, T14 is turned on, and 01 outputs a low voltage signal.

[0117] As shown in FIG. 14, during the operation of the driving circuit in FIG. 13, there is no step for a falling edge of the driving signal outputted by 01.

[0118] During the operation of the driving circuit in FIG. 13, at the first stage SI, the potential at N1 is a low voltage, the potential at N2 is a high voltage, the potential at N4 is a high voltage, the potential at N5 is a high voltage, the potential at N6 is a low voltage, and 01 outputs a low voltage signal. At the second stage S2, the potential at N1 is a high voltage, the potential at N2 is a high voltage, the potential at N4 is a high voltage, the potential at N5 is a high voltage, the potential at N6 is a low voltage, and 01 outputs a low voltage signal. At the third stage S3, the potential at Nl is a high voltage, the potential at N2 is a low voltage, the potential at N4 is a low voltage, the potential at N5 is a high voltage, the potential at N6 is a low voltage, and 01 outputs a high voltage signal. At the fourth stage S4, the potential at Nl is a low voltage, the potential at N2 is a high voltage, the potential at N4 is a high voltage, the potential at N5 is a high voltage, the potential at N6 is a low voltage, and 01 outputs a low voltage signal. At the fifth stage S5, the potential at Nl is a low voltage, the potential at N2 is a high voltage, the potential at N4 is a high voltage, the potential at N5 is a high voltage, the potential at N6 is a high voltage, and 01 outputs a low voltage signal.

[0119] The driving circuit in FIG. 16 differs from the driving circuit in FIG. 13 in that there is no storage capacitor CO, and the driving circuit in FIG. 16 further includes a fourth transistor T4. A gate electrode and a source electrode of the fourth transistor T4 are both electrically coupled to the low voltage end VGL, and a drain electrode of the fourth transistor T4 is electrically coupled to the second node N7. T4 is a p-type transistor.

[0120] In the driving circuit in FIG. 16, T8 is a double-gate transistor, so as to prevent the occurrence of current leakage of Cl via T8.

[0121] In the driving circuit in FIG. 16, in order to prevent the current leakage of Cl via T8, an always-on transistor is added. A gate electrode of the always-on transistor is electrically coupled to a low voltage end, and the always-on transistor is arranged between N1 and the gate electrode of T14, so as to stabilize the potential at Nl, and improve the current leakage of Nl.

[0122] During the operation of the driving circuit in FIG. 16, a display cycle includes a first stage, a second stage, a third stage, a fourth stage, a fifth stage and a sixth stage arranged one after another.

[0123] At the first stage, CK provides a high voltage signal, CKB provides a low voltage signal, and STV provides a high voltage signal. The potential at Nl is maintained as a low voltage, T1 and T2 are turned on, the potential at N7 is a high voltage, T3 is turned off, T12 is turned on, T15 is turned off, T14 is turned on, and 01 outputs a low voltage signal.

[0124] At the second stage, CK provides a low voltage signal, CKB provides a high voltage signal, and STV provides a high voltage signal. T8 is turned on, the potential at N1 is a high voltage, T4 is turned on, T1 and T2 are turned off, T12 is turned off, T14 and T15 are turned off, and 01 outputs a low voltage signal.

[0125] At the third stage, in a case that CK provides a high voltage signal and CKB provides a low voltage signal, STV provides a high voltage signal. The potential at N1 is a high voltage, T1 and T2 are turned off, T4 is turned on, the potential at N7 is a low voltage, T3 is turned on, the potential at N2 is a low voltage, T10 and Til are turned on, T12 is turned on, the potential at N4 is a low voltage, T15 is turned on, 01 outputs a high voltage signal, T8 is turned off, and T14 is turned off.

[0126] At the third stage, in a case that CK provides a low voltage signal and CKB provides a high voltage signal, STV provides a high voltage signal. T8 is turned on, the potential at N1 is a high voltage, T14 is turned off, T1 and T2 are turned off, T4 is turned on, the potential at N7 is a low voltage, T3 is turned on, the potential at N2 is a low voltage, T10 is turned on, T11 is turned off, T12 is turned off, the potential at N4 is maintained as a low voltage, T15 is turned on, and 01 outputs a high voltage signal.

[0127] At the fourth stage, CK provides a low voltage signal, CKB provides a high voltage signal, and STV provides a low voltage signal. T8 is turned on, the potential at N1 is a low voltage, T1 and T2 are turned on, the potential at N7 is a high voltage, T3 is turned off, the potential at N2 is a high voltage, T10 and Til are turned off, T6 and T7 are turned off, T13 is turned on, the potential atN4 is a high voltage, T15 is turned off, T14 is turned on, and 01 outputs a low voltage signal.

[0128] At the fifth stage, CK provides a high voltage signal, CKB provides a low voltage signal, and STV provides a low voltage signal. T8 is turned off, the potential at N1 is maintained as a low voltage, T1 and T2 are turned on, the potential at N7 is a high voltage, T3 is turned off, the potential atN2 is a high voltage, T10 is turned off, Til is turned off, T12 is turned on, the potential at N4 is a high voltage, T15 is turned off, T14 is turned on, and 01 outputs a low voltage signal.

[0129] FIG. 17 is a sequence diagram of the driving circuit in FIG. 16.

[0130] In the driving circuit in FIG. 16, the gate electrode and the source electrode of T4 are further electrically coupled to the first clock signal end, the second clock signal end or a control end.

[0131] In at least one embodiment of the present disclosure, a control signal from the control end has a phase inverse to an input signal from the STV

[0132] During the operation of the driving circuit in FIG. 16, there is no step for a falling edge of the driving signal outputted by 01.

[0133] The driving circuit in FIG. 18 differs from the driving circuit in FIG. 13 in that the driving circuit in FIG. 18 further includes a fifth transistor T5, a second capacitor C2 and a ninth transistor T9, and the driving circuit in FIG. 18 does not include Cl. A gate electrode of the fifth transistor T5 is electrically coupled to the first output node Nl, a source electrode of the fifth transistor T5 is electrically coupled to the first clock signal end CKB, and a drain electrode of the fifth transistor T5 is electrically coupled to a first end of the second capacitor C2. A second end of the second capacitor C2 is electrically coupled to the first output node Nl. A gate electrode of the ninth transistor T9 is electrically coupled to the low voltage end VGL, a source electrode of the ninth transistor T9 is electrically coupled to the third node N3, and a drain electrode of the ninth transistor T9 is electrically coupled to the first output node Nl. The drain electrode of the seventh transistor T7 is electrically coupled to the third node N3, and the drain electrode of the eighth transistor T8 is electrically coupled to the third node N3.

[0134] In the driving circuit in FIG. 18, all the transistors are, but not limited to, p-type transistors.

[0135] In at least one embodiment of the present disclosure, the driving circuit in FIG. 19 does not include T9.

[0136] The driving circuit in FIG. 18 is added with T5 and C2, and in a case that a potential of the first clock signal from CKB is pulled down from a high level to a low level each time, the potential at Nl is pulled down, so as to enable the driving signal outputted by 01 to be more stable.

[0137] As shown in FIG. 19, during the operation of the driving circuit in FIG. 18, at the first stage SI, STV provides a low voltage signal, CK provides a high voltage signal, and CKB provides a low voltage signal. The potential at N1 is a low voltage, T14 is turned on, and 01 outputs a low voltage signal. At the second stage S2, STV provides a high voltage signal, CK provides a low voltage signal, and CKB provides a high voltage signal. T8 is turned on, the potential at N1 is a high voltage signal, T1 and T2 are turned off, the potential at N7 is a high voltage signal, T3 is turned off, T12 is turned off, T9 is turned on, T14 and T15 are turned off, and 01 outputs a low voltage signal. At the third stage S3, STV provides a high voltage signal, CK provides a high voltage signal, and CKB provides a low voltage signal. T8 is turned off, the potential at N1 is maintained as a high voltage signal, T1 and T2 are turned off, the potential at N7 is a low voltage, T3 is turned on, the potential at N2 is a low voltage, T10 and Til are turned on, T12 is turned on, the potential at N4 is a low voltage, and 01 outputs a high voltage signal. At the fourth stage S4, STV provides a low voltage signal, CK provides a high voltage signal, and CKB provides a low voltage signal. T8 is turned off, the potential at N1 is maintained as a high voltage signal, T1 and T2 are turned off, the potential at N7 is a low voltage signal, T3 is turned on, the potential at N2 is a low voltage, T10 and f 11 are turned on, T12 is turned on, the potential at N4 is a low voltage, T15 is turned on, and 01 outputs a high voltage signal. At the fifth stage S5, STV provides a low voltage signal, CK provides a low voltage signal, and CKB provides a high voltage signal. T8 is turned on, the potential at N1 is a low voltage, T14 is turned on, 01 outputs a low voltage signal, T1 and T2 are turned on, the potential at N2 is a high voltage, T12 is turned off, T13 is turned on, the potential at N4 is a high voltage, and T15 is turned on. At the sixth stage S6, STV provides a low voltage signal, CK provides a high voltage signal, and CKB provides a low voltage signal. T5 is turned on, the potential at N1 is pulled down again due to a coupling effect of C2, T14 is turned on, and 01 outputs a low voltage signal.

[0138] The driving circuit in FIG. 20 differs from the driving circuit in FIG. 18 in that it does not includes the tenth transistor and the eleventh transistor.

[0139] During the implementation, the potential at N2 is controlled by the phase inversion circuit, so the driving circuit in FIG. 20 may operate normally in a case that it does not include the tenth transistor and the eleventh transistor.

[0140] The present disclosure further provides in some embodiments a driving method for the above-mentioned driving circuit, which includes: performing, by a phase inversion circuit, phase inversion on a potential at a first output node, to obtain a potential at a first node; controlling, by a first output node control circuit, the potential at the first output node; obtaining, by a second output node control circuit, a potential at a second output node based on the potential at the first node; and controlling, by an output circuit, a driving output end to output a driving signal under the control of the potential at the first output node and the potential at the second output node.

[0141] The present disclosure further provides in some embodiments a display device including the above-mentioned driving circuit.

[0142] The above are the preferred embodiments of the present disclosure. It should be appreciated that, a person skilled in the art may further make improvements and modifications without departing from the principle of the present disclosure, and these improvements and modifications shall also be considered as the scope of the present disclosure.

Claims

1. A driving circuit, comprising a phase inversion circuit, a first output node control circuit, a second output node control circuit and an output circuit,wherein the phase inversion circuit is electrically coupled to a first output node and a first node, and configured to perform phase inversion on a potential at the first output node within at least a part of stages of a display cycle, to obtain a potential at the first node;the first output node control circuit is electrically coupled to the first output node, and configured to control the potential at the first output node;the second output node control circuit is electrically coupled to the first node and a second output node, and configured to obtain a potential at the second output node based on the potential at the first node; andthe output circuit is electrically coupled to the first output node, the second output node and a driving output end, and configured to control the driving output end to output a driving signal under the control of the potential at the first output node and the potential at the second output node.

2. The driving circuit according to claim 1, further comprising a first energy storage circuit, wherein the first energy storage circuit is electrically coupled to the first output node and the driving output end and configured to storage electric energy.

3. The driving circuit according to claim 1, wherein the phase inversion circuit comprises a first transistor, a second transistor, a third transistor and a storage capacitor;a gate electrode of the first transistor is electrically coupled to the first output node, a first electrode of the first transistor is electrically coupled to a second node, and a second electrode of the first transistor is electrically coupled to a first voltage end;a gate electrode of the second transistor is electrically coupled to the first output node, a first electrode of the second transistor is electrically coupled to the first node, and a second electrode of the second transistor is electrically coupled to the first voltage end;a gate electrode of the third transistor is electrically coupled to the second node, a first electrode of the third transistor is electrically coupled to a second voltage end, and a second electrode of the third transistor is electrically coupled to the first node; anda first end of the storage capacitor is electrically coupled to a first clock signal end, and a second end of the storage capacitor is electrically coupled to the second node.

4. The driving circuit according to claim 1, wherein the phase inversion circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor;a gate electrode of the first transistor is electrically coupled to the first output node, a first electrode of the first transistor is electrically coupled to a second node, and a second electrode of the first transistor is electrically coupled to a first voltage end;a gate electrode of the second transistor is electrically coupled to the first output node, a first electrode of the second transistor is electrically coupled to the first node, and a second electrode of the second transistor is electrically coupled to the first voltage end;a gate electrode of the third transistor is electrically coupled to the second node, a first electrode of the third transistor is electrically coupled to a second voltage end, and a second electrode of the third transistor is electrically coupled to the first node; anda gate electrode and a first electrode of the fourth transistor are both electrically coupled to a first control end, and a second electrode of the fourth transistor is electrically coupled to the second node.

5. The driving circuit according to claim 4, wherein the first control end is the second voltage end, a first clock signal end, a second clock signal end or a frame resetting end.

6. The driving circuit according to claim 1, further comprising a second energy storage circuit and an on / off control circuit;the on / off control circuit is electrically coupled to the first output node, a first clock signal end and a first end of the second energy storage circuit, and configured to control the first end of the second energy storage circuit to be electrically coupled to or electrically decoupled from the first clock signal end under the control of the potential at the first output node; anda second end of the second energy storage circuit is electrically coupled to the first output node, and the second energy storage circuit is configured to store electric energy.

7. The driving circuit according to claim 6, wherein the on / off control circuitcomprises a fifth transistor, and the second energy storage circuit comprises a second capacitor;a gate electrode of the fifth transistor is electrically coupled to the first output node, a first electrode of the fifth transistor is electrically coupled to the first clock signal end, and a second electrode of the fifth transistor is electrically coupled to a first end of the second capacitor; anda second end of the second capacitor is electrically coupled to the first output node.

8. The driving circuit according to any one of claims 1 to 7, wherein the first output node control circuit is further electrically coupled to an input end, the first node, a first clock signal end, a second clock signal end and a first voltage end, and configured to control the first output node to be electrically coupled to or electrically decoupled from the first voltage end under the control of a first clock signal from the first clock signal end and the potential at the first node, and control the first output node to be electrically coupled to or electrically decoupled from the input end under the control of a second clock signal from the second clock signal end.

9. The driving circuit according to any one of claims 1 to 7, wherein the first output node control circuit is further electrically coupled to a third node, an input end, a secondclock signal end, the first node, a first voltage end, a first clock signal end and a third voltage end, and configured to control the third node to be electrically coupled to or electrically decoupled from the input end under the control of a second clock signal from the second clock signal end, control the third node to be electrically coupled to or electrically decoupled from the first voltage end under the control of the potential at the first node and a first clock signal from the first clock signal end, and control the third node to be electrically coupled to or electrically decoupled from the first output node under the control of a third voltage signal from the third voltage end.

10. The driving circuit according to any one of claims 1 to 7, further comprising a first node control circuit, wherein the first node control circuit is electrically coupled to the first node, a fourth voltage end and a first clock signal end, and configured to control the first node to be electrically coupled to or electrically decoupled from the fourth voltage end under the control of the potential at the first node and a first clock signal from the first clock signal end.

11. The driving circuit according to any one of claims 1 to 7, wherein the second output node control circuit is further electrically coupled to the first output node, a first clock signal end and a first voltage end, and configured to control the first node to be electrically coupled to or electrically decoupled from the second output node under the control of a first clock signal from the first clock signal end, and control the second output node to be electrically coupled to or electrically decoupled from the first voltage end under the control of the potential at the first output node.

12. The driving circuit according to any one of claims 1 to 7, wherein the output circuit is further electrically coupled to a first voltage end and a second voltage end, and the output circuit is configured to control the driving output end to be electrically coupled to or electrically decoupled from the second voltage end under the control of the potential at the first output node,and control the driving output end to be electrically coupled to or electrically decoupled from the first voltage end under the control of the potential at the second output node.

13. The driving circuit according to claim 8, wherein the first output node control circuit comprises a sixth transistor, a seventh transistor and an eighth transistor; a gate electrode of the sixth transistor is electrically coupled to the first clock signal end, and a first electrode of the sixth transistor is electrically coupled to the first voltage end; a gate electrode of the seventh transistor is electrically coupled to the first node, a first electrode of the seventh transistor is electrically coupled to a second electrode of the sixth transistor, and a second electrode of the seventh transistor is electrically coupled to the first output node; and a gate electrode of the eighth transistor is electrically coupled to the second clock signal end, a first electrode of the eighth transistor is electrically coupled to the input end, and a second electrode of the eighth transistor is electrically coupled to the first output node.

14. The driving circuit according to claim 13, wherein the eighth transistor is a double-gate transistor.

15. The driving circuit according to claim 9, wherein the first output node control circuit comprises a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor;a gate electrode of the sixth transistor is electrically coupled to the first clock signal end, and a first electrode of the sixth transistor is electrically coupled to the first voltage end;a gate electrode of the seventh transistor is electrically coupled to the first node, a first electrode of the seventh transistor is electrically coupled to a second electrode of the sixth transistor, and a second electrode of the seventh transistor is electrically coupled to the third node;a gate electrode of the eighth transistor is electrically coupled to the second clock signal end, a first electrode of the eighth transistor is electrically coupled to the input end, and a second electrode of the eighth transistor is electrically coupled to the third node; anda gate electrode of the ninth transistor is electrically coupled to the third voltage end, a first electrode of the ninth transistor is electrically coupled to the third node, and a second electrode of the ninth transistor is electrically coupled to the first output node.

16. The driving circuit according to claim 10, wherein the first node control circuit comprises a tenth transistor and an eleventh transistor;a gate electrode of the tenth transistor is electrically coupled to the first node, a first electrode of the tenth transistor is electrically coupled to the fourth voltage end, and a second electrode of the tenth transistor is electrically coupled to a first electrode of the eleventh transistor; anda gate electrode of the eleventh transistor is electrically coupled to the first clock signal end, and a second electrode of the eleventh transistor is electrically coupled to the first node.

17. The driving circuit according to claim 11, wherein the second output node control circuit comprises a twelfth transistor and a thirteenth transistor;a gate electrode of the twelfth transistor is electrically coupled to the first clock signal end, a first electrode of the twelfth transistor is electrically coupled to the first node, and a second electrode of the twelfth transistor is electrically coupled to the second output node; anda gate electrode of the thirteenth transistor is electrically coupled to the first output node, a first electrode of the thirteenth transistor is electrically coupled to the first voltage end, and a second electrode of the thirteenth transistor is electrically coupled to the second output node.

18. The driving circuit according to claim 12, wherein the output circuit comprises a fourteenth transistor and a fifteenth transistor;a gate electrode of the fourteenth transistor is electrically coupled to the first output node, a first electrode of the fourteenth transistor is electrically coupled to the driving output end,and a second electrode of the fourteenth transistor is electrically coupled to the second voltage end; anda gate electrode of the fifteenth transistor is electrically coupled to the second output node, a first electrode of the fifteenth transistor is electrically coupled to the first voltage end, and a second electrode of the fifteenth transistor is electrically coupled to the driving output end.

19. The driving circuit according to any one of claims 1 to 6, further comprising a third energy storage circuit, wherein a first end of the third energy storage circuit is electrically coupled to the second output node, a second end of the third energy storage circuit is electrically coupled to a first voltage end, and the third energy storage circuit is configured to store electric energy.

20. A driving method for the driving circuit according to any one of claims 1 to 19, comprising:performing, by a phase inversion circuit, phase inversion on a potential at a first output node, to obtain a potential at a first node;controlling, by a first output node control circuit, the potential at the first output node;obtaining, by a second output node control circuit, a potential at a second output node based on the potential at the first node; andcontrolling, by an output circuit, a driving output end to output a driving signal under the control of the potential at the first output node and the potential at the second output node.

21. A display device, comprising the driving circuit according to any one of claims 1 to 19.INTERNATIONAL SEARCH REPORT International application No. PCT / CN2024 / 099163A. CLASSIFICATION OF SUBJECT MATTER G09G3 / 20(2006.01)i According to International Patent Classification (IPC) or to both national classification and IPC B. FIELDS SEARCHED Minimum documentation searched (classification system followed by classification symbols) IPC: G09G3 Documentation searched other than minimum documentation to the extent that such documents are included in the fields searched Electronic data base consulted during the international search (name of data base and, where practicable, search terms used) CNABS, CNTXT, ENTXT, DWPI: g, 7?*, jWJfEM GOA, regist?r, gate, driv+, shift, revers+, phase, inverter, stor+, energy, node, on, off, control+ C. DOCUMENTS CONSIDERED TO BE RELEVANT Category* Citation of document, with indication, where appropriate, of the relevant passages Relevant to claim No. Y CN 110942742 A (BOE TECHNOLOGY GROUP CO., LTD.; SCHOOL OF SOFTWARE AND MICROELECTRONICS, PEKING UNIVERSITY) 31 March 2020 (2020-03-31) description, paragraphs 0030-0050, and figures 1-2 1-2, 20-21 Y A CN 115019731 A (HEFEI BOE ZHUOYIN TECHNOLOGY CO., LTD.; BOE TECHNOLOGY GROUP CO., LTD.) 06 September 2022 (2022-09-06) description, paragraphs 0098-0109, and figure 1 CN 113990233 A (FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.; BOE TECHNOLOGY GROUP CO., LTD.) 28 January 2022 (2022-01-28) entire description 1-2, 20-21 1-21 A CN 116403528 A (BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.; BOE TECHNOLOGY GROUP CO., LTD.) 07 July 2023 (2023-07-07) entire description 1-21 A US 2018144677 Al (BOE TECHNOLOGY GROUP CO., LTD.; BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.) 24 May 2018 (2018-05-24) entire description 1-21 | | Further documents are listed in the continuation of Box C. | J | See patent family annex. * Special categories of cited documents: “T” later document published after the international filing date or priority “A” document defining the general state of the art which is not considered date and not in conflict with the application but cited to understand the to be of particular- relevance principle or theory underlying the invention “D” document cited by the applicant in the international application -‘X” document of particular relevance; the claimed invention cannot be “E" earlier application or patent but published on or after the international considered novel or cannot be considered to involve an inventive step filing date when the document is taken alone “L" document which may throw doubts on priority claim(s) or which is “Y” document of particular relevance; the claimed invention cannot be cited to establish the publication date of another citation or other considered to involve an inventive step when the document is special reason (as specified) combined with one or more other such documents, such combination “O” document referring to an oral disclosure, use, exhibition or other being obvious to a person skilled in the ait means document member of the same patent family “P” document published prior to the international filing date but later than the priority date claimed Date of the actual completion of the international search 11 September 2024 Date of mailing of the international search report 11 September 2024 Name and mailing address of the ISA / CN China National Intellectual Property Administration (ISA / CN) China No. 6, Xitucheng Road, Jimenqiao, Haidian District, Beijing 100088 Authorized officer Telephone No.

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