Gate driver with temperature monitoring feature

Abstract

To provide a galvanically isolated gate driver for a power transistor, and a power switching system including the same.SOLUTION: In a power switching system, a gate driver 300 includes: a gate-driver temperature sensor 310 configured to measure a gate-driver temperature TGD; a gate-driver temperature sense circuit 400 configured to receive a signal (e.g., voltage) corresponding to the gate-driver temperature and output an internal fault signal based on the gated driver temperature; a transistor temperature sense circuit 510 configured to receive a transistor temperature from a transistor temperature sensor 330; and a transistor temperature monitor circuit 520. The transistor temperature sense circuit is configured to output an external fault signal based on the transistor temperature. The transistor temperature monitor circuit 520 is configured to output an external monitor signal based on the transistor temperature.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 63 / 219,876, filed July 9, 2021.

[0002] FIELD OF THE INVENTION The present disclosure relates to power switching systems, and more particularly to isolated gate drivers with circuitry for monitoring and transmitting temperature. [Background technology]

[0003] A gate driver is an integrated circuit configured to convert low-voltage (LV) switching signals into high-voltage (HV) signals suitable for driving power transistors ON / OFF. Some systems (e.g., automotive systems, computer systems) need to monitor thermal conditions to protect against potentially damaging faults. Summary of the Invention

[0004] In some aspects, the technology described herein relates to a power switching system comprising: a switch module including a power transistor and a transistor temperature sensor configured to measure a transistor temperature of the power transistor; a gate driver coupled to the switch module, the gate driver including a gate driver temperature sensor configured to measure a gate driver temperature of the gate driver, a gate driver temperature sense circuit configured to output an internal fault signal based on the gate driver temperature, the transistor temperature sense circuit configured to receive the transistor temperature from the transistor temperature sensor and to output an external fault signal based on the transistor temperature, and a transceiver configured to transmit a combined signal corresponding to the internal fault signal and the external fault signal across an isolation barrier of the gate driver via a shared communication channel.

[0005] In some aspects, the technology described herein relates to a power switching system in which a transceiver is configured to: transmit a composite signal to a low-voltage side of a gate driver over a shared communication channel, the composite signal including a first pulse train signal corresponding to an internal fault signal and a second pulse train signal corresponding to an external fault signal; output a ready signal at a ready pin of the gate driver, the ready signal corresponding to the first pulse train signal; and output a detected temperature fault signal at a temperature fault pin of the gate driver, the detected temperature fault signal corresponding to the second pulse train signal.

[0006] In some aspects, the technology described herein relates to a power switching system, wherein the gate driver temperature sense circuit includes a comparator configured to receive a voltage from the gate driver temperature sensor at a first input and a thermal shutdown threshold voltage at a second input, the comparator further configured to output an internal fault signal, the internal fault signal being at a normal level when no thermal fault exists in the gate driver.

[0007] In some aspects, the technology described herein relates to a power switching system, wherein the transistor temperature sense circuit includes a comparator, the comparator configured to receive a voltage from the transistor temperature sensor at a first input and a fault threshold voltage at a second input, the comparator further configured to output an external fault signal, the external fault signal being at a fault level when a thermal fault exists in the power transistor.

[0008] In some aspects, the technology described herein relates to a power switching system, including a transceiver including a ready encoder configured to generate a first pulse train signal while an internal fault signal is at a normal level and not generate the first pulse train signal otherwise; a temperature fault encoder configured to generate a second pulse train signal while a transistor temperature is at a fault level and not generate the second pulse train signal otherwise, the first pulse train signal having a lower bandwidth compared to the second pulse train signal and the second pulse train signal having a higher bandwidth compared to the first pulse train signal; and a multiplexer configured to combine an output of the ready encoder and an output of the temperature fault encoder to generate a composite signal and send the composite signal to a high voltage side of a transformer.

[0009] In some aspects, the technology described herein relates to a power switching system, wherein the transceiver further includes a ready decoder configured to receive a composite signal from a low voltage side of a transformer, the ready decoder including: a filter configured to separate a first pulse train signal from the composite signal based on a lower bandwidth of the first pulse train signal; and a pulse detector configured to detect pulses in the first pulse train signal and to output a ready signal at a ready level while the pulses of the first pulse train signal are detected.

[0010] In some aspects, the technology described herein relates to a power switching system, wherein the pulse detector is further configured to output a ready signal at a not-ready level after a plurality of pulses of the first pulse train signal are not detected.

[0011] In some aspects, the technology described herein relates to a power switching system, wherein the transceiver further includes a temperature fault decoder configured to receive the composite signal from the low voltage side of the transformer, the temperature fault decoder including a frequency detector configured to detect a higher bandwidth of the second pulse train signal and to detect the fault signal at a fault level while the second pulse train signal is detected in the composite signal.

[0012] In some aspects, the technology described herein relates to a power switching system, wherein the frequency detector is further configured to output a fault signal at a non-fault level while the second pulse train signal is not detected in the composite signal.

[0013] In some aspects, the technology described herein relates to a power switching system, further including: the transistor temperature sensor is a first transistor temperature sensor configured to measure a first transistor temperature of the power transistor; the switch module further includes a second transistor temperature sensor configured to measure a second transistor temperature of the power transistor; the transistor temperature sense circuit is a first temperature sense circuit configured to receive the first transistor temperature from the first transistor temperature sensor and output a first signal based on the first transistor temperature; the gate driver is a second temperature sense circuit configured to receive the second transistor temperature from the second transistor temperature sensor and output a second signal based on the second transistor temperature; and a logic gate configured to receive the first signal and the second signal and to output an external fault signal, the external fault signal having a level corresponding to a thermal fault when either the first signal or the second signal has a level corresponding to a thermal fault of the power transistor.

[0014] In some aspects, the technology described herein relates to a power switching system, wherein the transceiver of the gate driver is a first transceiver, the gate driver further including a transistor temperature monitoring circuit configured to compare a transistor temperature to a ramp signal and output an external monitoring signal, the external monitoring signal being pulse width modulated (PWM) according to the transistor temperature, and a second transceiver configured to transmit the external monitoring signal across an isolation barrier of the gate driver via a dedicated communication channel.

[0015] In some aspects, the technology described herein relates to a power switching system, wherein the second transceiver further includes an inverter configured to invert the external monitoring signal to a relatively low level for a longer period of time than the external monitoring signal is at a relatively high level while a transistor temperature of the power transistor is within a normal temperature range of the power transistor, to reduce power consumed by the second transceiver.

[0016] In some aspects, the technology described herein relates to a power switching system, wherein a gate driver is coupled to a transistor temperature sensor at a first temperature sense pin, the gate driver further including a second temperature sense pin and a disable circuit configured to disable the second temperature sense pin while the second temperature sense pin is not coupled to the second temperature sensor to reduce power consumed by the gate driver.

[0017] In some aspects, the technology described herein relates to a method for monitoring thermal conditions in a power switching system, the method including receiving a transistor temperature of a power transistor at a sense pin of a gate driver, comparing the transistor temperature to a fault threshold and generating an external fault signal based on the comparison, measuring the gate driver temperature with a gate driver sensor of the gate driver, comparing the gate driver temperature to a thermal shutdown threshold and generating an internal fault signal based on the comparison, generating a first pulse train signal based on the internal fault signal, generating a second pulse train signal based on the external fault signal, combining the first pulse train signal and the second pulse train signal to generate a composite signal, and transmitting the composite signal over a shared communication channel across an isolation barrier of the gate driver.

[0018] In some aspects, the techniques described herein relate to a method further including decoding a composite signal based on the first pulse train signal to generate a ready signal, and decoding the composite signal based on the second pulse train signal to generate a detected temperature fault signal, wherein the ready signal corresponds to a thermal fault condition of a gate driver temperature and the detected temperature fault signal corresponds to a thermal fault condition of a power transistor.

[0019] In some aspects, the techniques described herein relate to a method further including comparing a transistor temperature to a ramp signal to generate an external monitoring signal, the external monitoring signal being pulse-width modulated (PWM) according to the transistor temperature, and transmitting the external monitoring signal across an isolation barrier of the gate driver via a dedicated communication channel.

[0020] In some aspects, the techniques described herein relate to a method in which transmitting an external monitoring signal over a dedicated communication channel includes inverting the external monitoring signal to reduce power consumed to transmit the external monitoring signal across an isolation barrier of a gate driver.

[0021] In some aspects, the technology described herein relates to a gate driver including a temperature sensing and monitoring circuit that includes: a gate driver temperature sensor configured to measure a gate driver temperature of the gate driver; a gate driver temperature sense circuit configured to output an internal fault signal based on the gate driver temperature; a transistor temperature sense circuit configured to receive a transistor temperature from a transistor temperature sensor coupled to the gate driver and to output an external fault signal based on the transistor temperature; and a transceiver configured to transmit a combined signal corresponding to the internal fault signal and the external fault signal across an isolation barrier of the gate driver via a shared communication channel.

[0022] In some aspects, the technology described herein relates to a gate driver in which a transceiver is configured to: transmit a composite signal to a low-voltage side of the gate driver over a shared communication channel, the composite signal including a first pulse train signal corresponding to an internal fault signal and a second pulse train signal corresponding to an external fault signal; output a ready signal at a ready pin of the gate driver, the ready signal corresponding to the first pulse train signal; and output a detected temperature fault signal at a temperature fault pin of the gate driver, the detected temperature fault signal corresponding to the second pulse train signal.

[0023] In some aspects, the technology described herein relates to a gate driver further including a transistor temperature monitoring circuit configured to generate a pulse-width modulated signal corresponding to the transistor temperature, the pulse-width modulated signal being transmitted to a low-voltage side of the gate driver via a dedicated communication channel.

[0024] The foregoing exemplary summary, other exemplary objects and / or advantages of the present disclosure, and the manner in which they are accomplished are further described in the following detailed description and its accompanying drawings. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is a block diagram that schematically illustrates a power switching system according to one possible implementation of the present disclosure. [Figure 2] 1 is a flowchart of a method for monitoring thermal conditions in a power switching system according to one possible implementation of the present disclosure. [Figure 3] 1 is a block diagram illustrating a schematic circuit of a power switching system according to one possible implementation of the present disclosure. [Figure 4] FIG. 1 is a schematic diagram of a gate driver temperature sensing circuit according to one possible implementation of the present disclosure. [Figure 5] FIG. 1 is a schematic diagram illustrating a transistor temperature sensing monitoring circuit according to one implementation of the present disclosure. [Figure 6] 10 illustrates signals from a transistor temperature sensing circuit and a transistor temperature monitoring circuit for a first temperature sensing input and a second temperature sensing input of a gate driver according to one possible implementation of the present disclosure. [Figure 7] 1 shows a block diagram of a portion of a high voltage side of a gate driver of a power switching system according to one possible implementation of the present disclosure. [Figure 8] 1 shows a block diagram of a portion of a low-voltage side of a gate driver of a power switching system according to one possible implementation of the present disclosure. [Figure 9] FIG. 10 is a schematic diagram of a disable circuit for a temperature sense pin of a gate driver according to one possible implementation of the present disclosure.

[0026] The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals indicate corresponding parts throughout the several views. DETAILED DESCRIPTION OF THE INVENTION

[0027] Switching of large currents can be achieved using power transistors. The power transistors may be metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs). The power transistors may be fabricated using silicon (Si) or silicon carbide (SiC) processes. In high-voltage (HV) circuits, the power transistors may be configured to conduct current in an on-state or to block current in an off-state. The state of the power transistor may be set by a gate driver coupled to a control terminal (e.g., gate terminal) of the power transistor.

[0028] The gate driver is configured to convert low-voltage (LV) signals from the controller into high-voltage (HV) signals for the power transistors. Thus, the gate driver can have a low-voltage side including low-voltage circuits / devices that handle signals relative to a low-voltage ground and a high-voltage side including high-voltage circuits / devices that have signals relative to a high-voltage (i.e., power) ground. To separate these grounds and prevent low-voltage electronics on the low-voltage side from being damaged by high-voltage signals on the high-voltage side, an isolation barrier is included in the gate driver. In other words, the isolation barrier can provide galvanic isolation between the low-voltage side and the high-voltage side of the gate driver. Transmission of signals through (i.e., across) the isolation barrier may be performed using inductive coupling of magnetic signals. A transformer may be configured to provide the inductive coupling and the isolation barrier. Transmission of signals through (i.e., across) the isolation barrier may also be performed using capacitive coupling of electrical signals. A capacitor (or multiple capacitors) may be configured to provide the capacitive coupling and the isolation barrier. The techniques of this disclosure can use any of these implementations.

[0029] The isolation barrier may be implemented as a transformer having a primary winding on the LV side of the gate driver and a secondary winding on the HV side of the gate driver. The transformer can magnetically couple signals between its windings that are within the frequency bandwidth of the transformer. Thus, the gate driver may include a transmitter configured to encode (e.g., modulate) a signal so that the signal is in a bandwidth (e.g., frequency) suitable for magnetic coupling, and a receiver configured to decode the encoded signal after it is magnetically coupled. The transmitter and receiver may collectively be referred to as a transceiver.

[0030] In recent years, gate drivers have been expected to perform more functions than just switching. For example, gate drivers may be expected to perform fault monitoring and reporting functions. These additional functions may increase the number of signals that must be transmitted across an isolation barrier, which may in turn increase the size of the gate driver and / or increase the power consumed by the gate driver. Furthermore, some implementations may require redundant fault detection. One technical challenge in meeting these demands is maintaining a reasonable size, cost, and complexity of the gate driver. This disclosure describes a gate driver that reduces the complexity and power consumption of its thermal monitoring (i.e., temperature monitoring), fault detection, and thermal reporting circuitry.

[0031] High current levels switched by power transistors can be damaging or dangerous if the power transistors malfunction (i.e., fail) during operation. High temperatures in the power transistors and / or gate drivers can indicate malfunction. Therefore, temperature sensors can be included in power systems to measure the temperature of the power transistors and / or gate drivers. The gate drivers can be configured to generate a fault and communicate the fault to a controller when one or more of the measured temperatures exceed a threshold, and the controller can be programmed to take action to reduce the temperature or completely cease operation. In some implementations, continuous measurement of the power transistor's temperature is required in addition to a fault signal for diagnostics. This disclosure further describes gate drivers that can provide redundancy between real-time monitoring of temperature and over-temperature (i.e., failure) detection.

[0032] Gate drivers can be used in a variety of applications, such as automotive or computing. Each application can have different requirements for temperature safety. For example, some applications may require multiple (e.g., two) temperature sensors. Using redundant sensors to measure the temperature of power transistors can increase the certainty that a failure event can be detected and addressed before it becomes severe. This additional functionality requires the gate driver to consume more power, which is undesirable when used in applications that do not have such strict requirements. The present disclosure further describes a gate driver that can reduce power consumption in applications that do not require more than two temperature sensors. In other words, the gate driver of the present disclosure can automatically detect the absence of a temperature sensor and, in response to this detection, reduce the power consumed by the gate driver.

[0033] 1 is a block diagram schematically illustrating a power switching system according to one possible implementation of the present disclosure. The power switching system 100 includes a controller 110, a gate driver 150, and a switch module 130. The controller 110 can be configured to send LV switching signals to the gate driver 150 to control the power transistor 135 to an ON or OFF state. Furthermore, the controller 110 can be configured to receive feedback signals from the gate driver to indicate the status (e.g., a thermal fault status) of the gate driver 150 and / or the power transistor 135. These feedback signals can be transmitted between the gate driver 150 and the controller 110 via pin-to-pin communication. In other words, the feedback signals do not require digitization and communication circuitry to transmit this information back via a digital bus. The feedback signals can be signals having a HIGH or LOW level to indicate a status (i.e., binary) or analog signals corresponding to a continuous range of values ​​(e.g., voltage).

[0034] The gate driver 150 can be configured to send a ready signal (RDY) to the controller 110 on the ready pin 155. The level of the ready signal indicates whether the gate driver 150 is in a thermal fault state (i.e., not ready for operation) or not in a thermal fault state (i.e., ready for operation). A thermal fault state can occur when the gate driver 150 is at a temperature outside (e.g., above) its normal operating range. For example, if the gate driver temperature is higher than the maximum temperature (i.e., higher than the thermal shutdown (TSD) threshold), the RDY signal on the ready pin 155 can indicate a thermal fault exists in the gate driver. In one possible implementation, the RDY signal is HIGH for normal gate driver temperatures and LOW for abnormal (i.e., high) gate driver temperatures (i.e., a fault).

[0035] The gate driver 150 can be further configured to send a detected temperature fault signal (TSFLT) at a fault pin 156 to the controller 110. The level of the detected temperature fault signal indicates whether the power transistor 135 is in a thermal fault state or not. A thermal fault state can occur when the power transistor 135 is at a temperature outside (e.g., above) a normal operating range (e.g., 100° C.≦T≦175° C.). For example, if the transistor temperature of the power transistor 135 is higher than a maximum temperature (i.e., above a fault threshold), the TSFLT signal at the fault pin 156 can indicate that a thermal fault exists in the switch module 130 (i.e., the power transistor 135). In one possible implementation, the TSFLT signal is HIGH for normal transistor temperatures and LOW for abnormal (i.e., high) transistor temperatures.

[0036] The gate driver 150 may be further configured to send a transistor temperature signal (TSPWM) at a pulse-width modulated output pin (i.e., PWM output pin 157) to the controller 110. The transistor temperature signal (TSPWM) may be a square-wave signal with a frequency (e.g., 10 kilohertz (KHz)) pulse-width modulated to have a duty cycle corresponding to a first signal (i.e., first transistor temperature (TS1)) received at the first temperature sense pin 151 or a second signal (i.e., second transistor temperature TS2) received at the second temperature sense pin 152. In one possible implementation, a temperature range of −40° C. to +175° C. may be mapped to a duty cycle range of 10% to 90%. Thus, the controller may be configured to continuously measure the duty cycle of the TSPWM signal to monitor the temperature of the power transistor 135.

[0037] The gate driver 150 includes an isolation barrier 102 that separates a high-voltage side 103 of the gate driver 150 from a low-voltage side 104 of the gate driver. Signals from the high-voltage side of the gate driver output at a ready pin 155 and a fault pin 156 may be transmitted across the isolation barrier 102 via a shared communication channel 158, and signals from the high-voltage side of the gate driver output at a PWM output pin 157 may be transmitted across the isolation barrier 102 of the gate driver 150 via a dedicated communication channel 159.

[0038] The first temperature sense pin 151 may be coupled to a first transistor temperature sensor 131 of the switch module 130. The first transistor temperature sensor 131 may be configured to measure a first transistor temperature (i.e., TS1) of the power transistor 135. The second temperature sense pin 152 is optionally coupled to a second transistor temperature sensor 132 of the switch module 130. The second transistor temperature sensor 132 may be configured to measure a second transistor temperature (i.e., TS2) of the power transistor 135. The first transistor temperature sensor 131 and the second transistor temperature sensor 132 may be the same type of sensor (e.g., a thermistor, an NTC, etc.) or may be different. Furthermore, the second transistor temperature sensor 132 may be integrated with the switch module 130 or may be a single device coupled to the switch module 130 or other circuitry within the power switching system 100.

[0039] The gate driver 150 may include a gate driver temperature sensor 160 configured to measure a gate driver temperature of the gate driver 150. The gate driver temperature sensor 160 may be integrated with other circuits of the gate driver 150 in a common package (i.e., an integrated circuit (IC)). A fault signal (e.g., thermal shutdown, IGBT temperature detection) determined based on signals from the first temperature sense pin 151 and the gate driver temperature sensor 160 (and optionally a second temperature sense pin) may be transmitted across the isolation barrier 102 via a shared communication channel 158. Furthermore, a real-time temperature based on signals at the first temperature sense pin (and optionally a second temperature sense pin) may be transmitted across the isolation barrier 102 via a dedicated communication channel 159. Thus, the techniques of the present disclosure describe multiple communication paths for temperature information that provide an additional layer of safety to the system.

[0040] 1 shows that the switch module 130 may be coupled to an output pin 153 of the gate driver 150 so that an output signal (OUT) from the gate driver can control the on / off of a power transistor 135 (e.g., an IGBT). The switch module 130 may further be coupled to a ground pin 154. The gate driver 150 and the switch module 130 are grounded to a power ground 140.

[0041] 2 illustrates a method for monitoring thermal conditions in a power switching system. For example, gate driver 150 may be configured to perform the operations of this method. Accordingly, temperatures and faults may be referred to as internal if they correspond to circuitry within gate driver 150, or external if they correspond to circuitry coupled to the outside of gate driver 150 (e.g., switch module 130).

[0042] The method 200 includes step 205 of measuring a gate driver temperature, such as from a gate driver temperature sensor 160. The method 200 further includes step 210 of determining an internal fault condition by comparing the gate driver temperature to a thermal shutdown (TSD) threshold 215. The comparison may result in an internal fault signal. The internal fault signal may have two levels (e.g., binary levels) corresponding to the presence / absence of the internal fault condition. The method 200 further includes step 220 of generating a first pulse train signal based on the internal fault signal. For example, pulses may be generated while the internal fault condition is not present (i.e., during normal conditions) and not transmitted while the internal fault condition is present (i.e., during thermal shutdown).

[0043] Method 200 further includes receiving 230 a transistor temperature 225, such as a first transistor temperature (i.e., TS1), from first transistor temperature sensor 131 at first temperature sense pin 151. Method 200 further includes determining 235 an external fault condition by comparing transistor temperature 225 to a fault threshold 240. The comparison may result in an external fault signal. The external fault signal may have two levels (e.g., binary levels) corresponding to the presence / absence of the external fault condition. Method 200 further includes generating 245 a second pulse train signal based on the external fault signal. For example, pulses may be generated while the external fault condition is present and not transmitted while the external fault condition is not present (i.e., during normal conditions).

[0044] The method 200 further includes step 250 of combining the first pulse train signal and the second pulse train signal to form a composite signal. The first pulse train signal and the second pulse train signal may have different bandwidths. For example, the pulses of the first pulse train signal may have a first pulse width that is longer than the second pulse width of the pulses of the second pulse train signal. Furthermore, the first period of the first pulse train signal may be longer than the second period of the second pulse train signal. In one possible implementation, the first pulse train signal may include a first pulse width of 65 nanoseconds (65 ns) and a first period of 3 microseconds (3 μs), and the second pulse train signal may include a second pulse width of 10 ns and a second period of 150 ns. Thus, the first pulse train signal may have a lower bandwidth than the second pulse train signal. The composite signal may include pulses of a first pulse width and a first period, and pulses of a second pulse width and a second period.

[0045] The method 200 further includes transmitting 255 the combined signal over the shared communication channel 158. This can advantageously simplify the electronics required to communicate the two signals from the high-voltage side 103 to the low-voltage side 104 of the gate driver 150.

[0046] The method 200 further includes decoding 260 the composite signal based on the first pulse train signal. The decoding 260 may include filtering the composite signal to recover the first pulse train signal from the composite signal. The decoding 260 may further include detecting pulses and generating a ready signal (RDY) at the ready pin 155.

[0047] The method 200 further includes decoding 270 the composite signal based on the second pulse train signal. The decoding 270 may include detecting a high frequency in the composite signal to determine that the second pulse train signal is present in the composite signal. Based on this determination, the decoding may generate a sensed temperature fault signal (TSFLT) at the fault pin 156.

[0048] 3 is a block diagram that schematically illustrates the circuitry of a power switching system according to one possible implementation of the present disclosure. The block diagram includes the devices and circuitry of a gate driver 300 that can be configured to perform the operations of the above-described method. The gate driver 300 is configured to measure the gate driver temperature (T GD ) A signal (e.g., a voltage) corresponding to the gate driver temperature is received by a gate driver temperature sense circuit 400 configured to output an internal fault signal based on the gate driver temperature.

[0049] 4 is a schematic diagram of a gate driver temperature sense circuit according to one possible implementation of the present disclosure. The gate driver temperature sense circuit 400 may include a comparator 401 configured to receive a voltage from the gate driver temperature sensor 310 at a first input 410 and a thermal shutdown threshold voltage (VREF) at a second input 420. The thermal shutdown threshold voltage may be generated using various circuits and devices (e.g., a voltage divider, a current / resistor, a bandgap reference, etc.). The comparator is configured to output an internal fault signal. The internal fault signal is a voltage (VREF) that is at a low level when the voltage from the gate driver temperature sensor is less than the thermal shutdown threshold voltage. TSD ) may also be used. TSD ) may be at a HIGH level when the voltage from the gate driver temperature sensor exceeds the thermal shutdown threshold voltage.

[0050] 3, the gate driver 300 further includes a transistor temperature sensing circuit 510 and a transistor temperature monitoring circuit 520 configured to receive the transistor temperature from the transistor temperature sensor 330. The transistor temperature sensing circuit can be configured to output an external fault signal based on the transistor temperature, and the transistor temperature monitoring circuit 520 can be configured to output an external monitoring signal based on the transistor temperature.

[0051] 5 is a schematic diagram illustrating a transistor temperature sensing monitoring circuit according to one implementation of the present disclosure. The temperature sensing monitoring circuit 500 includes a transistor temperature sense circuit 510 and a transistor temperature monitoring circuit 520. The temperature sensing monitoring circuit 500 may be coupled to a first temperature sense pin or a second temperature sense pin of a gate driver to receive a transistor temperature (e.g., TS1, TS2) from a transistor temperature sensor (e.g., first transistor temperature sensor 131, second transistor temperature sensor 132). If a power switching system includes two temperature sensors, the gate driver may include a temperature sensing monitoring circuit 500 for each transistor temperature sensor.

[0052] The transistor temperature sense circuit 510 of the temperature detection monitoring circuit 500 includes a first comparator 511. The first comparator is coupled to the first temperature sense pin 151 (or the second temperature sense pin 152) of the gate driver. The first comparator 511 can be configured to receive a signal at a first input corresponding to the transistor temperature from the first transistor temperature sensor 131 (or the second transistor temperature sensor 132). If the first transistor temperature sensor 131 (or the second transistor temperature sensor 132) is implemented as a thermistor, the signal may be a voltage that decreases as the transistor temperature increases. The first comparator 511 compares this voltage with a fault threshold voltage (V FLT ), the first comparator 511 may be further configured to output an external fault signal. The external fault signal is generated when the voltage from the first transistor temperature sensor 131 (or the second transistor temperature sensor 132) exceeds a fault threshold voltage (V FLT ) is at a HIGH level when TSFLT) In this case, a HIGH level indicates a thermal failure of the power transistor because a low voltage output by the thermistor corresponds to a high physical temperature. In practice, the signal levels can be reversed. In general, the disclosure of specific signal levels herein is provided to aid in understanding how to implement possible implementations and should not be considered limiting of the invention.

[0053] The transistor temperature monitoring circuit 520 of the temperature sensing monitoring circuit 500 includes a second comparator 521. The second comparator 521 is coupled to the first temperature sense pin 151 (or the second temperature sense pin 152) of the gate driver. The second comparator 521 may be configured to receive a signal corresponding to the transistor temperature from the first transistor temperature sensor 131 (or the second transistor temperature sensor 132) at a first input of the second comparator 521. If the first transistor temperature sensor 131 (or the second transistor temperature sensor 132) is implemented as a thermistor, the signal may be a voltage that decreases as the transistor temperature increases. Therefore, the second comparator 521 may be configured to compare this voltage with a ramp signal 522 to generate an external monitoring signal. The external monitoring signal is a pulse-width modulated voltage (V TSPWM ) may also be used.

[0054] 6 shows signals from a transistor temperature sensing circuit and a transistor temperature monitoring circuit for a first temperature sensing input and a second temperature sensing input of a gate driver according to one possible implementation of the present disclosure. In a first graph 601, a ramp signal is applied to V TS1 PWM voltage (V TSPWM ) (i.e., an external monitoring signal) TS1 ) is compared to the ramp signal. As shown in the second graph 602, the duty cycle of the PWM voltage is TS1decreases. In other words, the duty cycle increases as the temperature of the transistor increases. In one possible implementation, a duty cycle that exceeds the maximum duty cycle may trigger a fault.

[0055] In the first graph 601, the voltage from the second transistor temperature sensor (V TS2 ) is the failure threshold voltage (V FLT ) is compared with V TS2 When the external fault signal drops below the fault threshold voltage, the state of the external fault signal may change. As shown in third graph 603, the inverted external fault signal may change from a non-fault state (i.e., HIGH) to a fault state (i.e., LOW). Again, the levels corresponding to the fault / non-fault states may be modified to match the logic of a particular implementation.

[0056] Returning to FIG. 3 , the gate driver 300 further includes a first transceiver 320 configured to transmit an internal fault signal from the gate driver temperature sense circuit 400 and an external fault signal from the transistor temperature sense circuit 510 across the isolation barrier 102 via a shared communication channel. The first transceiver 320 (i.e., the shared transceiver) may include a number of encoders 321 that process (e.g., modulate) signals for transmission and a number of decoders 322 that process (e.g., detect) received signals. The first transceiver 320 may output a ready signal (RDY) on a ready pin 155. The ready signal (RDY) may be at a level indicating that the gate driver is at a normal operating temperature or at a non-ready level indicating that the gate driver is not at a normal operating temperature (i.e., an over-temperature condition). The first transceiver 320 may also output a fault signal on a fault pin 156. The fault signal (TSFLT) may be at a level indicating that the power transistor 135 is at a normal operating temperature, or at a not-ready level indicating that the power transistor is not at a normal operating temperature (e.g., an over-temperature condition).

[0057] 3, the gate driver 300 further includes a second transceiver 340 configured to transmit an external monitoring signal from the transistor temperature monitoring circuit 520 across the isolation barrier 102 via a dedicated communication channel. The second transceiver 340 (i.e., a dedicated transceiver) may include an encoder 341 that processes (e.g., modulates) the signal for transmission and a decoder 342 that processes (e.g., detects) the received signal. The second transceiver 340 may output a temperature monitoring signal (i.e., a PWM signal) at the PWM output pin 157. The PWM signal (TSPWM) may have a duty cycle that corresponds to the temperature measurement of the power transistor.

[0058] 7 shows a block diagram of a portion of the high voltage side of a gate driver of a power switching system according to one possible implementation of the present disclosure. FIG. 7 includes a transmitter portion of a first transceiver 320. The transmitter portion of the first transceiver transmits an internal fault signal (V TSD The transmitter portion of the first transceiver includes a ready encoder 710 configured to generate a first pulse train signal while the external fault signal (V) is at a normal level and not generate a fault signal otherwise. TSFLT The transmitter portion of the first transceiver further includes a multiplexer 730. The multiplexer is configured to generate a combined signal (TX_IN) from the first pulse train signal (A) and the second pulse train signal (B). For example, the multiplexer 730 may be configured to generate a combined signal (TX_IN) from the first pulse train signal (A) and the second pulse train signal (B). For example, the multiplexer 730 may be configured to generate a combined signal (TX_IN) from the external fault signal (V TSFLT ) is at a HIGH level, selects the second pulse train signal, and the external fault signal (V TSFLT ) is at a LOW level. The transmitter can then transmit the composite signal to the high voltage winding 740 (i.e., side) of the first transformer (HV TX).

[0059] FIG. 7 illustrates the transmitter portion of the second transceiver 340. The transmitter portion of the second transceiver includes a PWM inverter (i.e., inverter 750) configured to invert the external monitoring signal to a relatively low level for a longer period of time than the external monitoring signal is at a relatively high level while the transistor temperature is within a typical temperature range (e.g., 100° C.≦T≦175° C.), which may correspond to a duty cycle within a typical duty range (e.g., 67%≦DUTY≦90%). The inverter 750 can consume less current at a low level than at a high level, thereby reducing the current consumed by the transmitter portion of the second transceiver. In other words, the transistor temperature monitoring circuit 520 may output a PWM signal that is high most of the time during operation within the normal temperature range, and the inverter can output an inverted version of this PWM signal that is low most of the time. The inverted PWM signal (C) conveys the same information but requires less power. The transmitter can then transmit the inverted PWM signal (C) to the high voltage winding 760 (ie, side) of the second transformer (HV TX).

[0060] 8 shows a block diagram of a portion of the low-voltage side of a gate driver of a power switching system according to one possible implementation of the present disclosure. Figure 8 includes a receiver portion of a first transceiver 320. The receiver portion of the first transceiver receives a composite signal from a low-voltage winding 840 of a first transformer. The composite signal is then split into two channels.

[0061] The first channel includes a ready decoder including a filter 810 configured to output a signal (FILT_OUT) in which the first pulse train signal has been recovered (i.e., separated) from the composite signal. For example, the filter 810 may have a relatively high time constant (e.g., 20 ns) so that the lower bandwidth first pulse train signal can pass through the filter 810 while the higher bandwidth second pulse train signal is blocked (i.e., attenuated). In other words, the filter 810 may be a low-pass filter. The ready decoder further includes a decoder implemented as a pulse detector 820 configured to detect pulses in the first pulse train signal. The pulse detector 820 may output a ready signal while a pulse is detected and a not-ready signal after a certain number (e.g., three) of missing pulses (i.e., absences).

[0062] The second channel includes a temperature fault decoder configured to receive the composite signal (RX_OUT) from the low voltage winding 840 of the first transformer. The temperature fault decoder includes a decoder implemented as a frequency detector 830 configured to detect the higher bandwidth of the second pulse train signal and output a fault signal at a fault level while the second pulse train signal is detected in the composite signal.

[0063] 8 further includes a receiver portion of the second transceiver 340. The receiver portion of the second transceiver receives the inverted PWM signal from the low-voltage winding 850 of the second transformer. The receiver portion of the second transceiver includes a PWM decoder 860 configured to restore the PWM signal by inverting the inverted PWM signal.

[0064] 5, the gate driver includes a current source 530 for reading a signal at the temperature sense pin. The gate driver may include multiple (e.g., two) temperature sense pins for redundant sensing, although not all implementations use all temperature sense pins. In these implementations, the current source associated with the unused temperature sense pin may consume power (current) unnecessarily. As a result, the gate driver may include a disable circuit configured to disable the temperature sense pin while the temperature sense pin is not coupled to a temperature sensor to reduce power consumed by the gate driver.

[0065] 9 is a schematic diagram of a disable circuit for a temperature sense pin of a gate driver according to one possible implementation of the present disclosure. The disable circuit includes a switch 920 configured to decouple the current source 530 from the temperature sense pin 910 when the pin is not coupled to a sensor.

[0066] The disable circuit may be coupled to a high voltage supply rail (e.g., 15V), while the signal at the temperature sense pin 910 may be a low voltage (e.g., 5V). If the temperature sense pin is decoupled, it may voltage float through the current source 530 to the high voltage supply rail. To prevent this, the disable circuit includes a low voltage rail 911 that is supplied by a low dropout voltage regulator (LDO 912). The low voltage rail 911 is connected to a pull-up resistor (R PU ) to the temperature sense pin 910. In this case, the floating temperature sense pin is pulled up to the low voltage rail 911. In this state, the disabling voltage (TSDIS) is pulled to a high voltage, which causes switch 920 to open. However, if the temperature sense pin is not floating (i.e., coupled to a sensor), the disabling voltage (TSDIS) is pulled to a low voltage, which causes switch 920 to close.

[0067] Exemplary implementations have been disclosed in the specification and / or drawings. The disclosure is not limited to such exemplary implementations. The use of the term "and / or" includes any and all combinations of one or more of the associated listed items. The figures are schematic and, therefore, are not necessarily to scale. Unless otherwise indicated, certain terms are used in a generic and descriptive sense and not for purposes of limitation.

[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present disclosure. As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. As used herein, the term "comprises" and variations thereof are used synonymously with the term "comprises" and variations thereof and are open, non-limiting terms. As used herein, the term "optional" or "optionally" means that the subsequently described feature, event, or circumstance may or may not occur, and that the description includes instances when the feature, event, or circumstance occurs and instances when it does not occur. Ranges may be expressed herein as from "about" one particular value and / or to "about" another particular value. When such a range is expressed, the aspect includes from the one particular value and / or to the other particular value. Similarly, when values ​​are expressed as approximations, by use of the antecedent "about," it will be understood that the particular value forms another aspect. It will be further understood that the endpoints of each of the ranges are significant in relation to the other endpoint, and independently of the other endpoint.

[0069] Some implementations may be implemented using various semiconductor processing and / or packaging technologies, such as, but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and / or various types of semiconductor processing technologies associated with semiconductor substrates.

[0070] While certain features of the disclosed implementations have been described as set forth herein, those skilled in the art will recognize many variations, substitutions, changes, and equivalents. It is therefore to be understood that the appended claims are intended to cover all such modifications and variations as fall within the scope of the implementations. It should be understood that these have been presented by way of example only, and not limitation, and that various changes in form and detail may be made. Any portion of the devices and / or methods described herein may be combined in any combination, except in mutually exclusive combinations. The various devices described herein may include various combinations and / or subcombinations of the functions, components, and / or features of the various devices described.

[0071] It will also be understood that in the above description, when an element is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled with another element, the element can be directly disposed on, connected to, or coupled with the other element, or one or more intervening elements can be present. Conversely, when an element is referred to as being directly disposed on, directly connected to, or directly coupled with another element or layer, no intervening elements or layers are present. Throughout the detailed description of the present invention, the terms directly disposed on, directly connected, or directly coupled may not be used, but elements illustrated as directly disposed on, directly connected, or directly coupled may be referred to as such. The claims of this application (if included) may be amended to describe the exemplary relationships described or illustrated herein.

[0072] As used herein, the singular can include the plural unless the context clearly dictates otherwise. Spatial relative terms (e.g., throughout, above, above, below, underside, below, underneath, etc.) are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the drawings. In some implementations, the relative terms above and below can include vertically above and vertically below, respectively. In some implementations, the term adjacent can include laterally adjacent or horizontally adjacent.

Claims

1. A power switching system comprising: a switch module including a power transistor and a transistor temperature sensor configured to measure the transistor temperature of the power transistor; a gate driver coupled to the switch module, a gate driver temperature sensor configured to measure the gate driver temperature of the gate driver; a gate driver temperature sense circuit configured to output a first pulse train signal corresponding to an internal fault signal based on the gate driver temperature; a transistor temperature sense circuit configured to receive the transistor temperature from the transistor temperature sensor and output a second pulse train signal corresponding to an external fault signal based on the transistor temperature; a transceiver configured to transmit a composite signal including the first pulse train signal and the second pulse train signal across a separation barrier of the gate driver via a shared communication channel; a gate driver, and a power switching system comprising the same.

2. The transceiver is configured to: transmit the composite signal to the low voltage side of the gate driver via the shared communication channel; output a ready signal at a ready pin of the gate driver, the ready signal corresponding to the first pulse train signal; output a detected temperature fault signal at a temperature fault pin of the gate driver, the detected temperature fault signal corresponding to the second pulse train signal; The power switching system according to claim 1.

3. The gate driver temperature sense circuit includes a comparator configured to receive a voltage from the gate driver temperature sensor at a first input and a thermal shutdown threshold voltage at a second input, the comparator further configured to output the internal fault signal, the internal fault signal being at a normal level when there is no thermal fault in the gate driver. The transistor temperature sense circuit includes a comparator configured to receive a voltage from the transistor temperature sensor at a first input and a fault threshold voltage at a second input, the comparator being further configured to output the external fault signal, the external fault signal being at a fault level when there is a thermal fault in the power transistor, the power switching system according to claim 1.

4. The transceiver is a ready encoder configured to generate a first pulse train signal while the internal fault signal is at the normal level and not to generate the first pulse train signal otherwise; a temperature fault encoder configured to generate a second pulse train signal while the transistor temperature is at the fault level and not to generate the second pulse train signal otherwise, the first pulse train signal having a lower bandwidth compared to the second pulse train signal, the second pulse train signal having a higher bandwidth compared to the first pulse train signal; a multiplexer configured to combine the output of the ready encoder and the output of the temperature fault encoder to generate a composite signal and transmit the composite signal to the high voltage side of a transformer; a ready decoder configured to receive the composite signal from the low voltage side of the transformer, a filter configured to separate the first pulse train signal from the composite signal based on the lower bandwidth of the first pulse train signal; a pulse detector configured to detect pulses in the first pulse train signal and output a ready signal at a ready level while the pulses in the first pulse train signal are detected and at a non-ready level after a plurality of pulses in the first pulse train signal are not detected; including a ready decoder; a temperature fault decoder configured to receive the composite signal from the low voltage side of the transformer, a frequency detector configured to detect the higher bandwidth of the second pulse train signal and output a fault signal at a fault level while the second pulse train signal is detected in the composite signal and at a non-fault level when the second pulse train signal is not detected in the composite signal; including a temperature fault decoder; including the power switching system according to claim 3.

5. The transistor temperature sensor is a first transistor temperature sensor configured to measure a first transistor temperature of the power transistor, and the switch module further includes a second transistor temperature sensor configured to measure a second transistor temperature of the power transistor, and the transistor temperature sense circuit is a first temperature sense circuit configured to receive the first transistor temperature from the first transistor temperature sensor and output a first signal based on the first transistor temperature, and the gate driver further includes a second temperature sense circuit configured to receive the second transistor temperature from the second transistor temperature sensor and output a second signal based on the second transistor temperature, and a logic gate configured to receive the first signal and the second signal and output the external fault signal, where the external fault signal has a level corresponding to the thermal fault when either the first signal or the second signal has a level corresponding to the thermal fault of the power transistor. The power switching system according to claim 1, further including the above.

6. The transceiver of the gate driver is a first transceiver, and the gate driver further includes a transistor temperature monitoring circuit configured to compare the transistor temperature with a lamp signal and output an external monitoring signal, where the external monitoring signal is pulse width modulated (PWM) according to the transistor temperature. A second transceiver configured to transmit the external monitoring signal across the isolation barrier of the gate driver via a dedicated communication channel, and an inverter configured to invert the external monitoring signal so that it remains at a relatively low level for a longer time than when it is at a relatively high level while the transistor temperature of the power transistor is within the normal temperature range of the power transistor, in order to reduce the power consumed by the second transceiver. The power switching system according to claim 1, further including the second transceiver including the above. The power switching system according to claim 1, further including the above.

7. The gate driver is coupled to the transistor temperature sensor at a first temperature sense pin, and the gate driver further includes a second temperature sense pin and an inactivation circuit configured to inactivate the second temperature sense pin while the second temperature sense pin is not coupled to a second temperature sensor in order to reduce the power consumed by the gate driver. The power switching system according to claim 1.

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