Image sensor and operation method thereof

Abstract

To provide an efficient image sensor and an operation method thereof, in which a sampling time is reduced when a pixel signal is sampled a plurality of times during a readout time.SOLUTION: An image sensor for sampling a pixel signal a plurality of times during a readout time includes: an analog comparator configured to compare a signal level of the pixel signal with a signal level of a target ramp signal that is one of a plurality of ramp signals; a counter configured to output counting data based on a comparison result of the analog comparator; and a digital comparing circuit configured to compare a binary value of a target reference code corresponding to the target ramp signal with a binary value of the counting data and determine whether or not to output a digital signal corresponding to the counting data to a data output circuit based on a result of the comparison between the binary value of the counting data and the binary value of the target reference code.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an image sensor, and more particularly to an image sensor that performs multiple sampling of pixel signals and a method of operating the same. [Background technology]

[0002] An image sensor is a device that captures a two- or three-dimensional image of an object. The image sensor creates an image of an object using photoelectric conversion elements that respond to the intensity of light reflected from the object. In recent years, CMOS (Complementary Metal-Oxide Semiconductor) technology has developed, and CMOS image sensors using CMOS are widely used.

[0003] In addition, in recent years, image sensors can perform analog-to-digital conversion operations by double sampling the level of a reset signal and the level of an image signal to reduce noise in pixel signals and generating a comparison signal based on a level corresponding to the difference between the two.

[0004] Therefore, the challenge is to develop a system that can reduce the sampling time for multiple sampling and operate efficiently. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2003-229557 A Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made in consideration of the problems with the conventional image sensors described above, and an object of the present invention is to provide an efficient image sensor and an operating method thereof that reduce the sampling time when sampling a pixel signal multiple times during a readout time. [Means for solving the problem]

[0007] In order to achieve the above object, an image sensor according to the present invention is characterized in that, in an image sensor that samples a pixel signal multiple times during a readout time, the image sensor comprises: an analog comparator that compares the pixel signal with a signal level of a target ramp signal, which is one of a plurality of ramp signals; a counter that outputs counting data according to a comparison result of the analog comparator; and a digital comparator that compares a binary value of a target reference code corresponding to the target ramp signal with the binary value of the counting data, and determines whether to output a digital signal corresponding to the counting data to a data output circuit according to a comparison result between the binary value of the target reference code and the binary value of the counting data.

[0008] In order to achieve the above object, an image sensor according to the present invention provides an image sensor for sampling pixel signals in units of columns, the image sensor comprising: a pixel array including a plurality of pixels, the pixel array outputting a pixel voltage measured in each of the plurality of pixels to a column line connected to each pixel during a readout time; a plurality of analog comparators connected to the column lines to receive the pixel voltages and compare the pixel voltages with a signal level of a ramp signal; a plurality of counters outputting counting data according to a comparison result of the analog comparators; and a plurality of digital comparators comparing a binary value of a reference code corresponding to the ramp signal with a binary value of the counting data, and outputting to a data output circuit either a digital signal corresponding to the counting data or a digital signal generated based on a previous ramp signal for the ramp signal according to a comparison result between the binary value of the reference code and the binary value of the counting data.

[0009] In order to achieve the above object, an operating method of an image sensor according to the present invention is a method of operating an image sensor that samples a pixel signal a plurality of times during a readout time, the operating method comprising the steps of: outputting a first digital signal to a data output circuit based on a first sub-ramp signal among a plurality of sub-ramp signals during a first sub-readout time within the readout time; comparing a signal level of the pixel signal with a signal level of a second sub-ramp signal having a maximum signal level lower than a maximum signal level of the first sub-ramp signal during a second sub-readout time following the first sub-readout time; outputting counting data based on a comparison result between the signal level of the second sub-ramp signal and the signal level of the pixel signal; comparing a binary value of a reference code corresponding to the second sub-ramp signal with a binary value of the counting data; and controlling the data output circuit to output a digital signal corresponding to the counting data to the data output circuit or to generate the first digital signal as a second digital signal corresponding to the second sub-ramp signal according to a comparison result of the binary values.

[0010] In addition, according to an embodiment of the present invention, an analog-to-digital converter that generates a plurality of digital signals for a pixel signal during a readout time includes an analog comparator that receives a plurality of ramp signals for each of a plurality of sub-readout times included in the readout time and compares a signal level of the pixel signal with each of the plurality of ramp signals, a counter that outputs counting data corresponding to each of the plurality of sub-readout times according to a comparison result of the analog comparator, and a digital comparator that compares a binary value of the counting data with a reference code corresponding to each of the plurality of ramp signals and determines whether to output a digital signal corresponding to the counting data to a data output circuit for each of the sub-readout times according to a comparison result of the binary value of the counting data with the reference code. Effect of the Invention

[0011] According to the image sensor and the operating method thereof according to the present invention, the maximum signal level of the sub-ramp signal gradually decreases during the readout time, so that the length of the sub-readout period gradually shortens. Therefore, compared to the conventional technique in which sampling is performed multiple times based on a sub-read section having a time length like the first sub-read section, the total read time length is shortened, and therefore, there is an effect that the read operation can be performed even faster. [Brief description of the drawings]

[0012] [Figure 1] 1 is a block diagram showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Diagram 2] 1 is a block diagram showing a schematic configuration of an analog-to-digital converter according to an embodiment of the present invention. [Diagram 3] FIG. 4 is a timing diagram of ramp and clock signals generated while performing a reset operation to perform correlated double sampling according to one embodiment of the present invention. [Figure 4]FIG. 4 is a timing diagram of ramp and clock signals generated while performing a read operation according to an embodiment of the present invention. [Diagram 5] 4 is a flowchart illustrating a method for outputting a first digital signal to a data output circuit based on a first sub-ramp signal according to an embodiment of the present invention. [Figure 6] 10 is a timing diagram showing an example in which an analog comparison result signal is generated based on a first sub-ramp signal according to an embodiment of the present invention. FIG. [Figure 7] 11 is a flowchart illustrating a method for outputting a second digital signal to a data output circuit based on a second sub-ramp signal according to an embodiment of the present invention. [Figure 8] 11 is a timing diagram showing an example in which an analog comparison result signal is generated based on a second sub-ramp signal according to an embodiment of the present invention. FIG. [Figure 9] 4 is a flowchart illustrating a method for generating a final digital signal according to an embodiment of the present invention. [Figure 10] FIG. 2 is a block diagram showing a schematic configuration of a ramp signal generator according to an embodiment of the present invention. [Figure 11] FIG. 13 illustrates a signal generated by adding a redundancy signal level according to an embodiment of the present invention. [Figure 12] 1 is a block diagram showing a schematic configuration of an electronic device including a multi-camera module according to an embodiment of the present invention. [Figure 13] FIG. 13 is a block diagram showing a detailed configuration of the camera module of the embodiment shown in FIG. 12. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Next, specific examples of embodiments for carrying out an image sensor and an operating method thereof according to the present invention will be described with reference to the drawings.

[0014] FIG. 1 is a block diagram showing a schematic configuration of an image sensor according to an embodiment of the present invention. The image sensor 100 is mounted on an electronic device having an image or light sensing function. For example, the image sensor 100 can be installed in electronic devices such as cameras, smartphones, wearable devices, Internet of Things (IoT), tablet PCs (Personal Computers), PDAs (Personal Digital Assistants), PMPs (Portable Multimedia Players), and navigation devices. The image sensor 100 can also be mounted on electronic devices that are provided as components in vehicles, furniture, manufacturing equipment, doors, various measuring instruments, and the like.

[0015] The image sensor 100 includes a pixel array 110, a row driver 120, a ramp signal generator 130, a reference code generator 140, an analog-to-digital conversion circuit 150 (hereinafter referred to as ADC), a data output circuit 160, a timing controller 170, and a signal processing unit 180. The pixel array 110 includes a plurality of row lines RL, a plurality of column lines CL, and a plurality of pixels PX connected to the plurality of row lines RL and the plurality of column lines CL and arranged in a matrix. A current source CS is connected to each of the plurality of column lines CL.

[0016] Each of the pixels PX includes at least one photoelectric conversion element. The pixel PX senses light using the photoelectric conversion element and outputs an image signal, which is an electrical signal based on the sensed light. For example, the photoelectric conversion element includes a photodiode, a phototransistor, a photogate, a PIN photodiode, or the like. Each of the plurality of pixels PX senses light in a particular spectral region. For example, the plurality of pixels PX include a red pixel for converting light in the red spectral region into an electrical signal, a green pixel for converting light in the green spectral region into an electrical signal, and a blue pixel for converting light in the blue spectral region into an electrical signal. However, the present invention is not limited to this, and the plurality of pixels PX may further include a white pixel. As another example, the plurality of pixels PX may include pixels combined with other color configurations, for example, a yellow pixel, a cyan pixel, and a green pixel.

[0017] A color filter array for transmitting light in a specific spectral region is disposed on the upper part of the pixels PX, and the color sensed by each pixel is determined by the color filter disposed on the upper part of the pixels PX. However, without being limited thereto, in an embodiment, in the case of a specific photoelectric conversion element, light in a specific wavelength band can be converted into an electrical signal depending on the level of the electrical signal applied to the photoelectric conversion element. The current source CS provides a bias current Ib to a pixel PX (eg, a selected pixel) connected to a corresponding column line CL. Here, the bias current Ib means the current output from (or applied to) the drive transistor DX of the pixel PX.

[0018] The row driver 120 drives the pixel array 110 on a row-by-row basis. The row driver 120 decodes a row control signal (e.g., an address signal) received from the timing controller 170, and selects at least one of the row lines constituting the pixel array 110 in response to the decoded row control signal. For example, the row driver 120 generates a selection signal that selects one of a plurality of rows. The pixel array 110 outputs a pixel signal, for example a pixel voltage, from a row selected by a selection signal provided from a row driver 120 . The pixel signals include a reset signal and an image signal. The row driver 120 transmits control signals for outputting pixel signals to the pixel array 110, and the pixels PX operate in response to the control signals to output the pixel signals.

[0019] The ramp signal generator 130 generates a ramp signal RAMP whose level rises or falls at a predetermined gradient under the control of the timing controller 170 . The ramp signal RAMP is provided to each of a plurality of analog comparators 151 included in the ADC 150 . According to an embodiment of the present invention, the ramp signal generator 130 generates and provides a number of ramp signals RAMP to the analog comparator 151 during the readout time. The levels of the multiple ramp signals RAMP gradually decrease during the readout time, such that each ramp signal RAMP has a signal level that is less than or equal to the maximum signal level of the previous ramp signals generated during the readout time.

[0020] The reference code generator 140 sequentially provides a plurality of preset reference codes RC during a read time under the control of the timing controller 170 . The plurality of reference codes RC are codes set corresponding to the plurality of ramp signals RAMP, respectively. Exemplarily, each of the plurality of reference codes RC is the number of clock signals corresponding to the time period of each of the ramp signals RAMP.

[0021] The ADC 150 includes a plurality of analog comparators 151 , a plurality of counters 152 , and a plurality of digital comparison circuits 153 . The ADC 150 converts pixel signals (eg, pixel voltages) input from the pixel array 110 into pixel values, which are digital signals. Each pixel signal received via each of the plurality of column lines CL is converted by an analog comparator 151, a counter 152, and a digital comparison circuit 153 into a pixel value, which is a digital signal. According to an embodiment of the present invention, the ADC 150 stores in the memory 161 a digital signal generated based on the counting data according to the comparison result of the digital comparator included in the digital comparison circuit 153, or stores in the memory 161 a digital signal generated based on a previous ramp signal. The configuration and operation of the ADC 150 will be described in detail below with reference to FIG.

[0022] The data output circuit 160 temporarily stores the digital signal output from the ADC 150 and then outputs it. The data output circuit 160 includes a plurality of memories 161 and a column decoder 162 . In the embodiment, each of the multiple memories 161 is included in the digital comparison circuit 153 . The pixel values ​​stored in the memories 161 are output as image data IDTA under the control of a column decoder 181 . According to an embodiment of the present invention, the memories 161 are provided for each column and store digital signals corresponding to the ramp signals RAMP. The column decoder 162 provides a plurality of digital signals stored in the memory 161 to the signal processor 180 .

[0023] The timing controller 170 outputs control signals to each of the row driver 120, the ramp signal generator 130, the reference code generator 140, the ADC 150, and the data output circuit 160, and controls the operation or timing of the row driver 120, the ramp signal generator 130, the reference code generator 140, the ADC 150, and the data output circuit 160. The signal processing unit 180 performs noise reduction processing, gain adjustment, waveform shaping processing, interpolation processing, white balance processing, gamma processing, edge enhancement processing, binning, etc. on the image data IDTA corresponding to a plurality of digital signals. In an embodiment, the signal processor 180 generates a final digital signal based on the multiple digital signals. As an example, the signal processor 180 performs an average operation on the binary values ​​of a plurality of digital signals, and generates the average value of the digital signals as the final digital signal.

[0024] FIG. 2 is a block diagram showing a schematic configuration of an analog-to-digital conversion circuit (ADC) according to an embodiment of the present invention. Referring to FIG. 2, the ADC 150 includes an analog comparator 151 , a counter 152 , and a digital comparison circuit 153 . The analog comparator 151 receives the ramp signal RAMP generated by the ramp signal generator 130 , and the digital comparator circuit 153 receives the reference code RC generated by the reference code generator 140 . In this case, the ramp signal RAMP and the reference code RC received by the ADC 150 may be information mapped to one set of a plurality of ramp signals and a plurality of reference codes.

[0025] The analog comparator 151 compares the pixel signal PS received via the column line CL with the ramp signal RAMP, and outputs the comparison result. The analog comparator 151 outputs an analog comparison result signal CRS of a first level (e.g., logic high) when the level of the pixel signal PS is greater than or equal to the level of the ramp signal RAMP, and outputs an analog comparison result signal CRS of a second level (e.g., logic low) when the level of the pixel signal PS is less than the level of the ramp signal RAMP. The ADC 150 samples and holds the pixel signal PS provided from the pixel PX using a correlated double sampling (CDS) method, double samples the level of a specific noise (e.g., a reset signal) and the level of an image signal, and generates a digital signal DS based on the level corresponding to the difference.

[0026] The counter 152 receives the analog comparison result signal CRS output from the analog comparator 151 and the clock signal CLK, and outputs counting data CDT. In an embodiment, the counter 152 includes a latch circuit and an arithmetic circuit. The latch circuit receives the clock signal CLK from the timing controller 170 and the analog comparison result signal CRS from the analog comparator 151, and latches the number of times the logic level of the clock signal transitions when the level of the analog comparison result signal CRS is at a first level. The latch circuit latches a code value corresponding to the reset signal (eg, a reset value) and a code value corresponding to the image signal (eg, an image signal value), respectively. The calculation circuit calculates the reset value and the image signal value, and generates counting data CDT from which the reset level of the pixel PX has been removed. According to an embodiment of the present invention, the counter 152 latches code values ​​corresponding to a plurality of reset signals and a plurality of image signals, and the calculation circuit calculates the plurality of reset values ​​and the plurality of image signal values ​​to generate counting data CDT with the reset level removed. The number of counting data CDT corresponds to the number of image signals.

[0027] The digital comparison circuit 153 includes a digital comparator (153_1) and a control circuit (153_2). The digital comparator 153_1 receives the counting data CDT generated by the counter 152 and the reference code RC generated by the reference code generator 140, and provides a digital comparison result signal DCRS to the control circuit 153_2. The reference code RC received by the digital comparison circuit 153 is a reference code RC corresponding to the ramp signal RAMP among the multiple reference codes RC generated by the reference code generator 140 . The control circuit (153_2) generates one of the digital signal generated based on the previous ramp signal and the digital signal generated based on the counting data CDT as a digital signal DS corresponding to the target ramp signal depending on the logic level of the digital comparison result signal DCRS. For example, the control circuit (153_2) provides a digital signal generated based on the counting data to the data output circuit 160, or controls the data output circuit 160 to generate a previous digital signal corresponding to at least one previous ramp signal as a digital signal corresponding to the target ramp signal according to the logic level of the digital comparison result signal DCRS.

[0028] The digital comparator circuit 153 outputs the digital signal DS generated by the previous ramp signal to the data output circuit 160 if the binary value of the counting data CDT is equal to or greater than the binary value of the reference code RC. On the other hand, if the binary value of the counting data CDT is less than the binary value of the reference code RC, the digital comparison circuit 153 stores the digital signal DS corresponding to the counting data CDT in the memory 161 . The digital comparison circuit 153 according to an embodiment of the present invention determines a digital signal DS to be output to the data output circuit 160 based on a comparison result between the counting data CDT and the reference code RC, and if the binary value of the counting data CDT generated by the previous ramp signal is greater than the binary value of the counting data CDT generated by the target ramp signal by a threshold value or more, stores the digital signal DS generated by the previous ramp signal in the memory 161 in association with the target ramp signal.

[0029] FIG. 3 is a timing diagram of ramp and clock signals generated while performing a reset operation to perform correlated double sampling according to one embodiment. Referring to FIG. 3, the image sensor of the present invention receives a reset signal generated by a pixel during a reset period, and generates a ramp signal RAMP during a number of sub-reset periods. As an example, the reset period is composed of first to fourth sub-reset periods (RS1, RS2, RS3, RS4), and the image sensor generates a sub-ramp signal of the ramp signal RAMP in each of the first to fourth sub-reset periods (RS1, RS2, RS3, RS4). At this time, the ADC 150 receives the clock signal CLK twice in response to each ramp signal RAMP.

[0030] According to one embodiment, the ADC 150 generates a code value corresponding to the reset signal based on the clock signal CLK to perform correlated double sampling. The ADC 150 compares the sub-ramp signal with the reset signal, and generates a first level analog comparison result signal when the reset signal is greater than the sub-ramp signal. The ADC 150 counts the number of times the clock signal CLK occurs when the analog comparison result signal is at the first level, and generates the counted number of times the clock signal CLK occurs as a code value corresponding to the reset signal. The ADC 150 latches reset values ​​corresponding to a plurality of sub-reset intervals (RS1, RS2, RS3, and RS4), calculates the image signal value and the reset value, and generates counting data from which the reset levels of the pixels are removed. The ADC 150 performs correlated double sampling by subtracting a reset value from an image signal value generated in a sub-readout period corresponding to the sub-reset period. For example, the ADC 150 performs correlated double sampling by subtracting the reset value generated in the third sub-reset section RS3 from the image signal value generated in the third sub-readout section. The correlated double sampling of the present invention can be performed, but is not limited to, by subtracting the average value of the reset values ​​from the average value of the image signal values.

[0031] FIG. 4 is a timing diagram of the ramp signal RAMP and the clock signal CLK generated while performing a read operation according to an embodiment of the present invention. Referring to FIG. 4, the image sensor of the present invention receives an image signal generated by a pixel during a readout period, and generates a sub-ramp signal (also referred to as a target ramp signal) during a number of sub-readout periods. As an example, the readout section is composed of first to fourth sub-readout sections (RO1, RO2, RO3, RO4), and the image sensor generates first to fourth sub-ramp signals (also referred to as ramp signals in this specification) in the first to fourth sub-readout sections (RO1, RO2, RO3, RO4), respectively.

[0032] At this time, the ADC 150 receives the clock signal CLK at different times corresponding to each sub-ramp signal. As an example, the ADC 150 receives the clock signal CLK ten times corresponding to the first sub-ramp signal, and receives the clock signal CLK six times, four times, and three times corresponding to the second to fourth sub-ramp signals. During the readout time, the generated sub-ramp signal has a maximum signal level that is less than or equal to the maximum signal level of the previous sub-ramp signal previously generated. The previous sub-ramp signal is a sub-ramp signal generated at a previous time of the target sub-read section in which sampling is being performed. As an example, when ADC150 generates a digital signal in the third sub-readout period RO3, it receives a third sub-ramp signal having a maximum signal level that is smaller than or equal to the maximum signal levels of the first and second sub-ramp signals, which are the previous sub-ramp signals of the third sub-ramp signal.

[0033] In the image sensor according to the comparative example, sampling is repeatedly performed a plurality of times in a time length such as the first sub-readout section RO1, and a final digital signal is generated based on digital signals generated based on the plurality of samplings. Meanwhile, according to an embodiment of the present invention, the maximum signal level of the sub-ramp signal gradually decreases during the readout time, so that the length of the sub-readout section gradually shortens. Therefore, compared to the comparative embodiment in which sampling is performed multiple times based on a sub-read section having a time length such as the first sub-read section RO1, the total read time length is shortened, so that the read operation can be performed faster.

[0034] FIG. 5 is a flowchart illustrating a method of outputting a first digital signal to a data output circuit 160 based on a first sub-ramp signal according to an embodiment of the present invention, and FIG. 6 is a timing diagram showing an example in which an analog comparison result signal is generated based on the first sub-ramp signal according to an embodiment of the present invention. 5 and 6, the image sensor generates a first digital signal by comparing a first sub-ramp signal with a pixel signal in a first sub-readout period RO1. The first sub-readout section RO1 is a sub-readout section in which pixel signals are first read out after the reset operation is completed.

[0035] In step S10, the image sensor compares the signal levels of the first sub-ramp signal and the pixel signal, and generates an analog comparison result signal CRS as a comparison result. Referring to FIG. 6, when the signal level of the pixel signal PS is greater than the signal level of the sub-ramp signal, an analog comparison result signal CRS of a logic high level is generated, and when the signal level of the pixel signal PS is equal to or less than the signal level of the sub-ramp signal, an analog comparison result signal CRS of a logic low level is generated.

[0036] In step S20, the image sensor outputs first counting data according to the analog comparison result signal CRS and the clock signal CLK. When the counter 152 receives the analog comparison result signal CRS at a logic high level, the counter 152 counts the number of times the logic level of the clock signal CLK transitions from the first logic level to the second logic level to generate first counting data. Referring to FIG. 6, when the analog comparison result signal CRS is at a logic high level, the number of times the clock signal CLK transitions from the first logic level to the second logic level is seven, and the counter 152 outputs the binary value “111”, which corresponds to seven times, as the first counting data.

[0037] In step S30, the image sensor generates a first digital signal based on the first counting data, and outputs the first digital signal to the data output circuit 160, thereby storing the first digital signal in the memory 161. The first digital signal is a signal obtained by digitally converting a pixel signal in response to the first sub-ramp signal in the first sub-readout section RO1. The first digital signal generated in the first sub-reading period RO1 where no ramp signal exists previously is the first counting data. That is, in the embodiment of FIG. 6, the image sensor generates a first digital signal by subtracting the reset value generated during the reset period from "111." After storing the first digital signal in the memory 161, the image sensor ends the first sub-readout operation.

[0038] FIG. 7 is a flowchart illustrating a method of outputting a second digital signal to a data output circuit 160 based on a second sub-ramp signal according to an embodiment of the present invention, and FIG. 8 is a timing diagram showing an example in which an analog comparison result signal is generated based on the second sub-ramp signal according to an embodiment of the present invention. The image sensor that has executed the first sub-reading operation executes a second sub-reading operation subsequent to the first sub-reading operation. The second sub-readout operation refers to an operation of sampling a pixel signal based on a second sub-ramp signal in the presence of a previous sub-ramp signal.

[0039] In step S40, during the second sub-readout period RO2, the image sensor compares the signal level of the second sub-ramp signal with the pixel signal PS. The second sub-read section RO2 is any one of the sub-read sections following the first sub-read section RO1. The image sensor outputs an analog comparison result signal CRS as a result of comparing the second sub-ramp signal with the pixel signal PS, and exemplarily, outputs a logic high analog comparison result signal CRS when the pixel signal PS is greater than the second sub-ramp signal. According to the embodiment of FIG. 8, during the second sub-readout period RO2, if the pixel signal PS is greater than the second sub-ramp signal, the analog comparison result signal CRS is continuously output as logic high.

[0040] In step S50, the image sensor outputs second counting data according to the analog comparison result signal CRS. When the counter 152 receives the analog comparison result signal CRS at a logic high level, the counter 152 counts the number of times the logic level of the clock signal CLK transitions from the first logic level to the second logic level to generate second counting data. Referring to FIG. 8, the comparison result signal CRS is held at a logic high level, and the clock signal CLK transitions from the first logic level to the second logic level six times. At this time, the counter 152 outputs "110" as the second counting data.

[0041] In step S60, the image sensor compares the second counting data with the binary value of the reference code. The reference code is a code whose binary value is determined according to the length of the sub-ramp signal. Exemplarily, the binary value of the reference code has a value proportional to the length of a time interval of the sub-ramp signal. For example, the binary value of the reference code is the number of times the clock signal CLK received by the ADC 150 is toggled during the sub-readout interval. Referring to FIG. 8, during the second sub-read interval, the clock signal CLK is toggled six times, so that the reference code is "110." However, in the embodiment of the present invention, the reference code is not limited to only the number of times the clock signal CLK is toggled.

[0042] In step S70, if the image sensor determines that the binary value of the second counting data is greater than or equal to the binary value of the reference code, it proceeds to step S81, and if the image sensor determines that the binary value of the second counting data is less than the binary value of the reference code, it proceeds to step S82. In step S81, if the image sensor determines that the binary value of the second counting data is greater than or equal to the binary value of the reference code, it generates the first digital signal generated according to the embodiments of Figures 5 and 6 as a digital signal sampled in the second sub-readout section. That is, the image sensor controls the data output circuit 160 so that a digital signal, such as the first digital signal stored in the memory 161 in the first sub-reading interval RO1, is stored in the memory 161 in response to the second sub-reading interval RO2.

[0043] In step S82, if the image sensor determines that the binary value of the second counting data is less than the binary value of the reference code, it generates a digital signal based on the second counting data and stores the generated digital signal in the memory 161. As an example, the image sensor subtracts the reset value from the second counting data to generate a digital signal. Referring to FIG. 8, when the reference code corresponding to the second sub-read section RO2 is “110”, the binary value of the second counting data is greater than or equal to the binary value of the reference code, and the image sensor generates the first digital signal as a digital signal sampled in the second sub-read section.

[0044] FIG. 9 is a flow chart illustrating a method for generating a final digital signal according to an embodiment of the present invention. Referring to FIG. 9, the image sensor of the present invention generates a final digital signal by performing sampling on pixel signals a total of M times (M is a natural number). In step S100, the image sensor starts a readout operation, beginning with a first sub-readout operation by generating a first sub-ramp signal.

[0045] In step S200, the image sensor compares the k-th counting data generated in the k-th (k is a natural number) sub-reading period with the k-th reference code corresponding to the k-th sub-reading period. The method of generating counting data for each sub-readout section has been described above, and therefore a detailed description thereof will be omitted. In step S310, if the kth counting data is equal to or greater than the kth reference code, the image sensor determines that the kth digital signal sampled in the kth sub-readout period is a previous digital signal. The previous digital signal is any one of the first digital signal to the (k-1)th digital signal, but the embodiment of the present invention is not limited thereto, and the previous digital signal may also be an average value of the first digital signal to the (k-1)th digital signal.

[0046] In step S320, the image sensor generates a k-th digital signal based on the k-th counting data if the k-th counting data is less than the k-th reference code. For example, the image sensor determines the kth digital signal as a digital signal from which noise has been removed by subtracting a reset value from the kth counting data. In step S400, the image sensor increments "k" by "1" to perform a subsequent sub-readout operation; In step S500, the image sensor determines whether k is greater than M. If k is greater than M, the image sensor terminates the sub-readout operation. On the other hand, if k is less than or equal to M, the image sensor starts the subsequent sub-readout operation. In step S600, the image sensor generates a final digital signal based on the M digital signals generated by the multiple sub-readout operations. Illustratively, the image sensor generates a final digital signal that is an average of the binary values ​​of the M digital signals.

[0047] In a method for removing noise from an image signal according to an embodiment, when an image sensor senses an image signal with high illumination, the image signal with high illumination has a high signal level, so that a noise level relative to the image signal level is low. Meanwhile, when the image sensor senses an image signal with low illumination, the image signal with low illumination has a low signal level, and therefore the noise level relative to the image signal level is high. That is, the image sensor is more sensitive to noise when sensing an image signal in low illumination compared to high illumination.

[0048] Since the image sensor according to an embodiment of the present invention senses an image signal based on a ramp signal RAMP that gradually decreases during the readout period, most of the M digital signals generated from a high illumination image with a high signal level are signals generated based on a previous digital signal. Meanwhile, most of the M digital signals generated from a low illumination image with a low signal level are signals generated based on counting data counted in each sub-readout section. That is, since the image sensor of the present invention uses digital signals of various values ​​to generate a final digital signal for a low illumination image, the image sensor of the present invention can adaptively perform sampling according to illumination.

[0049] FIG. 10 is a block diagram showing a schematic configuration of the ramp signal generator 130 according to an embodiment of the present invention. Referring to FIG. 10, the ramp signal generator 130 includes at least one signal output circuit (135_1 to 135_n). The first to n-th signal output circuits (135_1 to 135_n) output, for example, a ramp signal RAMP including the sub-ramp signal shown in FIG. 4 or a ramp waveform. As described above, each of the sub-ramp signals has a signal level and a period. The ramp signal generator 130 outputs a ramp signal by generating a signal including sub-signals each corresponding to a different section / signal level.

[0050] According to one embodiment, the signal output circuit is composed of a first signal output circuit to an nth signal output circuit (135_1 to 135_n) (for example, to output a sub-signal having a specific interval), and a switch of any one of the first signal output circuit to the nth signal output circuit (135_1 to 135_n) is turned on to output a signal of a partial interval of the ramp signal RAMP. The switch of the signal output circuit (any one of 135_1 to 135_n) that has been turned on is turned off, and subsequently, the switches of the other signal output circuits (some of the remaining ones of 135_1 to 135_n) are turned on, thereby outputting other sub-signals of the ramp signal RAMP.

[0051] The ramp signal generator 130 receives the command signal CMD and determines whether to generate a ramp signal RAMP corresponding to a read operation or a ramp signal RAMP corresponding to a reset operation. The command signal CMD instructs the ramp signal generator 130 on which ramp signal to generate. In addition, the ramp signal generator 130 determines whether to turn the switch on or off in synchronization with the received clock signal CLK.

[0052] FIG. 11 is a diagram illustrating a signal generated by adding a redundancy signal level according to an embodiment of the present invention. 10 and 11, when each of the plurality of signal output circuits outputs a signal for a portion of the ramp signal RAMP, the signal output circuit outputs a signal including a redundancy signal level. The redundancy signal level is a margin signal level added to the signal level / section of the sub-ramp signal generated by each signal output circuit in order to minimize errors in the analog-to-digital conversion operation.

[0053] FIG. 12 is a block diagram showing a schematic configuration of an electronic device including a multi-camera module according to an embodiment of the present invention, and FIG. 13 is a block diagram showing a detailed configuration of the camera module of the embodiment of FIG. Referring to FIG. 12, an electronic device 1000 includes a camera module group 1100, an application processor 1200, a Power Manager IC (PMIC) 1300, and an external memory 1400.

[0054] The camera module group 1100 includes multiple camera modules (1100a, 1100b, 1100c). For example, although the figures show an embodiment in which three camera modules (1100a, 1100b, 1100c) are arranged, the embodiment is not limited thereto. In some embodiments, the camera module group 1100 may be modified and implemented to include only two camera modules. Also, in some embodiments, the camera module group 1100 can be modified and implemented to include n camera modules (n is a natural number equal to or greater than 4). Hereinafter, the detailed configuration of the camera module 1100b will be described in more detail with reference to FIG. 13, but the following description also applies equally to other camera modules (1100a, 1100b) according to the embodiment.

[0055] Referring to FIG. 13, a camera module 1100b includes a prism 1105, an optical path folding element (OPFE) 1110, an actuator 1130, an image sensing device 1140, and a storage unit 1150. The prism 1105 includes a reflecting surface 1107 made of a light reflecting material, and changes the path of light L incident from the outside.

[0056] In some embodiments, the prism 1105 changes the path of light L incident in a first direction X to a second direction Y perpendicular to the first direction X. In addition, the prism 1105 rotates the reflective surface 1107 of the light-reflecting material around the central axis 1106 in the direction A, or rotates the central axis 1106 in the direction B, thereby changing the path of the light L incident in the first direction X to a perpendicular second direction Y. At this time, the OPFE 1110 moves in a third direction Z perpendicular to the first direction X and the second direction Y.

[0057] In some embodiments, as shown in the figures, the maximum rotation angle of prism 1105 in the A direction is less than or equal to 15 degrees in the positive (+) A direction and greater than 15 degrees in the negative (-) A direction, although the embodiments are not limited thereto. In some embodiments, prism 1105 moves around 20° in the plus (+) or minus (-) B direction, or between 10° and 20°, or between 15° and 20°, where the angle of movement can be the same angle in the plus (+) or minus (-) B direction, or up to a similar angle within a range of around 1°.

[0058] In some embodiments, the prism 1105 can move the reflective surface 1106 of the light-reflective material in a third direction (eg, Z direction) parallel to the extension direction of the central axis 1106. The OPFE 1110 includes, for example, m groups of optical lenses (where m is a natural number). The m lenses can move in a second direction Y to change the optical zoom ratio of the camera module 1100b. For example, when the basic optical zoom magnification of camera module 1100b is Z, when m optical lenses included in OPFE 1110 are moved, the optical zoom magnification of camera module 1100b can be changed to an optical zoom magnification of 3Z, 5Z, or more than 5Z.

[0059] The actuator 1130 moves the OPFE 1110 or the optical lens (hereinafter referred to as the optical lens) to a particular position. For example, the actuator 1130 adjusts the position of the optical lens so that the image sensor 1142 is located at the focal length of the optical lens for accurate sensing. The image sensing device 1140 includes an image sensor 1142 , control logic 1144 , and a memory 1146 . The image sensor 1142 senses an image of a sensing target using light L provided through an optical lens. The control logic 1144 controls the overall operation of the camera module 1100b. For example, control logic 1144 controls the operation of camera module 1100b via control signals provided over control signal line CSLb.

[0060] The image sensor 1142 of the present invention converts pixel signals into digital signals based on multiple samplings, and during the readout time, the ramp signal generated for sampling gradually decreases. Also, the image sensor 1142 compares the binary values ​​of the reference code and the counting data, and determines whether to output a digital signal corresponding to the counting data to the data output circuit according to the comparison result.

[0061] Memory 1146 stores information necessary for the operation of camera module 1100b, such as calibration data 1147. The calibration data 1147 includes information necessary for the camera module 1100b to generate image data using light L provided from an external source. Calibration data 1147 includes, for example, information related to the degree of rotation, information related to the focal length, information related to the optical axis, and the like. If the camera module 1100b is implemented as a multi-state camera in which the focal length varies depending on the position of the optical lens, the calibration data 1147 includes focal length values ​​for each position (or state) of the optical lens and information related to autofocusing.

[0062] The storage unit 1150 stores the image data sensed by the image sensor 1142 . The storage unit 1150 is disposed outside the image sensing device 1140 and is implemented in a stacked form with a sensor chip constituting the image sensing device 1140 . In some embodiments, the storage unit 1150 may be embodied by an Electrically Erasable Programmable Read-Only Memory (EEPROM), although embodiments are not limited thereto.

[0063] 12 and 13, in some embodiments, each of the multiple camera modules (1100a, 1100b, 1100c) includes an actuator 1130. Thus, each of the multiple camera modules (1100a, 1100b, 1100c) may include calibration data 1147 that is equal to or different from one another due to the operation of the actuator 1130 contained therein. In some embodiments, one camera module (e.g., 1100b) of the multiple camera modules (1100a, 1100b, 1100c) is a folded lens type camera module including the above-mentioned prism 1105 and OPFE 1110, and the remaining camera modules (e.g., 1100a, 1100c) are vertical type camera modules that do not include the prism 1105 and OPFE 1110, but the embodiments are not limited thereto.

[0064] In some embodiments, one camera module (e.g., 1100c) of the multiple camera modules (1100a, 1100b, 1100c) may be, for example, a vertical depth camera that extracts depth information using infrared rays (IR). In that case, the application processor 1200 merges image data provided from such a depth camera with image data provided from a different camera module (e.g., 1100a or 1100b) to generate a 3D depth image.

[0065] In some embodiments, at least two camera modules (eg, 1100a, 1100b) of the multiple camera modules (1100a, 1100b, 1100c) have different fields of view (field of view angles). In that case, for example, but not limited to, the optical lenses of at least two camera modules (eg, 1100a, 1100b) among the multiple camera modules (1100a, 1100b, 1100c) may be different from each other. Also, in some embodiments, the viewing angles of each of the multiple camera modules (1100a, 1100b, 1100c) may be different from each other. In this case, the optical lenses included in each of the multiple camera modules (1100a, 1100b, 1100c) may be different from each other, but are not limited to this.

[0066] In some embodiments, each of the multiple camera modules (1100a, 1100b, 1100c) may be located physically separated from one another. In other words, the sensing area of ​​one image sensor 1142 is not divided and used by multiple camera modules (1100a, 1100b, 1100c), but an independent image sensor 1142 can be arranged inside each of the multiple camera modules (1100a, 1100b, 1100c). Also, referring to FIG. 12, the application processor 1200 includes an image processing unit 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 may be implemented separately from the multiple camera modules (1100a, 1100b, 1100c). For example, the application processor 1200 and the camera modules 1100a, 1100b, and 1100c may be implemented separately from each other on separate semiconductor chips.

[0067] The image processing device 1210 includes multiple sub-image processors (1212a, 1212b, 1212c), an image generator 1214, and a camera module controller 1216. The image processing device 1210 includes a number of sub-image processors (1212a, 1212b, 1212c) corresponding to the number of the camera modules (1100a, 1100b, 1100c).

[0068] Image data generated from each camera module (1100a, 1100b, 1100c) is provided to a corresponding sub-image processor (1212a, 1212b, 1212c) through mutually separated image signal lines (ISLa, ISLb, ISLc). For example, image data generated from camera module 1100a is provided to sub-image processor 1212a via image signal line ISLa, image data generated from camera module 1100b is provided to sub-image processor 1212b via image signal line ISLb, and image data generated from camera module 1100c is provided to sub-image processor 1212c via image signal line ISLc. Such image data transmission may be performed, for example, using a Camera Serial Interface (CSI) based on the Mobile Industry Processor Interface (MIPI), but the embodiments are not limited thereto.

[0069] On the other hand, in some embodiments, one sub-image processor may be arranged to correspond to multiple camera modules. For example, sub-image processor 1212a and sub-image processor 1212c may not be implemented separately from each other as shown in the figure, but may be implemented integrated into a single sub-image processor, and image data provided from camera module 1100a and camera module 1100c may be selected through a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor.

[0070] The image data provided to each of the sub-image processors (1212a, 1212b, 1212c) is provided to an image generator 1214. The image generator 1214 generates an output image using image data provided from each of the sub-image processors 1212a, 1212b, and 1212c in response to image generating information or a mode signal. Specifically, the image generator 1214 merges at least a portion of the image data generated from the camera modules (1100a, 1100b, 1100c) having different viewing angles according to image generation information or a mode signal to generate an output image. Also, the image generator 1214 selects one of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to image generation information or a mode signal, and generates an output image.

[0071] In some embodiments, the image generation information includes a zoom signal or zoom factor. Also, in some embodiments, the mode signal may be a signal based on a mode selected by a user, for example. When the image generation information is a zoom signal (zoom factor) and each camera module (1100a, 1100b, 1100c) has a different observation field of view (viewing angle), the image generator 1214 performs different operations according to the type of zoom signal.

[0072] For example, when the zoom signal is a first signal, the image data output from camera module 1100a and the image data output from camera module 1100c are merged, and then an output image is generated using the merged image signal and the image data output from camera module 1100b that was not used in the merging. If the zoom signal is a second signal different from the first signal, the image generator 1214 does not perform such image data merging, but instead selects one of the image data output from each camera module (1100a, 1100b, 1100c) to generate an output image. However, the embodiment is not limited thereto, and the method of processing image data can be modified as necessary.

[0073] In some embodiments, the image generator 1214 receives multiple image data having different exposure times from at least one of the multiple sub-image processors (1212a, 1212b, 1212c) and performs HDR (high dynamic range) processing on the multiple image data to generate merged image data with an increased dynamic range. The camera module controller 1216 provides control signals to each of the camera modules (1100a, 1100b, 1100c). The control signals generated by the camera module controller 1216 are provided to the corresponding camera modules (1100a, 1100b, 1100c) through separate control signal lines (CSLa, CSLb, CSLc).

[0074] One of the multiple camera modules (1100a, 1100b, 1100c) is designated as a master camera (e.g., 1100b) by image generation information or a mode signal including a zoom signal, and the remaining camera modules (e.g., 1100a, 1100c) are designated as slave cameras. Such information is included in control signals and provided to the corresponding camera modules (1100a, 1100b, 1100c) through separate control signal lines (CSLa, CSLb, CSLc). The camera modules acting as master and slave can be changed by a zoom factor or an operating mode signal. For example, if the viewing angle of camera module 1100a is wider than that of camera module 1100b and exhibits a lower zoom factor, then camera module 1100b acts as the master and camera module 1100a acts as the slave. Conversely, when the zoom factor indicates a high zoom magnification, the camera module 1100a operates as the master and the camera module 1100b operates as the slave.

[0075] In some embodiments, the control signals provided from the camera module controller 1216 to each camera module (1100a, 1100b, 1100c) include a sync enable signal. For example, if the camera module 1100b is the master camera and the camera modules (1100a, 1100c) are slave cameras, the camera module controller 1216 transmits a sync enable signal to the camera module 1100b. Upon receiving such a sync enable signal, camera module 1100b generates a sync signal based on the provided sync enable signal and provides the generated sync signal to camera modules (1100a, 1100c) via a sync signal line SSL. Camera module 1100b and camera modules 1100a and 1100c transmit image data to application processor 1200 in synchronization with such a sync signal.

[0076] In some embodiments, the control signals provided from the camera module controller 1216 to the multiple camera modules (1100a, 1100b, 1100c) include mode information via a mode signal. Based on such mode information, the multiple camera modules (1100a, 1100b, 1100c) can operate in a first operation mode and a second operation mode associated with the sensing speed. In a first operating mode, multiple camera modules (1100a, 1100b, 1100c) generate image signals at a first rate (e.g., generate image signals at a first frame rate), encode them at a second rate higher than the first rate (e.g., encode image signals at a second frame rate higher than the first frame rate), and transmit the encoded image signals to the application processor 1200. In this case, the second speed may be 30 times or less than the first speed.

[0077] The application processor 1200 stores the received image signal, i.e., the encoded image signal, in an internal memory 1230 or an external memory 1400 of the application processor 1200, and then reads out the encoded image signal from the internal memory 1230 or the external memory 1400, decodes it, and displays image data generated based on the decoded image signal. For example, a corresponding sub-processor among a plurality of sub-processors (1212a, 1212b, 1212c) of the image processing device 1210 performs decoding and also performs image processing on the decoded image signal.

[0078] In a second operating mode, multiple camera modules (1100a, 1100b, 1100c) generate image signals at a third rate lower than the first rate (e.g., generate image signals at a third frame rate lower than the first frame rate) and transmit the image signals to the application processor 1200. The image signal provided to the application processor 1200 may be an unencoded signal. The application processor 1200 performs image processing on the received image signal or stores the image signal in the internal memory 1230 or the external memory 1400 .

[0079] The PMIC 1300 supplies power, for example, a power supply voltage, to each of the multiple camera modules (1100a, 1100b, 1100c). For example, under the control of the application processor 1200, the PMIC 1300 supplies a first power to the camera module 1100a via a power signal line PSLa, a second power to the camera module 1100b via a power signal line PSLb, and a third power to the camera module 1100c via a power signal line PSLc. The PMIC 1300 responds to a power control signal PCON from the application processor 1200, generates power corresponding to each of the multiple camera modules (1100a, 1100b, 1100c), and adjusts the power level. The power control signal PCON includes a power adjustment signal for each operation mode of the multiple camera modules (1100a, 1100b, 1100c). For example, the operating mode may include a low power mode, where the power control signal PCON includes information related to the camera module operating in the low power mode and the power level to be set. The levels of power provided to each of the multiple camera modules (1100a, 1100b, 1100c) may be equal to or different from one another, and the levels of power may be dynamically changed.

[0080] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0081] 100 Image Sensor 110 pixel array 120 Row Driver 130 Ramp Signal Generator 140 Reference Code Generator 150 Analog-to-Digital Conversion Circuit (ADC) 151 Analog Comparator 152 Counter 153 Digital Comparison Circuit 153_1 Digital comparator 153_2 Control circuit 160 Data output circuit 161 Memory 162 Column Decoder 170 Timing Controller 180 Signal Processing Section RL Lowline CL Column Line PX Pixels CS Current Source

Claims

1. In an image sensor that samples a pixel signal multiple times during a readout time, an analog comparator that compares the pixel signal with the signal level of a target ramp signal that is any one of a plurality of ramp signals; a counter that outputs counting data according to a comparison result of the analog comparator; a digital comparator that compares the binary value of a target reference code corresponding to the target ramp signal with the binary value of the counting data, and determines whether to output a digital signal corresponding to the counting data to a data output circuit according to a comparison result between the binary value of the target reference code and the binary value of the counting data; a ramp signal generator that generates the plurality of ramp signals during the readout time and transmits the plurality of ramp signals to the analog comparator, wherein the plurality of ramp signals are a plurality of consecutive ramp signals, and each of the plurality of ramp signals has a maximum signal level smaller than a maximum signal level of a previous ramp signal generated previously during the readout time. An image sensor characterized by this.

2. The digital comparator circuit includes a digital comparator configured to compare the binary value of the target reference code with the binary value of the counting data to generate a digital comparison result signal; a control circuit configured to control the data output circuit to output the digital signal generated based on the counting data to the data output circuit or to generate a previous digital signal corresponding to any one of at least one of the previous ramp signals as a digital signal corresponding to the target ramp signal according to a logic level of the digital comparison result signal. The image sensor according to claim 1, characterized by this.

3. The digital comparator circuit is further configured such that when the binary value of the first counting data output based on the first target ramp signal is greater than or equal to a threshold value than the binary value of the second counting data output based on the second target ramp signal generated subsequent to the first target ramp signal during the readout time, the first digital signal generated based on the first target ramp signal is output to the data output circuit as the second digital signal corresponding to the second target ramp signal. The image sensor according to claim 1, characterized by this.

4. The digital comparison circuit is further configured to output the first digital signal as the second digital signal to the data output circuit when the binary value of the second counting data is equal to or greater than the binary value of the second target reference code. The image sensor according to claim 3, characterized in that.

5. The digital comparison circuit is further configured to output, as the second digital signal, a digital signal generated based on the second counting data to the data output circuit when the binary value of the second counting data is less than the binary value of the second target reference code. The image sensor according to claim 3, characterized in that.

6. Each of the plurality of ramp signals has a maximum signal level and an interval. The ramp signal generator includes a plurality of signal output circuits configured to output output signals corresponding to the maximum signal level and the interval, respectively. Each of the plurality of signal output circuits is configured to generate one of the plurality of ramp signals when at least a part of the plurality of signal output circuits is switched off. The image sensor according to claim 1, characterized in that.

7. The plurality of signal output circuits are further configured to output a signal obtained by adding a redundancy signal level to at least one of the output signals. The image sensor according to claim 6, characterized in that.

8. The analog comparator is further configured to provide a comparison result signal of logic high to the counter when the signal level of the pixel signal is greater than the signal level of the target ramp signal. The image sensor according to claim 1, characterized in that.

9. The counter receives a clock signal, outputs a counting bit having a logic level determined based on the comparison result signal each time the logic level of the clock signal transitions from a first logic level to a second logic level, The image sensor according to claim 8, further configured to generate the counting data based on a series of the counting bits.

10. The binary value of the target reference code is the number of clock signals corresponding to the time interval of the target ramp signal. The image sensor according to claim 1, characterized in that.

11. In an image sensor that samples pixel signals in column units, a pixel array including a plurality of pixels, wherein each of the plurality of pixels is configured to output a measured pixel voltage to each of a plurality of column lines connected to the pixel during a read time; a plurality of analog comparators connected to each of the column lines to receive the pixel voltage and configured to compare the signal level of the pixel voltage with that of a ramp signal; a plurality of counters configured to output counting data based on a comparison result of the analog comparator; a plurality of digital comparison circuits configured to compare a binary value of a reference code corresponding to the ramp signal with a binary value of the counting data of each of the counters, output a digital signal corresponding to the counting data to a data output circuit based on a first result of the comparison between the binary value of the reference code and the binary value of the counting data, and output a digital signal generated based on a previous ramp signal with respect to the ramp signal to the data output circuit based on a second result of the comparison between the binary value of the reference code and the binary value of the counting data. An image sensor characterized by comprising:

12. further comprising a ramp signal generator configured to generate a plurality of ramp signals and provide the plurality of ramp signals to the plurality of analog comparators during the read time; The image sensor according to claim 11, wherein each of the plurality of ramp signals has a maximum signal level equal to or lower than the maximum signal level of at least one of the previous ramp signals.

13. The image sensor according to claim 12, further comprising a reference code generator configured to generate a reference code corresponding to each of the plurality of ramp signals and provide the reference code to the plurality of digital comparison circuits.

14. Each of the plurality of digital comparison circuits a digital comparator configured to compare a binary value of the counting data with a binary value of the reference code to generate a digital comparison result signal; According to the logic level of the digital comparison result signal, output a digital signal generated based on the counting data to the data output circuit, or control the data output circuit to generate, as a digital signal corresponding to the lamp signal, a digital signal corresponding to any one of at least one previous lamp signal, and a control circuit configured as such, wherein the image sensor according to claim 11 is characterized by including the same.

15. In an operation method of an image sensor that samples a pixel signal multiple times during a readout time, during a first sub-readout time within the readout time, output a first digital signal to a data output circuit based on a first sub-lamp signal among a plurality of sub-lamp signals; during a second sub-readout time following the first sub-readout time, compare the signal level of a second sub-lamp signal having a maximum signal level smaller than the maximum signal level of the first sub-lamp signal with the signal level of the pixel signal; output counting data based on a comparison result between the signal level of the second sub-lamp signal and the signal level of the pixel signal; compare the binary value of a reference code corresponding to the second sub-lamp signal with the binary value of the counting data; according to the comparison result of the binary values, output a digital signal corresponding to the counting data to the data output circuit, or control the data output circuit to generate the first digital signal as a second digital signal corresponding to the second sub-lamp signal, and an operation method of an image sensor characterized by including the same.

16. The operation method of the image sensor according to claim 15, further comprising determining a final digital signal corresponding to the pixel signal based on a plurality of digital signals generated corresponding to each of the plurality of sub-lamp signals.

17. The counting data is second counting data, the step of outputting the first digital signal to the data output circuit includes during the first sub-readout time, comparing the signal level of the first sub-lamp signal with the signal level of the pixel signal; outputting first counting data based on a comparison result between the signal level of the first sub-lamp signal and the signal level of the pixel signal; outputting the first digital signal corresponding to the pixel signal to the data output circuit based on the first counting data, the method for operating an image sensor according to claim 15, characterized by including this step.

18. The step of outputting a digital signal corresponding to the second counting data to the data output circuit or controlling the data output circuit to generate the first digital signal as a second digital signal corresponding to a second sub-lamp signal is when the binary value of the first counting data is greater than or equal to a threshold value than the binary value of the second counting data, including the step of controlling the data output circuit to output the first digital signal as the second digital signal, the method for operating an image sensor according to claim 17.

19. The step of outputting a digital signal corresponding to the second counting data to the data output circuit or controlling the data output circuit to generate the first digital signal as a second digital signal corresponding to a second sub-lamp signal is when the binary value of the second counting data is greater than or equal to the binary value of the reference code, including the step of controlling the data output circuit to output the first digital signal as the second digital signal, the method for operating an image sensor according to claim 17.

Images