Integrated circuit device with crossbar for routing traffic

Abstract

To provide an integrated circuit (IC) device, such as a microcontroller device, that includes a crossbar unit that snoops around bandwidth usage in memory AXI data channels, and based on that information, determines where to route future requests in order to balance AXI traffic.SOLUTION: An IC device includes: an interconnect bus that is for communicating with an external memory device and that includes a plurality of different channels directly connected to a first set of masters; and a crossbar unit that is connected to a second set of masters and for monitoring bandwidth usage of the plurality of different channels, and based on the monitored bandwidth usage, selectively routing traffic between the second set of masters and the plurality of different channels.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] Background technology Integrated circuits can use a variety of different types of interconnect buses. One example of an interconnect bus is the Advanced eXtensible Interface (AXI) bus. The AXI bus is a bus structure available within microcontrollers that connects subsystems (including, but not limited to, the CPU subsystem, analog subsystem, digital subsystem, memory subsystem, clock subsystem, and I / O subsystem) and / or components (e.g., analog-to-digital converters, memory, sensor controllers, and real-time clocks). Microcontroller subsystems can connect to external memory through an interconnect bus such as the AXI bus. However, unbalanced traffic on the AXI channels to memory can result in performance loss. [Brief explanation of the drawings]

[0002] [Figure 1] 1 is a block diagram illustrating a microcontroller system including a subsystem with a crossbar unit, according to one embodiment. [Figure 2A] FIG. 2 is a block diagram illustrating a subsystem with a crossbar unit according to one embodiment. [Figure 2B] FIG. 10 is a block diagram illustrating a subsystem with a crossbar unit according to another embodiment. [Figure 2C] FIG. 10 is a block diagram illustrating a subsystem with a crossbar unit according to yet another embodiment. [Figure 3] FIG. 2 is a block diagram illustrating address channels of a crossbar according to one embodiment. [Figure 4] FIG. 2 is a block diagram illustrating address and data channels of a crossbar unit according to one embodiment. [Figure 5]FIG. 2 is a block diagram illustrating a reordering logic element according to one embodiment. [Figure 6] 1 is a block diagram illustrating an integrated circuit (IC) device according to one embodiment. [Figure 7] FIG. 1 is a block diagram illustrating a system with a crossbar unit according to one embodiment. [Figure 8] 1 is a flow diagram illustrating a method for routing a read request according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0003] In the following detailed description, references are made to the accompanying drawings, which form a part hereof and which show, by way of illustration, specific embodiments in which the present disclosure may be practiced. It is to be understood that alternative embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims. It is to be understood that the features of the various embodiments described herein can be combined with each other either in part or in whole, unless otherwise stated.

[0004] Microcontroller subsystems can connect to external memory through an interconnect bus, such as the Advanced eXtensible Interface (AXI) bus. Unbalanced traffic on the AXI channel to memory can result in performance loss. A memory AXI channel may be connected to multiple masters through an arbiter. These masters can request more than 100% of the channel's bandwidth, while at the same time, another master can request less than 60% of another memory AXI channel's bandwidth. This scenario can create a bottleneck on the memory channel, generating backpressure on that master. Response times per AXI request can increase, which reduces the overall performance of the system.

[0005] Some embodiments disclosed herein are directed to an integrated circuit (IC) device, such as a microcontroller device, that includes a crossbar unit that snoops bandwidth usage on memory AXI data channels and, based on that information, determines where to route future requests to balance AXI traffic. In some embodiments, the crossbar unit balances traffic routing of low-priority read memory requests from low-priority masters across multiple channels of an interconnect bus based on information from the bandwidth monitoring mechanism to improve system bandwidth efficiency.

[0006] FIG. 1 is a block diagram illustrating a microcontroller system 100 according to one embodiment. The microcontroller system 100 may include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), an application processor, a digital signal processor (DSP), a network controller, a video and audio controller, a graphics processing unit, digital components such as timers and input / output (I / O), analog components such as analog-to-digital converters (ADCs) and analog comparators, a communication interface, a clock source such as a crystal oscillator, a timer such as a real time clock (RTC), etc. Among other components (not shown in FIG. 1 ), the microcontroller system 100 includes a microcontroller 102 and external memory 114. The microcontroller 102 includes a processor 104, a memory 106, and a subsystem 110. The subsystem 110 includes a crossbar unit 112. In the illustrated embodiment, the processor 104, the memory 106, and the subsystem 110 are communicatively coupled to each other via a communication link 108, which may be an internal communication bus. It should be noted that in various implementations and embodiments, different components or combinations of components may be used to perform the operations described herein.

[0007] The processor 104 includes a central processing unit (CPU) or another suitable processor. In one embodiment, the memory 106 stores machine-readable instructions executed by the processor 104 to operate the microcontroller 102. The memory 106 and the external memory 114 include any suitable combination of volatile and / or non-volatile memory, such as random access memory (RAM), read-only memory (ROM), flash memory, and / or other suitable memory combinations. These are examples of non-transitory computer-readable storage media. The memory 106 and the external memory 114 are non-transitory in the sense that they do not contain transient signals, but instead consist of at least one memory component that stores machine-executable instructions for performing the techniques described herein.

[0008] In one embodiment, memory 106 may be any type of memory integrated on the same die as processor 104 (e.g., memory 106 may be in the same microcontroller chip as processor 104). In one embodiment, external (e.g., off-chip) memory 114 is external to the chip or chip module that houses microcontroller 102. For example, microcontroller 102 and external memory 114 may be located on the same printed circuit board (PCB) or equivalent structure and may be connected to each other over PCB tracks / pads, switches, buses, hubs, trace lines, interconnects, wires, and / or any other type of equivalent signal conducting structure.

[0009] In one embodiment, the subsystem 110 may be connected to the external memory 114 via a communication link 113 that includes an interconnect bus. The subsystem 110 is configurable to read from and write to the external memory 114 via the interconnect bus. In one embodiment, the interconnect bus may include multiple different channels that are directly connected to relatively high-priority masters in the subsystem 110. The crossbar unit 112 may be connected to multiple relatively low-priority masters in the subsystem 110. The crossbar unit 112 may monitor bandwidth usage between the subsystem 110 and the external memory 114 and selectively route traffic between the multiple relatively low-priority masters and the multiple different channels based on the monitored bandwidth usage. In another embodiment, the crossbar unit 112 may be connected to any or all masters in the subsystem 110 and may balance outgoing traffic based on snooping information (e.g., bandwidth usage).

[0010] In one embodiment, various subcomponents or elements of system 100 may be implemented in multiple different systems, and different modules may be grouped or distributed across multiple different systems. To achieve desired functionality, system 100 may include various hardware components. These hardware components may include multiple processing units, multiple data storage units, multiple peripheral adapters, and multiple network adapters. These hardware components may be interconnected using multiple buses and / or network connections. The processing unit may include a hardware architecture for retrieving executable code from a data storage unit and executing the executable code. The executable code, when executed by the processing unit, may cause the processing unit to implement at least some of the functionality disclosed herein.

[0011] FIG. 2A is a block diagram illustrating subsystem 200(1) having crossbar unit 222, according to one embodiment. Subsystem 200(1) is an exemplary implementation of subsystem 110 (FIG. 1). FIG. 2A shows elements of subsystem 200(1) for read memory access. In one embodiment, subsystem 200(1) is a video subsystem of microcontroller 102. Subsystem 200(1) includes interconnect bus 202, crossbar unit 222, graphics cache 226, JPEG decoder bus master 233, 2D graphics bus master 236, and video I / O bus master 240.

[0012] In one embodiment, interconnect bus 202 is an AXI interconnect bus. AXI is a bus structure within a microcontroller that connects subsystems (including, but not limited to, a CPU subsystem, an analog subsystem, a digital subsystem, a memory subsystem, a clock subsystem, and an I / O subsystem) and / or components (e.g., an analog-to-digital converter, memory, a sensor controller, and a real-time clock). In one embodiment, interconnect bus 202 includes three channels 204(1) through 204(3) (collectively referred to as channels 204). In one embodiment, interconnect bus 202 provides a bus infrastructure used as a routing fabric for AXI transactions initiated by bus masters, and also performs decoding, bus arbitration, and error handling.

[0013] Interconnect bus 202 is connected to external memory 210. External memory 210 is an exemplary implementation of external memory 114 (FIG. 1). In one embodiment, external memory 210 is a Low-Power Double Data Rate 4 (LPDDR4) memory. External memory 210 includes a wrapper and memory controller (e.g., an LPDDR4 memory controller) 212 and a memory 218 (e.g., an LPDDR4 memory). Wrapper and memory controller 212 includes ports 214(1) through 214(4) (collectively referred to as ports 214) and an arbiter 216. As shown in FIG. 2A, channel 204(1) is connected to port 214(1) via communication link 206(1), channel 204(2) is connected to port 214(2) via communication link 206(2), and channel 204(3) is connected to port 214(3) via communication link 214(3). Port 214(4) may be connected to the CPU subsystem via communication link 208.

[0014] In one embodiment, channel 204 arbitrates by port identifier (ID), and arbiter 216 arbitrates by master ID. In one embodiment, the arbitration provided by arbiter 216 is priority-based with round-robin arbitration within an arbitration priority group. The priority is referenceable by master ID. Arbitration may be postponed (i.e., arbitration is calculated for the next cycle). The AXI master currently executing the transaction is involved in arbitration, which may result in idle cycles. However, the master with the highest priority can permanently win arbitration, allowing back-to-back transfers to be performed even if there is another requesting master.

[0015] Graphics cache 226 includes command cache 228 and pixel cache 230. JPEG decoder master 233 includes JPEG decoder read master 234(1), which is directly connected to channel 204(1) of interconnect bus 202. 2D graphics masters include draw read master 234(2), command sequence read master 234(3), and fetch bit read masters 238(1)-238(3). Draw read master 234(2) is directly connected to channel 204(2) of interconnect bus 202. Command sequence read master 234(3) is connected to channel 204(3) of interconnect bus 202 via command cache 228. Fetch bit read masters 238(1)-238(3) are connected to crossbar unit 222 via pixel cache 230. In another embodiment, masters 238(1)-238(3) may be directly connected to crossbar unit 222.

[0016] The video input / output masters 240 include a fetch warp master 242(1), a fetch eco master 242(2), a fetch decode master 242(3), a fetch layer master 242(4), a fetch decode master 242(5), a fetch eco master 242(6), and a fetch layer master 242(7). The fetch warp master 242(1) is connected to channel 204(1) of the interconnect bus 202 via the pixel cache 230. The fetch eco master 242(2) is connected directly to channel 204(3) of the interconnect bus 202. The fetch decode master 242(3) is connected directly to channel 204(1) of the interconnect bus 202. The fetch layer master 242(4) is connected directly to channel 204(2) of the interconnect bus 202. Fetch decode master 242(5) is directly connected to channel 204(2) of interconnect bus 202. Fetch eco master 242(6) is directly connected to channel 204(3) of interconnect bus 202. Fetch layer master 242(7) is directly connected to channel 204(3) of interconnect bus 202.

[0017] In one embodiment, all bus masters, such as masters 233, 236, and 240, that access external memory 210 via interconnect bus 202 are internal to subsystem 200(1). Because there are many bus masters, bus arbitration is handled by interconnect bus 202. In one embodiment, each master shown in FIG. 2A has an assigned traffic priority of low, medium, or high. Some masters have relatively higher priority than other masters to avoid visible video artifacts. In one embodiment, masters 238(1) through 238(3) are low-priority masters (collectively referred to as low-priority masters 238), masters 234(1), 234(2), and 234(3) are medium-priority masters (collectively referred to as medium-priority masters 234), and masters 242(1) through 242(7) are high-priority masters (collectively referred to as high-priority masters 242). In one embodiment, each medium priority master 234 and high priority master 242 is connected to interconnect bus 202 either directly or through one of graphics caches 226. In one embodiment, neither medium priority master 234 nor high priority master 242 is connected to crossbar unit 222. In one embodiment, each low priority master 238 is connected to interconnect bus 202 through pixel cache 230 and crossbar unit 222.

[0018] In the example shown in FIG. 2A , high-priority master 242 has a lower limit on the amount of bandwidth it can request compared to low-priority master 238, and that bandwidth is spread relatively evenly across three channels 204. As shown in FIG. 2A , channel 204(1) has 80% (40% + 40%) of the maximum bandwidth that can be requested by high-priority masters 242(1) and 242(3), channel 204(2) has 80% (40% + 40%) of the maximum bandwidth that can be requested by high-priority masters 242(4) and 242(5), and channel 204(3) has 60% (10% + 10% + 40%) of the maximum bandwidth that can be requested by high-priority masters 242(2), 242(6), and 242(7). High-priority master 242 may not be able to tolerate long latencies and is therefore considered “high priority” as used herein. In contrast, the low priority master 238 is considered "low priority" because it can tolerate a longer latency than the high priority master 242.

[0019] Crossbar unit 222 includes three slave ports 232(1)-232(3) for receiving read memory requests from low-priority masters 238(1)-238(3), respectively. Crossbar unit 222 includes three master ports 220(1)-220(3), which are connected to channels 204(1)-204(3), respectively, of interconnect bus 202. Crossbar unit 222 may include an "AHB" (Advanced High-Performance Bus) port for reading / writing internal registers and reordering logic. In one embodiment, crossbar unit 222 includes a monitoring mechanism 224 that snoops or monitors traffic on communication links 206(1)-206(3), respectively, between interconnect bus 202 and external memory 210. In another embodiment, monitoring mechanism 224 may monitor traffic at other locations within subsystem 200(1). Crossbar unit 222 may include an ordering mechanism for transmitting AXI data transactions in order via slave ports 232(1)-232(3).

[0020] In one embodiment, to improve system bandwidth efficiency, crossbar unit 222 balances traffic routing of low-priority read memory requests from low-priority masters 238 across multiple channels 204 of interconnect bus 202 based on information from monitor mechanism 224. The numbers on channels 204 indicate the percentage of the total bandwidth of that channel 204 that may be requested by each master. For example, master 242(7) may request up to 40% of the bandwidth of channel 204(3). In one embodiment, crossbar unit 222 dynamically arbitrates AXI accesses from low-priority masters 238 to ports 214(1), 214(2), or 214(3) of external memory 210 at the lowest bandwidth, thereby ensuring that high-priority master 242 receives the bandwidth it requires. Bandwidth requests may not be constant over time, and in some periods, some bus masters may request more bandwidth than is available for a single channel 204. In this bottleneck condition for one channel 204, there may be another channel 204 that has a bandwidth demand that is less than the maximum value. Crossbar unit 222 addresses this problem by routing read memory requests from lower priority masters to channels 204 of interconnect bus 202 with lower bandwidth demands to avoid congestion in channel 204.

[0021] In one embodiment, crossbar unit 222 includes multiple selectable operating modes, including a neutral mode, a static mode, a dynamic readiness mode, and a loaded dynamic mode. In the neutral mode, crossbar unit 222 is inactive and all slave ports 232 are directly connected to their respective master ports 220. In the static mode, crossbar unit 222 uses a static mapping between slave ports 232 and master ports 220 based on values ​​in configuration registers. In the dynamic readiness mode, crossbar unit 222 uses a dynamic mapping between slave ports 232 and master ports 220 based on the readiness state of arbiter inputs of interconnect bus 202, and may select the port with the longest time since the arbiter has been busy. In the loaded dynamic mode, crossbar unit 222 uses a dynamic mapping between slave ports 232 and master ports 220 based on data bandwidth usage (e.g., outstanding transaction counts on arbiter outputs of interconnect bus 202), and may select the port with the least data bandwidth usage.

[0022] Figure 2B is a block diagram illustrating subsystem 200(2) with crossbar unit 222 according to another embodiment. Subsystem 200(2) is another exemplary implementation of subsystem 110 (Figure 1). Figure 2B shows elements of subsystem 200(2) for read memory access. In one embodiment, subsystem 200(2) is the video subsystem of microcontroller 102.

[0023] 2B, each master 238(1) and 238(2) is connected to interconnect bus 202 via pixel cache 230 and crossbar unit 222. In the illustrated embodiment, monitoring mechanism 224 of crossbar unit 222 snoops or monitors traffic at three master ports 220(1) through 220(3), which are respectively connected to channels 204(1) through 204(3) of interconnect bus 202. In alternative embodiments, monitoring mechanism 224 may monitor traffic at other locations within subsystem 200(2).

[0024] In one embodiment, to improve system bandwidth efficiency, crossbar unit 222 balances the traffic routing of read memory requests from masters 238(1) and 238(2) across multiple channels 204 of interconnect bus 202 based on information from monitor mechanism 224. In one embodiment, crossbar unit 222 balances the unbalanced traffic of masters 238(1) and 238(2) so that each of the three channels 204 receives 33.33% of the total bandwidth from masters 238(1) and 238(2).

[0025] As an example, assuming there is no crossbar unit 222 or that crossbar unit 222 is in static mode, master 238(1) can request 50% of the bandwidth of channel 204(1), and master 238(2) can request 50% of the bandwidth of channel 204(2). Further assume that masters 234(1), 242(1), and 242(3) can request 25%, 20%, and 20% of the maximum bandwidth of channel 204(1), respectively. If all masters connected to channel 204(1) were at 100% of their bandwidth usage, 115% (i.e., 25% + 50% + 20% + 20%) of the bandwidth of channel 204(1) would be used by these masters. However, using crossbar unit 222 in load dynamic mode results in 98.33% (ie, 25% + 33.33% (max) + 20% + 20%) of the bandwidth of channel 204(1) being used by the master.

[0026] Figure 2C is a block diagram illustrating subsystem 200(3) with crossbar unit 222 according to another embodiment. Subsystem 200(3) is another exemplary implementation of subsystem 110 (Figure 1). Figure 2C shows elements of subsystem 200(3) for read memory access. In one embodiment, subsystem 200(3) is the video subsystem of microcontroller 102.

[0027] As shown in FIG. 2C , crossbar unit 222 is connected between interconnect bus 202 and external memory 210. Crossbar unit 222 shown in FIG. 2C may be internal or external to subsystem 200(3). In the illustrated embodiment, monitoring mechanism 224 of crossbar unit 222 snoops or monitors traffic at three master ports 220(1)-220(3), which are connected to ports 214(1)-214(3) of wrapper and memory controller 212, respectively. In another embodiment, monitoring mechanism 224 may monitor traffic at other locations within subsystem 200(3). In one embodiment, based on information from monitoring mechanism 224, crossbar unit 222 balances traffic routing of read memory requests from all masters 234, 238, and 242 across multiple ports 214(1)-214(3) to improve system bandwidth efficiency.

[0028] FIG. 3 is a block diagram illustrating an address channel 300 of a crossbar unit, according to one embodiment. In one embodiment, address channel 300 is part of crossbar unit 222 (FIGS. 2A-2C). Address channel 300 includes master ports 302(1)-302(3) (collectively referred to as master ports 302), an arbiter 304, a crossbar routing element 316, and slave ports 322(1)-322(3) (collectively referred to as slave ports 322). Arbiter 304 includes counters 306. In one embodiment, address channel 300 includes the same number of counters 306 as the number of master ports 302, with each counter 306 corresponding to one of the multiple master ports 302. Crossbar routing element 316 selectively routes transactions between master ports 302 and slave ports 322 based on the operational mode of the crossbar unit and the value of counter 306.

[0029] Counter 306 can be used in different configurations depending on the crossbar unit's operating mode. In a first configuration, corresponding to a dynamic readiness mode, counter 306 for each port 302 is reset and the masen_arready bit is set low when the arbiter is busy with relatively high priority traffic. Each cycle that the masen_arready bit is set high is counted by counter 306. Counter 306 measures the time since the last time masen_arready was low. The port selection criterion is the port with the highest count value, and this port is selected by arbiter 304 via port select signal 310. In a second configuration, corresponding to a load dynamic mode, counter 306 is incremented by the byte length of an address request and decremented when the requested data is received. In another embodiment, counter 306 is incremented by one with each address request and decremented by one when the requested data is received.

[0030] FIG. 4 is a block diagram illustrating an address and data channel 400 of a crossbar unit according to one embodiment. In one embodiment, the address and data channel 400 is part of the crossbar unit 222 (FIGS. 2A-2C). The address and data channel 400 includes master address ports 402(1)-402(3) (collectively referred to as master address ports 402), master address pipelines 404(1)-404(3) (collectively referred to as master address pipelines 404), an address channel crossbar 406, slave address pipelines 418(1)-418(3) (collectively referred to as slave address pipelines 418), slave address ports 420(1)-420(3) (collectively referred to as slave address ports 420), and synchronous first-in-first-out (synchronous first-out) ... FIFO buffers 422(1) through 422(3) (collectively referred to as FIFOs 422), master data ports 428(1) through 428(3) (collectively referred to as master data ports 428), master data pipelines 430(1) through 430(3) (collectively referred to as master data pipelines 430), data channel crossbar 432, slave data pipelines 436(1) through 436(3) (collectively referred to as slave data pipelines 436), and slave data ports 440(1) through 440(3) (collectively referred to as slave data ports 440).

[0031] Address channel crossbar 406 includes crossbar routing unit 412 and ID addition logic elements 414(1) through 414(3) (collectively referred to as ID addition logic 414). Data channel crossbar 432 includes crossbar routing unit 433 and reordering logic elements 434(1) through 434(3) (collectively referred to as reordering logic 434).

[0032] For every address request received through slave address port 420, information is added to the request to enable the appropriate routing of incoming data to that slave data port 440. In one embodiment, every incoming address request is tagged to enable subsequent ordering in the data channel. Address requests are received through slave address port 420 and provided to ID attachment logic 414 through slave address pipeline 418. In one embodiment, ID attachment logic 414 attaches ID information to each address request, including a transaction ID 424 and a slave ID 426. Slave ID 426 is used to identify to which slave the incoming data should be routed back. Transaction ID 424 is used to identify transaction order. For example, a data transaction with transaction ID "2" can be stored in a reordering memory in data channel crossbar 432 until it can be sent to a port if a transaction with transaction ID "1" has not yet been received.

[0033] The ID appending logic 414 provides the address request with the appended ID information to the crossbar routing unit 412, which selectively routes the address request with the appended ID information to an output port of the crossbar routing unit 412. The routing may be based on a counter value that may be incremented by the cnt_inc signal 408 and decremented by the cnt_dec signal 410. The address request with the appended ID information is then sent to the master address port 402 via the master address pipeline 404. Based on the address request, data is read from the external memory and a data transaction is received at the master data port 428. The data transaction is provided to the crossbar routing unit 433 via the master data pipeline 430. The crossbar routing unit 433 selectively routes the data transaction to the reordering logic 434.

[0034] In one embodiment, ID information for all master ports is stored in FIFO 422. The FIFO ID information can be used for routing and ordering in the data channel. For example, if an address request is received at slave address port 420(3), address channel crossbar 406 can route the request to master address port 402(2) and store the ID information in its FIFO 422. When data is read from external memory and received at master data port 428(2), crossbar routing unit 433 routes the data to the slave data port 440(3) associated with the request. The crossbar routing unit routes the data using slave ID 426 previously stored in FIFO 422. In this embodiment, crossbar routing unit 433 routes the data to reordering logic 434(3). Reordering logic 434(3) receives the data and checks whether transaction ID 424 corresponds to the next transaction expected by the cache. If the transaction ID is not the next expected transaction ID, the transaction can be stored in memory (e.g., memory 506 shown in FIG. 5). If the transaction ID is the next expected transaction ID, the transaction can be sent to slave port 440(3) via slave data pipeline 436(3).

[0035] FIG. 5 is a block diagram illustrating a reordering logic element 500 according to one embodiment. The reordering logic 500 is one exemplary implementation of the reordering logic elements 434(1)-434(3). In one embodiment, each of the reordering logic elements 434(1)-434(3) is configurable in the manner shown in FIG. 5. The reordering logic element 500 includes a counter 502, a logic unit 504, a memory 506, a port 508, and a port 510. The reordering logic element 500 receives data transactions via port 508. The logic unit 504 can reorder the received data transactions using the memory 506 and the counter 502 and can output the reordered data transactions via port 510, as described in more detail below.

[0036] FIG. 5 is described in additional detail below with further reference to FIG. 4. The reordering logic 434 may have a counter (e.g., counter 502 shown in FIG. 5) that tracks what the next transaction ID expected by the cache should be. For example, assume that the data channel receives two data transactions out of order for slave port 440(2) (e.g., transaction 0x120 is received first, followed by transaction 0x110). In the correct order, transaction 0x110 should be first and transaction 0x120 should be next. The 0x120 data transaction arrives at the reordering logic 434, which checks whether the transaction ID of this transaction matches the transaction ID expected by the cache. The cache may have already received the 0x100 data transaction and is expecting the 0x110 transaction. Because this data transaction does not match the transaction ID expected by the cache, the reordering logic 434 can store the data transaction of 0x120 in the reordering memory (e.g., memory 506 shown in FIG. 5). Because the memory has not yet been released, the reordering logic 434 does not release the transaction ID to the address channel.

[0037] Sometime later, the 0x110 data transaction arrives at the reordering logic 434. The reordering logic 434 determines that the transaction ID matches the next transaction ID expected by the cache and removes the transaction ID appended in the address channel before sending it to the cache. When the data is completely sent to the data pipeline 436 and the address channel allows another request to be sent appending the transaction ID, the transaction ID is released (as shown at 438 in FIG. 4). The reordering logic 434 increments the next transaction ID expected by the cache, checks the next transaction ID, and determines that it has already been received (i.e., the 0x120 data). The reordering logic 434 sends the 0x120 data to the cache and removes the appended ID. The transaction ID is released for use in future requests (as shown at 438 in FIG. 4).

[0038] One embodiment of the present disclosure is directed to an integrated circuit (IC) device. FIG. 6 is a block diagram illustrating an IC device 600 according to one embodiment. As shown in FIG. 6, the IC device 600 includes an interconnect bus 602 for communicating with an external memory device, the interconnect bus including a plurality of different channels directly connected to a first set of masters. The IC device 600 also includes a crossbar unit 604 connected to a second set of masters, the crossbar unit 604 monitoring bandwidth usage on the plurality of different channels and selectively routing traffic between the second set of masters and the plurality of different channels based on the monitored bandwidth usage.

[0039] The interconnect bus 602 may be an AXI bus. The crossbar unit 604 may selectively route traffic across multiple different channels in a manner that balances the traffic. The interconnect bus 602 and the crossbar unit 604 may be part of a video processing subsystem of an IC device. The first set of masters may include multiple relatively high-priority masters, and the second set of masters may include multiple relatively low-priority masters. The multiple relatively high-priority masters may include a high-priority master and a medium-priority master, and the multiple relatively low-priority masters may include a low-priority master that has a latency-tolerance-based priority that is lower than the latency-tolerance-based priority of the high-priority master and the medium-priority master.

[0040] The crossbar unit 604 may include at least one counter, and monitoring bandwidth usage on the different channels by the crossbar unit may include incrementing the at least one counter based on read requests sent to the external memory device. The crossbar unit 604 may increment the at least one counter according to a byte length of data requested in each read request. The crossbar unit 604 may decrement the at least one counter when the requested data is received in the read request. The crossbar unit 604 may include reordering logic for reordering data transactions received from the external memory device in an order different from that expected by the crossbar unit, and the crossbar unit 604 may transmit the reordered data transactions to a second set of masters.

[0041] The crossbar unit 604 may include multiple selectable operating modes, allowing the crossbar unit 604 to selectively route requests between the slave ports of the crossbar unit 604 and the master ports of the crossbar unit 604 based on one of the currently selected operating modes. The operating modes may include a load dynamic mode, in which the crossbar unit 604 uses dynamic mapping between slave ports and master ports based on data bandwidth usage for each of multiple different channels of the interconnect bus 602 (e.g., by counting data on the channel on the fly). The operating modes may also include a dynamic readiness mode, in which the crossbar unit 604 uses dynamic mapping between slave ports and master ports based on ready states of multiple different channels of the interconnect bus 602, where the ready states include respective lengths of time that the multiple different channels have been busy. The operating modes may further include a neutral mode in which all slave ports are directly connected to a respective one of the master ports, and a static mode in which a static mapping between slave ports and master ports is used by the crossbar unit based on the value of a configuration register.

[0042] Another embodiment of the present disclosure is directed to a system including a crossbar unit. FIG. 7 is a block diagram illustrating a system 700 including a crossbar unit according to one embodiment. The system 700 includes at least one memory device 702 and a microcontroller 704 external to the at least one memory device 702. The microcontroller 704 includes an interconnect bus 706 for communicating with the at least one memory device 702, the interconnect bus 706 including a plurality of different channels. The microcontroller 704 includes a first plurality of masters 708, each directly connected to one of the channels of the interconnect bus 706. The microcontroller 704 includes a second plurality of masters 710. The microcontroller 704 includes a crossbar unit 712 connected to the second plurality of masters 710, the crossbar unit 712 monitoring bandwidth usage on the plurality of different channels and selectively routing traffic between the second plurality of masters 710 and the plurality of different channels based on the monitored bandwidth usage.

[0043] The interconnect bus 706 may be an AXI bus, and the crossbar unit 712 may selectively route traffic across different channels of the AXI bus in a manner to balance the traffic. The crossbar unit 712 may include at least one counter, and monitoring bandwidth usage on the different channels by the crossbar unit 712 may include incrementing the at least one counter based on read requests sent to the at least one memory device. The crossbar unit 712 may include reordering logic for reordering data transactions received from the at least one memory device in an order different from an expected order by the crossbar unit 712, and the crossbar unit 712 may transmit the reordered data transactions to the second plurality of masters 710.

[0044] Another embodiment of the present disclosure is directed to a method for routing read requests. Figure 8 is a flow diagram illustrating a method 800 for routing read requests, according to one embodiment. At step 802, method 800 includes transmitting read requests from a first plurality of masters to an external memory device over multiple channels of an interconnect bus. At step 804, method 800 includes monitoring usage of the multiple channels. At step 806, method 800 includes selectively routing read requests from a second plurality of masters to the multiple channels based on the monitored usage of the multiple channels.

[0045] In method 800, in step 806, selective routing may be performed by the crossbar unit, and method 800 may further include selecting an operating mode of the crossbar unit and selectively routing read requests from a second plurality of rows to the plurality of channels based on the monitored usage of the plurality of channels and the selected operating mode of the crossbar unit.

[0046] While specific examples have been shown and described herein, various alternative and / or equivalent implementations may be substituted for the specific examples shown and described herein without departing from the scope of the present disclosure. This application is intended to include any adaptations or variations of the specific embodiments described herein. Accordingly, it is intended that the present disclosure be limited only by the claims and equivalents thereof.

Claims

1. A subsystem included in a microcontroller; a crossbar unit configured to communicate with the subsystems; An apparatus comprising: the crossbar unit is further configured to communicate with an external memory device over a plurality of channels, the crossbar unit being connected to a set of masters, the crossbar unit being configured to monitor bandwidth usage on the plurality of channels and route traffic between the set of masters and the plurality of channels based on the monitored bandwidth usage; the crossbar unit comprising a crossbar routing element configured to route traffic based on an operational mode of the crossbar unit; Device.

2. The plurality of channels are included in a communication link.

10. The apparatus of claim 1.

3. the crossbar unit is configured to selectively route the traffic across the plurality of channels in a manner that balances the traffic.

10. The apparatus of claim 1.

4. The crossbar routing element is further configured to selectively route requests between a plurality of master ports of the crossbar unit and a plurality of slave ports of the crossbar unit based on an operational mode of the crossbar unit.

10. The apparatus of claim 1.

5. The method of claim 1, wherein the operating mode is one of a plurality of selectable operating modes, and the crossbar routing element is further configured to selectively route requests based on the currently selected operating mode.

5. The apparatus of claim 4.

6. the plurality of selectable operating modes includes a load dynamic mode, the load dynamic mode employing dynamic mapping between the slave ports and the master ports based on outstanding transaction counts for each of the plurality of channels; 6. The apparatus of claim 5.

7. The method of claim 1, wherein the set of masters comprises a set of relatively high priority masters and a set of relatively low priority masters.

10. The apparatus of claim 1.

8. the crossbar unit includes at least one counter, and monitoring the bandwidth usage of the plurality of channels by the crossbar unit includes incrementing the at least one counter based on a read request sent to the external memory device.

10. The apparatus of claim 1.

9. the subsystem is part of a video processing subsystem; 10. The apparatus of claim 1.

10. at least one memory device; a microcontroller connected to the at least one memory device via a plurality of channels; A system comprising: The microcontroller a plurality of masters connected to the plurality of channels; A crossbar unit; a crossbar routing element configured to route traffic based on an operational mode of the crossbar unit; Equipped with the crossbar unit is configured to communicate with the at least one memory device over the plurality of channels, the crossbar unit is connected to the plurality of masters, and the crossbar unit is configured to monitor bandwidth usage on the plurality of channels and route traffic between the plurality of masters and the plurality of channels based on the monitored bandwidth usage. system.

11. The plurality of channels are included in a communication link. The system of claim 10.

12. The crossbar unit configured to selectively route the traffic across the plurality of channels in a manner that balances the traffic. The system of claim 10.

13. The crossbar routing element is further configured to selectively route requests between a plurality of master ports of the crossbar unit and a plurality of slave ports of the crossbar unit based on an operational mode of the crossbar unit. The system of claim 10.

14. The method of claim 13, wherein the operating mode is one of a plurality of selectable operating modes, and the crossbar routing element is further configured to selectively route requests based on the currently selected operating mode. The system of claim 13.

15. The plurality of selectable operating modes includes a load dynamic mode, the load dynamic mode employing a dynamic mapping between the slave port and the master port based on a significant transaction count for each of the plurality of channels.

15. The system of claim 14.

16. The method of claim 15, further comprising: transmitting read requests from a plurality of masters to an external memory device via a plurality of channels connecting said external memory device to a crossbar unit; monitoring the use of the plurality of channels using the crossbar unit; using a crossbar routing element to selectively route read requests from at least some of the plurality of masters to the plurality of channels based on the monitored usage of the plurality of channels, the routing being performed based at least in part on an operational mode of the crossbar unit; A method comprising:

17. The plurality of channels are included in a communication link.

17. The method of claim 16.

18. The routing method according to claim 1, further comprising selectively routing the traffic across the plurality of channels in a manner that balances the traffic.

17. The method of claim 16.

19. The routing method according to claim 18, further comprising: routing transactions between a plurality of master ports and a plurality of slave ports using the crossbar routing element based on an operational mode of the crossbar unit.

17. The method of claim 16.

20. The operating mode is one of a plurality of selectable operating modes, the plurality of selectable operating modes including a load dynamic mode, the load dynamic mode using dynamic mapping between the slave port and the master port based on a significant transaction count for each of the plurality of channels.

20. The method of claim 19.

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