SiC-BASED ELECTRONIC DEVICE WITH ENHANCED ROBUSTNESS, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE

Abstract

To provide a SiC-based electronic device with enhanced robustness, and a method for manufacturing the electronic device.SOLUTION: An electronic device (50, 100) includes: a semiconductor body (53) of silicon carbide; a first insulating layer (61) of a first material with electrical-insulator or dielectric characteristics, on a first surface (53a) of the semiconductor body (53); a first layer of a metal material (58) extending in part on the first surface (53a) of the semiconductor body (53) and in part on the first insulating layer (61); an interface layer (63) of a second material different from the first material, on the first layer of a metal material (58) and on the first insulating layer (61); and a passivation layer (69) of the first material on the interface layer (63). The first material is a silicon oxide, and the second material is a silicon nitride.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an electronic device and a method of manufacturing the same. In particular, the electronic device is an SIC-based device and has improved robustness.

Background Art

[0002] The semiconductor industry has shown considerable interest in silicon carbide (SiC) for manufacturing electronic components such as diodes or transistors, especially for power applications.

[0003] Electronic devices formed on silicon carbide substrates in its different polytypes (e.g., 3C-SiC, 4H-SiC, 6H-SiC) have many advantages such as low on-state output resistance, low leakage current, high operating temperature, and durability against high operating frequencies.

[0004] However, the development and manufacturing of SiC-based electronic devices are limited by factors such as the electrical and mechanical properties of the passivation layer (which is included in these electronic devices and, for example, extends over the SiC semiconductor body of the electronic device). In particular, it is known to obtain the passivation layer by using a polymeric material (e.g., polyimide) that enables the electronic device to withstand high operating temperatures and, for example, provides a higher dielectric strength than 400 kV / mm. Specifically, the high dielectric strength of the polymeric material ensures that the passivation layer can withstand a high electric field and, as a result, can withstand a high potential difference across the high electric field without causing electrical breakdown and thus without becoming conductive.

[0005] However, polymeric materials have a high coefficient of thermal expansion (CTE) (e.g., for polybenzoxazole, i.e., PIX, the material has a CTE = 43e -6 1 / K), which causes the SiC passivation layer with a lower coefficient of thermal expansion (CTE = 3.8e -6This causes adhesion problems of 1 / K.

[0006] In particular, adhesion problems between the passivation layer and SiC may occur during thermal cycling tests (e.g., between approximately -50°C and approximately +150°C) or during the service life of electronic devices exposed to high temperature swings (e.g., exposure to operating temperature differences equal to or greater than approximately 200°C). Due to the large difference in CTE between the passivation layer and SiC, these high-temperature swings generate mechanical stress at the interface between the passivation layer and SiC, which may result in delamination (at least partially) of the passivation layer from the SiC semiconductor body.

[0007] If this delamination is sufficiently extensive (for example, if no portion of the passivation layer intervenes between the two metallizations of an electronic device set to different potentials, and is therefore separated from each other only by air), an electrical discharge may occur at the interface, resulting in damage to the electronic device itself. In particular, the risk of damage to the electronic device increases when it is used under reverse bias conditions, due to the high voltage difference it must withstand (e.g., much higher than 1000V).

[0008] Known solutions to address this problem include using multiple dielectric layers made of different materials (e.g., silicon nitride, silicon oxide, and polyimide in a contiguous sequence) to form a passivation multilayer designed to limit mechanical stress at the interface with the SiC semiconductor body.

[0009] Figure 1 shows a portion of a known type of electronic device 1 (here, as an example, a JBS, i.e., a junction barrier Schottky diode) in a cross-sectional view in a (three-axis) Cartesian coordinate system with axes X, Y, and Z.

[0010] The JBS apparatus 1 has a semiconductor body 3 made of N-type SiC having a surface 3a opposite to surface 3b. The semiconductor body includes, for example, a substrate and one or more regions epitaxially grown on the N-type substrate having doping concentrations of respective values. The JBS apparatus 1 further has a plurality of junction barrier (JB) elements 9 within the semiconductor body 3, each facing the upper surface 3a and each including a P-type injection region in the semiconductor body 3 and an ohmic contact on the injection region at the level of the upper surface 3a of the semiconductor body 3. The JBS apparatus 1 further has a first metallization 8 that extends over the upper surface 3a and is in electrical contact with the junction barrier elements 9 via their respective ohmic contacts. The JBS apparatus 1 further has an end-termination region (or protective ring) 10, in particular a P-type injection region, which completely surrounds the JB elements 9.

[0011] The Schottky diode 12 is formed at the interface between the anode metallization 8 and the semiconductor body 3 where the semiconductor-metal Schottky junction is formed. The region of the MPS apparatus 1 that includes the JB element 9 and the Schottky diode 12 (i.e., the region included within the protective ring 10) is the active region 4 of the JBS apparatus 1.

[0012] The JBS device 1 further includes a second metallization 6, which extends over the bottom surface 3b. The first and second metallizations 8 and 6 form electrical anode and cathode terminals, respectively, which can be biased during the use of the JBS device 1.

[0013] An electrically passive region 16 extends outside the end terminal region 10.

[0014] An insulating layer 18, made of an insulating or dielectric material, particularly silicon oxide (SiO2), partially extends over the end terminal region 10.

[0015] The first metallization 8 is in electrical contact with a portion of the end-terminal region 10 where the end-terminal region 10 is not covered by the insulating layer 18, and extends partially over the insulating layer 18. Here, an interface layer 20 made of silicon nitride (SiN) extends over the first metallization 8 and the insulating layer 18. Furthermore, the JBS apparatus 1 has a passivation layer 22 made of polyimide in particular, which extends over the interface layer 20. That is, the interface layer 20 acts as an interface between the passivation layer 22 and the layer below it, in this case the first metallization 8 and the insulating layer 18. The interface layer 20 can be omitted, but the inventors have found that the interface layer 20 improves the adhesion between the passivation layer 22 and the layer below it.

[0016] A protective layer 24 made of a resin such as bakelite extends over the passivation layer 22 and protects the JBS device 1 when inserted into a package (not shown).

[0017] However, as described above, while the interface layer 22 improves adhesion between the passivation layer 22 and the layer below it, certain critical conditions of use or testing of the JBS apparatus 1 (e.g., thermal-mechanical or thermal stress) may cause delamination or partial separation of the passivation layer 22 from the interface layer 20. This occurs particularly under stress conditions resulting from use at high temperatures (e.g., above 150°C). This effect can contribute to making the JBS apparatus 1 structurally brittle and may also cause unwanted electrical discharges that affect the electrical operation of the JBS apparatus 1. In fact, the inventors have found that, for example, mechanical stress during assembly can generate stress within the interface layer 20 that causes localized cracks throughout the entire thickness of the first metal layer 8, which are the cause of these electrical discharges. These problems are even more pronounced when the electronic apparatus 1 is exposed to high thermal swings and high voltage differences under reverse bias conditions. [Overview of the project] [Problems that the invention aims to solve]

[0018] The present invention aims to solve the problems of the prior art described above and to provide an electronic device based on SiC with improved robustness, as well as a method for manufacturing such an electronic device. [Means for solving the problem]

[0019] According to the present invention, an electronic device and a method for manufacturing an electronic device are provided, as defined in the claims.

[0020] To better understand the present invention, preferred embodiments of the invention, as purely non-limiting examples, are described below with reference to the accompanying drawings. [Brief explanation of the drawing]

[0021] [Figure 1] A cross-sectional view illustrating a known type of electronic device. [Figure 2] Cross-sectional view illustrating an electronic device according to an embodiment of the present invention. [Figure 3A] Cross-sectional view showing a state in a certain step of a method of manufacturing the electronic device of FIG. 2 based on an embodiment of the present invention. [Figure 3B] Cross-sectional view showing a state in a certain step of a method of manufacturing the electronic device of FIG. 2 based on an embodiment of the present invention. [Figure 3C] Cross-sectional view showing a state in a certain step of a method of manufacturing the electronic device of FIG. 2 based on an embodiment of the present invention. [Figure 3D] Cross-sectional view showing a state in a certain step of a method of manufacturing the electronic device of FIG. 2 based on an embodiment of the present invention. [Figure 4] Cross-sectional view illustrating an electronic device according to another embodiment of the present invention.

Mode for Carrying Out the Invention

[0022] FIG. 2 shows a cross-sectional view of an electronic device 50 based on one aspect of the present invention in the same (three-axis) Cartesian coordinate system consisting of the axes X, Y, Z of FIG. 1. In particular, the device 50 is a JBS diode similar to that described with reference to FIG. 1, but the present invention is not limited to this device only and is also applicable to other types of electronic devices, especially in power devices such as MOSFETs, IGBTs, MPSs, Schottky diodes, PN diodes, PiN diodes, etc.

[0023] The electronic device 50 has the elements described below and illustrated with reference to FIG. 2.

[0024] A semiconductor body 53 made of SiC doped with N or P type (in the following description, N-type doping will be used as an example) (i.e., encompassing a substrate and optionally one or more epitaxial layers grown thereon) has a surface 52a and a surface 53b opposite to it in the Z-axis direction. In this example, the semiconductor body 53 encompasses a substrate 53' on which a drift layer (epitaxial layer) 53'' is grown, which is made of N-type SiC (in particular 4H-SiC, but not limited to these, other polytypes such as 2H-SiC, 3C-SiC, and 6H-SiC can also be used). For example, the substrate is 1 × 10 19 at / cm 3 and 1 x 10 22 at / cm 3 The drift layer has an N-type dopant concentration between 300 μm and 450 μm, and its thickness, measured along axis Z between surfaces 53a and 53b, is particularly equal to approximately 360 μm. The drift layer has a dopant concentration even lower than that of the substrate and a thickness, for example, between 5 μm and 15 μm.

[0025] An ohmic contact layer 56 (for example, made of nickel silicide) extends on the surface 53b of the substrate 53, and a metallation 57, which is cathode metallization in this example and is made of Ti / NiV / Ag or Ti / NiV / Au, extends on the ohmic contact region 56.

[0026] One or more P-type doped regions 59' extend into the semiconductor body 53 (particularly in the drift layer) facing the upper surface 53a, and each doped region 59' accommodates its respective ohmic contact (not shown, of known types) such that each doped region 59' forms its respective junction barrier (JB) element 59. An end-termination region 60, i.e., a protective ring, particularly an additional P-type doped region, extends into the drift layer, faces the upper surface 53a, and completely surrounds the JB element 59 (in the plane XY defined by axes X and Y in the plan view). The end-termination region 60 may be omitted.

[0027] An insulating layer 61 (made of an insulating or dielectric material, i.e., silicon oxide or TEOS) extends over the upper surface 53a so as to completely surround the JB element 59 (within plane XY) and partially overlap with the protective ring 60 (if present).

[0028] Metallization 58, in this example, an anode metallization consisting of Ti / AlSiCu or Ni / AlSiCu, extends over a portion of the upper surface 53a whose outer side is partitioned by the insulating layer 61 (i.e., in the JB element 59 / active region 54), and partially over the insulating layer 61.

[0029] One or more Schottky diodes 62 are formed along the doped region 59' at the interface between the semiconductor body 53 and the anode metallization 58. In particular, the (semiconductor-metal) Schottky junction is formed by the portion of the semiconductor layer 53 that is in direct electrical contact with each portion of the anode metallization 58.

[0030] Furthermore, each ohmic contact extending within each doped region 59' provides an electrical connection having an electrical resistivity value even lower than the electrical resistivity value of the doped region 59' that houses it. Thus, the JB element 59 is a PiN diode.

[0031] The region of the electronic device 50 that includes the JB element 59 and the Schottky diode 62 (i.e., the region partitioned by the protective ring 60) is the active region 54 of the electronic device 50.

[0032] Outside the active region 54, i.e., beyond the end-termination region 60, there exists a lateral surface 53c of the semiconductor body 53, which extends substantially perpendicular to, for example, the upper surface 53a. The lateral surface 53c is formed by a dicing, or individualization, step of the SiC wafer from which multiple electronic devices 50 are obtained. The dicing step has the function of separating one electronic device 50 from another device 50 on the same wafer. The dicing is performed along a scribe line (not shown) of the SiC wafer from which the electronic devices 50 are obtained, and this scribe line surrounds the active region 54, the protective ring 60, and the insulating layer 61 at a distance in plane XY.

[0033] For example, a protective layer 74 made of a resin such as bakelite extends over the passivation layer 69 and protects the electronic device 50 when inserted into a package (not shown).

[0034] In particular, a further insulating layer 64 made of a dielectric or insulating material (for example, silicon oxide or TEOS, the same material used for the insulating layer 61) extends over the anode metallization 58 and the insulating layer 61 exposed along the anode metallization 58.

[0035] The insulating layer 61 has a thickness between 0.5 μm and 2 μm along axis Z, for example, and the insulating layer 64 has a thickness between 0.5 μm and 2 μm along axis Z.

[0036] Here, an interface layer 63 made of silicon nitride (SiN) extends over the insulating layer 64.

[0037] The passivation layer 69 extends over the interface layer 63. The interface layer 63 acts as an interface between the passivation layer 69 and the layer below it, in this case the isolation layer 64.

[0038] According to one aspect of the present invention, the passivation layer 69 is made of an insulating or dielectric material, particularly the same material as that of the insulating layer 64. In this way, any potential thermal stress that the device 50 is exposed to during use or testing does not have a significant effect on the interface layer 63 in terms of stress, and therefore the likelihood of cracking is reduced. The passivation layer 69 is made of, for example, silicon oxide or TEOS.

[0039] The steps for manufacturing the electronic device 50 shown in Figure 2 will be described below with reference to Figures 3A-3D, but will be limited to manufacturing steps useful for understanding the present invention. Figure 3A-3D is shown in the same three-axis system as in Figure 2.

[0040] Referring to Figure 3A, a wafer is provided containing a SiC semiconductor body 53 after a manufacturing step in which the elements of the electronic device 50 described above (and therefore identified by the same reference number) are formed.

[0041] Referring to Figure 3A, after forming the insulating layer 61 and the anode metallization 58, a step is performed to deposit an insulating or dielectric material to form an insulating layer 64. This step is performed, for example, by a CVD or LPCVD process. The insulating layer 61 is formed on the entire surface of the wafer and, in particular, completely covers the anode metallization 58 and the insulating layer 61.

[0042] Next, referring to Figure 3B, after forming the insulating layer 64, an insulating layer 63 is formed, for example, by CVD-type deposition of silicon nitride. The interface layer 63 is formed on the entire surface of the wafer, and in particular, the insulating layer 64 is completely covered.

[0043] Next, referring to Figure 3C, a passivation layer 69 is formed. This step aims to deposit an insulating material, such as silicon oxide or TEOS, which is deposited using CVD or LPCVD techniques. The passivation layer 69 has a thickness selected, for example, within the range of 1 μm to 10 μm.

[0044] The passivation layer 69 completely covers the interface layer 63 and, if necessary, can be patterned (for example, by lithography and etching steps).

[0045] In this manufacturing process, subsequent steps are taken to form further elements of the electronic device 50, but a detailed explanation of these steps is omitted here (for example, the formation of the ohmic contact layer 56 and cathode metallization 57).

[0046] Figure 4 illustrates an electronic device 100 based on a further embodiment of the present invention. The electronic device 100 is shown in the same (three-axis) Cartesian coordinate system with the same axes X, Y, and Z as those in Figures 1 and 2. In particular, the electronic device 100 is a JBS diode similar to those described with reference to Figures 1 and 2, but even in this case, the present invention should not be limited to JBS devices, but is also applicable to other types of electronic devices, particularly in power devices, such as MOSFETs, IGBTs, MPSs, Schottky diodes, PN diodes, and PiN diodes.

[0047] The elements of electronic device 100, which are common to electronic device 50 in Figure 2, are given the same reference numerals, and further explanation of them is omitted.

[0048] In particular, the electronic device 100 does not include an insulating layer 64. Therefore, in this embodiment, the interface layer 63 extends directly over and is in contact with the anode metallization 58 and the insulating layer 61.

[0049] The passivation layer 69 of the type described above extends over the interface layer 63 and is physically separated from the anode metallization 58 and the insulating layer 61 by the interface layer 63. The steps for manufacturing the electronic device 100 are the same as those described with reference to Figure 3A-3D, except for the steps related to the formation of the insulating layer 64.

[0050] By examining the characteristics of this disclosure relating to the present invention, the advantages obtained from the present invention become clear.

[0051] In particular, the passivation layer obtained according to the present invention is especially robust and reliable during thermal stress testing of electronic devices. Furthermore, it reduces the propagation of stress that causes cracks in the interface layer 63.

[0052] In other words, the present invention (which avoids the need to provide a passivation layer 69 made of polymer material) guarantees high electrical performance of the electronic devices 50,100 and at the same time eliminates structural problems linked to the potential delamination of the polymer passivation layer (for example, following a thermal cycle or usage cycle of the electronic devices 50,100).

[0053] Although specific embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and it is of course possible to make various changes and modifications without departing from the technical scope of the present invention.

Claims

1. In an electronic device (50; 100), a semiconductor body (53) of silicon carbide; a first insulating layer (61) of a first material having electrical insulating or dielectric properties, provided on a first surface (53a) of the semiconductor body (53); a first layer of metallic material (58) extending partially over the first surface (53a) of the semiconductor body (53) and partially over the first insulating layer (61); an interface layer (63) of a second material different from the first material disposed on the first layer of metal material (58) and on the first insulating layer (61); and a passivation layer (69) of said first material on said interface layer (63); An electronic device having:

2. 2. The electronic device of claim 1, wherein the first material is silicon oxide or TEOS.

3. 3. The electronic device of claim 1, wherein the second material is silicon nitride.

4. 3. The electronic device of claim 1, further comprising a second insulating layer (64) interposed between the interface layer (63) and the underlying first insulating layer (61) and first layer of metallic material (58).

5. 5. The electronic device of claim 4, wherein said second insulating layer (64) comprises said first material.

6. 3. The electronic device of claim 1, further comprising an active area (54), wherein the first layer of metal material (58) extends in the active area (54) at least partially overlapping and in electrical contact with the first surface (53a) of the semiconductor body.

7. 7. The electronic device of claim 6, further comprising an edge termination region (60) at least partially surrounding the active area (54), the edge termination region (60) being a region implanted in the semiconductor body at the first surface (53 a) and having an electrical conductivity type opposite that of the semiconductor body (53), and the first insulating layer (61) extending over the first surface (53 a) at a distance from the active area (54) and at least partially overlapping the edge termination region (60).

8. 7. The electronic device of claim 6, further comprising a second layer of metallic material (57) on a second surface (53b) of the semiconductor body (53) opposite the first surface (53a), the first layer of metallic material (58) and the second layer of metallic material (57) forming respective electrically conductive terminals of the electronic device (50, 100).

9. 3. An electronic device according to claim 1 or 2, further comprising one or more junction barrier diodes (59) and / or Schottky diodes in the active area (54) at the first surface (53a).

10. 3. An electronic device according to claim 1 or 2, selected from the group consisting of Schottky diodes, PiN diodes, PN diodes, MPS devices, JBS diodes, MOSFETs, IGBTs, and power devices.

11. A method of manufacturing an electronic device (50, 100), comprising: forming a first insulating layer (61) of a first material having electrical insulating or dielectric properties on a first surface (53a) of a silicon carbide semiconductor body (53); forming a first layer of metallic material (58) partially on the first surface (53a) of the semiconductor body (53) and partially on the first insulating layer (61); forming an interface layer (63) of a second material different from the first material over the first layer of metal material (58) and over the first insulating layer (61); forming a passivation layer (69) of said first material on said interface layer (63); A method having the following.

12. 12. The method of claim 11, wherein the first material is silicon oxide or TEOS.

13. 13. The method of claim 11 or 12, wherein the second material is silicon carbide.

14. 13. The method of claim 11 or 12, further comprising forming a second insulating layer (64) over the first insulating layer (61) and over the first layer of metallic material (58), and wherein the step of forming the interface layer (63) comprises forming the interface layer (63) on the second insulating layer (64).

15. The method of claim 14, wherein the second insulating layer (64) comprises the first material.

16. 13. The method of claim 11 or 12, further comprising forming an active area (54), wherein the first layer of metal material (58) is formed in the active area (54) at least partially overlapping and in electrical contact with the first surface (53a) of the semiconductor body.

17. 17. The method of claim 16, further comprising the step of implanting a dopant species having a conductivity type opposite to that of the semiconductor body at the first surface (53 a) and at least partially surrounding the active area (54) into the semiconductor body, thereby forming an edge termination region (60), and wherein the first insulating layer (61) is formed on the first surface (53 a) at a distance from the active area (54) and at least partially overlapping the edge termination region (60).

18. 17. The method of claim 16, further comprising forming a second layer of metallic material (57) on a second surface (53b) of the semiconductor body (53) opposite the first surface (53a), wherein the first layer of metallic material (58) and the second layer of metallic material (57) form respective electrically conductive terminals of the electronic device (50, 100).

19. 17. The method of claim 16, further comprising forming one or more junction barrier diodes (59) and / or Schottky diodes in the active area (54) at the first surface (53a).

20. 13. The method of claim 11 or 12, wherein the electronic device is selected from the group consisting of a Schottky diode, a PiN diode, a PN diode, an MPS device, a JBS diode, a MOSFET, an IGBT, and a power device.

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