METHOD FOR MANUFACTURING ANCHORING ELEMENT OF SiC-BASED ELECTRONIC DEVICE, ANCHORING ELEMENT, AND ELECTRONIC DEVICE

Abstract

To provide a highly reliable silicon carbide (SiC) electronic power device, a method for manufacturing an anchoring element of the same, and an anchoring element.SOLUTION: An electronic device 50 includes: a semiconductor body 53 of silicon carbide; an insulating layer 61 on a surface 53a of the semiconductor body 53; a layer of a metal material 58 extending in part on the surface 53a of the semiconductor body 53 and in part on the insulating layer 61; a SiN interface layer 63 on the layer of a metal material 58 and the insulating layer 61; a passivation layer 69 on the interface layer 63; and an anchoring element 82. The anchoring element 82 protrudes from the passivation layer 69 towards the first insulating layer 61 and extends in the first insulating layer 61 underneath the interface layer 63.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a method for manufacturing an anchor element of an electronic device, an anchor element, and an electronic device including the anchor element. In particular, the present invention relates to an anchor element designed to improve the reliability of silicon carbide (SiC) electronic power devices when high voltages are expected under operating conditions and difficulties in trench formation are required.

Background Art

[0002] The semiconductor industry has shown significant interest in silicon carbide (SiC), particularly for the manufacture of electronic components such as diodes or transistors, especially for power applications.

[0003] In its various polytypes (e.g., 3C-SiC, 4H-SiC, 6H-SiC), electronic devices formed within silicon carbide have a number of advantages such as low on-state output resistance, low leakage current, resistance to high operating temperatures, and high operating frequencies.

[0004] However, the development and manufacture of SiC-based electronic devices are limited by factors such as the electrical and mechanical properties of the passivation layer (which is included within these devices and, for example, extends over the semiconductor body of the SiC of the electronic device). In particular, it is known to manufacture the passivation layer using a polymeric material (e.g., polyimide) that can withstand the high operating temperatures of the electronic device and has a high dielectric strength, for example, even higher than 400 kV / mm. Specifically, the high dielectric strength of the polymeric material ensures that the passivation layer can withstand a high electric field and thus withstand a high potential difference across them without generating electrical breakdown and without becoming electrically conductive.

[0005] ​However, polymer materials have a high coefficient of thermal expansion (CTE) (for example, in the case of polybenzobisoxazole substances or PIX, CTE = 43e). ―6 1 / K), and this means that the passivation layer has an even lower coefficient of thermal expansion (CTE = 3.8e -6 1 / K) Causes adhesion problems to SiC.

[0006] In particular, adhesion problems between the passivation layer and SiC may occur during thermal cycling tests (e.g., between approximately -50°C and approximately +150°C) or during the period of use of electronic devices when they are exposed to high thermal swings (e.g., operating temperature differences equal to or greater than approximately 200°C). Due to the large difference in CTE between the passivation layer and SiC, these high thermal swings generate mechanical stress at the interface between the passivation layer and SiC, which may cause (at least partial) delamination of the passivation layer relative to the SiC semiconductor body.

[0007] If this delamination is sufficiently extensive (for example, if no portion of the passivation layer is interposed between two metallizations of an electronic device set to different potentials, and they are separated from each other only by air), electrical discharge may occur at the interface, potentially damaging the electronic device itself. In particular, when the electronic device is used under reverse bias conditions, the risk of damage to the electronic device increases because the voltage difference it must withstand is high (e.g., much higher than 1000V).

[0008] Known solutions to this problem include using multiple dielectric layers made of different materials (e.g., silicon nitride, silicon oxide, and polyimide in a continuous pattern) to form a passivation multilayer designed to limit mechanical stress at the interface with the SiC semiconductor body.

[0009] Figure 1 shows a cross-sectional view of a portion of a known type of electronic device (here, as an example, a JBS or junction barrier Schottky diode) 1 in a Cartesian coordinate system consisting of axes X, Y, and Z (3 axes).

[0010] The JBS apparatus 1 has a semiconductor body 3 made of N-type SiC having a surface 3a and an opposite surface 3b. The semiconductor body includes, for example, a substrate and one or more regions epitaxially grown on the substrate, which are N-type and have respective doping concentration values. The JBS apparatus 1 further has a plurality of junction barrier (JB) elements 9 in the semiconductor body 3, each of which faces the upper surface 3a and each of which includes a P-type injection region within the semiconductor body 3, and ohmic contacts are formed on the injection region at the level of the upper surface 3a of the semiconductor body 3. The JBS apparatus 1 further has a first metallization 8 which extends on the upper surface 3a and is in electrical contact with the junction barrier elements 9 via their respective ohmic contacts. The JBS apparatus 1 further has an end-termination region 10 (or protective ring), which is in particular a P-type injection region that completely surrounds the JB elements 9.

[0011] A Schottky diode 12 is formed at the interface between the anode metallization 8 and the semiconductor body 3, where a semiconductor-metal Schottky junction is formed. The region of the MPS apparatus 1 that includes the JB element 9 and the Schottky diode 12 (i.e., the region confined within the protective ring 10) is the active region 4 of the JBS apparatus 1.

[0012] The JBS device 1 further incorporates a second metallization 6, which extends over the bottom surface 3b. The first and second metallizations 8 and 6 form electrical anode and cathode terminals, respectively, which can be biased during the use of the JBS device 1.

[0013] An electrically passive region 16 extends outside the end-terminal region 10.

[0014] An insulating layer 18, made of an insulating or dielectric material, particularly silicon oxide (SiO2), extends partially over the edge region 10.

[0015] The first metallization 8 is in electrical contact with a portion of the end-terminal region 10 that is not covered by the insulating layer 18, and also extends partially onto the insulating layer 18. Here, an interface layer 20 made of silicon nitride (SiN) extends over the first metallization 8 and the insulating layer 18. Furthermore, the JBS apparatus 1 has a passivation layer 22, which is made of polyimide in particular and extends over the interface layer 20. That is, the interface layer 20 acts as an interface between the passivation layer 22 and the layer below it, in this case between the first metallization 8 and the insulating layer 18. The interface layer 20 can be omitted, but the inventors have found that the interface layer 20 improves the adhesion of the passivation layer 22 to the layer below it.

[0016] A protective layer 24 made of a resin such as bakelite extends over the passivation layer 22, protecting the JBS device 1 when it is inserted into a package (not shown).

[0017] However, as mentioned above, even if the interface layer 20 improves adhesion to the layer beneath the passivation layer 22, certain critical conditions in the use of the JBS apparatus 1 or in thermal or thermomechanical testing may cause delamination or partial delamination of the passivation layer 22 from the interface layer 20 (due to stress generated by the test). This occurs particularly under stress conditions generated by high temperatures used (e.g., exceeding 150°C). Such effects not only make the JBS apparatus 1 structurally brittle but can also cause unwanted electrical discharges that affect the electrical operation of the JBS apparatus 1. In fact, the inventors have found that under certain thermomechanical or mechanical stress conditions following the assembly process, the interface layer 20 has one or more localized cracks that penetrate its thickness, which cause these electrical discharges in the first metal layer 8. Such problems are more apparent when the electronic device 1 is exposed to high thermal swings or high voltage differences under reverse bias conditions. [Overview of the Initiative] [Problems that the invention aims to solve]

[0018] Therefore, there is a need to resolve the problems mentioned above. [Means for solving the problem]

[0019] According to the present invention, a method for manufacturing an anchor element for an electronic device, an anchor element, and an electronic device comprising the anchor element are provided as defined in the claims. To better understand the present invention, preferred embodiments as purely non-limiting examples are described below with reference to the accompanying drawings. [Brief explanation of the drawing]

[0020] [Figure 1] A cross-sectional view illustrating a known type of electronic device. [Figure 2]Cross-sectional view illustrating an electronic device based on one embodiment of the present invention. [Figure 3A] Planar view showing the electronic device of FIG. 2 based on one embodiment of the present invention. [Figure 3B] Planar view showing the electronic device of FIG. 2 based on another embodiment of the present invention. [Figure 4] Cross-sectional view illustrating a part of an electronic device based on a further embodiment of the present invention. [Figure 5A] Cross-sectional view showing a state restricted to the manufacture of an anchor device, which is a certain step in manufacturing the electronic device of FIG. 2 based on one embodiment of the present invention. [Figure 5B] Cross-sectional view showing a state restricted to the manufacture of an anchor device, which is another step in manufacturing the electronic device of FIG. 2 based on one embodiment of the present invention. [Figure 5C] Cross-sectional view showing a state restricted to the manufacture of an anchor device, which is yet another step in manufacturing the electronic device of FIG. 2 based on one embodiment of the present invention. [Figure 6] Cross-sectional view illustrating an electronic device based on a further embodiment of the present invention. [Figure 7A] Cross-sectional view showing a state restricted to the manufacture of an anchor device, which is a certain step in manufacturing the electronic device of FIG. 6 based on one embodiment of the present invention. [Figure 7B] Cross-sectional view showing a state restricted to the manufacture of an anchor device, which is another step in manufacturing the electronic device of FIG. 6 based on one embodiment of the present invention. [Figure 7C] Cross-sectional view showing a state restricted to the manufacture of an anchor device, which is yet another step in manufacturing the electronic device of FIG. 6 based on one embodiment of the present invention. [Figure 7D] Cross-sectional view showing a state restricted to the manufacture of an anchor device, which is yet another step in manufacturing the electronic device of FIG. 6 based on one embodiment of the present invention.

Mode for Carrying Out the Invention

[0021] Figure 2 is a cross-sectional view illustrating an electronic device 50 based on one aspect of the present invention in a Cartesian coordinate system consisting of axes X, Y, and Z, similar to Figure 1. In particular, the device 50 is a JBS diode, which is similar to the one described with reference to Figure 1. However, the present invention is not limited to this device and is particularly applicable to other types of electronic devices, such as power devices, including MOSFETs, IGBTs, MPSs, Schottky diodes, PN diodes, and PiN diodes.

[0022] The electronic device 50 includes the elements described below, illustrated with reference to Figure 2.

[0023] A semiconductor body 53 made of N-type or P-type (hereinafter, only N-type will be referred to as an unrestricted example) SiC (for example, comprising a substrate 53' and optionally one or more epitaxial layers 53'' grown thereon) has a front (upper) surface 53a and a rear (bottom) surface 53b opposite to it, along the direction of axis Z. In the example illustrated in Figure 2, the semiconductor body 53 has a substrate 53' on which an epitaxial layer 53'' is grown, which functions as a drift layer of the electronic device 50, and both are made of N-type SiC (in particular 4H-SiC, but not limited to these; other polytypes such as 2H-SiC, 3C-SiC, 6H-SiC, etc. can also be used). For example, the substrate 53' is 1 × 10 19 at / cm 3 and 1 x 10 22 at / cm 3 The dopant layer has a concentration of N-type dopant between 5 μm and 5 μm, and has a thickness particularly equal to about 360 μm between 300 μm and 450 μm measured along axis Z between surfaces 53a and 53b. The drift layer 53" has a dopant concentration lower than that of the substrate and a thickness, for example, between 5 μm and 15 μm.

[0024] An ohmic contact layer 56 (for example, made of nickel silicide) extends over the rear surface 53b, and a metallization 57, in this example cathode metallization, made of, for example, Ti / NiV / Ag or Ti / NiV / Au, extends over the ohmic contact region 56.

[0025] One or more P-type doped regions 59' extend within the semiconductor body 53 (particularly within the drift layer), facing the front surface 53a, and each doped region 59' accommodates its respective ohmic contact (not shown, but of a known type) such that each doped region 59' forms its respective junction barrier (JB) element 59. End-termination regions 60, i.e., protective rings, particularly further P-type doped regions, extend within the drift layer, facing the front surface 53a, and completely enclose the JB elements 59 (in the plan view, on the plane XY defined by axes X and Y). The end-termination regions 60 are optional.

[0026] An insulating layer 61 (made of an insulating or dielectric material, such as silicon oxide or TEOS) extends over the upper surface 53a such that it completely surrounds the JB element 59 (in plane XY) and partially overlaps the protective ring 60 (if present).

[0027] Metallization 58, in this example, an anode metallization consisting of Ti / AlSiCu or Ni / AlSiCu, extends over a portion of the upper surface 53a, which is partitioned on the outside by the insulating layer 61 (i.e., in the JB element 59 / active region 54), and partially over the insulating layer 61.

[0028] A passivation layer 69 made of a polymer material such as polyimide (e.g., PIX) extends over the anode metallization layer 58 and the insulating layer 61.

[0029] Here, an interface layer 63 made of silicon nitride (SiN) extends over the anode metallization layer 58 and the insulating layer 61, and under the passivation layer 69. In other words, the interface layer 63 acts as an interface between the passivation layer 69 and the layer below it, in this case the metallization layer 58 and the insulating layer 61, and also improves the adhesion of the passivation layer 69 located above it.

[0030] Next to the doped region 59', one or more Schottky diodes 62 are formed at the interface between the semiconductor body 53 and the anode metallization 58. In particular, the (semiconductor-metal) Schottky junction is formed by each portion of the semiconductor layer 53 that is in direct electrical contact with each portion of the anode metallization 58.

[0031] Furthermore, each ohmic contact extending within each doped region 59' provides an electrical connection having an electrical resistance value even lower than the electrical resistance value of the doped region 59' that houses it. Thus, the JB element 59 is a PiN diode.

[0032] The region of the electronic device 50 that includes the JB element 59 and the Schottky diode 62 (i.e., the region partitioned by the protective ring 60) is the active region 54 of the electronic device 50.

[0033] Outside the active region 54, i.e., beyond the end-termination region 60, exists the side surface 53c of the semiconductor body 53, which extends substantially perpendicular to the upper surface 53a, for example. The side surface 53c is formed following a dicing or individualization step of the SiC wafer, in which multiple electronic devices 50 are obtained. The dicing step has the function of separating one electronic device 50 from another device 50 from the same wafer. Dicing is performed along a scribe line (not shown) of the SiC wafer from which the electronic devices 50 are obtained. This scribe line surrounds the active region 54, the protective ring 60, and the insulating layer 61 at a certain distance in plane XY.

[0034] For example, a protective layer 74 made of a resin such as bakelite extends over the passivation layer 69, protecting the electronic device 50 when it is inserted into a package (not shown).

[0035] According to one aspect of the present invention, the passivation layer 69 has an anchor element 82 that protrudes from the passivation layer 69 (particularly along the direction of axis Z) and extends within the insulating layer 61 until it reaches the upper surface 53a of the semiconductor body 53. The anchor element 82 anchors and fixes the passivation layer 69 to the insulating layer 61. The anchor element 82 is integral with the passivation layer 69 and, in particular, is an extension of the passivation layer itself. Thus, the anchor element 82 extends from the passivation layer without interruption or interface and is made of the same material as the passivation layer. That is, the anchor element 82 and the passivation layer 69 form a single, or monolithic, structure.

[0036] The anchor element 82 is formed outside the active area 54, and in particular outside the end-terminal region 60; that is, the anchor element 82 is interposed between the end-terminal region 60 and the side surface 53c. If the end-terminal region 60 is absent, the anchor element 82 is formed outside the active area 54, that is, between the active area 54 and the side surface 53c in the electrically passive region of the device.

[0037] The anchor element 82 is patterned to fix the passivation layer 69 to the insulating layer 61 and is configured to prevent and / or block the peeling and / or detachment of the passivation layer 69.

[0038] In particular, the anchor element 82 is inserted, housed, and positioned within a housing or cavity extending within the insulating layer 61 such that it bonds the passivation layer 69 to the insulating layer 61 and integrates them together. The cavity housing the anchor element 82 has a shape complementary to the shape of the anchor element 82. That is, the anchor element 82 completely fills the cavity housing it.

[0039] In one embodiment, the anchor element 82 is measured along axis X, which increases as the distance from the passivation layer 69 (along axis Z) increases, and has the dimensions shown in the cross-sectional view of Figure 2.

[0040] In another embodiment, the anchor element 82 has a first dimension in the opening 84, measured along axis X and shown in the cross-sectional view of Figure 2, which coincides with the aforementioned diameter d1 of the opening 84. The anchor element 82 further has a second dimension in the insulating layer 61, measured along axis X and shown in the cross-sectional view of Figure 2. This second dimension is even larger than the first dimension (for example, twice as large, i.e., 2d1, but not limited to this). Within the insulating layer 61, the anchor element 82 is variable, but in any case, it can have any geometric shape selected at the design stage, with a dimension even larger than the aforementioned first dimension d1 in the opening 84 (again measured along axis X and considered in the cross-sectional view of Figure 2).

[0041] Within the insulating layer 61, the anchor element 82 may have, in addition to or alternative to, the dimensions along X described above, further dimensions measured along axis Y that are larger than the corresponding dimensions of the opening 84 (again, measured along axis Y).

[0042] Thus, since the anchor element 82 extends below the opening 84 and has at least one dimension in plane XY that is larger than the corresponding dimension in plane XY of the opening 84, the anchor element 82 serves to fix the passivation layer 69, which is restricted from moving along axis Z and therefore prevents any peeling or detachment.

[0043] In further embodiments, within the insulating layer 61, the anchor element 82 locally has dimensions equal to or smaller than the first dimension described above, but in any case, it is possible to have at least a portion having dimensions larger than the first dimension described above.

[0044] In the example shown in Figure 2, the portion of the anchor element 82 extending within the insulating layer 61 has a trapezoidal shape (along the axis X and in the cross-sectional view), with its large diameter portion directly facing the interface layer 63 and its small diameter portion in contact with the upper surface 53a of the semiconductor body. In further embodiments not shown, the portion of the anchor element 82 extending within the insulating layer 61 has a rectangular or roughly polygonal shape, or an elliptical shape, or a roughly curved or curved shape (along the axis X and in the cross-sectional view).

[0045] In a further embodiment, the anchor element 82 does not extend through the thickness of the insulating layer 61, but terminates within the insulating layer 61 at a certain distance from the upper surface 53a of the semiconductor body. In this case as well, its shape and dimensions can be selected in the same manner as described above.

[0046] Figures 3A and 3B schematically show the electronic device 50 in a plan view (in plane XY) based on each embodiment.

[0047] Referring to Figure 3A, the anchor element 82 extends in plane XY so as to completely enclose the anode metallization 58. In the view of plane XY in Figure 3A, the anchor element 82 defines an annular and closed polygonal shape, and more specifically, a square shape with rounded corners (other different shapes such as circular shapes are also possible, and it can also be a rectangular shape, a roughly polygonal shape, or an irregular shape).

[0048] Referring to Figure 3B, the electronic device 50 has multiple anchor elements (all of which are similar to the anchor elements 82 described earlier and are therefore shown with the same reference number). The anchor elements 82 extend at a certain distance from each other on the upper surface 53a, and at a certain distance from each other on each portion of the upper surface 53a. For example, the arrangement in plane XY of Figure 3B shows four anchor elements 82 arranged around the anode metallization 58 so as to be at equal angular distances with respect to the anode metallization 58, and more specifically, at the corners of an ideal square geometric shape. However, other arrangements are also possible.

[0049] As is obvious, in alternative embodiments to that of Figure 2, it is possible to set two or more anchor elements 82 side by side. For example, as illustrated in Figure 4 (where only a part of an electronic device similar to the electronic device 50 is shown), two anchor elements 82 extend within the insulating layer 61 at a distance from each other along axis X equal to a few microns or tens of microns, for example, between 5 μm and 20 μm. One, some, or all of these multiple anchor elements 82 either extend through the thickness of the insulating layer 61 (along Z) or partially extend within the insulating layer 61 and terminate within the insulating layer 61 without reaching the upper surface 53a.

[0050] The steps for manufacturing the electronic device 50 shown in Figure 2 (which are also applicable to the embodiment in Figure 4) will be described below with reference to Figures 5A-5C, and limited to the step of forming the anchor element 82. Figures 5A-5C are shown in the same three-axis system as in Figure 2.

[0051] Referring to Figure 5A, a wafer is provided which contains a SiC semiconductor body 53 that constitutes the aforementioned electronic device 50 (further explanation omitted) and has undergone a manufacturing step to form elements with the same reference number.

[0052] The interface layer 63 is selectively etched to form an opening 84. For this purpose, for example, a photoresist mask is provided, and the opening 84 having the aforementioned shape, dimensions, and position is formed by lithography and etching steps that are known in themselves. The opening 84 extends through the thickness of the interface layer 63, exposing each surface portion of the insulating layer 61.

[0053] Next, referring to Figure 5B, etching of the insulating layer 61 is performed through the previously formed opening 84. If the etching is, for example, a wet type etching and uses an etching chemical that is selective to the material of the insulating layer 61 (e.g., hydrofluoric acid in the case of silicon oxide) and therefore does not remove the interface layer 63, then the etching can be performed without a further etching mask. In this case, the interface layer 63 forms the etching mask. Otherwise, a mask similar to the one used in the step of forming the opening 84 can be used.

[0054] The etching of the insulating layer 61 is isotropic, removing the insulating layer material both vertically (along the Z axis) and horizontally (in the XY plane) beneath the interface layer 63. The etching is interrupted according to a shape desired to be applied to the anchor element 82, for example, a timed etch. In the embodiment shown in Figure 5B, the etching proceeds until the upper surface 53a of the semiconductor body 53 is exposed. As previously mentioned, the etching also proceeds laterally (along the X axis). Thus, a cavity 86 is formed in the insulating layer 61.

[0055] Next, referring to Figure 5C, a passivation layer 69 is formed. A polymer material, which is either liquid or semi-liquid, is applied to the wafer and distributed onto the interface layer 63 via spinning. During this process, the polymer material penetrates through the openings 84 and completely fills both the cavity 86 and the openings 84. Then, heat treatment is performed until the polymer material hardens to form the passivation layer 69 (curing process), and simultaneously, the anchor elements 82. The polymer material is, for example, polyimide.

[0056] The manufacturing process then continues with subsequent steps to form further elements of the electronic device 50 (e.g., an ohmic contact layer 56 and cathode metallization 57), which will not be described in detail.

[0057] Figure 6 illustrates an electronic device 100 based on a further embodiment of the present invention. The electronic device 100 is represented in the same (three-axis) Cartesian coordinate system consisting of axes X, Y, and Z as in Figures 1 and 2. In particular, the electronic device 100 is a JBS diode similar to those described with reference to Figures 1 and 2. However, even in this case, the present invention is not limited to JBS devices and is applicable to other types of electronic devices, in particular power devices such as MOSFETs, IGBTs, Schottky diodes, PN diodes, and PiN diodes.

[0058] The elements of electronic device 100, which are common to electronic device 50 in Figure 2, are given the same reference numbers, and further explanation is omitted.

[0059] In particular, the electronic device 100 includes, in addition to what has been described for the electronic device 50, a further insulating layer 102 made of a dielectric or insulating material such as silicon oxide. In particular, the material of the insulating layer 102 is the same as that used for the insulating layer 61. The insulating layer 102 has a thickness of, for example, between 0.5 μm and 2 μm along axis Z.

[0060] The insulating layer 102 extends laterally relative to the anode metallization 58 on the anode metallization 58 and the insulating layer 61.

[0061] The interface layer 63 is optional and, if present, extends over the insulating layer 102. The passivation layer 69 extends over and in contact with the interface layer 63, if present. Alternatively, the passivation layer 69 extends over and in contact with the insulating layer 102.

[0062] In the embodiment shown in Figure 6, the passivation layer 69 has an anchor element 82, similar to the embodiment in Figure 2, which protrudes from the passivation layer 69 (particularly along the direction of axis Z). However, in this case, the anchor element 82 extends entirely within the insulating layer 102 (i.e., through the thickness of the insulating layer 102 along Z) and partially within the insulating layer 61 (terminating within the insulating layer 61), and does not reach the upper surface 53a of the semiconductor body 53. The anchor element 82 anchors and fixes the passivation layer 69 to both the insulating layer 102 and the insulating layer 61. The anchor element 82 is integral with the passivation layer 69 and, in particular, is an extension of the passivation layer itself. The anchor element 82 thus extends from the passivation layer without interruption and interface and is made of the same material as the passivation layer. In other words, the anchor element 82 and the passivation layer 69 form a single, or monolithic, body.

[0063] If an interface layer 63 is present, the anchor element 82 extends through an opening 84 formed via the interface layer 63. The opening 84 has a diameter d1 equal to several microns, for example, between 2 μm and 5 μm, and has a shape that can be freely selected during the design stage, such as a circular, elliptical, or polygonal shape.

[0064] The anchor element 82 is formed outside the active area 54, and particularly outside the end-terminal area 60, at a certain distance from the anode metallization 58. That is, the anchor element 82 is interposed between the end-terminal area 60 and the side surface 53c. If the end-terminal area 60 is not present, the anchor element 82 is formed outside the active area 54, i.e., between the active area 54 and the side surface 53c in the electrically passive area of ​​the device, at a certain distance from the anode metallization 58.

[0065] In particular, the anchor element 82 is inserted, housed, and positioned within a housing or cavity extending into the insulating layer 102 and insulating layer 61 in order to bond the passivation layer 69 and the insulating layer 102 together and integrate them into one unit. The cavity housing the anchor element 82 has a shape complementary to the shape of the anchor element 83. That is, the anchor element 82 completely fills the cavity housing it.

[0066] The anchor element 82 has the dimensions already described with reference to Figure 2, so that description will be omitted here.

[0067] In a further embodiment not shown, the anchor element 82 extends exclusively (partially or completely) within the insulating layer 102 (and thus terminates within the insulating layer 102 or at the interface between the insulating layer 102 and the insulating layer 61 below it).

[0068] In a further embodiment not shown, the anchor element 82 extends through the thickness of the insulating layer 102 and through the thickness of the insulating layer 61.

[0069] In further embodiments not shown, it is possible to have multiple anchor elements 82, similar to those described with reference to Figure 4. One, some, or all of these multiple anchor elements 82 extend exclusively within the insulating layer 102 (but not the insulating layer 61), or through the thickness of the insulating layer 102 and through the thickness of the insulating layer 61, or through the thickness of the insulating layer 102 and partially within the insulating layer 61.

[0070] In the embodiment shown in Figure 6, the insulating layer 102 has the function of forming a further interface between the interface layer 63 and the anode metallization 58 in order to obtain electrical insulation in the anode metallization 58 when a crack occurs in the interface layer 63.

[0071] Figures 7A-7D show the steps for manufacturing the electronic device 100 of Figure 6, limited to the step of forming the anchor element 82. Figures 7A-7D are represented in the same triaxial system as Figure 6.

[0072] Referring to Figure 7A, a wafer is provided which contains SiC semiconductor bodies 53 after the manufacturing steps for forming each element of the electronic device 100, as previously described (and therefore omitted here) and assigned the same reference numerals.

[0073] Referring to Figure 7A, after forming the insulating layer 61 and the anode metallization, an insulating or dielectric material deposition step is performed to form the insulating layer 102. This step is performed, for example, by a CVD process. The insulating layer 102 is formed on the entire surface of the wafer and, in particular, completely covers the anode metallization 50 and the insulating layer 61.

[0074] Next, after forming the insulating layer 102, an interface layer 63 is formed, for example, by depositing a CVD-type silicon nitride. The interface layer 63 is formed on the entire surface of the wafer and, in particular, completely covers the insulating layer 102.

[0075] Next, referring to Figure 7B, the interface layer 63 is selectively etched to form an opening 84. For this purpose, for example, a photoresist mask is supplied, and the opening 84 having the aforementioned shape, dimensions, and position is formed by lithographic and etching steps known to themselves. The opening 84 extends through the thickness of the interface layer 63, exposing each surface portion of the insulating layer 102.

[0076] Next, referring to Figure 7C, etching of the insulating layer 102 is performed through the previously formed opening 84. If this etching is of the wet type and uses an etching chemical that is selective with respect to the material of the insulating layer 102 and therefore does not remove the interface layer 63 (for example, hydrofluoric acid in the case of silicon oxide), this etching can be performed in the absence of a mask. Otherwise, a mask similar to the one used in the step of forming the opening 84 can be used.

[0077] The etching of the insulating layer 102 is isotropic, and the material of the insulating layer 102 is removed both vertically (along the Z axis) and horizontally (in plane X and Y) beneath the interface layer 63. The etching is a timed etch, selected according to the type of shape desired to be given to the anchor element 82, for example. In the embodiment of Figure 7C, the etching proceeds until the insulating layer 102 is completely removed and also with partial removal of the material of the underlying insulating layer 61. If it is possible to etch the material of insulating layer 102 and the material of insulating layer 61 using the same etching chemical, the removal of portions of insulating layer 102 and insulating layer 61 is performed during the same etching step period. Otherwise, after removing the desired portion of insulating layer 102, the etching chemical is changed to remove the desired portion of insulating layer 61. As mentioned above, in both insulating layer 102 and insulating layer 61, the etching also proceeds laterally (along the axis x axis). Thus, cavities 86 are formed within insulating layers 102 and 61.

[0078] Next, referring to Figure 7D, a passivation layer 69 is formed. A polymer material, which is liquid or semi-liquid, is applied to the wafer and distributed onto the interface layer 63 by spinning. During this process, the polymer material penetrates through the openings 84 and completely fills both the cavity 86 and the openings 84. Then, a heat treatment is performed so that the polymer material hardens to form the passivation layer 69 (curing process) and simultaneously forms the anchor elements 82. The polymer material is, for example, polyimide.

[0079] Next, although a detailed explanation is omitted here, subsequent steps are carried out to form various other elements of the electronic device 100 (for example, the ohmic contact layer 56 and the cathode metallization 57).

[0080] The advantages obtained by the present invention are clear from examining the features of the present invention based on the disclosures made in accordance with the present invention.

[0081] In particular, the anchor element 82 ensures the adhesion of the passivation layer 69 and prevents delamination. Therefore, it is possible to obtain the passivation layer 69 using a polymer material, thereby ensuring the high electrical performance of the electronic devices 50,100 (due to the high dielectric strength of the passivation layer 69) and simultaneously eliminating structural problems linked to the potential delamination of the passivation layer 69 (e.g., due to thermal cycling or the use of the electronic devices 50,100).

[0082] As a result, the risk of damage to the electronic devices 50,100 due to electrical discharge between metallizations set to different potentials (for example, between equipotential rings, i.e., EQR metallization and anode metallization 58) is prevented, and thus the reliability of the electronic devices 50,100 is increased, especially when exposed to high thermal swings and operating under reverse bias conditions.

[0083] The manufacturing steps described with reference to Figures 5A-5C and 7A-7D enable the acquisition of electronic devices 50 and 100, each containing an anchor element 82, starting from a SiC wafer. The etching performed with reference to Figures 5B-5C and 7B-7D is isotropic, which allows for patterning to form cavities and enables the formation of the anchor elements 82 without limitations arising from an anisotropic etching process or from the crystal orientation of the SiC wafer from which the electronic devices 50 and 100 are obtained.

[0084] Although specific embodiments of the present invention have been described in detail above, the present invention should not be limited to these specific embodiments, and it is of course possible to make various modifications without departing from the technical scope of the present invention.

Claims

1. A method for manufacturing an anchor element (82) of a passivation layer (69) of an electronic device (50; 100), comprising: forming a first insulating layer (61) of a first material on a surface (53a) of a semiconductor body (53) of silicon carbide; forming a layer (58) of metallic material partially on the surface (53a) of the semiconductor body (53) and partially on the first insulating layer (61); forming an interface layer (63) of a second material different from the first material on the layer (58) of metallic material and on the first insulating layer (61); removing a selective portion of the interface layer (63) at a distance from the layer of metallic material (58) to form an opening (84) through the interface layer (63) and expose the first insulating layer (61); removing selective portions of the first insulating layer (61) through the opening (84) to form a cavity (86) in the first insulating layer (61) at and below the opening (84) and having at least one dimension (d1) in a direction parallel to the surface (53a) that is greater than a corresponding dimension of the opening (84); and simultaneously providing a passivation material on the first insulating layer (61), in the opening (84), and in the cavity (86), the passivation material forming the passivation layer (69) on the first insulating layer (61) and the anchor element (82) in the opening (84) and in the cavity (86); The method has the following features:

2. 2. The method of claim 1, wherein the step of applying the passivation material comprises applying the passivation material in a liquid or semi-liquid form such that the passivation material fills the cavity (86).

3. 3. The method of claim 1, wherein the step of applying the passivation material comprises performing a step of spinning the passivation material.

4. 3. The method of claim 2, further comprising the step of solidifying or curing the passivation material such that the anchor element (82) and the passivation layer (69) form a unitary or monolithic body.

5. 3. The method of claim 1, wherein removing selective portions of the first insulating layer (61) comprises performing an isotropic etch of the first insulating layer (61).

6. 3. The method of claim 1 or 2, wherein the interface layer (63) is configured to promote adhesion of the passivation layer (69) to the insulating layer (61).

7. 3. The method of claim 1, wherein forming the anchor element (82) in the opening (84) and in the cavity (86) comprises confining the anchor element (82) below the interface layer (63) and within the first insulating layer (61).

8. 3. The method of claim 1, wherein forming the openings (84) includes forming an etching mask for the first insulating layer (61), and wherein the step of removing selective portions of the first insulating layer (61) through the openings (84) includes performing a wet etch of the first insulating layer (61).

9. 3. The method of claim 1 or 2, wherein the cavity (86) has a volume greater than the volume of the opening (84).

10. 3. The method of claim 1 or 2, wherein the passivation material (69) comprises a polymeric material.

11. 3. The method of claim 1 or 2, wherein the material of the interface layer is silicon nitride.

12. The step of forming the cavity (86) comprises: forming the cavity (86) through the thickness of the first insulating layer (61); or forming the cavity (86) through a portion of the thickness of the first insulating layer (61) and terminating within the first insulating layer (61); 3. The method of claim 1 or 2, comprising:

13. 3. The method of claim 1 or 2, further comprising forming a second insulating layer (102) on the first insulating layer (61) and on the layer of metallic material (58) below the interface layer (63).

14. The step of forming the cavity (86) further comprises: forming the cavity (86) solely in the second insulating layer (102); or forming the cavity (86) through the second insulating layer (61) and partially through the first insulating layer (61) and terminating within the first insulating layer (61); or forming the cavity (86) through the second insulating layer (102) and the first insulating layer (61); 14. The method of claim 13, comprising:

15. 14. The method of claim 13, wherein the second insulating layer (102) is made of the same material as the first insulating layer (61).

16. 3. The method of claim 1 or 2, wherein the anchor element (62) is formed in an electrically passive area of ​​the electronic device at a distance from the layer of metallic material (58).

17. In an anchor element (82) of a passivation layer (69) of an electronic device (50; 100), An anchor element is arranged below an interface layer (63) on a surface (53a) of a silicon carbide semiconductor body (53), and has a protrusion starting from the passivation layer (69), penetrating the interface layer (63) and extending at least partially through an insulating structure (61; 61, 102), said protrusion terminating in the insulating structure and forming a single or monolithic body with the passivation layer (69).

18. a first portion extending within the interface layer (63) at a first distance from the surface (53a) and having a maximum dimension with a first value (d1) in a direction parallel to a first axis (X; Y) parallel to the surface (53a); a second portion extending within the insulating structure in structural continuity with the first portion and having a respective maximum dimension in a direction parallel to the first axis (X; Y) having a second value greater than the first value (d1); 18. The anchor element of claim 17, comprising:

19. 19. An anchor element according to claim 18, wherein the second portion of the anchor element extends partially within or through the insulating construction (61, 102).

20. Anchoring element according to any one of claims 17 to 19, wherein the passivation layer (69) comprises a polymer material.

21. Anchoring element according to any one of claims 17 to 19, extending within an electrically passive area of ​​the electronic device (50; 100).

22. In an electronic device (50; 100), a semiconductor body (53) of silicon carbide; a first insulating layer (61; 102) made of a first material on one surface (53a) of the semiconductor body (53); a layer (58) of metallic material extending partially over the surface (53a) of the semiconductor body (53) and partially over the first insulating layer (61); an interface layer (63) made of a second material different from the first material and on the first insulating layer (61) and the layer of metallic material (58); a passivation layer (69) on the interface layer (63), and an anchor element (82) protruding from the passivation layer (69) toward the first insulating layer (61; 102) and extending through an opening (84) in the interface layer (63) and terminating within the first insulating layer (61; 102), the anchor element (82) having at least one dimension (d1) in a direction parallel to the surface (53a) that is greater than a corresponding dimension of the opening (84); An electronic device having:

23. 23. The electronic device of claim 22, wherein the anchor element (82) and the passivation layer (69) form a single or monolithic body.

24. 24. An electronic device according to claim 22 or 23, wherein the interface layer (63) is configured to promote adhesion of the passivation layer (69) to the insulating layer (61).

25. 24. The electronic device of claim 22 or 23, wherein the anchor element (82) is configured to constrain the passivation layer (69) beneath the interface layer (63) and within the first insulating layer (61).

26. The anchor element (82) a first portion extending into the insulating structure at a first distance from the surface (53a) and having a maximum dimension with a first value (d1) in a direction parallel to a first axis (X; Y) parallel to the surface (53a); and a second portion extending within the insulating structure in a structural continuation of the first portion and having a respective maximum dimension in a direction parallel to the first axis (X; Y) having a second value greater than the first value (d1); 24. The electronic device according to claim 22 or 23, comprising:

27. 24. An electronic device according to claim 22 or 23, wherein the passivation layer (69) comprises a polymer material.

28. 24. An electronic device according to claim 22 or 23, wherein the material of the interface layer (63) is silicon nitride.

29. 24. The electronic device of claim 22 or 23, wherein the anchor element (82) extends through the thickness of the interface layer (63) and the first insulating layer (61), or through the thickness of the interface layer (63) and part of the thickness of the first insulating layer (61) and terminates within the first insulating layer (61).

30. 24. An electronic device according to claim 22 or 23, further comprising a second insulating layer (102) on the first insulating layer (61) and on the layer of metallic material (58).

31. 31. The electronic device of claim 30, wherein the anchor element (82) extends through the thickness of the interface layer (63) and at the second insulating layer (102) terminating within the second insulating layer (102), or through the second insulating layer (102) and partially within the first insulating layer (61) terminating within the first insulating layer (61), or through the second insulating layer (102) and the first insulating layer (61) and terminating at the surface (53a) of the semiconductor body (53).

32. 24. An electronic device according to claim 22 or 23, wherein the anchor element (82) extends into an electrically passive area of ​​the electronic device (50; 100).

33. 24. An electronic device according to claim 22 or 23, selected from the group consisting of a Schottky diode, a PiN diode, a PN diode, an MPS device, a JBS diode, a MOSFET, an IGBT, or a power device.

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