Oxide semiconductor thin film transistor device and method for manufacturing the same

Abstract

To facilitate mounting of oxide semiconductor thin film transistors having desired characteristics.SOLUTION: A first oxide semiconductor thin film transistor includes a first oxide semiconductor layer, a first top gate electrode disposed above the first oxide semiconductor layer, and a first source / drain electrode. The first oxide semiconductor layer includes a first channel region overlapping the first top gate electrode in plan view, and two first low resistance regions sandwiching the first channel region therebetween. The first source / drain electrode is located in a layer above the first top gate electrode, penetrates an insulating region that overlaps one of the first low resistance regions in plan view, and comes into contact with one of the first low resistance regions. Each region of the two first low resistance regions and the first channel region includes a lower amorphous layer and an upper crystal layer having the same composition as the amorphous layer.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present disclosure relates to an oxide semiconductor device and a manufacturing method thereof. [Background technology]

[0002] The use of OLED (Organic Light-Emitting Diode) elements is expanding in the field of display devices. OLED elements are current-driven light-emitting elements, which eliminate the need for backlighting and offer the advantages of low power consumption, a wide viewing angle, and a high contrast ratio.

[0003] An active matrix type OLED display device includes a pixel circuit that includes a switch thin film transistor (TFT) that selects a pixel (sub-pixel) and a drive TFT that supplies current to the OLED element of that pixel. The pixel circuit may use an amorphous silicon TFT, a polysilicon TFT, or an oxide semiconductor TFT.

[0004] Oxide semiconductor TFTs are increasingly being used in pixel circuits of display devices due to their low leakage current, relatively high electron mobility, etc. Oxide semiconductor TFTs are also used in various fields other than display devices. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2018 / 0175077 [Patent Document 2] U.S. Patent Application Publication No. 2021 / 0288079 [Patent Document 3] U.S. Patent Application Publication No. 2021 / 0202540 Summary of the Invention [Problem to be solved by the invention]

[0006] Oxide semiconductor TFTs in a circuit are required to have different characteristics depending on their function. For example, in a circuit that controls a current-driven light-emitting element, a switch TFT that selects the light-emitting element is required to have a sharp rise characteristic (low S value) of the drain current relative to the gate voltage. Conversely, a driver TFT is required to have a gradual rise characteristic (high S value). [Means for solving the problem]

[0007] An oxide semiconductor thin film transistor device according to one embodiment of the present disclosure includes a substrate and one or more oxide semiconductor thin film transistors disposed above the substrate. The one or more oxide semiconductor thin film transistors include a first oxide semiconductor thin film transistor. The first oxide semiconductor thin film transistor includes a first oxide semiconductor layer, a first top gate electrode disposed above the first oxide semiconductor layer, and first source / drain electrodes. The first oxide semiconductor layer includes a first channel region overlapping the first top gate electrode in a planar view and two first low-resistance regions sandwiching the first channel region. The first source / drain electrodes are located above the first top gate electrode and contact one of the first low-resistance regions through an insulating region overlapping one of the first low-resistance regions in a planar view. Each of the two first low-resistance regions and the first channel region includes a lower amorphous layer and an upper crystalline layer having the same composition as the amorphous layer.

[0008] A method for manufacturing an oxide semiconductor thin-film transistor device according to one aspect of the present disclosure includes forming an oxide semiconductor layer, forming a gate insulating layer on the oxide semiconductor layer, forming a top gate electrode on the gate insulating layer, and forming a low-resistance region in the oxide semiconductor layer by a resistance reduction process using the top gate electrode as a mask. The formation of the oxide semiconductor layer includes forming a lower amorphous layer and then forming an upper crystalline layer. [Effects of the Invention]

[0009] According to one aspect of the present disclosure, an oxide semiconductor TFT with desired characteristics can be easily mounted on a circuit. [Brief explanation of the drawings]

[0010] [Figure 1] 1 shows a schematic configuration example of an OLED display device. [Figure 2A] 1 shows an example of the configuration of a pixel circuit. [Figure 2B] 10 shows another example of the configuration of the pixel circuit. [Figure 2C] 10 shows another example of the configuration of the pixel circuit. [Figure 3] 1 is a schematic diagram illustrating a configuration example of an oxide semiconductor TFT according to an embodiment of the present specification. [Figure 4] FIG. 4 is a plan view schematically showing the upper surface structure of the oxide semiconductor TFT shown in FIG. [Figure 5] 1 is a schematic diagram illustrating a configuration example of an oxide semiconductor TFT according to an embodiment of the present specification. [Figure 6] The results of measuring the top gate characteristics and bottom gate characteristics of the oxide semiconductor TFT having the configuration shown in FIG. 3 are shown. [Figure 7A] The steps of an example of a method for manufacturing the oxide semiconductor TFT shown in FIG. 3 are shown below. [Figure 7B] The steps of an example of a method for manufacturing the oxide semiconductor TFT shown in FIG. 3 are shown below. [Figure 7C] The steps of an example of a method for manufacturing the oxide semiconductor TFT shown in FIG. 3 are shown below. [Figure 7D] The steps of an example of a method for manufacturing the oxide semiconductor TFT shown in FIG. 3 are shown below. [Figure 8A] The steps of an example of a method for manufacturing the oxide semiconductor TFT shown in FIG. 5 are shown below. [Figure 8B] The steps of an example of a method for manufacturing the oxide semiconductor TFT shown in FIG. 5 are shown below. [Figure 8C] The steps of an example of a method for manufacturing the oxide semiconductor TFT shown in FIG. 5 are shown below. [Figure 8D] The steps of an example of a method for manufacturing the oxide semiconductor TFT shown in FIG. 5 are shown below. [Figure 9A]The azimuthal expansion of the diffraction spots of the (111) plane of the upper crystal layer is shown. [Figure 9B] The azimuthal expansion of the diffraction spots of the (111) plane of the lower amorphous layer is shown. [Figure 9C] TEM and Fourier transform images of the upper crystalline layer are shown. [Figure 9D] The TEM image and Fourier transform image of the lower amorphous material are shown. [Figure 10A] The azimuthal expansion of the diffraction spots on the (111) plane of the channel region is shown. [Figure 10B] The azimuthal expansion of the diffraction spots of the (111) plane of the source / drain region is shown. [Figure 11] 1 shows an example of the structure of a pixel circuit including a switch oxide semiconductor TFT and a drive oxide semiconductor TFT having different S values. [Figure 12] 1 shows an example of the structure of a pixel circuit including a switch TFT and a driver TFT having different S values. [Figure 13] An example of the structure of a circuit including two TFTs is shown. [Figure 14] An example of the structure of a circuit including two TFTs is shown. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. It should be noted that this embodiment is merely an example for realizing the present invention and does not limit the technical scope of the present invention. The same reference numerals are used to designate common components in each drawing. For clarity of explanation, the dimensions and shapes of the illustrated objects may be exaggerated.

[0012] [Summary] In the following, an OLED (Organic Light-Emitting Diode) display device will be described as an example of an oxide semiconductor thin film transistor (TFT) device. The OLED display device of the present disclosure includes an oxide semiconductor TFT, for example, in a pixel circuit. The oxide semiconductor layer (active layer) of the oxide semiconductor TFT includes a lower amorphous layer and an upper crystalline layer. This structure of the oxide semiconductor TFT makes it possible to easily implement an oxide semiconductor TFT with desired characteristics in a circuit. In this specification, the side farther from the substrate is called the upper side, and the side closer to the substrate is called the lower side.

[0013] Furthermore, by adding a bottom gate electrode below the oxide semiconductor layer, it is possible to fabricate bottom-gate TFTs using the lower amorphous layer as a channel and top-gate TFTs using the upper crystalline layer as a channel, thereby realizing circuits that make the most of the characteristics of each TFT. Note that the characteristic configuration of a circuit including an oxide semiconductor TFT disclosed below can be applied to pixel circuits and driver circuits within a display device, as well as circuits in devices other than a display device.

[0014] [Display device configuration] 1 schematically shows an example of the configuration of an OLED display device 1. The OLED display device 1 includes a TFT (Thin Film Transistor) substrate 10 on which OLED elements are formed, a sealing substrate 20 that seals the organic light-emitting elements, and a bonding portion (glass frit seal portion) 30 that bonds the TFT substrate 10 and the sealing substrate 20 together. Dry nitrogen, for example, is sealed between the TFT substrate 10 and the sealing substrate 20, and the space between them is sealed by the bonding portion 30. The sealing substrate 20 and the bonding portion 30 are part of a sealing structure, and as another example, the sealing structure may have, for example, a thin film encapsulation (TFE) structure.

[0015] A scan driver 31, an emission driver 32, a driver IC 34, and a demultiplexer 36 are arranged around the cathode electrode formation region 14 outside the display region 25 of the TFT substrate 10. The driver IC 34 is connected to external devices via an FPC (Flexible Printed Circuit) 35. The scan driver 31 and the emission driver 32 are peripheral circuits formed on the TFT substrate 10.

[0016] The scan driver 31 drives the scan lines of the TFT substrate 10. The emission driver 32 drives the emission control lines to control the light emitting period of each pixel. The driver IC 34 is implemented using, for example, an anisotropic conductive film (ACF).

[0017] The driver IC 34 provides power and timing signals (control signals) to the scan driver 31 and the emission driver 32. In addition, the driver IC 34 provides power and data signals to the demultiplexer 36.

[0018] The demultiplexer 36 sequentially outputs the output of one pin of the driver IC 34 to d data lines (d is an integer equal to or greater than 2). The demultiplexer 36 switches the output data line of the data signal from the driver IC 34 d times within a scanning period, thereby driving d times as many data lines as the number of output pins of the driver IC 34.

[0019] [Pixel circuit configuration] A plurality of pixel circuits are formed on the TFT substrate 10, and each pixel circuit controls the current supplied to the anode electrode of a plurality of sub-pixels (also simply referred to as pixels). FIG. 2A shows an example of the configuration of a pixel circuit. Each pixel circuit includes a drive transistor T1, a selection transistor T2, an emission transistor T3, and a storage capacitor C1 that stores a signal voltage applied to the gate of the drive transistor T1. The pixel circuit controls the light emission of an OLED element E1.

[0020] The selection transistor T2 is a switch (switch transistor) that selects a sub-pixel. The selection transistor T2 is an n-channel oxide semiconductor TFT, and its gate is connected to a scan line 16. One of its source / drain terminals is connected to a data line 15. The other of its source / drain terminals is connected to the gate of the drive transistor T1.

[0021] The driving transistor T1 is a transistor (driving TFT) for driving the OLED element E1. The driving transistor T1 is an n-channel oxide semiconductor TFT, and its gate is connected to the source / drain of the selection transistor T2. One source / drain of the driving transistor T1 is connected to the source / drain of the emission transistor T3. The other source / drain is connected to the OLED element E1 and a storage capacitor C1. The storage capacitor C1 is formed between the gate and source / drain (source) of the driving transistor T1. Here, the source / drain refers to either the source or the drain, and depending on the operating status of the oxide semiconductor thin-film transistor, the one with a higher potential is the drain and the one with a lower potential is the source.

[0022] The emission transistor T3 is a switch that controls the supply and stop of drive current to the OLED element E1. The emission transistor T3 is an n-channel oxide semiconductor TFT, and its gate is connected to an emission control line 17. One source / drain of the emission transistor T3 is connected to the source / drain of the drive transistor T1. The other source / drain is connected to a power supply line 18. FIG. 2 shows a circuit using an n-channel oxide semiconductor TFT, in which Vdd (power supply voltage) is set to a positive potential and Vss, which is a cathode potential, is set to a potential lower than Vdd. The emission transistor T3 may be disposed between the OLED element E1 and the drive transistor T1.

[0023] Next, the operation of the pixel circuit will be described. The scan driver 31 outputs a selection pulse to the scan line 16, turning on the selection transistor T2. The data voltage supplied from the driver IC 34 via the data line 15 is stored in the storage capacitor C1. The storage capacitor C1 holds the stored voltage throughout one frame period. The hold voltage changes the conductance of the drive transistor T1 in an analog manner, and the drive transistor T1 supplies a forward bias current corresponding to the light emission gradation to the OLED element E1.

[0024] The emission transistor T3 is located on the supply path of the driving current. The emission driver 32 outputs a control signal to the emission control line 17 to control the on / off of the emission transistor T3. When the emission transistor T3 is in the on state, the driving current is supplied to the OLED element E1. When the emission transistor T3 is in the off state, this supply is stopped. By controlling the on / off of the emission transistor T3, the lighting period (duty ratio) within one frame period can be controlled.

[0025] FIG. 2B shows another example of the pixel circuit configuration. This pixel circuit has a reset transistor T4 instead of the emission transistor T3 of FIG. 2A. The reset transistor T4 is an n-channel oxide semiconductor TFT. The reset transistor T4 controls the electrical connection between the reference voltage supply line 11 and the anode of the OLED element E1. This control is performed by supplying a reset control signal to the gate of the reset transistor T4 from a reset control line 19. The reset transistor T4 can be used for various purposes.

[0026] 2C shows another example of the pixel circuit configuration. This pixel circuit includes transistors T1 to T6, which are n-channel TFTs. A Vscan2 signal is input to the gate of transistor T2, and a Vscan1 signal is input to the gates of transistors T4 and T6. A data signal (voltage) is applied to storage capacitor C1 via transistors T2, T1, and T6, correcting the threshold voltage of transistor T1. Transistor T4 applies reference voltage Vref to the anode of OLED element E1. Transistors T3 and T5 are connected in series with drive transistor T1, and signals Vem1 and Vem2 are input to their gates, respectively, to control whether OLED element E1 emits light.

[0027] In the circuit configuration of Fig. 2C, the gate of the drive transistor T1 is connected to the source / drain of the switch transistor T6. The storage capacitor C1 is connected to the gate of the drive transistor T1 and a node between the source / drain of the switch transistor T3 and the OLED element E1. The storage capacitor C1 holds a gate voltage (gate-source voltage) that determines the amount of drive current supplied by the drive transistor T1.

[0028] The pixel circuit described above includes a drive TFT (T1), a storage capacitor (C1) that stores a signal voltage between the source / drain and gate of the drive TFT, and a switch TFT (T2 or T6) whose source / drain is connected to the gate of the drive TFT. The circuit shown in FIG. 2C further includes a switch TFT (e.g., T2 and T3) connected in series. The TFT structure described herein allows the drive TFT and switch TFT to have specific characteristics. Note that the pixel circuits in FIGS. 2A, 2B, and 2C are examples, and pixel circuits may have other configurations.

[0029] Switch TFTs are required to have a sharp rise characteristic of the drain current relative to the gate voltage (low S value [V / dec]) in order to turn them on and off in response to a gate signal. A low S value allows the operating voltage amplitude (gate voltage amplitude) of the switch TFT to be reduced, which in turn allows the voltage applied to the TFT gate to be reduced and fluctuations in the threshold voltage to be reduced.

[0030] On the other hand, the driver TFT that controls the current flowing to the OLED element must have a gradual rise time (high S value). A high S value widens the available range of data signals and also reduces the effect of threshold voltage fluctuations at low gradations (low gate voltages).

[0031] In one embodiment of the present specification, at least some of the transistors in a pixel circuit are configured using oxide semiconductor TFTs. The oxide semiconductor layer (active layer) of the oxide semiconductor TFT includes a lower amorphous layer and an upper crystalline layer. The crystalline layer is a polycrystalline layer. In this specification, the side closer to the substrate is referred to as the lower side, and the side farther from the substrate is referred to as the upper side. Note that a portion of the oxide semiconductor layer may be made to have low resistance and exhibit conductive properties, and the material layer including this portion is referred to as the oxide semiconductor layer. The oxide semiconductor layer can be formed of, for example, a metal oxide.

[0032] The above-described structure of the oxide semiconductor layer can provide the oxide semiconductor TFT with different characteristics depending on whether the gate voltage for controlling the resistance or current of the channel region is applied to the top gate electrode or the bottom gate electrode. The top gate electrode is located above the oxide semiconductor layer, and the bottom gate electrode is located below the oxide semiconductor layer.

[0033] Specifically, an oxide semiconductor TFT in which a top gate electrode controls the characteristics of the channel region can exhibit a low S value. An oxide semiconductor TFT in which a bottom gate electrode controls the characteristics of the channel region can exhibit a high S value. An oxide semiconductor TFT with such a structure can facilitate the design of pixel circuits.

[0034] For example, a better pixel circuit can be constructed by using an oxide semiconductor TFT with a high S value (a gradual rise in the Vg-Id characteristics) as the drive transistor and an oxide semiconductor TFT with a low S value (a steep rise in the Vg-Id characteristics) as the switch transistor.

[0035] The pixel circuit may include only one type of oxide semiconductor TFT, either an oxide semiconductor TFT controlled by a voltage from a top gate electrode or an oxide semiconductor TFT controlled by a voltage from a bottom gate electrode.The pixel circuit may also include other types of TFTs, such as polysilicon TFTs, in addition to the oxide semiconductor TFTs.

[0036] In one embodiment of the present specification, the source / drain regions of the oxide semiconductor are formed by a self-aligned gate (also simply referred to as self-alignment) method using the top gate electrode as a mask. The self-alignment method can reduce the feedthrough of the oxide semiconductor TFT and can also eliminate the need to form a mask only for the process.

[0037] [Structure of oxide semiconductor TFT] An example structure of an oxide semiconductor TFT according to an embodiment of the present specification will be described below. As described above, the oxide semiconductor layer (active layer) of the oxide semiconductor TFT includes a lower amorphous layer and an upper crystalline layer. The crystalline layer is a polycrystalline layer. The oxide semiconductor TFT also includes a top gate electrode and one or more source / drain electrodes. The oxide semiconductor TFT may include a bottom gate electrode in addition to or instead of the top gate electrode.

[0038] The channel region of the oxide semiconductor layer overlaps with each of the top gate electrode and the bottom gate electrode in a plan view (in the stacking direction). In a plan view, the channel region is included in each of the top gate electrode and the bottom gate electrode. A gate insulator is sandwiched between the oxide semiconductor layer and each of the top gate electrode and the bottom gate electrode.

[0039] A control voltage for controlling the resistance or current flow in the channel region is applied to one of the top gate electrode and the bottom gate electrode. The other electrode may be, for example, supplied with a constant potential or may be floating. When the oxide semiconductor TFT includes only one of the top gate electrode and the bottom gate electrode, the control potential is applied to that electrode from a drive circuit.

[0040] The source / drain electrodes contact the source / drain regions of the oxide semiconductor layer. These contact regions are located outside the top gate electrode in a plan view. In one embodiment of the present specification, the source / drain electrodes include vias that pass through an interlayer insulating layer covering the top gate electrode, and the vias contact the source / drain regions. The vias may penetrate not only the interlayer insulating layer above the top gate electrode but also other insulating layers, such as an insulating layer that includes the top gate insulator as a part thereof. This configuration enables a self-aligned gate and allows efficient production of oxide semiconductor TFTs with excellent characteristics.

[0041] Fig. 3 is a schematic diagram showing an example of the configuration of an oxide semiconductor TFT according to an embodiment of the present specification. The example of the configuration of the oxide semiconductor TFT shown in Fig. 3 includes a top gate electrode 123 and a bottom gate electrode 133. The oxide semiconductor TFT can be used as, for example, either a drive transistor or a switch transistor.

[0042] When used as a drive transistor, for example, a control potential for the channel is applied to the bottom gate electrode 133, and a constant potential is applied to the top gate electrode 123. When used as a switch transistor, for example, a control potential for the channel is applied to the top gate electrode 123, and a constant potential is applied to the bottom gate electrode 133. When used as a switch transistor, the bottom gate electrode 133 may be omitted.

[0043] The oxide semiconductor TFT is formed on a flexible or inflexible insulating substrate 101 made of resin or glass. The oxide semiconductor TFT includes a bottom gate electrode 133 and a lower insulating layer 135 between the bottom gate electrode 133 and the oxide semiconductor layer 102. An insulating layer (not shown) may be present between the bottom gate electrode 133 and the insulating substrate 101. The bottom gate electrode 133 is a conductor and can be made of, for example, a high-melting-point metal such as W, Mo, or Ta, or an alloy thereof.

[0044] The oxide semiconductor layer 102 includes source / drain regions (S / D regions) 105 and 107 and a channel region 103 between the source / drain regions 105 and 107 in the in-plane direction. A part of the lower insulating layer 135 is a bottom gate insulator between the bottom gate electrode 133 and the channel region 103.

[0045] The lower insulating layer 135 is, for example, a silicon oxide layer or a stack of silicon oxide (upper) and silicon nitride (lower). The oxide semiconductor layer 102 is formed directly on (in contact with) the lower insulating layer 135. The source / drain regions 105 and 107 are regions with reduced resistance. The channel region 103 is a region without reduced resistance. Resistance reduction will be described later.

[0046] The oxide semiconductor layer 102 is formed of, for example, a metal oxide, and one example is IGZO (Indium Gallium Zinc Oxygen).

[0047] Examples of other oxide semiconductor materials include high-mobility materials such as indium gallium zinc tin oxide (IGZTO), indium gallium oxide (IGO), and indium zinc oxide (IZO), and low-mobility materials such as zinc oxide (ZnO).

[0048] The oxide semiconductor layer 102 includes a lower amorphous layer and an upper crystalline layer. Specifically, the channel region 103 is composed of an amorphous layer 111 and a crystalline layer 112. The source / drain region 105 is composed of an amorphous layer 113 and a crystalline layer 114. The source / drain region 107 is composed of an amorphous layer 115 and a crystalline layer 116. Note that FIG. 3 is a schematic diagram, and the interface between the amorphous layer and the crystalline layer is not actually flat but has a more complex shape.

[0049] The channel region 103 and the source / drain regions 105, 107 have the same composition, and the amorphous and crystalline layers in each region are in different ordered states, but have the same composition.

[0050] The bottom gate electrode 133 faces the channel region 103 with the lower insulating layer 135 sandwiched therebetween. The bottom gate electrode 133, the lower insulating layer 135, and the channel region 103 are stacked in this order from below (from the substrate side). A part of the lower insulating layer 135 is in contact with the channel region 103 and the bottom gate electrode 133. The part of the lower insulating layer 135 that is in contact with the bottom gate electrode 133 and the channel region 103 is a bottom gate insulator of the oxide semiconductor TFT.

[0051] The oxide semiconductor TFT further includes a top gate electrode 123 and an upper insulating layer 117 located between the top gate electrode 123 and the channel region 109 in the stacking direction. The top gate electrode 123 is a conductor and can be made of, for example, a high-melting-point metal such as W, Mo, or Ta, or an alloy thereof.

[0052] The upper insulating layer 117 covers the oxide semiconductor layer 102. The upper insulating layer 117 has, for example, a silicon oxide layer, a silicon nitride layer, or a laminated structure of these. The oxide semiconductor layer 102, the upper insulating layer 117, and the top gate electrode 123 are laminated in this order from below (from the substrate side), and the upper insulating layer 117 is in contact with the lower insulating layer 135, the oxide semiconductor layer 102, and the top gate electrode 123. A portion of the upper insulating layer 117 that is in contact with the top gate electrode 123 and the channel region 103 constitutes a top gate insulator.

[0053] For example, when used as a drive transistor, the bottom gate electrode 133 is supplied with a data signal (signal voltage) that controls the drive current to the OLED element. The top gate electrode 123 is supplied with a constant potential or is electrically floating. When used as a switch transistor, the top gate electrode 123 is supplied with an ON / OFF control signal. The bottom gate electrode 133 may be supplied with a constant potential, be electrically floating, or may be omitted. As will be described later, the top gate electrode 123 is used as a mask for reducing the resistance of the source / drain regions 105, 107 (self-aligned).

[0054] The oxide semiconductor TFT includes an interlayer insulating layer 118 above the top gate electrode 123. The interlayer insulating layer 118 covers the top gate electrode 123 and is in contact with the top gate electrode 123 and the upper insulating layer 117. The interlayer insulating layer 118 is made of, for example, a silicon insulating layer, and may have a multi-layer structure of different insulating materials.

[0055] The oxide semiconductor TFT includes source / drain electrodes 121 and 122 sandwiching a top gate electrode 123 in the in-plane direction. The source / drain electrodes 121 and 122 are formed of a conductor and may have, for example, a single Al layer or a Ti / Al / Ti laminated structure.

[0056] The source / drain electrodes 121 include contact portions 125 that penetrate the interlayer insulating layer 118 and the upper insulating layer 117. The contact portions 125 are in contact (directly connected) with the source / drain regions 105 through contact holes formed in the interlayer insulating layer 118 and the upper insulating layer 117.

[0057] The source / drain electrodes 122 include contact portions 126 that penetrate the interlayer insulating layer 118 and the upper insulating layer 117. The contact portions 126 are in contact (directly connected) with the source / drain regions 107 through contact holes formed in the interlayer insulating layer 118 and the upper insulating layer 117.

[0058] The contact portions 125 and 126 penetrate the interlayer insulating layer 118 and the upper insulating layer 117 in a region outside the top gate electrode 123 in a plan view, and do not overlap the top gate electrode 123 in a plan view. The tops of the source / drain electrodes 121 and 122 are present in the interlayer insulating layer 118. In the configuration example of FIG. 3, the source / drain electrodes 121 and 122 are formed so as not to overlap the top gate electrode 123 in a plan view.

[0059] Fig. 4 is a plan view schematically showing the top surface structure of the oxide semiconductor TFT shown in Fig. 3. Fig. 4 shows the shape in a plan view (viewed in the stacking direction). As shown in Fig. 4, in a plan view from the upper layer side, the source / drain electrodes 121 and 122 are located outside the top gate electrode 123 and do not overlap with each other.

[0060] 5 is a schematic diagram illustrating an example of the configuration of an oxide semiconductor TFT according to an embodiment of the present specification. Differences from the example configuration illustrated in FIG. 3 will be mainly described. The upper insulating layer 127 is etched and does not cover the source / drain regions 105, 107 in plan view. The upper insulating layer 127 covers the channel region 103. A part or all of the upper insulating layer 127 constitutes a top gate insulator between the channel region 103 and the top gate electrode 123.

[0061] The source / drain regions 105, 107 are exposed from the upper insulating layer 127 relative to the interlayer insulating layer 128, which contacts and covers the source / drain regions 105, 107. A contact portion 125 of the source / drain electrode 121 penetrates the interlayer insulating layer 128 and contacts (directly connects) the source / drain region 105 within the hole of the interlayer insulating layer 128. A contact portion 126 of the source / drain electrode 122 penetrates the interlayer insulating layer 128 and contacts (directly connects) the source / drain region 107 within the hole of the interlayer insulating layer 128.

[0062] Figure 6 shows the results of measuring the top-gate and bottom-gate characteristics of an oxide semiconductor TFT having the configuration shown in Figure 3. In the graph shown in Figure 6, the horizontal axis represents the electric field applied from the top gate electrode or bottom gate electrode, and the vertical axis represents the drain current. Line 203 represents the top-gate characteristics, and line 201 represents the bottom-gate characteristics. The source-drain voltage Vd was 10 V.

[0063] The bottom gate characteristics indicate the change in drain current with respect to the change in electric field strength between the bottom gate electrode and the oxide semiconductor layer. In the measurement of the bottom gate characteristics, the top gate electrode was in a floating state. The top gate characteristics indicate the change in drain current with respect to the change in electric field strength between the top gate electrode and the oxide semiconductor layer. In the measurement of the top gate characteristics, the bottom gate electrode was in a floating state.

[0064] As shown in Figure 6, bottom gate driving has a larger S value and a gradual rise in drain current compared to top gate driving. This makes it advantageous for use as a drive transistor. On the other hand, top gate driving has a smaller S value and a steeper rise in drain current. Top gate driving exhibits good switching characteristics and is advantageous for use as a switch transistor.

[0065] [Manufacturing method] An example of a method for manufacturing an oxide semiconductor TFT will be described below. Figures 7A to 7D schematically show an example of a method for manufacturing the oxide semiconductor TFT shown in Figure 3. This method reduces the resistance of the source / drain regions by injecting impurities into the oxide semiconductor through the upper insulating layer.

[0066] 7A, the manufacturing method forms a bottom gate electrode 133 on an insulating substrate 101. In this step, a metal layer is formed by, for example, a sputtering method, and then photolithography and etching are performed to form the bottom gate electrode 133. Any metal material can be used, and examples of the metal material that can be used include Mo, W, Nb, and Al.

[0067] Furthermore, in the manufacturing method, after forming a lower insulating layer 135 (for example, a silicon oxide layer) by a CVD (Chemical Vapor Deposition) method or the like, the oxide semiconductor layer 102 is formed. The oxide semiconductor layer 102 is formed, for example, by depositing an oxide semiconductor by a sputtering method and then patterning it by photolithography.

[0068] The oxide semiconductor layer 102 is formed by forming a lower amorphous layer 151 and an upper crystalline layer 152. For example, the oxide semiconductor layer 102 can be formed to have a crystalline (upper) / amorphous (lower) structure by appropriately setting gas conditions during sputtering. For example, a sputtering apparatus introduces a mixed gas of oxygen gas and argon gas into a chamber in which an oxide semiconductor target is placed. In the mixed gas of oxygen and argon gas introduced, the ratio of oxygen gas (O2 / (Ar+O2)) is, for example, 30% or more and 60% or less.

[0069] A high voltage is applied between the substrate on which the oxide semiconductor is to be formed and the oxide semiconductor target. Any method such as DC sputtering, RF sputtering, or magnetron sputtering may be used. By reactive sputtering using oxygen as described above, an oxide semiconductor layer having a crystalline (upper) / amorphous (lower) structure can be formed.

[0070] Next, the upper insulating layer 117 is formed by, for example, CVD. After that, a metal film is formed by a sputtering method or the like, and after patterning a mask by photolithography, the metal film is etched to form the top gate electrode 123. Any metal material can be used, and examples of the metal material that can be used include Mo, W, Nb, and Al.

[0071] 7B, in the manufacturing method, impurities (for example, boron ions) are implanted into the oxide semiconductor layer 102 through the upper insulating layer 117, using the top gate electrode 123 as a mask. By implanting the impurity ions, low-resistance source / drain regions 105 and 107 are formed in the oxide semiconductor layer 102.

[0072] The source / drain regions 105, 107 are regions outside the top gate electrode 123, and are implanted with impurity ions to reduce their resistance. The source / drain region 105 is composed of a lower amorphous layer 113 and an upper crystalline layer 114, and the source / drain region 107 is composed of a lower amorphous layer 115 and an upper crystalline layer 116. The impurity ion implantation increases oxygen vacancies in the source / drain regions 105, 107, thereby reducing their resistance. As will be described later, the impurity ion implantation reduces the degree of orientation of the source / drain regions 105, 107, thereby reducing their resistance.

[0073] The high resistance region is the channel region 103. The channel region 103 is not exposed to impurity ions. Therefore, the lower amorphous layer 111 and the upper crystalline layer 112 have the same properties as the amorphous layer 151 and the crystalline layer 152 before the impurity ion implantation. The high resistance of the channel region 103 is maintained. In this way, a low resistance region is formed by self-alignment using the top gate electrode 123 as a mask.

[0074] 7C, the process then forms an interlayer insulating layer 118 to cover the top gate electrode 123 and the upper insulating layer 117. The interlayer insulating layer 118 can be formed by, for example, using CVD to form one or more insulating layers, such as a silicon oxide layer or a silicon nitride layer.

[0075] 7D , next, in the manufacturing method, contact holes are formed in the interlayer insulating layer 118 and the upper insulating layer 117 outside the top gate electrode 123 in a plan view by etching after patterning a mask by photolithography. The contact holes penetrate the interlayer insulating layer 118 and the upper insulating layer 117 at positions that do not overlap with the top gate electrode 123, and expose the source / drain regions 105, 107 of the oxide semiconductor layer, respectively.

[0076] Furthermore, the manufacturing method involves forming a metal film by sputtering or the like, patterning a mask by photolithography, and then etching the metal film to form source / drain electrodes 121 and 122. The source / drain electrodes 121 and 122 penetrate the interlayer insulating layer 118 and the upper insulating layer 117 and come into contact with the upper surfaces of the source / drain regions 105 and 107, respectively.

[0077] Next, another example of a method for manufacturing an oxide semiconductor will be described. Figures 8A to 8D schematically show an example of a method for manufacturing the oxide semiconductor TFT shown in Figure 5. In this method, exposed regions of the oxide semiconductor are exposed to plasma to reduce the resistance of the source / drain regions. Below, differences from the description made with reference to Figures 7A to 7D will be mainly described.

[0078] 8A is substantially the same as FIG. 7A, except that an insulating layer 141 is formed instead of the upper insulating layer 117. The shape and forming method of the insulating layer 141 may be the same as those of the upper insulating layer 117. The other components are the same as those of FIG. 7, and the forming methods thereof may also be the same.

[0079] 8B, the insulating layer 141 is etched using the top gate electrode 123 as a mask to form the upper insulating layer 127. This exposes a portion of the oxide semiconductor layer 102. The exposed portion of the oxide semiconductor layer 102 is exposed to He plasma to reduce its resistance. This results in the formation of reduced-resistance source / drain regions 105, 107.

[0080] The structure of the source / drain regions 105, 107 is as described with reference to FIG. 7B. Exposure to He plasma increases oxygen vacancies in the source / drain regions 105, 107, lowering their resistance. As will be described later, exposure to He plasma reduces the degree of orientation of the source / drain regions 105, 107, lowering their resistance.

[0081] The high-resistance region is the channel region 103. The channel region 103 is not exposed to He plasma. Therefore, the lower amorphous layer 111 and the upper crystalline layer 112 have the same characteristics as the amorphous layer 151 and the crystalline layer 152 before exposure to He plasma. The high resistance of the channel region 103 is maintained. In this way, a low-resistance region is formed by self-alignment using the top gate electrode 123 as a mask.

[0082] 8C, the process then forms an interlayer insulating layer 128 to cover the top gate electrode 123 and the upper insulating layer 127. The interlayer insulating layer 128 can be formed by, for example, using CVD to form one or more insulating layers such as a silicon oxide layer or a silicon nitride layer.

[0083] 8D , next, in the manufacturing method, contact holes are formed in the interlayer insulating layer 128 outside the top gate electrode 123 in a plan view by etching after patterning a mask by photolithography. The contact holes penetrate the interlayer insulating layer 128 at positions that do not overlap with the top gate electrode 123, and expose the source / drain regions 105, 107 of the oxide semiconductor layer, respectively.

[0084] Furthermore, the manufacturing method involves forming a metal film by sputtering or the like, patterning a mask by photolithography, and then etching the metal film to form source / drain electrodes 121 and 122. The source / drain electrodes 121 and 122 penetrate the interlayer insulating layer 128 and contact the upper surfaces of the source / drain regions 105 and 107, respectively.

[0085] In the manufacturing of an OLED display device, after forming the transistors in the pixel circuits as described above, the OLED elements and the sealing structure are formed. For example, the manufacturing method may include forming a metal layer including source / drain electrodes, then forming an insulating layer (e.g., a silicon oxide layer) by a CVD method or the like, forming a passivation layer by photolithography and etching, and then forming an overcoat layer made of an organic material on top of that.

[0086] Next, the manufacturing method involves forming an anode electrode on the overcoat layer and connecting it to the source / drain electrodes through contact holes formed in the passivation layer and the overcoat layer. The anode electrode includes, for example, three layers: a transparent conductive film, a metal reflective film, and another transparent conductive film. The transparent conductive material is, for example, ITO, IZO, etc. The reflective metal material is, for example, Ag, Mg, Al, etc. The anode electrode can be formed by sputtering and etching.

[0087] The manufacturing method further includes depositing a photosensitive organic resin film by spin coating or the like and patterning it to form a pixel definition layer. Holes are formed in the pixel definition layer, and the anode electrodes are exposed at the bottom of the holes. The pixel definition layer separates the light-emitting regions of each sub-pixel. The manufacturing method further includes depositing organic light-emitting materials for each color (red, green, and blue) to form organic light-emitting films on the anode electrodes, and then forming cathode electrodes over the entire substrate. The manufacturing method then includes forming a sealing structure.

[0088] [Electron diffraction measurement results] The results of electron diffraction measurements of an oxide semiconductor TFT according to an embodiment of the present specification are described below. A TEM (transmission electron microscope) was used for the electron diffraction measurements. An electron beam was irradiated onto the oxide semiconductor layer of the oxide semiconductor TFT to obtain a diffraction pattern, and the diffraction pattern data and its azimuth expansion graph, which are described below, were generated. It was shown that the oxide semiconductor layer was composed of a lower amorphous layer and an upper crystalline layer. It was shown that the degree of orientation in the low-resistance region (source / drain region) was lower than that in the high-resistance region (channel region).

[0089] 9A and 9B show the results of electron diffraction measurements of a sample prepared by the method described with reference to FIGS. 7A to 7D. FIG. 9A shows the azimuthal expansion of diffraction spots on the (111) plane of the upper crystalline layer. FIG. 9B shows the azimuthal expansion of diffraction spots on the (111) plane of the lower amorphous layer. These images show the azimuthal dependence of diffraction spot intensity in Fourier transform images (equivalent to electron diffraction images) obtained from TEM images such as those shown in FIGS. 9C and 9D. Comparing these Fourier transform images, brighter diffraction spots are clearly observed in the upper crystalline layer. The horizontal axis of the two graphs represents the azimuthal angle, and the vertical axis represents the electron diffraction intensity. FIGS. 9A and 9B show the results of measurements in a 40 nm × 40 nm local cross-sectional area of ​​a 70 nm-thick oxide semiconductor layer.

[0090] The measurement result for the upper crystalline layer in Figure 9A shows a high peak. On the other hand, the measurement result for the lower amorphous layer in Figure 9B is flat without showing a high peak. These two measurement results indicate that the upper layer is a crystalline layer and the lower layer is an amorphous layer. The crystalline layer is below the average background level (200 × 10 6 The maximum peak intensity of the amorphous layer is greater than the average background level (200×10 6 ) where the average background level is the average signal level in the region where no clear peaks exist.

[0091] 10A and 10B show the results of electron diffraction measurements of a sample prepared by the method described with reference to FIGS. 7A to 7D. FIG. 10A shows the azimuthal spread of diffraction spots on the (111) plane in the channel region. FIG. 10B shows the azimuthal spread of diffraction spots on the (111) plane in the source / drain region. The horizontal axis of the two graphs represents the azimuthal angle, and the vertical axis represents the electron diffraction intensity. FIGS. 10A and 10B show the results of measurements in a relatively wide cross-sectional area of ​​70 nm × 0.7 μm in a 70-nm-thick oxide semiconductor layer.

[0092] The (111) orientation degree calculated from the measurement results shown in Figure 10A was 17.2. The (111) orientation degree calculated from the measurement results shown in Figure 10B was 13.7. This reduction in orientation degree appropriately reduces the resistance of the source / drain regions. The orientation degree of amorphous is 1. The orientation degree is expressed by the magnitude of the intensity peak in the azimuthal expansion.

[0093] Note that the local orientation of the channel region and the source / drain regions may exhibit values ​​different from the above characteristics. That is, the local region of the channel region (high-resistance region) may exhibit a high orientation, while the local region of the source / drain region (low-resistance region) may exhibit a low orientation. According to the inventors' investigations, a cross-sectional region of the oxide semiconductor film thickness × 0.5 μm or more appropriately exhibits a high orientation in the channel region and a low orientation in the source / drain regions.

[0094] [Device Structure] Several structural examples of circuits including multiple oxide semiconductor TFTs are described below. Fig. 11 shows a structural example of a pixel circuit including a switch oxide semiconductor TFT (hereinafter simply referred to as a switch TFT) and a drive oxide semiconductor TFT (hereinafter simply referred to as a drive TFT) having different S values.

[0095] 11 schematically shows an example of the cross-sectional structure of a switch TFT and a driver TFT. A switch TFT 310 and a driver TFT 330 are formed on a flexible or non-flexible insulating substrate 325 made of resin or glass. The switch TFT is a first oxide semiconductor TFT, and the switch TFT 330 is a second oxide semiconductor TFT. The switch TFT 310 has the same configuration as described with reference to FIG. 3 except that the bottom gate electrode is removed. The driver TFT 330 has the same configuration as described with reference to FIG. 3. The TFTs 310 and 330 can be formed simultaneously by the method described with reference to FIGS. 7A to 7D.

[0096] The driving TFT 330 includes a bottom gate electrode 337 and an upper oxide semiconductor layer 338. A lower insulating layer 326 is present between the bottom gate electrode 337 and the oxide semiconductor layer 338. The oxide semiconductor layer 338 includes source / drain regions 331, 332 and a channel region 333 between the source / drain regions 331, 332 in the in-plane direction.

[0097] The oxide semiconductor layer 338 is formed on and in direct contact with the lower insulating layer 326. The source / drain regions 331 and 332 are regions in which the oxide semiconductor has been made low-resistance. The channel region 333 is a region in which the oxide semiconductor has not been made low-resistance. As described with reference to FIG. 3, the source / drain regions 331 and 332 and the channel region 333 are each composed of a lower amorphous layer and an upper crystalline layer.

[0098] The bottom gate electrode 337 faces the channel region 333 across the lower insulating layer 326. The lower insulating layer 326 is in direct contact with the channel region 333 and the bottom gate electrode 337. A data signal is applied to the bottom gate electrode 333 to control the drive current to the OLED element.

[0099] The driving TFT 330 further includes a top gate electrode 336. An upper insulating layer 327 is present between the top gate electrode 336 and the oxide semiconductor layer 338. The oxide semiconductor layer 338, the upper insulating layer 327, and the top gate electrode 336 are stacked in this order from below (from the substrate side), and the upper insulating layer 327 is in direct contact with the oxide semiconductor layer 338 and the top gate electrode 336.

[0100] An interlayer insulating layer 328 is formed to cover the top gate electrode 336 and the upper insulating layer 327. Source / drain electrodes 334, 335 pass through the interlayer insulating layer 328 and the upper insulating layer 327 and are directly connected to the source / drain regions 331, 332, respectively. The tops of the source / drain electrodes 334, 335 are in direct contact with the upper surface of the interlayer insulating layer 328. Of the source / drain electrodes 334, 335, the electrode 334 having the lower potential is connected to the anode electrode of the OLED element (not shown in FIG. 11 ).

[0101] The source / drain electrodes 334, 335 include contact portions 339, 340, respectively, which penetrate the outside of the top gate electrode 336 in a plan view. The contact portion 339 penetrates the interlayer insulating layer 328 and the upper insulating layer 327 and is in direct contact with the source / drain region 331. The contact portion 340 penetrates the interlayer insulating layer 328 and the upper insulating layer 327 and is in direct contact with the source / drain region 332.

[0102] The source / drain electrode 334 and the top gate electrode 336 are connected by an interconnection portion 341, which maintains them at the same potential. The interconnection portion 341 is continuous with the source / drain electrode 334 and can be formed simultaneously using the same material. The interconnection portion 341 is directly connected to the top gate electrode 336. The interconnection portion 341 includes a contact portion 342, which penetrates the interlayer insulating layer 328 and is in direct contact with the upper surface of the top gate electrode 336. A source potential, for example, is applied to the source / drain electrode 334. The top gate electrode 336 is connected to the source / drain electrode 334 by the interconnection portion 341, and its potential is the same as that of the source / drain electrode 334.

[0103] The switch TFT 310 is disposed at a different position from the drive TFT 330 in a plan view. The switch TFT 310 includes an oxide semiconductor layer 318. The oxide semiconductor layer 318 is formed on and in direct contact with a lower insulating layer 326. The oxide semiconductor layer 318 includes source / drain regions 311, 312, and a channel region 313 between the source / drain regions 311, 312 in the in-plane direction.

[0104] The source / drain regions 311 and 312 are regions in which the oxide semiconductor is made to have low resistance. The channel region 313 is a region in which the oxide semiconductor is not made to have low resistance. As described with reference to FIG. 3, the source / drain regions 311 and 312 and the channel region 313 are each composed of a lower amorphous layer and an upper crystalline layer.

[0105] The switch TFT 310 further includes a top gate electrode 316. An upper insulating layer 327 is present between the top gate electrode 316 and the oxide semiconductor layer 318. The oxide semiconductor layer 318, the upper insulating layer 327, and the top gate electrode 316 are stacked in this order from below (from the substrate side), and the upper insulating layer 327 is in direct contact with the oxide semiconductor layer 318 and the top gate electrode 316. A control signal for turning the switch TFT 310 on and off is supplied to the top gate electrode 316.

[0106] An interlayer insulating layer 328 is formed to cover the top gate electrode 316 and the upper insulating layer 327. The source / drain electrodes 314, 315 pass through the interlayer insulating layer 328 and the upper insulating layer 327 and directly connect to the source / drain regions 311, 312, respectively. The tops of the source / drain electrodes 314, 315 are in direct contact with the upper surface of the interlayer insulating layer 328.

[0107] The source / drain electrodes 314, 315 each include a contact portion 319, 320 that penetrates the outside of the top gate electrode 316 in a plan view. The contact portion 319 penetrates the interlayer insulating layer 328 and the upper insulating layer 327 and is in direct contact with the source / drain region 311. The contact portion 320 penetrates the interlayer insulating layer 328 and the upper insulating layer 327 and is in direct contact with the source / drain region 312.

[0108] The source / drain electrodes 314 of the switch TFT 310 and the bottom gate electrode 337 of the drive TFT are connected by an interconnect 323. The interconnect 323 is continuous with the source / drain electrodes 314 and can be formed at the same time using the same material. The interconnect 323 is directly connected to the bottom gate electrode 337.

[0109] The interconnect portion 323 includes a contact portion 324, which penetrates the interlayer insulating layer 328, the upper insulating layer 327, and the lower insulating layer 326 to directly contact the upper surface of the portion 321 extending from the bottom gate electrode 337. The bottom gate electrode 337 is connected to the source / drain electrode 314 by the interconnect portion 323, and its potential is the same as that of the source / drain electrode 314.

[0110] FIG. 12 shows an example of the structure of a pixel circuit including a switch TFT and a driver TFT having different S values. Differences from the example structure shown in FIG. 11 will be mainly described. FIG. 12 schematically shows an example of the cross-sectional structure of the switch TFT and the driver TFT. A switch TFT 350 and a driver TFT 370 are formed on a flexible or non-flexible insulating substrate 325 made of resin or glass. The switch TFT 350 has a structure described with reference to FIG. 5 except that the bottom gate electrode is removed. The driver TFT 370 has the structure described with reference to FIG. 5. The TFTs 350 and 370 can be formed simultaneously by the method described with reference to FIGS. 8A to 8D.

[0111] 11 , a top gate insulator 365 of the drive TFT 370 and a top gate insulator 367 of the switch TFT are present instead of the upper insulating layer 327. The top gate insulators 365 and 367 can be simultaneously formed by etching the insulating layer. The top gate insulator 365 is present between the top gate electrode 336 and the channel region 333 and does not overlap with the source / drain regions 331 and 332 in plan view. The top gate insulator 367 is present between the top gate electrode 316 and the channel region 313 and does not overlap with the source / drain regions 311 and 312 in plan view.

[0112] An interlayer insulating layer 368 is present in place of the interlayer insulating layer 328. The interlayer insulating layer 368 is in direct contact with and covers the source / drain regions 311, 312, 331, and 332. In the switch TFT 350, a contact portion 319 of the source / drain electrode 314 penetrates the interlayer insulating layer 368 and contacts (directly connects) with the source / drain region 311 within the hole of the interlayer insulating layer 368. A contact portion 320 of the source / drain electrode 315 penetrates the interlayer insulating layer 368 and contacts (directly connects) with the source / drain region 312 within the hole of the interlayer insulating layer 368.

[0113] In the driving TFT 370, a contact portion 339 of the source / drain electrode 334 penetrates the interlayer insulating layer 368 and makes contact (direct connection) with the source / drain region 331 within the hole of the interlayer insulating layer 368. A contact portion 340 of the source / drain electrode 335 penetrates the interlayer insulating layer 368 and makes contact (direct connection) with the source / drain region 332 within the hole of the interlayer insulating layer 368.

[0114] FIG. 13 shows an example of the structure of a circuit including two TFTs. The first and second TFTs have the same structure as the switch TFT 310 shown in FIG. 11. The configuration example shown in FIG. 13 uses low-resistance oxide as wiring. Specifically, the source / drain regions of the first TFT 410 and the source / drain regions of the second TFT 430 are connected by low-resistance oxide wiring (wiring portion) 440. This makes it possible to avoid contact resistance between the source / drain regions of the TFTs and the metal electrodes. The TFTs 410 and 430 are the first and third oxide semiconductor TFTs, and can be formed simultaneously by the method described with reference to FIGS. 7A to 7D.

[0115] The first TFT 410 and the second TFT 430 are present on a lower insulating layer 426 formed on a substrate 425. The first TFT 410 is disposed at a different position from the second TFT 430 in a plan view.

[0116] The first TFT 410 includes an oxide semiconductor layer 418. The oxide semiconductor layer 418 includes source / drain regions 411, 412, and a channel region 413 between the source / drain regions 411, 412 in the in-plane direction.

[0117] The source / drain regions 411 and 412 are regions in which the oxide semiconductor is made to have low resistance. The channel region 413 is a region in which the oxide semiconductor is not made to have low resistance. The source / drain regions 411 and 412 and the channel region 413 are each composed of a lower amorphous layer and an upper crystalline layer.

[0118] The first TFT 410 includes a top gate electrode 416. An upper insulating layer 427 is present between the top gate electrode 416 and an oxide semiconductor layer 418. The oxide semiconductor layer 418, the upper insulating layer 427, and the top gate electrode 416 are stacked in this order from below (from the substrate side), and the upper insulating layer 427 is in direct contact with the oxide semiconductor layer 418 and the top gate electrode 416. For example, a control signal for turning the first TFT 410 on and off is applied to the top gate electrode 416.

[0119] An interlayer insulating layer 428 is formed to cover the top gate electrode 416 and the upper insulating layer 427. The source / drain electrodes 415 pass through the interlayer insulating layer 428 and the upper insulating layer 427 and are directly connected to the source / drain regions 412. The tops of the source / drain electrodes 415 are in direct contact with the upper surface of the interlayer insulating layer 428.

[0120] The source / drain electrodes 415 include contact portions 420 that, in a plan view, penetrate the outside of the top gate electrode 416. The contact portions 420 penetrate the interlayer insulating layer 428 and the upper insulating layer 427, and are in direct contact with the source / drain regions 412.

[0121] The second TFT 430 includes an oxide semiconductor layer 438. The oxide semiconductor layer 438 includes source / drain regions 431, 432, and a channel region 433 between the source / drain regions 431, 432 in the in-plane direction.

[0122] The source / drain regions 431 and 432 are regions in which the oxide semiconductor is made to have low resistance. The channel region 433 is a region in which the oxide semiconductor is not made to have low resistance. The source / drain regions 431 and 432 and the channel region 433 are each composed of a lower amorphous layer and an upper crystalline layer.

[0123] The second TFT 430 includes a top gate electrode 436. An upper insulating layer 427 is present between the top gate electrode 436 and an oxide semiconductor layer 438. The oxide semiconductor layer 438, the upper insulating layer 427, and the top gate electrode 436 are stacked in this order from below (from the substrate side), and the upper insulating layer 427 is in direct contact with the oxide semiconductor layer 438 and the top gate electrode 436. For example, a control signal for turning the second TFT 430 ON / OFF is supplied to the top gate electrode 436.

[0124] An interlayer insulating layer 428 is formed to cover the top gate electrode 436 and the upper insulating layer 427. The source / drain electrodes 435 penetrate the interlayer insulating layer 428 and the upper insulating layer 427 and directly connect to the source / drain regions 432. The tops of the source / drain electrodes 435 are in direct contact with the upper surface of the interlayer insulating layer 428.

[0125] The source / drain electrodes 435 include contact portions 442 that, in a plan view, penetrate the outside of the top gate electrode 436. The contact portions 442 penetrate the interlayer insulating layer 428 and the upper insulating layer 427 and are in direct contact with the source / drain regions 432.

[0126] The oxide semiconductor layer 418 of the first TFT and the oxide semiconductor layer 438 of the second TFT are part of a continuous semiconductor layer film, and a wiring (wiring region) 440 exists between them. The wiring 440 is made of a low-resistance oxide. The source / drain region 411 of the oxide semiconductor layer 418, the wiring 440, and the source / drain region 431 of the oxide semiconductor layer 438 are continuous and are formed simultaneously using the same material.

[0127] For example, in the manufacturing process, the top gate electrodes 416 and 436 are used as a mask, and impurity ions are implanted into the oxide semiconductor through the insulating layer 427 to reduce its resistance, thereby simultaneously forming the source / drain region 411, the wiring 440, and the source / drain region 431. As described above, the first TFT 410 and the second TFT 430 are connected in series by the wiring 440 made of oxide with reduced resistance. This reduces the contact resistance between the oxide and metal of the TFT.

[0128] FIG. 14 shows an example of the structure of a circuit including two TFTs. The first TFT 450 and the second TFT 470 have the same structure as the switch TFT 310 shown in FIG. 11. The first TFT 450 and the second TFT 470 are a first oxide semiconductor TFT and a fourth oxide semiconductor TFT. In the example configuration shown in FIG. 14, the source output of one TFT is connected to the top gate electrode of the other TFT. The source output of one TFT drives the gate of the other crystalline channel, thereby increasing the operating speed. For example, this configuration can be applied to connections within the drivers 31 and 32, or to connections between the outputs of the drivers 31 and 32 and the gates of TFTs in pixel circuits.

[0129] A first TFT 450 and a second TFT 470 are formed on an insulating substrate 465. The TFTs 450 and 470 have a configuration in which the bottom gate electrode is removed from the configuration described with reference to Fig. 3. The TFTs 450 and 470 can be formed simultaneously by the method described with reference to Figs. 7A to 7D.

[0130] The first TFT 450 and the second TFT 470 are present on a lower insulating layer 466 formed on a substrate 465. The first TFT 450 is disposed at a different position from the second TFT 470 in a plan view.

[0131] The first TFT 450 includes an oxide semiconductor layer 458. The oxide semiconductor layer 458 is formed on and in direct contact with a lower insulating layer 466. The oxide semiconductor layer 458 includes source / drain regions 451, 452, and a channel region 453 between the source / drain regions 451, 452 in the in-plane direction.

[0132] The source / drain regions 451 and 452 are regions in which the oxide semiconductor is made to have low resistance. The channel region 453 is a region in which the oxide semiconductor is not made to have low resistance. As described with reference to FIG. 3, the source / drain regions 451 and 452 and the channel region 453 are each composed of a lower amorphous layer and an upper crystalline layer.

[0133] The first TFT 450 further includes a top gate electrode 456. An upper insulating layer 467 is present between the top gate electrode 456 and the oxide semiconductor layer 458. The oxide semiconductor layer 458, the upper insulating layer 467, and the top gate electrode 456 are stacked in this order from below (from the substrate side), and the upper insulating layer 467 is in direct contact with the oxide semiconductor layer 458 and the top gate electrode 456. For example, a control signal for turning the first TFT 450 on and off is applied to the top gate electrode 456.

[0134] An interlayer insulating layer 468 is formed to cover the top gate electrode 456 and the upper insulating layer 467. The source / drain electrodes 454, 455 pass through the interlayer insulating layer 468 and the upper insulating layer 467 and directly connect to the source / drain regions 451, 452, respectively. The tops of the source / drain electrodes 454, 455 are in direct contact with the upper surface of the interlayer insulating layer 468.

[0135] The source / drain electrodes 454, 455 include contact portions 459, 460, respectively, which penetrate the outside of the top gate electrode 456 in a plan view. The contact portion 459 penetrates the interlayer insulating layer 468 and the upper insulating layer 467, and is in direct contact with the source / drain region 451. The contact portion 460 penetrates the interlayer insulating layer 468 and the upper insulating layer 467, and is in direct contact with the source / drain region 452.

[0136] The second TFT 470 includes an oxide semiconductor layer 478. The oxide semiconductor layer 478 is formed on and in direct contact with the lower insulating layer 466. The oxide semiconductor layer 478 includes source / drain regions 471, 472, and a channel region 473 between the source / drain regions 471, 472 in the in-plane direction.

[0137] The source / drain regions 471 and 472 are regions in which the oxide semiconductor is made to have low resistance. The channel region 473 is a region in which the oxide semiconductor is not made to have low resistance. As described with reference to FIG. 3, the source / drain regions 471 and 472 and the channel region 473 are each composed of a lower amorphous layer and an upper crystalline layer.

[0138] The second TFT 470 further includes a top gate electrode 476. An upper insulating layer 467 is present between the top gate electrode 476 and the oxide semiconductor layer 478. The oxide semiconductor layer 478, the upper insulating layer 467, and the top gate electrode 476 are stacked in this order from below (from the substrate side), and the upper insulating layer 467 is in direct contact with the oxide semiconductor layer 478 and the top gate electrode 476. A control signal for turning the second TFT 470 ON / OFF is applied to the top gate electrode 476, for example.

[0139] An interlayer insulating layer 468 is formed to cover the top gate electrode 476 and the upper insulating layer 467. Source / drain electrodes 474, 475 pass through the interlayer insulating layer 468 and the upper insulating layer 467 and directly connect to the source / drain regions 471, 472, respectively. The tops of the source / drain electrodes 474, 475 are in direct contact with the upper surface of the interlayer insulating layer 468.

[0140] The source / drain electrodes 474, 475 each include contact portions 479, 480 that penetrate the outside of the top gate electrode 476 in a plan view. The contact portion 479 penetrates the interlayer insulating layer 468 and the upper insulating layer 467 and is in direct contact with the source / drain region 471. The contact portion 480 penetrates the interlayer insulating layer 468 and the upper insulating layer 467 and is in direct contact with the source / drain region 472.

[0141] The source / drain electrodes 454 of the first TFT 450 and the top gate electrode 476 of the second TFT 470 are connected by an interconnection 483. The interconnection 483 is continuous with the source / drain electrodes 454 and can be formed simultaneously using the same material. The interconnection 483 is directly connected to the top gate electrode 476.

[0142] The interconnection portion 483 includes a contact portion 484, which penetrates the interlayer insulating layer 468 and directly contacts the upper surface of the top gate electrode 476. The top gate electrode 476 is connected to the source / drain electrode 454 by the interconnection portion 483, and its potential is the same as that of the source / drain electrode 454.

[0143] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. Those skilled in the art can easily modify, add, or convert each element of the above embodiments within the scope of the present disclosure. It is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of symbols]

[0144] 102, 318, 338 Oxide semiconductor layer 103, 109, 313, 333 channel regions 105, 107, 311, 312, 331, 332 Source / drain regions 111, 113, 115, 151 Amorphous layer 112, 114, 116, 152 Crystal layer 117, 127, 135, 141, 326, 327 Insulating layer 118, 128, 328, 368 Interlayer insulation layer 121, 122, 314, 315, 334, 335, 354 Source / drain electrodes 123, 316, 336 Top gate electrode 125, 126, 319, 320, 324, 339, 340, 342 Contact part 133, 337 Bottom gate electrode 323, 341, 483 Interconnection 365, 367 Top gate insulator 410, 450 1st TFT 430, 470 2nd TFT 440 Wiring

Claims

1. An oxide semiconductor thin film transistor device, A substrate; one or more oxide semiconductor thin film transistors disposed over the substrate; the one or more oxide semiconductor thin film transistors include a first oxide semiconductor thin film transistor; The first oxide semiconductor thin film transistor is A first oxide semiconductor layer; a first top gate electrode disposed on an upper side of the first oxide semiconductor layer; A first source / drain electrode; Including, The first oxide semiconductor layer is a first channel region overlapping the first top gate electrode in a plan view; two first low resistance regions sandwiching the first channel region; Including, the first source / drain electrode is located above the first top gate electrode, penetrates an insulating region overlapping one of the two first low-resistance regions in a plan view, and contacts the one of the two first low-resistance regions; Each of the two first low resistance regions and the first channel region includes a lower amorphous layer and an upper crystalline layer having the same composition as the amorphous layer. Oxide semiconductor thin film transistor device.

2. 2. The oxide semiconductor thin film transistor device according to claim 1 , the crystalline layer is a layer in which an intensity peak is observed in an azimuth angle expansion of an electron beam diffraction intensity, The amorphous layer is a layer in which no intensity peak is observed in an azimuth angle expansion of electron beam diffraction intensity. Oxide semiconductor thin film transistor device.

3. 2. The oxide semiconductor thin film transistor device according to claim 1 , the degree of orientation of the crystal layers in the two first low resistance regions is smaller than the degree of orientation of the crystal layer in the first channel region; Oxide semiconductor thin film transistor device.

4. 4. The oxide semiconductor thin film transistor device according to claim 3, The degree of orientation of the crystal layer is represented by the magnitude of the intensity peak in the azimuth angle expansion of the electron beam diffraction intensity. Oxide semiconductor thin film transistor device.

5. 2. The oxide semiconductor thin film transistor device according to claim 1 , Further comprising a second oxide semiconductor thin film transistor, The second oxide semiconductor thin film transistor is A second oxide semiconductor layer; a second top gate electrode disposed on an upper side of the second oxide semiconductor layer; a bottom gate electrode disposed below the second oxide semiconductor layer; A second source / drain electrode; Including, The second oxide semiconductor layer is a second channel region overlapping the second top gate electrode and the bottom gate electrode in the plan view; two second low resistance regions sandwiching the second channel region; Including, the second source / drain electrode is located above the second top gate electrode, penetrates an insulating region overlapping one of the two second low-resistance regions in a plan view, and contacts the one of the two second low-resistance regions; each of the two second low resistance regions and the second channel region includes a lower amorphous layer and an upper crystalline layer having the same composition as the amorphous layer; the first oxide semiconductor thin film transistor is turned on / off in response to a control signal applied to the first top gate electrode; the second oxide semiconductor thin film transistor controls an amount of current flowing through the second channel region in response to a control signal applied to the bottom gate electrode; Oxide semiconductor thin film transistor device.

6. 6. The oxide semiconductor thin film transistor device according to claim 5, the degree of orientation of the crystal layer in the two second low resistance regions is smaller than the degree of orientation of the crystal layer in the second channel region; Oxide semiconductor thin film transistor device.

7. 6. The oxide semiconductor thin film transistor device according to claim 5, The first source / drain electrode is connected to the bottom gate electrode of the second oxide semiconductor thin film transistor. Oxide semiconductor thin film transistor device.

8. 6. The oxide semiconductor thin film transistor device according to claim 5, The second top gate electrode of the second oxide semiconductor thin film transistor is given a constant potential or is in a floating state. Oxide semiconductor thin film transistor device.

9. 8. The oxide semiconductor thin film transistor device according to claim 7, The second top gate electrode is connected to the second source / drain electrode having a lower potential. Oxide semiconductor thin film transistor device.

10. 2. The oxide semiconductor thin film transistor device according to claim 1 , Further comprising a third oxide semiconductor thin film transistor, The third oxide semiconductor thin film transistor is The third oxide semiconductor thin film transistor is A third oxide semiconductor layer; a third top gate electrode disposed on an upper side of the third oxide semiconductor layer; A third source / drain electrode; Including, The third oxide semiconductor layer is a third channel region overlapping the third top gate electrode in a plan view; two third low resistance regions sandwiching the third channel region; Including, the third source / drain electrode is located above the third top gate electrode, penetrates an insulating region overlapping one of the two third low-resistance regions in a plan view, and contacts the one of the two third low-resistance regions; each of the two third low resistance regions and the third channel region includes a lower amorphous layer and an upper crystalline layer having the same composition as the amorphous layer; the first oxide semiconductor layer and the third oxide semiconductor layer are disposed on the same insulating layer; a low-resistance oxide semiconductor layer extending from the other of the first low-resistance region is connected to the other of the third low-resistance region; Oxide semiconductor thin film transistor device.

11. 2. The oxide semiconductor thin film transistor device according to claim 1 , a fourth oxide semiconductor thin film transistor; The fourth oxide semiconductor thin film transistor is a fourth oxide semiconductor layer; a fourth top gate electrode disposed on an upper side of the fourth oxide semiconductor layer; A fourth source / drain electrode; Including, The fourth oxide semiconductor layer is a fourth channel region overlapping the fourth top gate electrode in a plan view; two fourth low resistance regions sandwiching the fourth channel region; Including, the fourth source / drain electrode is located above the fourth top gate electrode, penetrates an insulating region overlapping one of the two fourth low-resistance regions in a plan view, and contacts the one of the two fourth low-resistance regions; each of the two fourth low resistance regions and the fourth channel region includes a lower amorphous layer and an upper crystalline layer having the same composition as the amorphous layer; the first source / drain electrode is connected to the fourth top gate electrode so as to have the same potential as the fourth top gate electrode; Oxide semiconductor thin film transistor device.

12. A method for manufacturing an oxide semiconductor thin film transistor device, comprising the steps of: forming an oxide semiconductor layer; forming a gate insulating layer on the oxide semiconductor layer; forming a top gate electrode on the gate insulating layer; forming a low resistance region in the oxide semiconductor layer by a low resistance treatment using the top gate electrode as a mask; The formation of the oxide semiconductor layer includes forming a lower amorphous layer and then forming an upper crystalline layer. Manufacturing method.

13. The method of claim 12, further comprising the steps of: After forming the top gate electrode, a portion of the gate insulating layer is removed by etching outside the top gate electrode to expose a portion of the oxide semiconductor layer; the resistance reducing treatment is performed by subjecting an exposed portion of the oxide semiconductor layer to a plasma treatment; Manufacturing method.

14. The method of claim 12, further comprising the steps of: The resistance reducing process is performed by performing an ion implantation process through the gate insulating layer to form the resistance reducing region. Manufacturing method.

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