Semiconductor device

Abstract

To provide a semiconductor device improved in reliability and performance.SOLUTION: A semiconductor device comprises: an element isolation structure 165, 166 including sidewalls extending in a first direction D1; a first fin-shaped pattern 110 being in contact with a first sidewall of the element isolation structure and extending in a second direction; a second fin-shaped pattern 210 extending in the second direction D2; a first gate electrode 120 extending in the first direction on the first fin-shaped pattern; a first source / drain contact 171 extending in the first direction; and a wiring structure disposed on and connected to the contact. The contact includes: a first lower contact region 181B intersecting the first fin-shaped pattern and the second fin-shaped pattern; a first upper contact region 181UC protruding from the first lower contact region; and a first dummy contact region 181UD. The wiring structure is in contact with an upper surface of the first upper contact region and not in contact with an upper surface of the first dummy contact region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having improved reliability and performance. [Background technology]

[0002] As one of the scaling technologies for increasing the density of semiconductor devices, a multi-gate transistor has been proposed in which a multi-channel active pattern (or silicon body) in the shape of a fin or nanowire is formed on a substrate and a gate is formed on the surface of the multi-channel active pattern.

[0003] Such multi-gate transistors are easy to scale because they use a three-dimensional channel. Moreover, the current control capability can be improved without increasing the gate length of the multi-gate transistor. In addition, it is possible to effectively suppress the short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage. Improving the reliability and performance of such multi-gate transistors presents further challenges. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 59-228762 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned problems with the conventional multi-gate transistors, and an object of the present invention is to provide a semiconductor device with improved reliability and performance. The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] In order to achieve the above object, a semiconductor device according to the present invention includes an isolation structure including a first sidewall and a second sidewall extending in a first direction, the first sidewall of the isolation structure being opposite to a second sidewall of the isolation structure in a second direction, a first fin-type pattern contacting the first sidewall of the isolation structure and extending in the second direction, a second fin-type pattern contacting the second sidewall of the isolation structure and extending in the second direction, spaced apart from the first fin-type pattern in the first direction, a first gate electrode extending in the first direction on the first fin-type pattern, and a second fin-type pattern contacting the second sidewall of the isolation structure and extending in the second direction, the first source / drain contact is disposed on a first fin-type pattern and the second fin-type pattern and extends in the first direction; and a wiring structure on the first source / drain contact is connected to the first source / drain contact, the first source / drain contact includes a first lower contact region intersecting the first fin-type pattern and the second fin-type pattern, a first upper contact region protruding from the first lower contact region, and a first dummy contact region, the wiring structure being in contact with an upper surface of the first upper contact region but not in contact with an upper surface of the first dummy contact region.

[0007] In order to achieve the above object, a semiconductor device according to the present invention includes a first fin type pattern extending in a first direction, a second fin type pattern spaced apart from the first fin type pattern in a second direction and extending in the first direction, a third fin type pattern extending in the first direction, a fourth fin type pattern spaced apart from the third fin type pattern in the second direction and extending in the first direction, an element isolation structure in contact with the first fin type pattern and the second fin type pattern and extending in the second direction, a first gate electrode extending in the second direction on the first fin type pattern, a second gate electrode extending in the second direction on the third fin type pattern, a third gate electrode extending in the second direction on the fourth fin type pattern, a first source / drain contact disposed on the first fin type pattern and the second fin type pattern between the first gate electrode and the element isolation structure and extending in the second direction, and a second source / drain contact disposed on the third fin type pattern and the fourth fin type pattern between the second gate electrode and the third gate electrode and extending in the second direction. and a wiring structure disposed on the first source / drain contacts and the second source / drain contacts and connected to the first source / drain contacts and the second source / drain contacts, the first source / drain contacts including a first lower contact region intersecting the first fin-type pattern and the second fin-type pattern and a first upper contact region protruding from the first lower contact region, the second source / drain contacts including a second lower contact region intersecting the third fin-type pattern and the fourth fin-type pattern and a second upper contact region protruding from the second lower contact region, the wiring structure including a via plug in contact with the first upper contact region and the second upper contact region, a bottom surface of the via plug having a via width in the second direction, a width of an upper surface of the first upper contact region in the second direction being greater than or equal to 1.5 times the via width, and a width of an upper surface of the second upper contact region in the second direction being greater than or equal to the via width and less than or equal to 1.2 times the via width.

[0008] In order to achieve the above object, a semiconductor device according to the present invention includes a first fin type pattern extending in a first direction, a second fin type pattern spaced apart from the first fin type pattern in a second direction and extending in the first direction, a third fin type pattern spaced apart from the first fin type pattern in the first direction and extending in the first direction, a fourth fin type pattern spaced apart from the second fin type pattern in the first direction and extending in the first direction, a first source / drain contact disposed on the first fin type pattern and the second fin type pattern and extending in the second direction, a second source / drain contact disposed on the third fin type pattern and the fourth fin type pattern and extending in the second direction, and a semiconductor device extending in the second direction separating the first fin type pattern and the third fin type pattern, and the second fin type pattern and the fourth fin type pattern. the first source / drain contact includes a first lower contact region intersecting the first fin-type pattern and the second fin-type pattern, a first upper contact region protruding from the first lower contact region, and a first dummy contact region; the second source / drain contact includes a second lower contact region intersecting the third fin-type pattern and the fourth fin-type pattern, and a second upper contact region protruding from the second lower contact region; and the wiring structure is in contact with an upper surface of the first upper contact region and an upper surface of the second upper contact region, but is not in contact with an upper surface of the first dummy contact region. Effect of the Invention

[0009] According to the semiconductor device of the present invention, by having a configuration including a fin field effect transistor (FinFET) including a channel region in a fin pattern shape, a transistor including a nanowire or a nanosheet, and an MBCFET (registered trademark) (Multi-Bridge Channel Field Effect Transistor), it is possible to provide a semiconductor device with improved reliability and performance. [Brief description of the drawings]

[0010] [Figure 1] 1 is a schematic layout diagram of a semiconductor device according to an embodiment of the present invention; [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] FIG. 2 is a cross-sectional view taken along line CC in FIG. [Diagram 5] FIG. 2 is a cross-sectional view taken along line DD in FIG. [Figure 6] FIG. 2 is a cross-sectional view taken along line EE in FIG. [Figure 7] FIG. 2 is a cross-sectional view taken along line FF in FIG. [Figure 8] FIG. 2 is a cross-sectional view taken along line GG in FIG. [Figure 9] FIG. 7 is an enlarged view of a portion P in FIG. 6. [Figure 10] FIG. 11 is a schematic layout diagram of a semiconductor device according to another embodiment of the present invention. [Figure 11] FIG. 11 is a cross-sectional view taken along line CC in FIG. [Figure 12] FIG. 11 is a cross-sectional view taken along line DD in FIG. [Figure 13] FIG. 11 is a schematic layout diagram of a semiconductor device according to another embodiment of the present invention. [Figure 14] FIG. 11 is a schematic layout diagram of a semiconductor device according to another embodiment of the present invention. [Figure 15]FIG. 15 is a cross-sectional view taken along line DD in FIG. [Figure 16] FIG. 11 is a schematic layout diagram of a semiconductor device according to another embodiment of the present invention. [Figure 17] FIG. 17 is a cross-sectional view taken along line DD in FIG. 16. [Figure 18] FIG. 11 is a schematic layout diagram of a semiconductor device according to another embodiment of the present invention. [Figure 19] FIG. 19 is a cross-sectional view taken along line DD in FIG. 18. [Figure 20] FIG. 11 is a schematic layout diagram of a semiconductor device according to another embodiment of the present invention. [Figure 21] 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention taken along line CC in FIG. 1. [Figure 22] 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention taken along line CC in FIG. 1. [Figure 23] 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention taken along line CC in FIG. 1. [Figure 24] 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention taken along line CC in FIG. 1. [Diagram 25] 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention taken along line GG in FIG. 1. [Figure 26] FIG. 11 is a schematic layout diagram of a semiconductor device according to another embodiment of the present invention. [Figure 27] FIG. 27 is a cross-sectional view taken along line AA in FIG. 26. [Figure 28] FIG. 27 is a cross-sectional view taken along line AA in FIG. 26. [Figure 29] 27 is a cross-sectional view taken along line CC in FIG. 26. [Diagram 30] FIG. 27 is a cross-sectional view taken along line FF in FIG. 26. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Next, specific examples of embodiments for carrying out the semiconductor device according to the present invention will be described with reference to the drawings.

[0012] In the drawings relating to the semiconductor device according to the embodiment of the present invention, as examples, a FinFET including a channel region having a fin-shaped pattern, a transistor including a nanowire or nanosheet, and a Multi-Bridge Channel Field Effect Transistor (MBCFET) (registered trademark) are shown. However, semiconductor devices according to embodiments of the present invention may include tunneling transistors, three-dimensional (3D) transistors, planar transistors, and 2D material based FETs and their heterostructures. Additionally, the semiconductor device according to the embodiment of the present invention may include a bipolar junction transistor, a lateral double-diffused transistor (LDMOS), and the like.

[0013] FIG. 1 is a schematic layout diagram of a semiconductor device according to an embodiment of the present invention. 2 to 8 are cross-sectional views taken along lines AA, BB, CC, DD, EE, FF and GG in FIG. 1, respectively. FIG. 9 is an enlarged view of a portion P in FIG. For convenience of explanation, interlayer insulating films (190, 191, 192), wiring structure 205, and the like are not shown in FIG.

[0014] 1 to 9, a semiconductor device according to an embodiment of the present invention includes, on a substrate 100, first to sixth fin-type patterns (110, 210, 310, 410, 510, 610), first to third gate electrodes (120, 220, 320), first and second element isolation structures (165, 166), a first source / drain contact 171, a second source / drain contact 172, first and second interconnected source / drain contacts (181, 182), and a gate isolation structure 160.

[0015] For example, the substrate 100 can be bulk silicon or silicon-on-insulator (SOI). As another example, the substrate 100 can be a silicon substrate or can include other materials, such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0016] The first fin-type pattern 110 , the third fin-type pattern 310 , and the fifth fin-type pattern 510 are disposed on the substrate 100 . The first fin-type pattern 110, the third fin-type pattern 310, and the fifth fin-type pattern 510 are formed in a first active region RX1 of the substrate 100. The first fin type pattern 110, the third fin type pattern 310, and the fifth fin type pattern 510 extend long along a first direction D1. The first fin type pattern 110, the third fin type pattern 310, and the fifth fin type pattern 510 are aligned in a line along a first direction D1. The first fin-type pattern 110 and the third fin-type pattern 310 are defined by a fin trench FT extending in a first direction D1.

[0017] The fin trench FT defines the sidewalls of the first fin-type pattern 110 and the third fin-type pattern 310 . The fifth fin-type pattern 510 is defined by a fin trench FT. The second fin-type pattern 210 , the fourth fin-type pattern 410 , and the sixth fin-type pattern 610 are disposed on the substrate 100 . The second fin-type pattern 210, the fourth fin-type pattern 410, and the sixth fin-type pattern 610 are formed in the second active region RX2. The second fin type pattern 210, the fourth fin type pattern 410, and the sixth fin type pattern 610 extend long along a first direction D1. The second fin type pattern 210, the fourth fin type pattern 410, and the sixth fin type pattern 610 are aligned in a line along a first direction D1.

[0018] The second fin-type pattern 210 and the fourth fin-type pattern 410 are defined by fin trenches FT extending in a first direction D1. The second fin pattern 210 is spaced apart from the first fin pattern 110 in the second direction D2. The fourth fin pattern 410 is spaced apart from the third fin pattern 310 in the second direction D2. The sixth fin pattern 610 is spaced apart from the fifth fin pattern 510 in the second direction D2. Here, the first direction D1 intersects with the second direction D2 and the third direction D3. In addition, the second direction D2 intersects with the third direction D3. The third direction D3 is a direction perpendicular to the upper surface of the substrate 100.

[0019] The field region FX is disposed between the first active region RX1 and the second active region RX2. The field region FX is defined by a deep trench DT that is deeper than the fin trench FT. The deep trench DT defines a first active region RX1 and a second active region RX2. For example, the deep trench DT extends long in the first direction D1. The deep trenches DT are continuously formed between the first fin type pattern 110 and the second fin type pattern 210, between the third fin type pattern 310 and the fourth fin type pattern 410, and between the fifth fin type pattern 510 and the sixth fin type pattern 610. In the semiconductor device according to the embodiment, the deep trench DT separates a first active region RX1 and a second active region RX2.

[0020] For example, one of the first active region RX1 and the second active region RX2 may be an NMOS forming region, and the other may be a PMOS forming region. As another example, the first active region RX1 and the second active region RX2 may be a PMOS formation region. As another example, the first active region RX1 and the second active region RX2 may be NMOS formation regions.

[0021] The first to sixth fin-type patterns (110, 210, 310, 410, 510, 610) are each a part of the substrate 100, and include an epitaxial layer grown from the substrate 100. Each of the first to sixth fin-type patterns (110, 210, 310, 410, 510, 610) may include, for example, an elemental semiconductor material such as silicon or germanium. Furthermore, each of the first to sixth fin-type patterns (110, 210, 310, 410, 510, 610) may include a compound semiconductor, for example, a IV-IV group compound semiconductor or a III-V group compound semiconductor.

[0022] The IV-IV compound semiconductor may be, for example, a binary compound containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), a ternary compound, or a compound doped with a Group IV element. The III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as a group III element with one of phosphorus (P), arsenic (As), and antimonium (Sb) as a group V element.

[0023] As an example, the fin-type pattern (110, 310, 510) disposed in the first active region RX1 includes the same material as the fin-type pattern (210, 410, 610) disposed in the second active region RX2. As another example, the fin-type pattern (110, 310, 510) disposed in the first active region RX1 may include other materials than the fin-type pattern (210, 410, 610) disposed in the second active region RX2.

[0024] The first fin pattern 110 and the second fin pattern 210 will be taken as examples for explanation. Although the number of the first fin-type patterns 110 arranged in the first active region RX1 is shown to be the same as the number of the second fin-type patterns 210 arranged in the second active region RX2, this is not limited thereto. For example, the figure shows a case in which there are two first fin-type patterns 110 arranged in the first active region RX1 and two second fin-type patterns 210 arranged in the second active region RX2, but this is not limited to this. Of course, the number of the first fin-type patterns 110 disposed in the first active region RX1 and the number of the second fin-type patterns 210 disposed in the second active region RX2 may be one or more than two.

[0025] The following description will be given using the first to fourth fin patterns (110, 210, 310, 410). The field insulating film 105 is disposed around the first to fourth fin patterns (110, 210, 310, 410). Although not shown in the figure, the field insulating film 105 may be disposed around the fifth fin-type pattern 510 and the sixth fin-type pattern 610. The field insulating film 105 fills the deep trench DT. The field insulating film 105 fills a part of the fin trench FT. Taking the first fin-type pattern 110 and the second fin-type pattern 210 as an example, the field insulating film 105 is formed on a part of the sidewall of the first fin-type pattern 110 and a part of the sidewall of the second fin-type pattern 210 .

[0026] The first to fourth fin patterns (110, 210, 310, 410) protrude above the upper surface of the field insulating film 105, respectively. The fifth fin-type pattern 510 and the sixth fin-type pattern 610 also protrude from the upper surface of the field insulating film 105 . The field insulating film 105 may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

[0027] The first isolation structure 165 and the second isolation structure 166 are disposed across the first active region RX1 and the second active region RX2, respectively. The first element isolation structure 165 and the second element isolation structure 166 each extend long in the second direction D2. The first element isolation structure 165 separates the first fin-type pattern 110 and the third fin-type pattern 310 adjacent to each other in the first direction D1. The first isolation structure 165 separates the second fin-type pattern 210 and the fourth fin-type pattern 410 adjacent to each other in the first direction D1. The second element isolation structure 166 separates the third fin-type pattern 310 and the fifth fin-type pattern 510 adjacent to each other in the first direction D1. The second isolation structure 166 separates the fourth fin-type pattern 410 and the sixth fin-type pattern 610, which are adjacent to each other in the first direction D1. The description of the second element isolation structure 166 is substantially the same as the description of the first element isolation structure 165, so the following description will focus on the first element isolation structure 165.

[0028] The first isolation structure 165 includes a first sidewall (165_LS1) and a second sidewall (165_LS2). A first sidewall (165_LS1) of the first isolation structure and a second sidewall (165_LS2) of the first isolation structure each extend long in a second direction D2. The first sidewall (165_LS1) of the first isolation structure is located opposite to the second sidewall (165_LS2) of the first isolation structure in the first direction D1.

[0029] The first fin-type pattern 110 and the second fin-type pattern 210 each contact the first sidewall (165_LS1) of the first isolation structure. The first fin-type pattern 110 and the second fin-type pattern 210 extend in a first direction D1 from a first sidewall 165_LS1 of the first isolation structure. The third fin-type pattern 310 and the fourth fin-type pattern 410 each contact the second sidewall (165_LS2) of the first isolation structure. The third fin-type pattern 310 and the fourth fin-type pattern 410 extend in a first direction D1 from the second sidewall 165_LS2 of the first isolation structure. For example, the upper surface 165US of the first element isolation structure is placed in the same plane as the upper surface of the gate capping pattern (145, 245, 345) described below.

[0030] The first element isolation structure 165 and the second element isolation structure 166 may be made of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), and combinations thereof. Each of the first isolation structure 165 and the second isolation structure 166 may be a single layer or multiple layers. For example, as shown in FIG. 2, the isolation structure spacer 165SP extends along a portion of the first sidewall (165_LS1) of the first isolation structure. The isolation structure spacer 165SP extends along a portion of the second sidewall (165_LS2) of the first element isolation structure.

[0031] The isolation structure spacers 165SP contain the same material as the gate spacers (140, 240, 340) described below. As another example, the isolation structure spacer 165SP does not have to be disposed on the sidewalls (165_LS1, 165_LS2) of the first element isolation structure.

[0032] The first to third gate electrodes (120, 220, 320) each extend in a second direction D2. The first to third gate electrodes (120, 220, 320) are disposed on the field insulating film 105, respectively. The first gate electrode 120 is disposed on the first active region RX1 and is not disposed on the second active region RX2. For example, the first gate electrode 120 is disposed only on the first active region RX1. The first gate electrode 120 is disposed on the fin-type pattern (110, 310, 510) disposed in the first active region RX1. The first gate electrode 120 is not disposed on the fin-type patterns (210, 410, 610) disposed in the second active region RX2.

[0033] The second gate electrode 220 is disposed on the second active region RX2 and is not disposed on the first active region RX1. For example, the second gate electrode 220 is disposed only on the second active region RX2. The second gate electrode 220 is disposed on the fin-type pattern (210, 410, 610) disposed in the second active region RX2. The second gate electrode 220 is not disposed on the fin-type pattern (110, 310, 510) disposed in the first active region RX1. The third gate electrode 320 is disposed continuously across the first active region RX1 and the second active region RX2. The third gate electrode 320 is disposed on the fin-type pattern (110, 310, 510) disposed in the first active region RX1. The third gate electrode 320 is disposed on the fin-type pattern (210, 410, 610) disposed in the second active region RX2.

[0034] The first gate electrode 120 and the second gate electrode 220 are spaced apart from each other in the second direction D2 and aligned with each other in the second direction D2. The first gate electrode 120 is disposed to correspond to the second gate electrode 220 . The third gate electrode 320 is spaced apart from the first gate electrode 120 in the first direction D1. The third gate electrode 320 is spaced apart from the second gate electrode 220 in the first direction D1. For example, as shown in FIG. 1, the first gate electrodes 120 and the second gate electrodes 220 have a one-to-one correspondence. As another example, at least one of the first gate electrodes 120 may be disposed in the second active region RX2 and may face an insulating material gate extending in the second direction D2. As another example, at least one of the second gate electrodes 220 is disposed in the first active region RX1 and faces an insulating material gate extending in the second direction D2. The insulating material gates are similar to the isolation structures (165, 166) described above.

[0035] For example, as shown in FIGS. 2 and 3, the upper surface of the gate electrode (120, 220, 320) includes a concave curved surface. Before forming a gate capping pattern (145, 245, 345) described below, a portion of the gate electrode (120, 220, 320) is removed. The etching process that removes a portion of the gate electrode (120, 220, 320) may turn at least a portion of the top surface of the gate electrode (120, 220, 320) into a concave curved surface. For example, the top surface of the first gate electrode 120 and the top surface of the second gate electrode 220 have a concave shape in the cross-sectional view of FIG.

[0036] The first to third gate electrodes (120, 220, 320) are each made of, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride, etc. The metal oxide may include at least one of titanium (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof.

[0037] The first to third gate electrodes (120, 220, 320) may each include a conductive metal oxide, a conductive metal oxynitride, or the like, and may include the oxidized forms of the above-mentioned materials. The first gate electrode 120 and the second gate electrode 220 are separated by a gate isolation structure 160 . The gate isolation structure 160 separates the first gate electrode 120 and the second gate electrode 220 in a second direction D2. A gate isolation structure 160 is disposed on the field region FX. A gate isolation structure 160 is disposed on the field dielectric 105 . The gate isolation structure 160 separates the corresponding first and second gate electrodes 120 and 220 from each other.

[0038] The gate isolation structure 160 may be made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), and combinations thereof. Although the gate isolation structure 160 is shown as being a single film, it is not limited thereto. For example, as shown in FIG. 8, a portion of the gate isolation structure 160 is recessed into the field insulating film 105, but the present invention is not limited to this. An upper surface 160US of the gate isolation structure is flush with an upper surface of the first gate capping pattern 145 and an upper surface of the second gate capping pattern 245 .

[0039] The first gate spacers 140 are disposed on the sidewalls of the first gate electrode 120 . The second gate spacers 240 are disposed on the sidewalls of the second gate electrode 220 . The third gate spacers 340 are disposed on the sidewalls of the third gate electrode 320 . The first to third gate spacers (140, 240, 340) extend along the second direction D2. The first to third gate spacers (140, 240, 340) are made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0040] The first gate insulating film 130 extends along the sidewalls and bottom surface of the first gate electrode 120 . The first gate insulating film 130 is disposed between the first gate electrode 120 and the fin-type pattern (110, 310, 510) disposed in the first active region RX1. The second gate insulating film 230 extends along the sidewalls and bottom surface of the second gate electrode 220 . The second gate insulating film 230 is disposed between the second gate electrode 220 and the fin-type pattern (210, 410, 610) disposed in the second active region RX2. The third gate insulating film 330 extends along the sidewalls and bottom surface of the third gate electrode 320 . The third gate insulating film 330 is disposed between the third gate electrode 320 and the fin-type pattern (110, 310, 510) disposed in the first active region RX1. The third gate insulating film 330 is disposed between the third gate electrode 320 and the fin-type pattern (210, 410, 610) disposed in the second active region RX2.

[0041] For example, as shown in FIG. 8, the first gate insulating film 130 is formed along the profile of the third fin-type pattern 310 protruding above the field insulating film 105 and along the upper surface of the field insulating film 105 . The second gate insulating film 230 is formed along the profile of the fourth fin-type pattern 410 protruding above the field insulating film 105 and along the upper surface of the field insulating film 105 . For example, as shown in FIG. 7, the third gate insulating layer 330 is formed along the profiles of the first fin-type pattern 110 and the second fin-type pattern 210 protruding above the field insulating layer 105 and along the top surface of the field insulating layer 105 . For example, the first gate insulating film 130 includes an interface film along the profile of the third fin-type pattern 310 protruding above the field insulating film 105 . For example, the interfacial film may include, but is not limited to, silicon oxide.

[0042] For example, as shown in FIG. 8, the first gate insulating film 130 extends along the sidewalls of the first gate electrode 120 and the sidewalls of the gate isolation structure 160 facing in the second direction D2. The second gate insulating film 230 extends along the sidewalls of the second gate electrode 220 and the sidewalls of the gate isolation structure 160 facing in the second direction D2. The first to third gate insulating films (130, 230, 330) may include silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide.

[0043] The high dielectric constant material may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0044] A semiconductor device according to an embodiment includes an NC (Negative Capacitance) FET using a negative capacitance. For example, the first to third gate insulating films (130, 230, 330) each include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties. The ferroelectric material film has a negative capacitance, and the paraelectric material film has a positive capacitance. For example, when two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance is less than the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the total capacitance has a positive value and may be greater than the absolute value of each individual capacitance.

[0045] When a ferroelectric material layer having a negative capacitance and a paraelectric material layer having a positive capacitance are connected in series, the total capacitance value of the series-connected ferroelectric material layer and paraelectric material layer increases. With this increased overall capacitance, a transistor including a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature. The ferroelectric material film has ferroelectric properties.

[0046] The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide is a material in which hafnium oxide is doped with zirconium (Zr). As another example, hafnium zirconium oxide is a compound of hafnium (Hf), zirconium (Zr) and oxygen (O).

[0047] The ferroelectric material film further includes a dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant contained in the ferroelectric material layer varies depending on the type of ferroelectric material contained in the ferroelectric material layer. When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0048] When the dopant is aluminum (Al), the ferroelectric material film may contain 3 to 8 at % (atomic %) of aluminum. Here, the ratio of the dopant is the ratio of aluminum to the sum of hafnium and aluminum. When the dopant is silicon (Si), the ferroelectric material film contains 2 to 10 at % of silicon. When the dopant is yttrium (Y), the ferroelectric material film contains 2 to 10 at % of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film contains 1 to 7 at % of gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film contains 50 to 80 at % of zirconium.

[0049] The paraelectric material film has paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide. The ferroelectric material film and the paraelectric material film include the same material. A ferroelectric material film has ferroelectric properties, whereas a paraelectric material film does not necessarily have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric material layer may be different from the crystal structure of the hafnium oxide contained in the paraelectric material layer.

[0050] The ferroelectric material film has a thickness such that it has ferroelectric properties. The thickness of the ferroelectric material film is, for example, 0.5 to 10 nm. Since each ferroelectric material has a different critical thickness at which it exhibits ferroelectric properties, the thickness of the ferroelectric material film varies depending on the ferroelectric material. As an example, each of the first to third gate insulating layers 130, 230, and 330 includes a ferroelectric material layer. As another example, each of the first to third gate insulating layers (130, 230, 330) may include a plurality of ferroelectric material layers spaced apart from each other. Each of the first to third gate insulating films (130, 230, 330) has a laminated film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately laminated.

[0051] The first to third gate capping patterns (145, 245, 345) are disposed on the first to third gate electrodes (120, 220, 320). In addition, the first to third gate capping patterns (145, 245, 345) are disposed on the upper surfaces of the first to third gate spacers (140, 240, 340). The first to third gate capping patterns (145, 245, 345) are each made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof.

[0052] Unlike the illustration, the first to third gate capping patterns (145, 245, 345) may be disposed between the first to third gate spacers (140, 240, 340), respectively. In this case, taking the first gate capping pattern 145 as an example, the top surface of the first gate capping pattern 145 is flush with the top surface of the first gate spacer 140 . The first source / drain pattern 150 is disposed on the first fin-type pattern 110 . The first source / drain pattern 150 is connected to the first fin-shaped pattern 110 . The third source / drain pattern 350 is disposed on the third fin-type pattern 310 . The third source / drain pattern 350 is connected to the third fin-shaped pattern 310 . The first source / drain pattern 150 and the third source / drain pattern 350 are disposed in the first active region RX1.

[0053] The second source / drain pattern 250 is disposed on the second fin-type pattern 210 . The second source / drain pattern 250 is connected to the second fin-shaped pattern 210 . A fourth source / drain pattern 450 is disposed on the fourth fin-type pattern 410 . The fourth source / drain pattern 450 is connected to the fourth fin-shaped pattern 410 . The second source / drain pattern 250 and the fourth source / drain pattern 450 are disposed in the second active region RX2. The second source / drain pattern 250 is separated from the first source / drain pattern 150 in a second direction D2. That is, the second source / drain pattern 250 is not directly connected to the first source / drain pattern 150 . The third source / drain pattern 350 is separated from the fourth source / drain pattern 450 in the second direction D2.

[0054] The first source / drain pattern 150 is connected to the plurality of first fin-type patterns 110 . The second source / drain pattern 250 is connected to the plurality of second fin-type patterns 210 . The third source / drain pattern 350 is connected to the plurality of third fin-type patterns 310 . The fourth source / drain pattern 450 is connected to the plurality of fourth fin-type patterns 410 . The first to fourth source / drain patterns (150, 250, 350, 450) are each a shared epitaxial pattern.

[0055] The first to fourth source / drain patterns (150, 250, 350, 450) are included in the source / drain of a transistor that uses the first to fourth fin-type patterns (110, 210, 310, 410) as a channel region, respectively. For example, a source / drain pattern is disposed on the fifth fin-type pattern 510 and the sixth fin-type pattern 610. The following description will be given using the first to fourth source / drain patterns (150, 250, 350, 450).

[0056] The source / drain etch stop layer 156 is disposed on the sidewalls of the first to third gate electrodes (120, 220, 320) and on the first to fourth source / drain patterns (150, 250, 350, 450). The source / drain etch stop layer 156 includes a material having an etch selectivity with respect to a lower interlayer insulating layer 190, which will be described later. The source / drain etch stop layer 156 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0057] A lower interlayer insulating layer 190 is disposed on the source / drain etch stop layer 156 . The lower interlayer insulating film 190 does not cover the upper surfaces of the first to third gate capping patterns (145, 245, 345). For example, the upper surface of the lower interlayer insulating film 190 may be flush with the upper surfaces of the first gate capping pattern 145 , the second gate capping pattern 245 , and the third gate capping pattern 345 . The upper surface of the lower interlayer insulating film 190 is placed in the same plane as the upper surface 165US of the first element structure. The lower interlayer insulating layer 190 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0058] Examples of low dielectric constant materials include Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane(HSQ), Bis-benzoCycloButene(BCB), TetraMethylOrthoSilicate(TMOS), OctaMethylCloTetraSiloxane(OMCTS), HexaMethylDiSiloxane(HMDS), TriMethylSilyl Borate(TMSB), DiAcetoxyDitertiaryButoSiloxane(DADBS), TriMethylSilil Polyimide nanofoams like Phosphate(TMSP), PolyTetraFluoroEthylene(PTFE), TOSZ(Tonen SilaZen), FSG(Fluoride Silicate Glass), polypropylene oxide, CDO(Carbon Doped silicon Oxide), OSG(Organo Silicate Glass), SiLK, Amorphous Fluorinated These may include, but are not limited to, carbon, silica aerogels, silica xerogels, mesoporous silica, or combinations thereof.

[0059] A first connecting source / drain contact 181 and a second connecting source / drain contact 182 are disposed across the first active region RX1 and the second active region RX2. The first connection source / drain contact 181 and the second connection source / drain contact 182 each extend long in the second direction D2. The first connection source / drain contact 181 and the second connection source / drain contact 182 are disposed on the source / drain patterns (150, 350) disposed in the first active region RX1 and the source / drain patterns (250, 450) disposed in the second active region RX2. The first connection source / drain contact 181 and the second connection source / drain contact 182 are simultaneously connected to the source / drain patterns (150, 350) disposed in the first active region RX1 and the source / drain patterns (250, 450) disposed in the second active region RX2. The first connection source / drain contact 181 and the second connection source / drain contact 182 are disposed on the fin-type pattern (110, 310) disposed on the first active region RX1 and the fin-type pattern (210, 410) disposed on the second active region RX2.

[0060] The first source / drain contact 171 is disposed on the source / drain pattern (150, 350) disposed in the first active region RX1. The second source / drain contact 172 is disposed on the source / drain pattern (250, 450) disposed in the second active region RX2. The first source / drain contact 171 is connected to the first and third source / drain patterns 150 and 350, but is not connected to the second and fourth source / drain patterns 250 and 450. The second source / drain contact 172 is connected to the second and fourth source / drain patterns 250 and 450, but is not connected to the first and third source / drain patterns 150 and 350.

[0061] For example, the second connection source / drain contact 182 , the first source / drain contact 171 , and the second source / drain contact 172 may be additionally disposed on the first source / drain pattern 150 and / or the second source / drain pattern 250 . The first connecting source / drain contact 181, the second connecting source / drain contact 182, the first source / drain contact 171 and the second source / drain contact 172 are disposed in the lower interlayer insulating film 190, respectively.

[0062] The first silicide film 155 is formed between the first source / drain pattern 150 and the source / drain contacts (181, 182, 171). A second silicide film 255 is formed between the second source / drain pattern 250 and the source / drain contacts (181, 182, 172). A third silicide film 355 is formed between the third source / drain pattern 350 and the source / drain contacts (181, 182, 171). A fourth silicide film 455 is formed between the fourth source / drain pattern 250 and the source / drain contacts (181, 182, 172). The first to fourth silicide films (155, 255, 355, 455) may each include, for example, a metal silicide material.

[0063] The first interconnecting source / drain contacts 181 are disposed between the element isolation structures (165, 166) and the gate electrodes (120, 220, 320). An isolation structure (165, 166) is disposed on one side of the first connection source / drain contact 181, and a gate electrode (120, 220, 320) is disposed on the other side of the first connection source / drain contact 181. The first interconnection source / drain contact 181 is, for example, an interconnection source / drain contact that is closest to the element isolation structure (165, 166) in the first direction D1. For example, as shown in FIG. 1, the isolation structure 165 is disposed between two first source / drain contacts 181 . That is, no additional gate electrode (120, 220, 320) is disposed between the first interconnection source / drain contact 181 and the element isolation structure (165, 166). In one embodiment of the semiconductor device, first interconnect source / drain contacts 181 are disposed on both sides of the isolation structures 165 and 166. In other words, the isolation structures (165, 166) are disposed between the first interconnection source / drain contacts 181 adjacent in the first direction D1.

[0064] For example, the first connection source / drain contact 181 connected to the first source / drain pattern 150 and the second source / drain pattern 250 is disposed between the first isolation structure 165 and the third gate electrode 320 . As another example, the first connecting source / drain contact 181 connected to the first source / drain pattern 150 and the second source / drain pattern 250 may be arranged between the first element isolation structure 165 and the first gate electrode 120 and between the first element isolation structure 165 and the second gate electrode 220.

[0065] For example, the first connecting source / drain contact 181 connected to the third source / drain pattern 350 and the fourth source / drain pattern 450 is disposed between the first element isolation structure 165 and the first gate electrode 120 and between the first element isolation structure 165 and the second gate electrode 220. As another example, the first connection source / drain contact 181 connected to the third source / drain pattern 350 and the fourth source / drain pattern 450 may be disposed between the first isolation structure 165 and the third gate electrode 320 . Since the description of the first connecting source / drain contact 181 closest to the second element isolation structure 166 is substantially the same as the description of the first connecting source / drain contact 181 closest to the first element isolation structure 165, the following description will focus on the first element isolation structure 165.

[0066] The second connecting source / drain contacts 182 are disposed between adjacent gate electrodes (120, 220, 320) in the first direction D1. The second interconnection source / drain contact 182 is not the interconnection source / drain contact most adjacent to the isolation structure (165, 166). That is, at least one gate electrode (120, 220, 320) is disposed between the second connecting source / drain contact 182 and the element isolation structure (165, 166).

[0067] For example, as shown in FIG. 1, the first gate electrode 120 and the second gate electrode 220 are disposed on one side of the second connecting source / drain contact 182 , and the third gate electrode 320 is disposed on the other side of the second connecting source / drain contact 182 . As another example, the first gate electrode 120 and the second gate electrode 220 may be disposed on one side of the second connection source / drain contact 182 and the other side of the second connection source / drain contact 182 . As another example, the second interconnecting source / drain contacts 182 may be disposed between the third gate electrodes 320 .

[0068] For example, as shown in FIG. 1, the first connection source / drain contact 181 and the second connection source / drain contact 182 are both disposed on the third fin-type pattern 310 and the fourth fin-type pattern 410 . As another example, an additional third isolation structure may be disposed between the first connecting source / drain contact 181 and the second connecting source / drain contact 182. In such a case, the first connecting source / drain contact 181 is disposed on the third fin-type pattern 310 and the fourth fin-type pattern 410, but the second connecting source / drain contact 182 is not disposed on the third fin-type pattern 310 and the fourth fin-type pattern 410. A second interconnection source / drain contact 182 is disposed on the seventh and eighth fin-type patterns disposed between the second isolation structure 166 and the third isolation structure.

[0069] In the following, a case where the first connection source / drain contact 181 and the second connection source / drain contact 182 are both disposed on the third fin-type pattern 310 and the fourth fin-type pattern 410 will be described. The first interconnection source / drain contact 181 includes a first lower contact region 181B, a first upper contact region 181UC, and a first dummy contact region 181UD. The first lower contact region 181B intersects with the first fin-type pattern 110 and the second fin-type pattern 210. The first lower contact region 181B is connected to the first source / drain pattern 150 and the second source / drain pattern 250 simultaneously. For example, the first lower contact region 181B is connected to the first source / drain pattern 150 and the second source / drain pattern 250 at the same time. The first lower contact region 181B intersects with the third fin-type pattern 310 and the fourth fin-type pattern 410. The first lower contact region 181B is connected to the third source / drain pattern 350 and the fourth source / drain pattern 450 simultaneously.

[0070] The first upper contact region 181UC and the first dummy contact region 181UD protrude from the first lower contact region 181B in the third direction D3. For example, the third direction D3 is a direction away from the fin pattern. The first upper contact region 181UC and the first dummy contact region 181UD are spaced apart in the second direction D2. The first connection source / drain contact 181 includes a plurality of contact regions protruding in the third direction D3 from the first lower contact region 181B.

[0071] The first lower contact region 181B is directly connected to the first upper contact region 181UC and the first dummy contact region 181UD. The first lower contact region 181B, the first upper contact region 181UC, and the first dummy contact region 181UD have an integral structure. For example, an integral structure is one that is homogenous and seam-free and is made of the same material. In the manufacturing process, after a pre-structure of the first connection source / drain contact 181 is formed, a part of the pre-structure is removed. The top surface of the pre-structure of the first connection source / drain contact 181 is flush with the top surface of the lower interlayer insulating film 190 .

[0072] By removing parts of the pre-structure, a first lower contact region 181B, a first upper contact region 181UC, and a first dummy contact region 181UD are formed. A portion of the pre-structure of the first connection source / drain contact 181 is etched to form the first upper contact region 181UC and the first dummy contact region 181UD, so that there is no boundary separating the first lower contact region 181B and the first upper contact region 181UC, and no boundary separating the first lower contact region 181B and the first dummy contact region 181UD. In other words, no boundary line is visible between the first lower contact region 181B and the first upper contact region 181UC and the first dummy contact region 181UD.

[0073] The top surface of the first connection source / drain contact 181 is the top surface of the first upper contact region (181UC_US) and the top surface of the first dummy contact region (181UD_US). The top surface of the first upper contact region (181UC_US) and the top surface of the first dummy contact region (181UD_US) are placed in the same plane as the top surface of the lower interlayer insulating film 190. The first lower contact region 181B includes a connecting portion (181B_CR) and a protruding portion (181B_PR). The coupling portion (181B_CR) of the first lower contact region is disposed between the first upper contact region 181UC and the first dummy contact region 181UD. The protruding portion (181B_PR) of the first lower contact region is a portion that protrudes in the second direction D2 from the first upper contact region 181UC and the first dummy contact region 181UD. The first upper contact region 181UC and the first dummy contact region 181UD are each disposed between the connection portion (181B_CR) of the first lower contact region and the protruding portion (181B_PR) of the first lower contact region.

[0074] The first upper contact region 181UC is a portion where a via plug 206, which will be described later, is landed. The first interconnection source / drain contact 181 is connected to the wiring structure 205 via a first upper contact region 181UC. The wiring structure 205 contacts the top surface 181UC_US of the first upper contact region. The first dummy contact region 181UD is a portion where the via plug 206 is not landed. The wiring structure 205 does not contact the top surface (181UD_US) of the first dummy contact region. A first etch stop layer 196, which will be described later, continuously covers the entire upper surface (181UD_US) of the first dummy contact region. Some of the contact regions protruding from the first lower contact region 181B in the third direction D3 contact the via plugs 206 penetrating the first etch stop layer 196, and the rest do not contact the via plugs 206.

[0075] As an example, as shown in FIG. 4, a width W12 in the second direction D2 of the top surface (181UD_US) of the first dummy contact region is greater than or equal to a width W11 in the second direction D2 of the top surface (181UC_US) of the first upper contact region. As another example, a width W12 in the second direction D2 of the top surface (181UD_US) of the first dummy contact region may be smaller than a width W11 in the second direction D2 of the top surface (181UC_US) of the first upper contact region. For example, as shown in FIG. 4, the first lower contact region 181B includes a first downward protruding region (181_DP) protruding toward the substrate 100 between the first source / drain pattern 150 and the second source / drain pattern 250. As shown in FIG. As another example, the first downward protruding region (181_DP) may contact the source / drain etch stop layer 156 or the field insulating layer 105.

[0076] The first lower contact region 181B includes a first downward protruding region (181_DP). The second interconnected source / drain contact 182 includes a second lower contact region 182B and a second upper contact region 182UC. The second lower contact region 182B intersects with the third fin-type pattern 310 and the fourth fin-type pattern 410. The second lower contact region 182B is connected to the third source / drain pattern 350 and the fourth source / drain pattern 450 simultaneously. The second upper contact region 182UC protrudes from the second lower contact region 182B in the third direction D3. The second connection source / drain contact 182 includes one contact region protruding in the third direction D3 from the second lower contact region 182B. The second lower contact region 182B is directly connected to the second upper contact region 182UC. The second lower contact region 182B and the second upper contact region 182UC have an integrated structure.

[0077] The top surface of the second interconnect source / drain contact 182 is the top surface of the second upper contact region (182UC_US). The upper surface of the second upper contact region (182UC_US) is placed in the same plane as the upper surface of the lower interlayer insulating film 190. The second upper contact region 182UC is a portion where the via plug 206 is landed. The second interconnection source / drain contact 182 is connected to the wiring structure 205 via a second upper contact region 182UC. The wiring structure 205 contacts the top surface of the second upper contact region (182UC_US). For example, as shown in FIG. 6, the second interconnected source / drain contact 182 has a shape similar to a "T" rotated 180 degrees. Depending on the position of the second upper contact region 182UC, the second interconnect source / drain contact 182 may have a shape similar to an "L".

[0078] For example, as shown in FIG. 6, the second lower contact region 182B includes a second downward protruding region (182_DP) that protrudes toward the substrate 100 between the third source / drain pattern 350 and the fourth source / drain pattern 450. As another example, the second downward protruding region (182_DP) may contact the source / drain etch stop layer 156 or the field insulating film 105. The second lower contact region 182B includes one second downward protruding region (182_DP).

[0079] A cross-sectional view of the first and second source / drain contacts 171 and 172 of FIG. 1 taken in a second direction D2 is similar to FIG. A cross-sectional view of the first source / drain contact 171 and the second source / drain contact 172 taken in the second direction D2 may be one of a "T" shape or an "L" shape rotated by 180 degrees.

[0080] The first connection source / drain contact 181 includes a first source / drain barrier layer 181BM and a first source / drain filling layer 181FM. The second interconnection source / drain contact 182 includes a second source / drain barrier layer 182BM and a second source / drain filling layer 182FM. The first gate contact 176 is disposed on the first gate electrode 120 . The second gate contact 177 is disposed on the second gate electrode 220 . The third gate contact 178 is disposed on the third gate electrode 320 . Taking the first gate contact 176 as an example, the first gate contact 176 is connected to the first gate electrode 120 through the first gate capping pattern 145 .

[0081] The first gate contact 176 includes a first gate barrier film 176BM and a first gate filling film 176FM. The second gate contact 177 includes a second gate barrier film 177BM and a second gate filling film 177FM. The third gate contact 178 includes a third gate barrier film 178BM and a third gate filling film 178FM. In terms of a plan view, the gate contacts (176, 177, 178) connected to the gate electrodes (120, 220, 320) closest to the first connection source / drain contact 181 do not overlap the first upper contact region 181UC and the first dummy contact region 181UD in the first direction D1. Taking the first connection source / drain contact 181 intersecting the first fin-type pattern 110 and the second fin-type pattern 210 in FIG. 1 as an example, the first upper contact region 181UC and the first dummy contact region 181UD do not overlap the third gate contact 178 in the first direction D1.

[0082] In one embodiment of a semiconductor device, the gate isolation structure 160 between the first gate electrode 120 and the second gate electrode 220 closest to the first connection source / drain contact 181 does not overlap with the first upper contact region 181UC and the first dummy contact region 181UD in the first direction D1. Taking the first connected source / drain contact 181 intersecting with the third fin-type pattern 310 and the fourth fin-type pattern 410 as an example in FIG. 1, the first upper contact region 181UC and the first dummy contact region 181UD do not overlap with the first gate contact 176, the second gate contact 177, and the gate isolation structure 160 in the first direction D1. In terms of a plan view, the gate contacts (176, 177, 178) connected to the gate electrodes (120, 220, 320) that are closest to the second connection source / drain contact 182 do not overlap the second upper contact region 182UC in the first direction D1. In the semiconductor device according to the embodiment, the gate isolation structure 160 between the first gate electrode 120 and the second gate electrode 220 that is closest to the second connection source / drain contact 182 does not overlap with the second upper contact region 182UC in the first direction D1.

[0083] The source / drain barrier film (181BM, 182BM) and the gate barrier film (176BM, 177BM, 178BM) may each include at least one of, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and two-dimensional (2D) material.

[0084] In a semiconductor device according to an embodiment, the two-dimensional material may be a metallic material and / or a semiconductor material. The 2D material may include a 2D allotrope or compound, such as graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe 2 ), tungsten diselenide (WSe 2 ), tungsten disulfide (WS 2 ) may include at least one of.

[0085] The source / drain filling films (181FM, 182FM) and the gate filling films (176FM, 177FM, 178FM) may each include at least one of, for example, aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), silver (Ag), gold (Au), manganese (Mn), and molybdenum (Mo).

[0086] A first etch stop layer 196 and a first upper interlayer insulating layer 191 are sequentially disposed on the first and second interconnection source / drain contacts 181 and 182. A first etch stop layer 196 and a first upper interlayer insulating layer 191 are disposed on the lower interlayer insulating layer 190 . The first etch stop layer 196 includes a material having an etch selectivity with respect to the first upper interlayer insulating layer 191 . The first etch stop film 196 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), aluminum nitride (AlN), and aluminum oxycarbide (AlOC), and combinations thereof. Unlike the illustration, the first etch stop layer 196 may not be formed. The first upper interlayer insulating film 191 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0087] The via plug 206 is disposed in the first etch stop layer 196 and the first upper interlayer insulating layer 191 . The via plugs 206 penetrate the first etch stop layer 196 and the first upper interlayer insulating layer 191 to be connected to the first and second connection source / drain contacts 181 and 182 and the first and second source / drain contacts 171 and 172. The via plug 206 contacts the upper surface of the first upper contact region (181UC_US) and the upper surface of the second upper contact region (182UC_US). However, the via plug 206 does not contact the upper surface (181UD_US) of the first dummy contact region. The via plugs 206 penetrate the first etch stop layer 196 and the first upper interlayer insulating layer 191 and are connected to the gate contacts 176, 177, and 178. The via plug 206 has a single-film structure. The via plug 206 has a structure formed of a single film. That is, the via plug 206 has a single conductive film structure. The via plug 206 may include, for example, one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), and molybdenum (Mo).

[0088] The via plugs 206 connected to the source / drain contacts (171, 172, 181, 182) are source / drain via plugs. The via plug 206 connected to the gate contacts (176, 177, 178) is a gate via plug. For example, one of the source / drain via plugs and the gate via plugs has a single-layer structure, and the other of the source / drain via plugs and the gate via plugs has a multi-layer structure (e.g., a combination of a barrier layer and a filling layer) such as the gate contacts (176, 177, 178). As another example, the via plug 206 can have a multi-layer structure.

[0089] In FIG. 9, the bottom surface 206BS of the via plug has a first via width W22 in the second direction D2. A width W21 in the second direction D2 of the top surface (182UC_US) of the second upper contact region is equal to or greater than the first via width W22. Furthermore, the width W21 in the second direction D2 of the top surface (182UC_US) of the second upper contact region is equal to or smaller than 1.2 times the first via width W22. For example, as shown in FIGS. 5 and 6, a second etch stop layer 197 and a second upper interlayer insulating layer 192 are sequentially disposed on a first upper interlayer insulating layer 191 . As another example, the second etch stop layer 197 may not be formed. The materials of the second etch stop layer 197 and the second upper interlayer insulating layer 192 are the same as those of the first etch stop layer 196 and the first upper interlayer insulating layer 191 .

[0090] The wiring line 207 is disposed in the second upper interlayer insulating layer 192 and the second etch stop layer 197 . The wiring line 207 is connected to the via plug 206 . At least a portion of the wiring line 207 extends long in the first direction D1. The wiring line 207 includes a wiring barrier film 207a and a wiring filling film 207b. The wiring barrier film 207a may include at least one of, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and a two-dimensional (2D) material. The wiring filling film 207b may include at least one of aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), and molybdenum (Mo), for example.

[0091] The wiring structure 205 includes a via plug 206 and a wiring line 207 . An interconnect structure 205 is disposed over the source / drain contacts (171, 172, 181, 182) and the gate contacts (176, 177, 178). The wiring structure 205 is connected to the source / drain contacts (171, 172, 181, 182). The wiring structure 205 is connected to the gate contacts (176, 177, 178). Unlike the illustration, the wiring line 207 and the via plug 206 have an integral structure. In such a case, the boundary between the wiring line 207 and the via plug 206 may not be distinct, eg, may not be visible.

[0092] 10 to 12 are diagrams relating to a semiconductor device according to another embodiment of the present invention. For convenience of explanation, the following will mainly explain the points that are different from the contents explained using FIGS. For reference, FIG. 10 is a schematic layout diagram of a semiconductor device according to an embodiment of the present invention, and FIGS. 11 and 12 are cross-sectional views taken along lines CC and DD in FIG. 10 to 12, a semiconductor device according to another embodiment of the present invention includes a third connection source / drain contact 183 that is closest to the first isolation structure 165.

[0093] The third interconnection source / drain contact 183 is disposed between the first isolation structure 165 and the gate electrode (120, 220, 320). The first isolation structure 165 is disposed on one side of the third connection source / drain contact 183 , and the gate electrode ( 120 , 220 , 320 ) is disposed on the other side of the third connection source / drain contact 183 . The third interconnection source / drain contact 183 is the interconnection source / drain contact that is most adjacent to the first isolation structure 165 . The first isolation structures 165 are disposed between the third connecting source / drain contacts 183 adjacent to each other in the first direction D1.

[0094] Third connecting source / drain contacts 183 may be disposed on both sides of the isolation structure 165 instead of the first connecting source / drain contacts (reference numeral 181 in FIG. 1). The third interconnected source / drain contact 183 includes a third lower contact region 183B and a third upper contact region 183UC. The third lower contact region 183B intersects with the first fin-type pattern 110 and the second fin-type pattern 210. The third lower contact region 183B is connected to the first source / drain pattern 150 and the second source / drain pattern 250 at the same time. The third lower contact region 183B intersects with the third fin-type pattern 310 and the fourth fin-type pattern 410. The third lower contact region 183B is connected to the third source / drain pattern 350 and the fourth source / drain pattern 450 at the same time.

[0095] The third upper contact region 183UC protrudes from the third lower contact region 183B in the third direction D3. The third connection source / drain contact 183 includes one contact region protruding in the third direction D3 from the third lower contact region 183B. The third lower contact region 183B and the third upper contact region 183UC have an integrated structure. The top surface of the third interconnect source / drain contact 183 is the top surface 183 (UC_US) of the third upper contact region. The top surface of the third upper contact region (183UC_US) is placed in the same plane as the top surface of the lower interlayer insulating film 190. The third lower contact region 183B includes a protruding portion (183B_PR). The protruding portion (183B_PR) of the third lower contact region is a portion that protrudes from the third upper contact region 183UC in the second direction D2. The third upper contact region 183UC is disposed between the protruding portions (183B_PR) of the third lower contact region.

[0096] The third upper contact region 183UC is a portion where the via plug 206 is landed. The third connecting source / drain contact 183 is connected to the wiring structure 205 via a third upper contact region 183UC. The wiring structure 205 contacts the top surface (183UC_US) of the third upper contact region. In FIG. 11, the third lower contact region 183B includes a third downward protruding region 183_DP protruding toward the substrate 100 between the first source / drain pattern 150 and the second source / drain pattern 250. The third interconnection source / drain contact 183 includes a third source / drain barrier film 183BM and a third source / drain filling film 183FM.

[0097] In terms of a plan view, the gate contacts (176, 177, 178) connected to the gate electrodes (120, 220, 320) that are closest to the third connecting source / drain contact 183 do not overlap the third upper contact region 183UC in the first direction D1. In the semiconductor device according to the embodiment, the gate isolation structure 160 between the first gate electrode 120 and the second gate electrode 220 that is closest to the third connecting source / drain contact 183 does not overlap with the third upper contact region 183UC in the first direction D1. The via plug 206 penetrates the first etch stop layer 196 and the first upper interlayer insulating layer 191 and is connected to the third connection source / drain contact 183 . The via plug 206 contacts the top surface (183UC_US) of the third upper contact region.

[0098] In FIG. 11, the bottom surface 206BS of the via plug has a second via width W32 in the second direction D2. A width W31 in the second direction D2 of the top surface (183UC_US) of the third upper contact region is greater than or equal to 1.5 times the second via width W32. The second via width W32 is the same as the first via width W22 in FIG. A width W31 in the second direction D2 of the top surface (183UC_US) of the third upper contact region is smaller than the width in the second direction D2 of the third lower contact region 183B. In the third connection source / drain contact 183 connected to the third source / drain pattern 350 and the fourth source / drain pattern 450, the width in the second direction D2 of the upper surface (183UC_US) of the third upper contact region is greater than or equal to 1.5 times the second via width (W32 in FIG. 11).

[0099] FIG. 13 is a schematic layout diagram of a semiconductor device according to another embodiment of the present invention. For the sake of convenience, the following description will focus on the differences from the contents described with reference to FIGS. 13, in a semiconductor device according to another embodiment of the present invention, a first isolation structure 165 is disposed between a first connection source / drain contact 181 and a third connection source / drain contact 183. In the semiconductor device shown in FIG. The first connecting source / drain contact 181 disposed on one side of the first isolation structure 165 includes a first dummy contact region 181UD. However, the third connecting source / drain contact 183 disposed on the other side of the first isolation structure 165 does not include a dummy contact region.

[0100] 14 and 15 are diagrams relating to a semiconductor device according to another embodiment of the present invention. For convenience of explanation, the following will mainly explain the points that are different from the contents explained using FIGS. For reference, FIG. 14 is a schematic layout diagram of a semiconductor device according to another embodiment of the present invention, and FIG. 15 is a cross-sectional view taken along line DD in FIG.

[0101] 14 and 15, in a semiconductor device according to another embodiment of the present invention, a first element isolation structure 165 is arranged between the first connection source / drain contact 181 and the first source / drain contact 171, and between the first connection source / drain contact 181 and the second source / drain contact 172. The first source / drain contact 171 and the second source / drain contact 172 are disposed closest to the first isolation structure 165 . A first connecting source / drain contact 181 is disposed on one side of the first isolation structure 165 . A first source / drain contact 171 and a second source / drain contact 172 are disposed on the other side of the first isolation structure 165 .

[0102] The first source / drain contact 171 includes a first single lower contact region 171B and a first single upper contact region 171UC. The second source / drain contact 172 includes a second single lower contact region 172B and a second single upper contact region 172UC. The first source / drain contact 171 and the second source / drain contact 172 each include a contact region protruding in the third direction D3 from a single lower contact region 171B, 172B.

[0103] The first single lower contact region 171B is connected to the third source / drain pattern 350 but is not connected to the fourth source / drain pattern 450. The second single lower contact region 172 B is connected to the fourth source / drain pattern 450 but is not connected to the third source / drain pattern 350 . The first single upper contact region 171UC protrudes from the first single lower contact region 171B in the third direction D3. The second single upper contact region 172UC protrudes from the second single lower contact region 172B in the third direction D3. The first source / drain contact 171 includes a first single source / drain barrier film 171BM and a first single source / drain filling film 171FM. The second source / drain contact 172 includes a second single source / drain barrier film 172BM and a second single source / drain filling film 172FM.

[0104] In terms of a plan view, the gate contacts (176, 177, 178) connected to the gate electrodes (120, 220, 320) closest to the first element isolation structure 165 do not overlap the first single upper contact region 171UC and the second single upper contact region 172UC in the first direction D1. The via plug 206 is connected to the first source / drain contact 171 and the second source / drain contact 172 .

[0105] 16 and 17 are diagrams relating to a semiconductor device according to another embodiment of the present invention. For convenience of explanation, the following will mainly explain the points that are different from the contents explained using FIGS. For reference, FIG. 16 is a schematic layout diagram of a semiconductor device according to another embodiment of the present invention, and FIG. 17 is a cross-sectional view taken along line DD in FIG. 16 and 17, in a semiconductor device according to another embodiment of the present invention, a first element isolation structure 165 is disposed between a first connection source / drain contact 181 and a second connection source / drain contact 182. The second interconnection source / drain contact 182 is disposed adjacent to the first isolation structure 165 . A first connecting source / drain contact 181 is disposed on one side of the first isolation structure 165 . The second connecting source / drain contact 182 is disposed adjacent to the other side of the first isolation structure 165 .

[0106] 18 and 19 are diagrams relating to a semiconductor device according to another embodiment of the present invention. For convenience of explanation, the following will mainly explain the points that are different from the contents explained using FIGS. For reference, FIG. 18 is a schematic layout diagram of a semiconductor device according to another embodiment of the present invention, and FIG. 19 is a cross-sectional view taken along line DD in FIG. 18 and 19, in a semiconductor device according to another embodiment of the present invention, a first element isolation structure 165 is disposed between a first connection source / drain contact 181 and a fourth connection source / drain contact 184.

[0107] The fourth interconnected source / drain contact 184 includes a fourth lower contact region 184B and a plurality of fourth upper contact regions 184UC. The fourth lower contact region 184B intersects with the third fin-type pattern 310 and the fourth fin-type pattern 410. The fourth lower contact region 184B is connected to the third source / drain pattern 350 and the fourth source / drain pattern 450 simultaneously. The plurality of fourth upper contact regions 184UC protrude from the fourth lower contact region 184B in the third direction D3. The multiple fourth upper contact regions 184UC are spaced apart in the second direction D2. Each of the fourth upper contact regions 184UC is a portion where a via plug 206 is landed.

[0108] The fourth interconnection source / drain contacts 184 are connected to the wiring structure 205 via respective fourth upper contact regions 184UC. The wiring structure 205 contacts the top surface (184UC_US) of each of the fourth upper contact regions. The plurality of fourth upper contact regions 184UC include a first sub-contact region and a second sub-contact region spaced apart in the second direction D2. The first sub-contact region and the second sub-contact region each contact the via plug 206 . A top surface of each of the first sub-contact regions and a top surface of the second sub-contact region are in contact with the wiring structure 205 . For example, the fourth interconnection source / drain contact 184 is the interconnection source / drain contact that is most adjacent to the first isolation structure 165 . The fourth interconnection source / drain contact 184 includes a fourth source / drain barrier film 184BM and a fourth source / drain filling film 184FM.

[0109] FIG. 20 is a schematic layout diagram of a semiconductor device according to another embodiment of the present invention. 21 to 25 each relate to a semiconductor device according to another embodiment of the present invention. For convenience of explanation, the following will mainly explain the points that are different from the contents explained using FIGS. For reference, FIGS. 21 to 24 are cross-sectional views taken along line CC in FIG. 1, and FIG. 25 is a cross-sectional view taken along line GG in FIG.

[0110] 20, in a semiconductor device according to another embodiment of the present invention, a fourth connection source / drain contact 184 is disposed between gate electrodes 120, 220, and 320 adjacent to each other in a first direction. For example, the fourth interconnection source / drain contact 184 may not be the interconnection source / drain contact most adjacent to the isolation structure (165, 166). The structure of the fourth connection source / drain contact 184 is the same as that described with reference to FIGS.

[0111] Referring to FIG. 21, in a semiconductor device according to another embodiment of the present invention, a first lower contact region 181B includes a plurality of first downward protrusion regions (181_DP) protruding toward a substrate 100 between a first source / drain pattern 150 and a second source / drain pattern 250. For example, the first lower contact region 181B includes two first downward protruding regions (181_DP). Unlike the illustration, at least one of the plurality of first downward protruding regions (181_DP) may contact the source / drain etch stop layer 156 or the field insulating layer 105. Also, unlike the illustration, a portion of the field insulating film 105 may protrude between the first downward protruding regions 181_DP adjacent to each other in the two directions D2. Although not shown, the second bottom contact region (182B in FIG. 6) may also include multiple downward protruding regions.

[0112] Referring to FIG. 22, in a semiconductor device according to another embodiment of the present invention, a first lower contact region 181B includes a first downward protruding region 181_DP and a first upper indented region 181_UP. A part of the lower interlayer insulating film 190 indents into the first lower contact region 181B. In the first upper indentation region (181_UP), the lower interlayer insulating film 190 indents into the first lower contact region 181B. In the first downward protrusion region 181_DP, the thickness of the first lower contact region 181B in the third direction D3 increases and then decreases as it becomes farther from the first source / drain pattern 150. In the first upper indented region (181_UP), the thickness of the first lower contact region 181B in the third direction D3 decreases and then increases.

[0113] 23, in a semiconductor device according to another embodiment of the present invention, the bottom surface of the first lower contact region 181B is flat between the first source / drain pattern 150 and the second source / drain pattern 250. In the embodiment of FIG. That is, the first lower contact region 181B does not include the first downward protruding region (reference numeral 181_DP in FIG. 4).

[0114] Referring to FIG. 24, in a semiconductor device according to another embodiment of the present invention, a field region FX is defined by a dummy fin pattern DFP. The first active region RX1 and the second active region RX2 are defined by a dummy fin pattern DFP. In other words, a first active region RX1 and a second active region RX2 are defined between the dummy fin patterns DFP. The upper surface of the dummy fin pattern DFP is entirely covered with a field insulating film 105. The upper surface of the dummy fin pattern DFP is lower than the upper surface of the field insulating film 105. The dummy fin pattern DFP includes, for example, the same material as the first fin type pattern 110 and / or the second fin type pattern 210.

[0115] 25, in a semiconductor device according to another embodiment of the present invention, a first gate insulating film 130 does not extend along the sidewalls of a first gate electrode 120 and a sidewall of a gate isolation structure 160 facing in a second direction D2. The second gate insulating film 230 does not extend along the sidewalls of the second gate electrode 220 and the sidewalls of the gate isolation structure 160 facing in the second direction D2. In this case, the gate isolation structure 160 between the first gate electrode 120 and the second gate electrode 220 closest to the first connection source / drain contact 181 overlaps with the first upper contact region (symbol 181UC in FIG. 1) and the first dummy contact region (symbol 181UD in FIG. 1) in the first direction D1. In addition, the gate isolation structure 160 between the first gate electrode 120 and the second gate electrode 220 closest to the second connecting source / drain contact (182 in FIG. 1) overlaps with the second upper contact region (182UC in FIG. 1) in the first direction D1.

[0116] 26 to 30 are diagrams relating to a semiconductor device according to another embodiment of the present invention. For reference, FIG. 26 is a schematic layout diagram of a semiconductor device according to another embodiment of the present invention, FIGS. 27 and 28 are cross-sectional views taken along line AA in FIG. 26, FIG. 29 is a cross-sectional view taken along line CC in FIG. 26, and FIG. 30 is a cross-sectional view taken along line FF in FIG. 26. For convenience of explanation, the following will mainly explain the points that are different from the contents explained using FIGS.

[0117] 26 to 30, a semiconductor device according to another embodiment of the present invention further includes a first sheet pattern NS1 spaced apart from the first fin-type pattern 110 in a third direction D3, a second sheet pattern NS2 spaced apart from the second fin-type pattern 210 in the third direction D3, and a third sheet pattern NS3 spaced apart from the third fin-type pattern 310 in the third direction D3. Although not shown in the figure, a sheet pattern is disposed on each of the fin patterns (410, 510, 610) of FIGS.

[0118] The first active region RX1 and the second active region RX2 are divided by a first fin-type pattern 110 and a second fin-type pattern 210. In addition, the first active region RX1 and the second active region RX2 are divided by a third fin-type pattern 310 and a fourth fin-type pattern 410. The first sheet pattern NS1 is disposed on the first fin-type pattern 110 at a distance therefrom. The first sheet pattern NS1 includes a plurality of sheet patterns. The second sheet pattern NS2 is disposed on the second fin-type pattern 210 at a distance therefrom. The second sheet pattern NS2 includes a plurality of sheet patterns. The third sheet pattern NS3 is disposed on the third fin-type pattern 310 at a distance therefrom.

[0119] Although the first sheet pattern NS1, the second sheet pattern NS2, and the third sheet pattern NS3 each have three patterns, this is only for convenience of explanation. The first gate insulating film 130 surrounds the periphery of the third sheet pattern NS1. The third gate insulating film 330 surrounds the periphery of the first sheet pattern NS1 and the periphery of the second sheet pattern NS2. The first gate electrode 120 is disposed on the third fin-type pattern 310 . The first gate electrode 120 intersects with the third fin-type pattern 310 . The first gate electrode 120 surrounds the third sheet pattern NS3. The third gate electrode 320 is disposed on the first fin-type pattern 110 and the second fin-type pattern 210 . The third gate electrode 320 intersects the first fin-type pattern 110 and the second fin-type pattern 210 . The third gate electrode 320 surrounds the first sheet pattern NS1 and the second sheet pattern NS2.

[0120] In FIG. 27, the first gate spacers 140 are not disposed between the third fin-type pattern 310 and the third sheet pattern NS3, and are not disposed between adjacent third sheet patterns NS3. Moreover, the third gate spacer 340 is not disposed between the first fin-type pattern 110 and the first sheet pattern NS1, and is not disposed between adjacent first sheet patterns NS1.

[0121] In FIG. 28, the first gate spacers 140 are disposed between the third fin-type pattern 310 and the third sheet pattern NS3 and between adjacent third sheet patterns NS3. The third gate spacers 340 are disposed between the first fin-type pattern 110 and the first sheet pattern NS1 and between adjacent first sheet patterns NS1. A cross-sectional view taken along the second fin-type pattern 210 is similar to the one in FIG. 29 or FIG. The first source / drain pattern 150 is connected to a first sheet pattern NS1 adjacent thereto in the first direction D1. The third source / drain pattern 350 is connected to the third sheet pattern NS3 adjacent thereto in the first direction D1. Although not shown, the second source / drain pattern 250 is connected to a second sheet pattern NS2 adjacent thereto in the first direction D1.

[0122] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0123] 100 Substrates 105 Field Insulation Film 110, 210, 310, 410, 510, 610 1st to 6th fin type patterns 120, 220, 320 First to third gate electrodes 140, 240, 340 1st to 3rd gate spacers 145, 245, 345 1st to 3rd gate capping patterns 150 First source / drain pattern 155, 255, 355 1st to 3rd silicide films 156 Source / Drain Etching Stop Film 160 Gate isolation structure 165, 166 First and second element isolation structures 171 First source / drain contact 172 2nd source / drain contact 176, 177, 178 1st to 3rd gate contacts 181, 182 First and second interconnected source / drain contacts 190, 191, 192 (first upper portion to third upper portion) interlayer insulating film 197 Second Etching Stop Film 205 Wiring structure 206 Via plug 207 Wiring Line

Claims

1. An element isolation structure including a first side wall and a second side wall extending in a first direction, The first side wall of the element isolation structure is located opposite the second side wall of the element isolation structure in the second direction, A first fin-shaped pattern that contacts the first side wall of the element isolation structure and extends in the second direction, A second fin-shaped pattern is in contact with the first side wall of the element isolation structure, and is separated from the first fin-shaped pattern in the first direction and extends in the second direction, A first gate electrode extending in the first direction is provided on the first fin-shaped pattern, A first source / drain contact is disposed on the first fin-shaped pattern and the second fin-shaped pattern between the first gate electrode and the element isolation structure, and extends in the first direction. The first source / drain contact has a wiring structure connected to the first source / drain contact, The first source / drain contact includes a first lower contact region disposed on the first fin-shaped pattern and the second fin-shaped pattern, a first upper contact region disposed on the first lower contact region, and a first dummy contact region. The semiconductor device is characterized in that the wiring structure is in contact with the upper surface of the first upper contact region and separated from the upper surface of the first dummy contact region.

2. The semiconductor device according to claim 1, characterized in that no gate electrode is disposed between the first source / drain contact and the element isolation structure.

3. The first gate electrode further has a first gate contact connected to the first gate electrode, The semiconductor device according to claim 1, characterized in that the first gate contact does not overlap the first upper contact region and the first dummy contact region in the second direction.

4. The semiconductor device according to claim 3, characterized in that the first gate electrode is arranged on the second fin-shaped pattern.

5. The second gate electrode is arranged on the second fin-shaped pattern and is separated from the first gate electrode in a first direction, The second gate electrode further has a second gate contact connected to the second gate electrode, The first source / drain contact is positioned between the second gate electrode and the element isolation structure. The semiconductor device according to claim 3, characterized in that the second gate contact does not overlap the first upper contact region and the first dummy contact region in the second direction.

6. The present invention further comprises a gate isolation structure disposed between the first gate electrode and the second gate electrode, The semiconductor device according to claim 5, characterized in that the gate separation structure does not overlap the first upper contact region and the first dummy contact region in the second direction.

7. A third fin-shaped pattern that contacts the second side wall of the element isolation structure and extends in the second direction, A fourth fin-shaped pattern that contacts the second side wall of the element isolation structure, is separated from the third fin-shaped pattern in the first direction, and extends in the second direction, The invention further comprises a third fin-shaped pattern and a second source / drain contact disposed on the fourth fin-shaped pattern, The second source / drain contact includes a second lower contact region positioned on the third fin-shaped pattern and the fourth fin-shaped pattern, and a second upper contact region positioned on the second lower contact region. The semiconductor device according to claim 1, characterized in that the upper surface of the second upper contact region is in contact with the wiring structure.

8. The second source / drain contact further includes a second dummy contact region located on the second lower contact region, The semiconductor device according to claim 7, characterized in that the upper surface of the second dummy contact area does not come into contact with the wiring structure.

9. The second source / drain contact further includes a third upper contact region located on the second lower contact region, The semiconductor device according to claim 7, characterized in that the upper surface of the third upper contact region is in contact with the wiring structure.

10. A third fin-shaped pattern that contacts the second side wall of the element isolation structure and extends in the second direction, A fourth fin-shaped pattern that contacts the second side wall of the element isolation structure, is separated from the third fin-shaped pattern in the first direction, and extends in the second direction, A second source / drain contact is arranged on the third fin-shaped pattern, The device further comprises a third source / drain contact arranged on the fourth fin-shaped pattern, The semiconductor device according to claim 1, characterized in that the second source / drain contact is separated from the third source / drain contact in the first direction.

11. The first lower contact region includes a connecting portion disposed between the first upper contact region and the first dummy contact region, a first protruding portion, and a second protruding portion. The semiconductor device according to claim 1, characterized in that the first upper contact region is positioned between the connecting portion of the first lower contact region and the first protruding portion of the first lower contact region, and the first dummy contact region is positioned between the connecting portion of the first lower contact region and the second protruding portion of the first lower contact region.

12. The first fin-shaped pattern further has a sheet pattern spaced apart from the first fin-shaped pattern, The semiconductor device according to claim 1, characterized in that the first gate electrode surrounds the sheet pattern.

13. A first fin-shaped pattern extending in the first direction, A second fin-shaped pattern is spaced apart from the first fin-shaped pattern in the second direction and extends in the first direction, A third fin-shaped pattern extending in the first direction, A third fin-shaped pattern and a fourth fin-shaped pattern that is separated in the second direction and extends in the first direction, An element isolation structure that contacts the first fin-shaped pattern and the second fin-shaped pattern and extends in the second direction, A first gate electrode extending in the second direction is provided on the first fin-shaped pattern, A second gate electrode extending in the second direction is provided on the third fin-shaped pattern, A third gate electrode extending in the second direction is provided on the fourth fin-shaped pattern, A first source / drain contact is disposed on the first fin-shaped pattern and the second fin-shaped pattern between the first gate electrode and the element isolation structure, and extends in the second direction. Displaced between the second gate electrode and the element isolation structure, and between the third gate electrode and the element isolation structure, and positioned on the third fin-shaped pattern and the fourth fin-shaped pattern, a second source / drain contact extending in the second direction, The system includes a wiring structure disposed on the first source / drain contact and the second source / drain contact, and connected to the first source / drain contact and the second source / drain contact, The first source / drain contact includes a first lower contact region disposed on the first fin-shaped pattern and the second fin-shaped pattern, and a first upper contact region disposed on the first lower contact region. The second source / drain contact includes a second lower contact region positioned on the third fin-shaped pattern and the fourth fin-shaped pattern, and a second upper contact region positioned on the second lower contact region. The wiring structure includes via plugs that contact the first upper contact region and the second upper contact region. The bottom surface of the via plug has a first width, The width of the upper surface of the first upper contact region is greater than or equal to 1.5 times the first width. A semiconductor device characterized in that the width of the upper surface of the second upper contact region is greater than or equal to the first width, and less than or equal to 1.2 times the first width.

14. The semiconductor device according to claim 13, characterized in that the first source / drain contact includes a first dummy contact region disposed on the first lower contact region.

15. A first fin-shaped pattern extending in the first direction, A second fin-shaped pattern is spaced apart from the first fin-shaped pattern in the second direction and extends in the first direction, A third fin-shaped pattern is spaced apart from the first fin-shaped pattern and extends in the first direction, A fourth fin-shaped pattern is spaced apart from the second fin-shaped pattern in the first direction and extends in the first direction, A first source / drain contact is arranged on the first fin-shaped pattern and the second fin-shaped pattern and extends in the second direction, A second source / drain contact is arranged on the third fin-shaped pattern and the fourth fin-shaped pattern and extends in the second direction, An element isolation structure disposed between the first fin-shaped pattern and the third fin-shaped pattern, and between the second fin-shaped pattern and the fourth fin-shaped pattern, The system includes a wiring structure disposed on the first source / drain contact and the second source / drain contact, and connected to the first source / drain contact and the second source / drain contact, The first source / drain contact includes a first lower contact region disposed on the first fin-shaped pattern and the second fin-shaped pattern, a first upper contact region disposed on the first lower contact region, and a first dummy contact region. The second source / drain contact includes a second lower contact region positioned on the third fin-shaped pattern and the fourth fin-shaped pattern, and a second upper contact region positioned on the second lower contact region. The semiconductor device is characterized in that the wiring structure is in contact with the upper surface of the first upper contact region and the upper surface of the second upper contact region, but is not in contact with the upper surface of the first dummy contact region.

16. The second source / drain contact further includes a second dummy contact region protruding from the second lower contact region. The semiconductor device according to claim 15, characterized in that the upper surface of the second dummy contact area does not come into contact with the wiring structure.

17. The semiconductor device according to claim 15, further comprising a first gate electrode disposed on the first fin-shaped pattern and a first gate contact disposed on the first gate electrode.

18. The semiconductor device according to claim 17, further comprising: a second gate electrode disposed on the third fin-shaped pattern; a third gate electrode disposed on the fourth fin-shaped pattern; and a gate isolation structure disposed between the second gate electrode and the third gate electrode.

19. The invention further comprises a first source / drain pattern disposed on the first fin-shaped pattern and a second source / drain pattern disposed on the second fin-shaped pattern, The first source / drain contact is arranged on the first source / drain pattern and the second source / drain pattern. The semiconductor device according to claim 15, characterized in that the bottom surface of the first source / drain pattern is located at a higher level than the bottom surface of the element isolation structure.

20. The first lower contact region includes a first portion positioned on the first source / drain pattern, a second portion positioned on the second source / drain pattern, and a third portion positioned between the first portion and the second portion. The semiconductor device according to claim 19, characterized in that the bottom surface of the third part is located at a lower level than the bottom surface of the first part and the bottom surface of the second part.

Images