Structure for a semiconductor device and method for manufacturing a structure for a semiconductor device - Patents.com

Abstract

Provided is a structure (1) for a semiconductor device, comprising a contact layer (4) containing a first dopant of a first conductivity type, a base layer (2) of a second conductivity type, and a defect layer (5) containing the first dopant of the first conductivity type, wherein the concentration of the activated first dopant in the contact layer (4) is higher than the concentration of the activated first dopant in the defect layer (5). Also provided is a method for manufacturing a structure for a semiconductor device.

Description

[Technical Field]

[0001] statement This disclosure relates to structures for semiconductor devices and methods for manufacturing structures for semiconductor devices. [Background technology]

[0002] Semiconductor devices are used in many technological fields. Design optimization of such power semiconductor devices often involves optimizing the injection efficiency of at least one of the anode and cathode layers. Controlling the injection efficiency is generally achieved by varying the dopant dose. [Overview of the project] [Problems that the invention aims to solve]

[0003] Embodiments of the present disclosure address all or part of the above-mentioned drawbacks by providing structures for semiconductor devices with improved injection efficiency and methods for manufacturing such structures. [Means for solving the problem]

[0004] The exemplary embodiments of this disclosure address the above-mentioned shortcomings by the subject matter of the independent claims. Further embodiments are evident from the dependent claims and the following description.

[0005] A first aspect of this disclosure relates to structures for semiconductor devices. Semiconductor devices include, for example, diodes, insulated-gate bipolar transistors (abbreviated as IGBTs), or metal-oxide-semiconductor field-effect transistors (abbreviated as MOSFETs). Exemplary examples of semiconductor devices include, for example, non-punch-through (NPT) devices or soft-punch-through (SPT) devices.

[0006] Semiconductor devices include, for example, power semiconductor devices. In this section and below, the term “power” refers to power semiconductor devices configured to handle voltages and currents greater than 100V and / or greater than 10A, such as voltages up to 1200V and currents of several hundred amperes.

[0007] According to an embodiment of the first aspect, the structure comprises a contact layer containing a first dopant of a first conductivity type. The contact layer contains, for example, a semiconductor material, or consists of a semiconductor material. For example, the contact layer contains a first dopant such that the first conductivity type is p-type conductivity. Alternatively, the contact layer contains a first dopant that is an n-type dopant such that the first conductivity type is n-type conductivity. Exemplarily, the contact layer is capable of contacting the outside in an electrically conductive manner.

[0008] The contact layer has, for example, a principal extending surface. For example, the horizontal direction is aligned parallel to the principal extending surface, and the vertical direction is aligned perpendicular to the principal extending surface.

[0009] According to the embodiment, the structure comprises a base layer having a second conductivity type different from a first conductivity type. The base layer includes, for example, a semiconductor material which is the same material as the semiconductor material of the contact layer, or consists of such a semiconductor material. The second conductivity type is, for example, n-type conductivity. Alternatively, the second conductivity type is p-type conductivity. Exemplarily, the second conductivity type is different from the first conductivity type. That is, if the contact layer is of p-conductivity, the base layer is of n-conductivity, and vice versa.

[0010] For example, the base layer does not contain the first dopant. Exemplarily, the base layer does not contain the first dopant at all.

[0011] According to one embodiment, the structure comprises a defect layer containing a first dopant of a first conductivity type, wherein the concentration of the first dopant activated in the contact layer is higher than the concentration of the first dopant activated in the defect layer.

[0012] The defective layer includes, by way of example, a semiconductor material that is the same semiconductor material as the semiconductor material of the contact layer, or consists of such a semiconductor material. For example, the concentration of the activated first dopant continuously decreases from the contact layer to the defective layer.

[0013] The first dopant, by way of example, contributes to the electronic properties of the contact layer and the defective layer such as conductivity. Further, due to the contribution of the first dopant to the electronic properties, for example, the injection efficiency also depends on the first dopant. Therefore, the injection efficiency can be preset according to the first dopant.

[0014] At least a part of the first dopant can be located, by way of example, at an interstitial lattice site of at least one of the contact layer and the defective layer. Further, at least a part of the first dopant can be located, by way of example, at a substitutional lattice site of at least one of the contact layer and the defective layer.

[0015] The first dopant is introduced, by way of example, by an implantation process. The implantation process disrupts, for example, the long-range order of the crystal lattice of at least one of the contact layer and the defective layer. For this reason, implantation increases the amorphousness of the crystal lattice of at least one of the contact layer and the defective layer.

[0016] When at least a part of the first dopant is located at an interstitial lattice site, the sites within the crystal lattice of at least one of the contact layer and the defective layer are places where there are usually no atoms, but are occupied by the first dopant. The amorphousness of at least one of the contact layer and the defective layer increases, for example, as the number of first dopants located at interstitial lattice sites increases, and vice versa.

[0017] When at least a part of the first dopant is located on the substitution lattice side, the sites in the crystal lattice of at least one of the contact layer and the defect layer, which are normally where atoms are present, are occupied by the first dopant. As a result, the first dopant is incorporated into the regular sites in the crystal structure. For example, the amorphousness of at least one of the contact layer and the defect layer decreases as the number of first dopants located at substitution lattice sites increases, and vice versa.

[0018] For example, when the amorphousness of at least one of the contact layer and the defect layer increases, the implantation efficiency of at least one of the contact layer and the defect layer decreases, and vice versa.

[0019] For example, the activated first dopant is, illustratively, located at substitution lattice sites. Further, the non-activated first dopant is, for example, illustratively located at interstitial lattice sites.

[0020] The concentration of the first dopant activated in the contact layer is, for example, at least 10% higher, illustratively 50% higher, than the concentration of the first dopant activated in the defect layer.

[0021] Illustratively, the concentration of the first dopant activated in the contact layer is at least 1·10

[0022] cm -3 . The concentration of the first dopant activated in the defect layer is, for example, at most 1·10 17 cm -3 .

[0022] In summary, such a structure for a semiconductor device can provide, among other things, the following advantages. Illustratively, the implantation efficiency of the structure can be preset by the concentration of the first dopant activated in the contact layer and the defect layer. Such a combination of the contact layer and the defect layer allows the implantation efficiency to be preset according to the needs of the semiconductor device.

[0023] According to at least one embodiment of the structure, the defect layer is provided between the contact layer and the base layer in at least some areas. For example, the base layer, the defect layer, and the contact layer are stacked vertically in the order shown herein. For example, the defect layer is in direct contact with the base layer.

[0024] For example, the defect layer is placed entirely between the contact layer and the base layer. In this case, the defect layer completely covers the main surface of the contact layer facing the defect layer.

[0025] Alternatively, the defect layer does not completely cover the main surface of the contact layer. In this case, the defect layer has a circular, elliptical, or polygonal cross-sectional shape in the horizontal direction. Furthermore, the defect layer may be located only in a few regions of the grid points of a grid, for example. At the grid points, the defect layer has a circular, elliptical, or polygonal cross-sectional shape in the horizontal direction.

[0026] For example, the contact layer and the defect layer have a difference in the concentration of the activated first dopant. Exemplarily, the defect layer extends to a boundary, which extends horizontally and is located vertically between the contact layer and the defect layer. For instance, the concentration of the activated first dopant in the defect layer rises to 50% of the difference at the boundary. Similarly, the concentration of the activated first dopant in the contact layer decreases to 50% of the difference at the boundary.

[0027] According to at least one embodiment of the structure, the defect layer is provided between the contact layer and the base layer in at least some areas. For example, the base layer, contact layer, and defect layer are stacked vertically in the order shown herein. In this embodiment, the contact layer is in direct contact with the base layer, for example. In this case, the defect layer is configured to be in contact with the outside. Thus, in this embodiment, the defect layer is configured to be in contact with the outside in an electrically conductive manner.

[0028] According to at least one embodiment of the structure, the defect concentration in the contact layer is lower than the defect concentration in the defect layer. For example, at least a portion of the first dopant forms crystallographic defects in at least one of the contact layer and the defect layer. Crystallographic defects are, exemplary, interruptions in the crystal lattice of at least one of the contact layer and the defect layer, such as atoms located at interstitial sites of the crystal lattice. Furthermore, crystallographic defects may be formed from vacancy defects. Vacancy defects are, exemplary, vacancies in the crystal lattice of at least one of the contact layer and the defect layer. For example, the defect concentration explains all crystallographic defects.

[0029] Furthermore, the injection efficiency of at least one of the contact layer and the defect layer depends on the defect concentration. For example, as the defect concentration increases, the injection efficiency decreases, and vice versa.

[0030] The defect concentration in the defect layer is, for example, at least 10% higher, and specifically 50% higher, than the defect concentration of the first dopant activated in the defect layer.

[0031] According to at least one embodiment of the structure, a second conductive buffer layer is provided between the contact layer and the defect layer and the base layer. The buffer layer includes or consists of a semiconductor material. In this embodiment, the base layer is in direct contact with the buffer layer.

[0032] For example, the buffer layer is doped to a higher concentration. Exemplarily, the base layer has a uniform doping concentration, while the buffer layer has a higher doping concentration than the uniform doping concentration of the base layer.

[0033] For example, the base layer, buffer layer, defect layer, and contact layer are stacked vertically in the order shown here. In this case, the buffer layer is in direct contact with the defect layer.

[0034] Alternatively, the base layer, buffer layer, contact layer, and defect layer are stacked vertically in the order shown here. In this case, the buffer layer is in direct contact with the contact layer.

[0035] According to at least one embodiment of the structure, the contact layer and the defect layer are at least one of the anode layer and the cathode layer for the semiconductor device. For example, at least one of the anode layer and the cathode layer is configured to contact metallization. Exemplarily, at least one of the anode layer and the cathode layer is freely accessible from the outside.

[0036] A second aspect of this disclosure relates to a semiconductor device, comprising the structures previously disclosed herein. Therefore, all features disclosed with respect to the structures are also disclosed with respect to the semiconductor device, and vice versa.

[0037] A third aspect of this disclosure relates to a method for manufacturing structures for semiconductor devices. For example, the method produces the structures for semiconductor devices described herein. Therefore, all features disclosed with respect to structures are also disclosed with respect to the method, and vice versa.

[0038] According to an embodiment of the second aspect of this method, a base layer and a semiconductor film disposed on the base layer are prepared. For example, the semiconductor film is epitaxially grown on the base layer.

[0039] According to an embodiment of this method, a first dopant is introduced into a semiconductor film. For example, the first dopant is injected into the semiconductor film. Exemplarily, the first dopant is introduced into the semiconductor film to a specific depth. For example, this depth is less than the thickness of the semiconductor film in the vertical direction. Alternatively, this depth is equal to the thickness of the semiconductor film in the vertical direction.

[0040] According to this embodiment of the method, the semiconductor film is heated in at least some regions, and contact layers and defect layers are generated in at least some regions. Exemplarily, heating allows at least a portion of the first dopant to migrate from interstitial lattice sites to substitutional lattice sites.

[0041] For example, the steps of this method are performed in the following order: preparing a base layer and a semiconductor film placed on the base layer; introducing a first dopant into the semiconductor film; and heating the semiconductor film in at least some regions.

[0042] According to this embodiment of the method, the contact layer and defect layer are of the first conductivity type, and the base layer is of the second conductivity type.

[0043] According to this embodiment of the method, the concentration of the first dopant in the activated first contact layer is higher than the concentration of the first dopant in the activated defect layer.

[0044] According to at least one embodiment of this method, the heating step is performed by laser treatment. For example, during laser treatment, laser light is applied to the semiconductor film.

[0045] For example, the laser light has an energy of at least 0.5 joules to a maximum of 8 J. The laser light includes, for example, a peak wavelength between 490 nm and 575 nm. The penetration depth of the laser light into the semiconductor film depends on the peak wavelength. The penetration depth of the laser light into the semiconductor film is, for example, between 0.01 μm and 10 μm.

[0046] According to at least one embodiment of this method, laser processing is applied to at least several regions on the outer surface of a semiconductor film. For example, this outer surface is oriented away from the base layer. Exemplarily, the horizontal cross-sectional shape of the defect layer depends on the horizontal cross-sectional shape of the laser beam.

[0047] For example, laser light can be applied completely to the outer surface of a semiconductor film so that the outer surface is completely covered by the laser light.

[0048] Alternatively, laser light can be applied to the outer surface of the semiconductor film at the lattice points of the grating. In this case, the resulting defect layer has a horizontal cross-sectional shape at the lattice points that matches the horizontal cross-sectional shape of the laser beam.

[0049] According to at least one embodiment of the present method, the laser treatment is an incomplete annealing treatment such that a defect layer is generated between the base layer and the contact layer. For example, the laser light of the laser treatment has a penetration depth perpendicular to the semiconductor film that is proportional to the peak wavelength of the laser light. Exemplarily, at least a portion of the first dopant introduced into the semiconductor film migrates from the interstitial lattice side to the substitution lattice side in a region perpendicular to the outer surface of the semiconductor film from the penetration depth. The semiconductor film is properly annealed within this region.

[0050] In this embodiment, the region of the semiconductor film closest to the outer surface is annealed, thereby properly forming a connecting layer, while the region of the semiconductor film closest to the base layer is not annealed, thereby forming a defect layer.

[0051] According to at least one embodiment of this method, the first dopant is at least 1.10 14 cm -2 It is introduced into the semiconductor film at a dose of . For example, the first dopant is at least 1.10 15 cm -2 It is introduced into the semiconductor film in a dose of . For example, the first dopant contains or consists of at least one of boron and phosphorus.

[0052] According to at least one embodiment of the present method, a first heating step is applied to the semiconductor film after the introduction of the first dopant. For example, in the first heating step, the semiconductor film is heated to at least 900°C. Exemplarily, in this step, the entire semiconductor film having the first dopant is annealed, and at least a portion of the first dopant moves from the interstitial lattice side to the substitution lattice side of the semiconductor film.

[0053] In this step, for example, the overall amorphousness of the semiconductor film decreases.

[0054] According to at least one embodiment of the present method, after the first heating step, a further first dopant is introduced into the semiconductor film. Exemplarily, the further first dopant is the same dopant as the first dopant. Alternatively, the further first dopant comprises a different material than the first dopant.

[0055] A further first dopant is introduced into the semiconductor film to a depth less than the thickness of the semiconductor film in the vertical direction, or to a depth equal to the thickness of the semiconductor film in the vertical direction.

[0056] If the first dopant is introduced into the semiconductor film to a depth less than the thickness of the semiconductor film in the vertical direction, then any further first dopants are introduced into the semiconductor film to a depth greater than the depth of the first dopant in the vertical direction.

[0057] If a further first dopant is introduced into the semiconductor film to a depth less than that of the first dopant, the region of the semiconductor film closer to the outer surface will contain the further first dopant, while the region of the semiconductor film closer to the base layer will not contain the further first dopant. For example, the amorphous nature of the semiconductor film increases in the region closer to the outer surface.

[0058] When a further first dopant is introduced into the semiconductor film to a depth greater than the depth of the first dopant, the region closer to the outer surface of the semiconductor film contains the further first dopant and the activated first dopant, and the region closer to the base layer in the semiconductor film contains the further first dopant. Exemplarily, in the region closer to the base layer, the amorphousness of the semiconductor film increases.

[0059] According to at least one embodiment of the present method, the further first dopant is introduced into the semiconductor film at a dose of up to 1×10 14 cm -2 . The further first dopant is introduced into the semiconductor film with an applied energy of up to 100 keV. For example, the further first dopant contains at least one of boron and phosphorus, or consists of them.

[0060] According to at least one embodiment of the present method, a second heating step is applied to the semiconductor film so that a defect layer is generated. For example, the semiconductor film is heated up to 500 °C in the second heating step. Exemplarily, at least a part of the further first dopant moves from the interstitial lattice site to the substitutional lattice site in the semiconductor film due to the second heating step. In this case, the movement is not as efficient as in the first heating step. Therefore, there is relatively little further first dopant moving from the interstitial lattice site to the substitutional lattice site.

[0061] Exemplarily, the region closer to the outer surface of the semiconductor film containing the further first dopant forms a defect region, and the region closer to the base layer of the semiconductor film not containing the further first dopant forms a contact layer.

[0062] Alternatively, the region closer to the base layer of the semiconductor film containing the further first dopant forms a defect region, and the region closer to the base layer of the semiconductor film containing the first dopant and the further first dopant forms a contact layer.

[0063] According to at least one embodiment of this method, the first heating step is laser treatment or furnace treatment.

[0064] According to at least one embodiment of this method, the second heating step is a sintering process.

[0065] For example, metallization is provided on the outer surface of a semiconductor film. Exemplarily, the metallization may contain or consist of a metal. For instance, this metallization can be provided on the outer surface of a semiconductor film by a sintering process.

[0066] According to at least one embodiment of this method, the temperature of the first heating step is higher than the temperature of the second heating step.

[0067] According to at least one embodiment of this method, the buffer layer is provided on the base layer. That is, the buffer layer is provided between the base layer and the contact layer.

[0068] The subject matter of this disclosure will be described in further detail below with reference to exemplary embodiments shown in the accompanying drawings. [Brief explanation of the drawing]

[0069] [Figure 1] The prior art and a schematic cross-sectional view of a structure according to one embodiment are shown. [Figure 2] The spread resistance profiles of various structures according to various embodiments are illustrated exemplarily. [Figure 3] The spread resistance profiles of various structures according to various embodiments are illustrated exemplarily. [Figure 4] The technical curves of various structures according to various embodiments are illustrated exemplarily. [Figure 5] The spread resistance profiles of various structures according to various embodiments are illustrated exemplarily. [Figure 6] The technical curves of various structures according to various embodiments are illustrated exemplarily. [Figure 7] This illustrates the waveform turn-off of a semiconductor device structure. [Figure 8] This illustrates the nominal on-state measurements of semiconductor device structures. [Figure 9] The spread resistance profiles of various structures according to various embodiments are illustrated exemplarily. [Figure 10] The spread resistance profiles of various structures according to various embodiments are illustrated exemplarily. [Figure 11] A schematic flowchart of a method for manufacturing a structure for a semiconductor device according to one embodiment is shown. [Modes for carrying out the invention]

[0070] The reference numerals used in the drawings and their meanings are listed in a summary format in the "Explanation of Symbols." As a general rule, identical parts are given the same reference numeral in the drawings.

[0071] The structure shown at the top of Figure 1 schematically represents structure 1A of a semiconductor device according to prior art.

[0072] The structure shown at the bottom of Figure 1 represents a semiconductor device structure 1 according to one embodiment.

[0073] Structure 1 in Figure 1 includes a contact layer 4 containing a first dopant of a first conductivity type and a defect layer 5 containing a first dopant of a first conductivity type. The contact layer 4 and the defect layer 5 are located on a buffer layer 3 and a base layer 2.

[0074] The contact layer 4, defect layer 5, buffer layer 3, and base layer 2 are stacked on top of each other and in direct contact with each other. Furthermore, the concentration of the first dopant activated in the contact layer 4 is higher than the concentration of the first dopant activated in the defect layer 5.

[0075] The width of the contact layer 4 is, for example, 5 μm or less. In this embodiment, the width of the defect layer 5 is smaller than the width of the contact layer 4.

[0076] Figure 2 shows the spread resistance profiles (SRPs) of four different structures 1. The SRP expresses the measured resistivity of a semiconductor device containing structure 1 as a function of position. The measured resistivity is proportional to the activated carrier density, i.e., the number of electrically active electrons or holes in a given volume. Therefore, the SRP is calculated using "ActiveNet" in cm². -3 It is proportional to the concentration of the first activated dopant represented by . The x-axis range in Figures 2, 3, and 5 is 0 μm to 3 μm, and the x-axis range in Figures 9 and 10 is 0 μm to 2.5 μm.

[0077] The contact layer 4 and defect layer 5 of structure 1 are used as the anode layer in a semiconductor device. The first dopant in this case is boron and phosphorus. Furthermore, all four different structures 1 have the same buffer layer 3.

[0078] Buffer layer 3 is of a second conductive type and is generated, for example, by ion implantation of a second dopant. The second dopant of buffer layer 3 is activated, for example, by laser treatment.

[0079] The contact layer 4 and the defect layer 5 are generated by first incorporating a first dopant into the semiconductor film. The dose of the first dopant is the same for all four structures 1.

[0080] The first dopants in the contact layer 4 and defect layer 5 of structure 1 are activated by laser processing, which is an incomplete laser annealing process, using four different laser energies ranging from 1.1 joules to 1.4 joules, such that the total injection efficiency of the contact layer 4 and defect layer 5 differs for all four structures 1.

[0081] The SRP with the lowest concentration at 1 μm corresponds to a laser energy of 1.1 J. The SRP with the second lowest concentration at 1 μm, i.e., the fourth division on the x-axis, corresponds to a laser energy of 1.4 J, the SRP with the third lowest concentration at 1 μm corresponds to a laser energy of 1.2 J, and the SRP with the highest concentration at 1 μm corresponds to a laser energy of 1.3 J.

[0082] Figure 3 shows the SRPs of two structures 1. Structure 1 with SRP "E" is manufactured in a single heating step. However, the contact layer 4 and defect layer 5 of structure 1 with SRP "F" are generated by performing a first heating step after incorporating a first dopant into the semiconductor film, and a second heating step after incorporating a further first dopant into the semiconductor film.

[0083] Figure 4 shows the turn-off loss Eoff (in mJ) for various structures 1, depending on the collector-emitter voltage Vce (in V). This type of representation is also called a "technical curve."

[0084] The first Dopant was 1.10 15 cm -2 The first dopant is incorporated into the semiconductor film of the semiconductor device structure 1 corresponding to "G" and "I" at a dose of 5.10. 15 cm -2 The semiconductor film of the device structure 1 corresponding to "H" and "J" is incorporated in the dose of . Subsequently, the semiconductor film of the structure 1 corresponding to "G" and "H" is heated with an energy of 1.3 J by an incomplete annealing process to generate the contact layer 4 and the defect layer 5. Furthermore, the semiconductor film of the structure 1 corresponding to "I" and "J" is heated with an energy of 1.1 J by an incomplete annealing process to generate the contact layer 4 and the defect layer 5.

[0085] By having the same laser processing energy, a semiconductor device structure 1 processed at a higher dose will have a higher ON state due to incomplete annealing of defects during the laser annealing process. Therefore, as the dose increases, the injection efficiency decreases, i.e., the ON state increases.

[0086] Figure 5 shows the SRPs of the six structures 1. The two structures 1 corresponding to "L" do not contain any further inclusion of the first dopant. The two structures 1 corresponding to "M" use an energy of 25 keV to obtain 1.10 13 cm -2 Further doses of the first dopant are incorporated. Two structures corresponding to "N" are given 1.10 using an energy of 25 keV. 14 cm -2 Further doses of the first dopant are being incorporated.

[0087] Furthermore, each of the three SRPs with three concentrations at 1 μm corresponds to a laser energy of 1.6 J. Each of the three SRPs with the highest concentration at 1 μm corresponds to a laser energy of 1.4 J.

[0088] Figure 6 shows the turn-off loss Eoff (in mJ) for various structures 1, corresponding to the collector-emitter voltage Vce (in V).

[0089] Various semiconductor devices indicated by unfilled symbols, i.e., structure 1 of the device indicated by "R", are annealed with a laser treatment having an energy of 1.6 J. Various semiconductor devices indicated by filled symbols, i.e., structure 1 of the device indicated by "Q", are annealed with a laser treatment having an energy of 1.4 J. Devices indicated by circles are manufactured in one injection step and one incomplete annealing step. Devices indicated by squares and triangles are manufactured in two injection steps and two annealing steps. The defect layer 5 of the device indicated by a square is manufactured with a smaller dose of an additional first dopant than the defect layer 5 of the device indicated by a triangle.

[0090] Figure 7 schematically shows the turn-off waveforms measured under reverse bias safe operating area (RBSOA) conditions, where a maximum voltage of 1300V and 300A are applied at 175°C, for three different 1700V semiconductor devices, each comprising structure 1 according to one embodiment.

[0091] Devices indicated by "S" and "V" are manufactured in one injection step and one incomplete annealing step. Defect layer 5 of devices indicated by "T" and "W" as well as "U" and "X" is manufactured in two injection steps and two annealing steps. With respect to devices indicated by "T" and "W", a further first dopant is produced in 1.10 13 cm -2 It is introduced into the semiconductor film at a dose of 5.10. For devices indicated by "U" and "X", a further first dopant is introduced at 5.10. 13 cm -2 It is introduced into the semiconductor film in a dose. A further first dopant is formed, for example, with boron.

[0092] The nominal on-state measurements of various semiconductor device structures 1 are shown in Figure 8. The measurement point group indicated by "a" corresponds to four semiconductor device structures 1 manufactured by one injection step and one incomplete annealing step. The first dopant is at least 10 13 cm -2 and up to 5 10 16 cm -2 It is taken in at the dose. Structure 1 is annealed with an incomplete laser treatment having energies of 1.5 J for the device in the first position from the left, 2.0 J for the device in the second position from the left, 2.5 J for the device in the third position from the left, and 3.0 J for the device in the fourth position from the left.

[0093] The measurement point cluster indicated by "b" corresponds to four semiconductor device structures 1 manufactured by two injection steps and two annealing steps. Compared to the device indicated by "a", an additional first dopant, such as boron, is incorporated into the semiconductor film to generate a defect layer 5.

[0094] The measurement point cloud indicated by "c" corresponds to structure 1 of four semiconductor devices manufactured similarly to the device indicated by "a". In comparison, the first dopant is incorporated into the semiconductor film to generate a defect layer 5 with a higher dose than that of the first dopant for the device indicated by "a".

[0095] The measurement point cloud indicated by "d" corresponds to structure 1 of four semiconductor devices manufactured similarly to the device indicated by "b". In comparison, the first dopant is incorporated into the semiconductor film in the first incorporation step to generate a defect layer 5 with a higher dose of the first dopant than the dose of the first dopant for the device indicated by "a".

[0096] Figure 9 shows the SRPs of seven structures 1 of various semiconductor devices. The device contact layers 4 and defect layers 5 are fabricated by laser processing at different annealing energies. Compared to Figure 5, the doses for incorporating the first dopant and further first dopants are higher. In the depth range from 0.0 μm to 0.5 μm, the region indicated by "Y" corresponds to the SRP of devices fabricated with higher doses of further first dopants than the device indicated by "N" in Figure 5.

[0097] Figure 10 shows the SRPs of four structures 1 of various semiconductor devices, and the dose of the first dopant is 10 15 cm -2 Larger than that, the dose of the first dopant is 10 15 cm -2 It is larger than that.

[0098] According to Figure 11, first, a base layer 2 and a semiconductor film placed on the base layer 2 are prepared (100). Next, a first dopant is introduced into the semiconductor film (200). In the next step, the semiconductor film is heated in at least some regions (300), and a contact layer 4 and a defect layer 5 are generated in at least some regions (400). Here, the contact layer 4 and the defect layer 5 are of the first conductivity type, and the base layer 2 is of the second conductivity type. Furthermore, the concentration of the first dopant in the activated contact layer 4 is higher than the concentration of the first dopant in the activated defect layer 5. [Explanation of Symbols]

[0099] Explanation of the symbols 1 structure 1A Structures based on prior art 2 Base layer 3 Buffer Layers 4. Contact Layer 5. Defective layer ad measurement point cloud EF SRP Structure corresponding to the GJ measurement point LP SRP Structure corresponding to the Q,R measurement points Structure corresponding to the SX measurement point A part of Y SRP

Claims

1. A structure (1) for a semiconductor device, comprising: a contact layer (4) of first conductivity type containing a first dopant of the first conductivity type; a base layer (2) of a second conductivity type different from the first conductivity type; a defect layer (5) of said first conductivity type containing a first dopant of said first conductivity type; Equipped with the concentration of the first dopant activated in the contact layer (4) is higher than the concentration of the first dopant activated in the defect layer (5); A structure (1), wherein the buffer layer (3) of the second conductivity type is provided between the contact layer (4) and the defect layer (5) and the base layer (2).

2. 2. The structure (1) according to claim 1, wherein the defect layer (5) is provided between the contact layer (4) and the base layer (2) in at least some regions.

3. The structure (1) according to claim 1, wherein the contact layer (4) is provided between the defect layer (5) and the base layer (2).

4. The structure (1) according to any one of claims 1 to 3, wherein a defect concentration in the contact layer (4) is lower than a defect concentration in the defect layer (5).

5. The structure (1) according to any one of claims 1 to 4, wherein the contact layer (4) and the defect layer (5) are at least one of an anode layer and a cathode layer for a semiconductor device.

6. A semiconductor device comprising a structure (1) described in any one of claims 1 to 5.

7. A method for manufacturing a structure (1) for a semiconductor device, comprising the steps of: Providing a base layer (2) and a semiconductor film disposed on said base layer (2); - introducing a first dopant into the semiconductor film; - heating said semiconductor film in at least some regions such that a contact layer (4) and a defect layer (5) are generated in at least some regions; Including, the contact layer (4) and the defect layer (5) are of a first conductivity type and the base layer (2) is of a second conductivity type; the concentration of the first dopant in the contact layer (4) to be activated is higher than the concentration of the first dopant in the defect layer (5) to be activated; The method, wherein the buffer layer (3) of the second conductivity type is provided between the contact layer (4) as well as the defect layer (5) and the base layer (2).

8. The heating step is carried out by laser processing; the laser treatment is applied to an outer surface of the semiconductor film in at least some areas; the laser treatment is an incomplete annealing treatment so that the defect layer (5) is created between the base layer (2) and the contact layer (4); The method of claim 7.

9. The first dopant has a dopant content of at least 1.10 １４ cm －２ The method of claim 8 , wherein the semiconductor film is introduced at a dose of

10. The heating step includes at least two heating steps, - after said introduction of said first dopant, a first heating step is applied to said semiconductor film; - after the first heating step, a further first dopant is introduced into the semiconductor film; - after said introduction of said further first dopant, a second heating step is applied to said semiconductor film so as to generate said defect layer (5); The method of claim 7.

11. The further first dopant has a maximum of 1.10 １４ cm －２ The method of claim 10, wherein the semiconductor film is introduced at a dose of

12. the first heating step is a laser treatment or a furnace treatment, the second heating step is a sintering process; 12. The method according to claim 10 or 11.

13. The method according to any one of claims 10 to 12, wherein the temperature of the first heating step is higher than the temperature of the second heating step.

14. The method according to any one of claims 8 to 13, wherein the buffer layer (3) comprises a second dopant.

15. The method according to any one of claims 8 to 14, wherein the second dopant of the buffer layer (3) is activated by a laser treatment.

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