Photoelectric conversion device, and apparatus

Abstract

To provide a photoelectric conversion device that can be driven at high speed.SOLUTION: A photoelectric conversion device comprises: a first member in a first semiconductor layer having a photoelectric conversion unit, and a transfer transistor that transfers electric charges generated in the photoelectric conversion unit; a second member in a second semiconductor layer having a read-out circuit that outputs signals based on the electric charges transferred from the transfer transistor; and a third member in a third semiconductor layer having a signal processing circuit that processes signals. The first member, second member, and third member are laminated, and a source region or a drain region of a transistor forming the read-out circuit is provided with a salicide structure.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device and an instrument. [Background technology]

[0002] In recent years, in order to achieve miniaturization, high sensitivity, and multi-function in photoelectric conversion devices such as imaging devices, back-illuminated sensors and stacked sensors in which a substrate for a sensor and a substrate for a signal processing circuit are stacked have been proposed. Patent Document 1 discloses a configuration in which a first semiconductor layer in which a photoelectric conversion unit and a transfer transistor are provided is stacked with a second semiconductor layer in which a readout circuit having an amplification transistor, a reset transistor, and a selection transistor is provided. As a result, Patent Document 1 realizes a further high density of pixels. Patent Document 1 also discloses that the resistance value is reduced by providing silicide to the gate of the selection transistor and the gate of the amplification transistor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2020 / 262643 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, there is no consideration of reducing the resistance of the source / drain of the transistor constituting the readout circuit. Therefore, an object of the present invention is to provide a photoelectric conversion device that can be driven at high speed with lower resistance than the transistor constituting the readout circuit disclosed in Patent Document 1. [Means for solving the problem]

[0005] A photoelectric conversion device according to the present invention comprises a first member having, in a first semiconductor layer, a photoelectric conversion unit and a transfer transistor that transfers charges generated in the photoelectric conversion unit; a second member having, in a second semiconductor layer, a readout circuit that outputs a signal based on the charges transferred from the transfer transistor; and a third member having, in a third semiconductor layer, a signal processing circuit that processes the signal, wherein the photoelectric conversion device is stacked such that a first wiring structure of the first member is provided between the first semiconductor layer and the second semiconductor layer, and a second wiring structure of the second member and a third wiring structure of the third member are provided between the second semiconductor layer and the third semiconductor layer, and the readout circuit is configured to output the signal from the second member to the third member via an output line provided in the second wiring structure, and the photoelectric conversion device is characterized in that a source region or a drain region of a transistor constituting the readout circuit has a salicide structure. Effect of the Invention

[0006] According to the present invention, it is possible to provide a photoelectric conversion device that has lower resistance and can be driven at high speed compared to the transistors constituting the readout circuit disclosed in Patent Document 1. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a configuration of a photoelectric conversion device according to a first embodiment. [Diagram 2] FIG. 1 is a circuit diagram showing a schematic configuration of a photoelectric conversion unit and a readout circuit according to a first embodiment; [Diagram 3] FIG. 1 is a diagram showing a configuration of a photoelectric conversion device according to a first embodiment. [Figure 4] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a photoelectric conversion device according to a first embodiment. [Diagram 5] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a photoelectric conversion device according to a first embodiment. [Figure 6] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a photoelectric conversion device according to a first embodiment. [Figure 7]5A to 5C are cross-sectional views illustrating steps of a method for manufacturing a photoelectric conversion device according to a second embodiment. [Figure 8] 5A to 5C are cross-sectional views illustrating steps of a method for manufacturing a photoelectric conversion device according to a second embodiment. [Figure 9] FIG. 13 is a diagram showing the configuration of a photoelectric conversion device according to a third embodiment. [Figure 10] FIG. 13 is a diagram showing the configuration of an apparatus according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The embodiments described below are intended to embody the technical ideas of the present invention, and are not intended to limit the present invention. The size and positional relationship of the components shown in each drawing may be exaggerated to clarify the explanation. The same configurations may be given the same numbers and the explanation may be omitted. The configurations described in each embodiment may be mutually substituted or combined with the configurations described in other embodiments, as long as there is no technical problem.

[0009] In the following description, terms indicating specific directions or positions (for example, "upper", "lower", "right", "left" and other terms including these terms) are used as necessary. The use of these terms is for the purpose of facilitating understanding of the invention with reference to the drawings, and the technical scope of the present invention is not limited by the meaning of these terms. In other words, even a configuration in which the top and bottom are reversed falls within the technical scope of the present invention.

[0010] In each embodiment, a photoelectric conversion device and an apparatus having the photoelectric conversion device will be described. Photoelectric conversion devices include an imaging device, a distance measuring device, a photometry device, and the like. A distance measuring device is, for example, a device that performs distance measurement using focus detection or TOF (Time Of Flight). A photometry device is, for example, a device that measures the amount of incident light.

[0011] The conductivity types of the semiconductor regions and wells and the dopants to be implanted described in the following embodiments are merely examples and are not limited to those described in the embodiments. The conductivity types and dopants described in the embodiments can be changed as appropriate. In addition, the potentials of the semiconductor regions and wells are changed as appropriate in accordance with the changes.

[0012] The conductivity type of the transistor described in the following embodiment is an example, and is not limited to the conductivity type described in the embodiment. The conductivity type can be changed as appropriate to the conductivity type described in the embodiment. For example, the following description will be given with an N-type semiconductor as an example of the first conductivity type semiconductor, and a P-type semiconductor as an example of the second conductivity type semiconductor, but this relationship may be reversed.

[0013] In the following embodiments, the connection between elements of a circuit may be described. In this case, even if another element is interposed between the elements of interest, the elements of interest are treated as being electrically connected to each other unless otherwise specified. For example, assume that element A is connected to one node of a capacitive element C having multiple nodes, and element B is connected to the other node. Even in such a case, element A and element B are treated as being electrically connected to each other unless otherwise specified.

[0014] Metallic members such as wiring and pads described in this specification may be composed of a single metal element or may be a mixture (alloy). For example, wiring described as copper wiring may be composed of a single copper element or may be composed mainly of copper and further contain other components. Also, for example, pads connected to external terminals may be composed of a single aluminum element or may be composed mainly of aluminum and further contain other components. The copper wiring and aluminum pads shown here are examples and can be changed to various metals.

[0015] (First embodiment) 1 shows an example of the configuration of a photoelectric conversion device according to this embodiment. The photoelectric conversion device includes three substrates (a first member 10, a second member 20, and a third member 30), and is an imaging device with a three-dimensional structure configured by bonding these three parts together. The first member 10, the second member 20, and the third member 30 are stacked in this order. That is, the second member 20 is stacked on the first member 10, and the third member 30 is stacked on the second member 20.

[0016] The first member 10 has a plurality of sensor units 12 that perform photoelectric conversion. A sensor region 13 is provided in the semiconductor layer 100 (first semiconductor layer), and a plurality of sensor units 12 are provided in a matrix in the sensor region 13. Each sensor unit 12 is sometimes called a "pixel."

[0017] The second member 20 has a readout circuit 22 in the semiconductor layer 200 (second semiconductor layer) that outputs a signal based on the signal charge output from the sensor unit 12. For example, one readout circuit 22 is provided for each of four sensor units 12. The second member 20 has a plurality of drive lines 24 extending in the row direction and a plurality of output lines 25 extending in the column direction. The drive lines 24 are control lines for controlling the transistors that constitute the readout circuit 22. For example, the drive lines 24 are arranged so as to be electrically connected to the gates of the reset transistor and the selection transistor. The output lines 25 are wiring for inputting the output signal from the sensor unit 12 to the third member 30.

[0018] The third member 30 has a logic circuit in the semiconductor layer 300 (third semiconductor layer) for processing a signal output from the semiconductor layer 21. The logic circuit has, for example, a vertical scanning circuit 42, a column signal processing circuit 34, a horizontal scanning circuit 35, a memory 36, and an output circuit 38. The horizontal scanning circuit 35 outputs a signal from the sensor unit 12 stored in the memory 36 to the outside of the photoelectric conversion device via the output circuit 38. In the logic circuit, for example, a low resistance region made of a silicide structure formed by a salicide (self aligned silicide) process may be formed on the surface of the impurity diffusion region in contact with the source and drain. The salicide process will be described in detail later.

[0019] The vertical scanning circuit 42, for example, sequentially selects the plurality of sensor units 12 on a row-by-row basis. The column signal processing circuit 34, for example, performs correlated double sampling (CDS) processing on signals output from each sensor unit 12 in the row selected by the vertical scanning circuit 42. The column signal processing circuit 34, for example, has an AD conversion circuit that converts a signal (analog signal) output by an amplification transistor into a digital signal. The memory 36 holds data according to the amount of light received by each sensor unit 12. The horizontal scanning circuit 35, for example, sequentially outputs the data held in the memory 36 to the outside via the output circuit 38. The control circuit (not shown), for example, controls the driving of each block (the vertical scanning circuit 42, the column signal processing circuit 34, and the horizontal scanning circuit 35) in the logic circuit.

[0020] Fig. 2 shows a configuration example of the sensor unit 12 of the first member 10 and a configuration example of the readout circuit 22 of the second member 20. In the following, a case will be described in which four sensor units 12_a to 12_d share one readout circuit 22 as shown in Fig. 2. Here, "shared" refers to the outputs of the four sensor units 12_a to 12_d being input to a common readout circuit 22. In the following, when common matters regarding the sensor units 12_a to 12_d are described, they may be referred to as sensor unit 12.

[0021] Each sensor unit 12 has, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a first FD node FD1 that is a part of a floating diffusion (FD). The photodiode and the transfer gate components in each sensor unit 12 are designated by the suffixes a to d.

[0022] The readout circuit 22 has a second FD node FD2 which is another part of the floating diffusion FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The four first FD nodes FD1_a to FD1_d are connected to one second FD node FD2. The second FD node FD2 is an input node of the amplification transistor AMP.

[0023] The photodiode PD (photoelectric conversion unit) is an element that generates charges according to the amount of received light. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is given a potential that is applied to the well region. For example, a reference potential (e.g., a ground potential) is electrically connected to the anode and well region of the photodiode PD. In addition, the photodiode PD is provided inside the well region connected to this reference potential line. The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to a drive line 24.

[0024] The floating diffusions FD of the sensor units 12 sharing one readout circuit 22 are electrically connected to each other and to an input terminal of the common readout circuit 22. The readout circuit 22 includes, for example, a reset transistor RES, a selection transistor SEL, and an amplification transistor AMP. The selection transistor SEL may be omitted as necessary.

[0025] The source of the reset transistor RES (the input terminal of the read circuit 22) is electrically connected to the floating diffusion FD. In addition, the drain of the reset transistor RES is electrically connected to a power supply line (SVDD). In addition, the drain of the amplification transistor AMP is electrically connected to the power supply line (SVDD). The gate of the reset transistor RES is electrically connected to a drive line 24. The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RES. The source of the selection transistor SEL (the output terminal of the read circuit 22) is electrically connected to an output line 25, and the gate of the selection transistor SEL is electrically connected to the drive line 24.

[0026] When the transfer transistor TR is turned on (conductive), the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD. The reset transistor RES resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RES is turned on, the potential of the floating diffusion FD is reset to the potential of the power supply line (SVDD). The selection transistor SEL controls the output timing of the signal from the readout circuit 22. The amplification transistor AMP generates a signal having a voltage corresponding to the level of the charge held in the floating diffusion FD. The amplification transistor AMP constitutes a source follower type amplifier, and outputs a pixel signal having a voltage corresponding to the level of the charge generated in the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the column signal processing circuit 34 via the output line 25. The transfer transistor TX, the reset transistor RES, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors.

[0027] The selection transistor SEL may be provided between the power supply line (SVDD) and the amplification transistor AMP. In this case, the drain of the reset transistor RES is electrically connected to the power supply line (SVDD) and the selection transistor SEL. Also, the source of the amplification transistor AMP (the output terminal of the readout circuit 22) is electrically connected to the output line 25. Also, a switch for changing the capacitance value of FD may be further provided in the electrical path between the reset transistor RES and the second FD node FD2.

[0028] 3 is a schematic cross-sectional view of the photoelectric conversion device of this embodiment. This cross-sectional view shows a cross section of a line passing through the photodiode PD and the gate of the transfer transistor TR in the first member 10, the second member 20, and the third member 30.

[0029] The lower side of Fig. 3 is the light incident surface side, and the upper side of Fig. 3 is the opposite side to the light incident surface side. Since the configuration shown in Fig. 3 is a back-illuminated type (BSI type), the light incident surface side (lower side) is sometimes called the back surface side, and the opposite side to the light incident surface type (upper side) is sometimes called the front surface side.

[0030] The photoelectric conversion device of this embodiment has a first semiconductor layer 100, a second semiconductor layer 200, and a third semiconductor layer 300. A first wiring structure 190 is provided between the first semiconductor layer 100 and the second semiconductor layer 200, and a second wiring structure 290 and a third wiring structure 390 are provided between the second semiconductor layer 200 and the third semiconductor layer 300.

[0031] The first semiconductor layer 100 includes a sensor region, and has a photoelectric conversion unit 111 and an FD 112. The photoelectric conversion unit 111 is composed of a semiconductor region of a first conductivity type (e.g., N type), and serves as a region for generating and accumulating signal charges (e.g., electrons). The region surrounding the photoelectric conversion unit is composed of a semiconductor region of a second conductivity type (e.g., P type). As a result, a PN junction diode is formed by the semiconductor region constituting the photoelectric conversion unit 111 of the first conductivity type and the semiconductor region of the second conductivity type. The FD 112 is composed of a semiconductor region of the first conductivity type (e.g., N type).

[0032] On the first semiconductor layer 100, a gate electrode 120 of a transfer transistor that transfers the charge accumulated in the photoelectric conversion unit 111 to the FD 112 is provided. A channel region is formed by applying a predetermined voltage to the gate electrode 120, and a signal charge is transmitted from the photoelectric conversion unit 111 to the FD 112. Each photoelectric conversion unit 111 is separated by a separation unit (not shown). The separation unit has a function of electrically separating each photoelectric conversion unit 111. The separation unit may be configured to include an insulating unit such as silicon oxide. Typically, the separation unit is configured by LOCOS, STI, DTI, or the like. The separation unit may also be configured by a semiconductor region that forms a potential barrier. Typically, the separation unit is a semiconductor region in which charges of the opposite polarity to the signal charge accumulated by the photoelectric conversion unit 111 are used as the main carrier. Specifically, the separation unit is a semiconductor region of a second conductivity type (e.g., P type), and the photoelectric conversion unit 111 and this second conductivity type semiconductor region form a PN junction.

[0033] In addition, in Fig. 2, four sensor units 12 are connected to one amplification transistor AMP. However, in the cross-sectional view of Fig. 3, the configuration of Fig. 2 is appropriately simplified.

[0034] A first diffusion prevention layer 121 against metal elements is disposed on the photoelectric conversion section 111, the FD 112, and the gate electrode 120. The first diffusion prevention layer 121 has an effect of suppressing diffusion of metal elements from the second semiconductor layer 200 and the third semiconductor layer 300 side to the first semiconductor layer 100. The metal elements provided in the second semiconductor layer 200 and the third semiconductor layer 300 will be described later. The first diffusion prevention layer 121 is, for example, silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbide (SiC). Typically, it is silicon nitride. Note that the first diffusion prevention layer 121 is disposed on the FD 112, but a contact electrode is disposed so as to contact the FD 112, so that a part of the first diffusion prevention layer 121 provided on the FD 112 is removed.

[0035] A second semiconductor layer 200 is provided on the first semiconductor layer 100, and an insulating film 130 is disposed between the front surface side of the first semiconductor layer 100 and the back surface side of the second semiconductor layer 200. The insulating film 130 is a part of the first wiring structure 190. The insulating film 130 is, for example, silicon oxide (SiO).

[0036] In the second semiconductor layer 200, an element isolation region 201 such as silicon oxide (SiO) is disposed. In the second semiconductor layer 200, a read circuit 22 is disposed. As described above, the read circuit 22 has, for example, a reset transistor RES, a selection transistor SEL, and an amplification transistor AMP. The first semiconductor layer 100 and the second semiconductor layer 200 are bonded together such that the front side of the first semiconductor layer 100 and the back side of the second semiconductor layer 200 face each other. That is, these semiconductor layers are bonded face-to-back. A source / drain region 211 of a transistor disposed in the second semiconductor layer 200 has an impurity diffusion region 212 and a low resistance region 213. The low resistance region 213 is a silicide structure formed by using a salicide (Self Aligned Silicide) process.

[0037] The salicide process is carried out in the following steps: (a) forming a film of metal elements on a semiconductor layer, (b) silicidation, and (c) removing the metal elements. First, a film containing metal elements is formed on the surface of the semiconductor layer by a PVD method or the like. Next, when the semiconductor layer is heated, the metal elements on the semiconductor layer react to form silicide. The metal film on the region that is not the semiconductor layer, for example, the metal film on an insulating film such as a silicon oxide film, is not silicided and remains as a metal film. Next, only the metal film on the insulating film is selectively removed by a chemical treatment. According to this process, if an insulating film is not provided on the gate, source, and drain of a transistor, silicide will remain on these. Since silicide is formed in a self-aligned manner in this way, it is called the salicide process.

[0038] In addition, when a semiconductor region that is to become a source or drain region is heated in a state where the semiconductor region is in contact with a metal such as a contact electrode, the contact portion between the semiconductor region and the metal may be silicided. In this case, the silicide is in contact with the metal, but is not in contact with the insulating film. In this specification, the silicide formed in such a process is not included in the salicide structure or silicide structure.

[0039] The metal element constituting the silicide structure is, for example, at least one selected from the group consisting of titanium, nickel, cobalt, tungsten, molybdenum, tantalum, chromium, palladium, and platinum, or an alloy containing the same as a main component. As an example, the silicide structure provided in the source / drain region 211 of the transistor in the second semiconductor layer 200 is cobalt silicide, and the metal element constituting the silicide structure is cobalt.

[0040] A second diffusion prevention layer 217 is disposed so as to cover the source / drain region 211 and the gate electrode 214 of the transistor provided in the second semiconductor layer 200. The second diffusion prevention layer 217 has an effect of suppressing diffusion of metal elements contained in the low resistance region 213. The second diffusion prevention layer 217 is, for example, silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbide (SiC).

[0041] Here, the first semiconductor layer 100 and the second semiconductor layer 200 are bonded face-to-back. If the first semiconductor layer 100 and the second semiconductor layer 200 are bonded face-to-face, the distance between the low resistance region 213 provided in the second semiconductor layer 200 and the photoelectric conversion section 111 is shortened. Then, the metal element in the silicide structure formed in the low resistance region 213 is likely to diffuse to the photoelectric conversion section 111 and become a noise component in the photoelectric conversion section 111. On the other hand, if the first semiconductor layer 100 and the second semiconductor layer 200 are bonded face-to-back, the distance between the low resistance region 213 and the photoelectric conversion section 111 is long. Therefore, the metal element in the silicide structure formed in the low resistance region 213 is unlikely to diffuse to the photoelectric conversion section 111 and become a noise component in the photoelectric conversion section 111. Therefore, in this embodiment, a configuration is adopted in which the first semiconductor layer 100 and the second semiconductor layer 200 are bonded together face-to-back.

[0042] Insulating films 230 and 330 are disposed between the front surface side of the second semiconductor layer 200 and the front surface side of the third semiconductor layer 300. The insulating film 230 is a part of the second wiring structure 290, and the insulating film 330 is a part of the third wiring structure 390. The insulating films 230 and 330 are, for example, silicon oxide (SiO).

[0043] Transistors constituting a logic circuit are provided in the third semiconductor layer 300. The second semiconductor layer 200 and the third semiconductor layer 300 are bonded together such that the front surface side of the second semiconductor layer 200 and the front surface side of the third semiconductor layer 300 face each other. That is, these semiconductor layers are bonded together face-to-face.

[0044] The transistors provided in the third semiconductor layer 300 are transistors that are more miniaturized than the transistors provided in the second semiconductor layer 200. As described above, the transistors provided in the third semiconductor layer 300 are transistors that constitute a logic circuit. For example, they are a horizontal scanning circuit, a column signal processing circuit, a horizontal scanning circuit, and the like. The column signal processing circuit also includes, for example, an AD conversion circuit. The source / drain region 311 of the transistor in the third semiconductor layer 300 has an impurity diffusion region 312 and a low resistance region 313. The low resistance region 313 is a silicide structure formed by using a salicide process. The metal element that constitutes the silicide structure is, for example, at least one selected from the group consisting of titanium, nickel, cobalt, tungsten, molybdenum, tantalum, chromium, palladium, and platinum, or an alloy containing it as a main component. As an example, the silicide structure provided in the source / drain region 211 of the transistor in the third semiconductor layer 200 is nickel silicide, and the metal element that constitutes the silicide is nickel. That is, the metal element constituting the silicide of the transistor in the second semiconductor layer 200 is different from the metal element constituting the silicide structure of the transistor in the third semiconductor layer 300. This is because the transistor in the third semiconductor layer 300 is miniaturized more than the transistor in the second semiconductor layer 200, and accordingly the metal elements used are different.

[0045] A third diffusion prevention layer 317 is disposed so as to cover the source / drain region 311 and the gate electrode 314 of the transistor provided in the third semiconductor layer 300. The third diffusion prevention layer 317 has an effect of suppressing diffusion of metal elements contained in the low resistance region 313. The third diffusion prevention layer 317 is made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbide (SiC).

[0046] Fourth diffusion prevention layers 257, 357 are provided between the insulating film 230 of the second member 20 and the insulating film 330 of the third member 30. The fourth diffusion prevention layers 257, 357 have the effect of suppressing diffusion of metal elements contained in the low resistance region 313. The fourth diffusion prevention layers 257, 357 are made of, for example, silicon carbide (SiC).

[0047] In the first member 10, a conductor 240 is arranged in the insulating film 130, the element isolation region 201, and the insulating film 230 as a first wiring structure 190. The conductor 240 is a through-wiring provided so as to penetrate the insulating film 130 and the element isolation region 210. The conductor 240 is also a wiring that connects the FD 112 arranged in the first semiconductor layer 100 and the gate of the amplification transistor AMP arranged on the second semiconductor layer 200. Although not shown, the through-wiring that penetrates the insulating film 130 and the element isolation region 210 is also provided so as to be electrically connected to the second semiconductor region that constitutes a PN junction with the first semiconductor region of the photoelectric conversion unit 111.

[0048] In the second member 20, a conductor 255 made up of multiple layers is arranged in an insulating film 230 as a second wiring structure 290. The conductor 255 is, for example, a wiring constituting the drive line 24 or the output line 25. A conductor 250 is arranged in the uppermost layer of the insulating film 230.

[0049] In the third member 30, a conductor 355 made up of multiple layers is disposed in an insulating film 330 as a third wiring structure 390, and a conductor 350 is disposed in the uppermost layer of the insulating film 330. The conductor 250 provided so as to be exposed from the second member 20 and the conductor 350 provided so as to be exposed from the third member 30 are joined to each other by metal bonding.

[0050] The conductors 250 and 350 are, for example, conductors mainly made of copper. Furthermore, the insulating film 235 of the uppermost layer of the second member 20 and the insulating film 335 of the uppermost layer of the third member are bonded to each other by covalent bonds of the insulating films. That is, the second member 20 and the third member 30 are bonded by a so-called hybrid junction. The insulating films 235 and 335 are, for example, silicon oxide films. However, they may be silicon oxynitride films, silicon nitride films, or laminated structures of these insulating films including silicon oxide films.

[0051] In the first member 10 to the third member 30, the conductor is composed of a conductor mainly containing a metal material such as copper, aluminum, or tungsten. A barrier metal for suppressing diffusion of metals such as copper and tungsten may be provided between the insulating film and the conductor. The first member 10, the second member 20, and the third member 30 are configured to be electrically connected to each other by such a combination of the insulating film and the conductor.

[0052] Although not shown, optical structures such as a color filter layer and a microlens may be arranged on the back side (light-irradiated surface type) of the first semiconductor layer 100. Another microlens (intralayer lens) may be provided between the microlens and the first semiconductor layer 100. A fixed charge film (not shown) may be provided on the back side of the first semiconductor layer 100 to reduce dark current. For example, examples of negative fixed charge films include hafnium oxide (HfO2) film, aluminum oxide (Al2O3) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, and titanium oxide (TiO2) film. Furthermore, a conductor for suppressing optical crosstalk between each pixel may be provided between the color filter layers or between the color filter layer and the first semiconductor layer 100. In a plan view, the conductors may be arranged discretely, or a mesh-shaped / lattice-shaped conductor may be arranged.

[0053] (Manufacturing method) Next, a method for manufacturing the photoelectric conversion device according to this embodiment will be described with reference to FIGS.

[0054] In Fig. 4(A), the first semiconductor layer 100A is, for example, a silicon substrate, and includes a photoelectric conversion unit 111 and an FD 112. It is also possible to form an element isolation region (not shown) made of an insulator. A gate electrode 120 of a transfer transistor is formed on the first semiconductor layer 100A, and then a first diffusion prevention layer 121 made of, for example, silicon nitride is formed. After that, an insulating film 130A made of a silicon oxide film is formed on the first semiconductor layer 100A.

[0055] 4(B), the second semiconductor layer 200A is disposed on the insulating film 130. Here, for example, the first semiconductor layer 100A and the second semiconductor layer 200A can be bonded via a silicon oxide film. Specifically, a silicon oxide film is formed on the back surface side of the second semiconductor layer 200A, and the back surface of the second semiconductor layer 200A and the front surface of the first semiconductor layer 100A are bonded face-to-face.

[0056] 4(C), the second semiconductor layer 200A is thinned to form the second semiconductor layer 200. After that, a part of the second semiconductor layer 200 is removed by etching, and an insulating film is filled in to form an element isolation region 201. The element isolation region 201 electrically isolates well regions 202 of the reset transistor RES, the amplification transistor AMP, the selection transistor SEL, the FD capacitance switching transistor, and the like, which are arranged in the second semiconductor layer 200. The well region is, for example, a semiconductor region of a second conductivity type (e.g., P type).

[0057] Next, as shown in FIG. 5(A), a gate electrode 214 and a sidewall 215 of a transistor are formed using photolithography and etching techniques. The gate electrode is made of, for example, polysilicon. The sidewall 215 is made of, for example, silicon nitride. After the gate electrode 214 and the sidewall 215 are formed, an impurity diffusion region 212 of the source / drain region 211 is formed using ion implantation or plasma doping techniques. The impurity diffusion region 212 is, for example, a semiconductor region of a first conductivity type (e.g., N type). Next, a low-resistance region 213 made of a silicide structure is formed using a salicide (Self Aligned Silicide) process. In addition, a second diffusion prevention layer 217 made of, for example, silicon nitride is formed. In this process, a low-resistance region 216 may also be formed on the gate electrode.

[0058] It is desirable to form the second diffusion prevention layer 217 so as to be in direct contact with the low resistance region 213 in order to suppress the diffusion of metal elements contained in the low resistance region 213. It is also desirable to dispose the second diffusion prevention layer 217 so as to cover the low resistance region 213 more widely than the low resistance region 213 in a top view in order to prevent the diffusion of metal elements.

[0059] 5(B), an insulating film 230A is formed on the second semiconductor layer 200. After that, an opening process is performed to provide a conductor connected to the first semiconductor layer 100A, the gate electrode 120, the second semiconductor layer 200, and the gate electrode 214 in the insulating film 230A. This opening is a via opening for a through wiring connected to the FD112 and the gate electrode 120, and this via opening is filled with a metal such as tungsten (W) to form a through wiring. In addition, a conductive member such as copper or aluminum is appropriately formed to form a conductor 240. In the above-mentioned via opening process, a via connecting to the first semiconductor layer 100A and the gate electrode 120 is opened and filled with a metal (first opening process and first filling process). Next, a via connecting to the second semiconductor layer 200 and the gate electrode 214 is opened and filled with a metal (second opening process and second filling process). According to such an order of steps, it is possible to suppress diffusion of metal elements from the low-resistance region 213 to the first semiconductor layer 100A. In the above-mentioned via opening step, the first diffusion prevention layer 121 and the second diffusion prevention layer 217 may be used as an etching stop layer. Also, a layer different from the first diffusion prevention layer 121 and the second diffusion prevention layer 217 may be used as the etching stop layer.

[0060] Next, as shown in FIG. 6, conductors 255 and 250 are further formed in the insulating film 230, and then the third semiconductor layer 300 and the first semiconductor layer 100A having the second semiconductor layer 200 are laminated. As described above, the conductors 250 and 350, and the insulating film 230 and 330 are laminated face-to-face so as to face each other. That is, as described above, these members are bonded by so-called hybrid bonding, so that the conductors 250 and 350 are electrically connected. Note that the bonding between the second semiconductor layer 200 and the third semiconductor layer 300 can be not only so-called hybrid bonding, but also bonding between insulating films.

[0061] After laminating the first semiconductor layer 100A and the third semiconductor layer 300, the first semiconductor layer 100A is thinned to form the first semiconductor layer 100. In addition, optical structures such as a color filter layer, a microlens, and an inner-layer lens, and a conductor for suppressing optical crosstalk between pixels are provided on the first semiconductor layer 100.

[0062] According to this embodiment, the source or drain of the transistor constituting the readout circuit provided in the second semiconductor layer is made to have a salicide structure to reduce resistance. This configuration makes it possible to provide a photoelectric conversion device capable of high-speed operation of the readout circuit.

[0063] Second embodiment Regarding this embodiment, the description of the same parts as those in the first embodiment will be omitted, and only the differences will be described below.

[0064] This embodiment differs from the first embodiment in that it has an element that does not have a low-resistance region formed by a salicide process in the second semiconductor layer 200. On the other hand, similar to Figs. 4(A) to (C) of the first embodiment, the second semiconductor layer 200A is thinned to form the second semiconductor layer 200, and further, the element isolation region 201 is formed. Thereafter, an impurity diffusion region 218 that will become a resistor element and the like and a gate electrode 214 are formed. A cross-sectional view of this state is shown in Fig. 7(A).

[0065] Next, as shown in Fig. 7(B), impurity diffusion regions 212 that will become the source / drain of the transistor are formed, an insulating film 219 is deposited, and the insulating film 219 is patterned by etching to form sidewalls 215. At this time, the patterning is performed so that the insulating film 219 remains on elements that do not form a low-resistance region. An example of an element that does not have a low-resistance region is a resistor element. Also, some of the transistors used in the read circuit may be configured not to include a low-resistance region.

[0066] 8A, a low-resistance region 213 made of a silicide structure having a metal element is formed by a salicide process. After that, for example, silicon nitride is deposited and patterned to form a second diffusion prevention layer 217.

[0067] 8(B), an insulating film 230A and a conductor 240 are formed. At this time, the first diffusion prevention layer 121, the second diffusion prevention layer 217, and the insulating film 219 may be used as an etch stop film when opening a via. Thereafter, similarly to the first embodiment, a further conductor is formed, stacked with a third semiconductor layer 300, and an optical structure is formed.

[0068] According to this embodiment, the source or drain of the transistor constituting the readout circuit provided in the second semiconductor layer is made to have a salicide structure to reduce resistance. This configuration makes it possible to provide a photoelectric conversion device capable of high-speed operation of the readout circuit.

[0069] (Third embodiment) Regarding this embodiment, the description of the same parts as those in the above embodiment will be omitted, and only the differences will be described below.

[0070] As shown in FIG. 9, this embodiment is different from the other embodiments in that a fifth diffusion prevention layer 117 is provided in the first wiring structure. The fifth diffusion prevention layer 117 is, for example, silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbide (SiC). For example, assume that the material of the insulating film 130 is silicon oxide (SiO), and the fifth diffusion prevention layer 117 is silicon nitride. In this case, an opening for the conductor 240, which is a through-wire, needs to be formed in both the insulating film 130 and the fifth diffusion prevention layer 117. Since the materials of the insulating film 130 and the fifth diffusion prevention layer 117 are different, the etching rates during etching are also different. Therefore, it is preferable to set the fifth diffusion prevention layer 117 to a certain degree of thinness. For example, the thickness of the fifth diffusion prevention layer 117 is set to be thinner than the thickness of the first diffusion prevention layer 121. With such a configuration, openings can be formed in the insulating film 130 and the fifth diffusion prevention layer 117 in the same process, which is beneficial.

[0071] According to this embodiment, the source or drain of the transistor constituting the readout circuit provided in the second semiconductor layer is made to have a salicide structure to reduce resistance. This configuration makes it possible to provide a photoelectric conversion device capable of high-speed operation of the readout circuit.

[0072] (Fourth embodiment) FIG. 10 is a diagram of an apparatus according to this embodiment. This embodiment is applicable to any of the above-mentioned embodiments. FIG. 10(a) is a schematic diagram for explaining an apparatus 9191 including the semiconductor device 930 of this embodiment. The photoelectric conversion device of each of the above-mentioned embodiments can be used for the semiconductor device 930. The apparatus 9191 including the semiconductor device 930 will be explained in detail. As described above, the semiconductor device 930 can include a package 920 that houses the semiconductor device 910 in addition to the semiconductor device 910 having the semiconductor layer 10. The package 920 can include a base to which the semiconductor device 910 is fixed and a cover such as glass that faces the semiconductor device 910. The package 920 can further include a bonding member such as a bonding wire or a bump that connects a terminal provided on the base and a terminal provided on the semiconductor device 910.

[0073] The device 9191 can include at least one of an optical device 940, a control device 950, a processing device (signal processing unit) 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0074] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0075] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) included in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit included in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0076] The device 9191 is also suitable for electronic devices such as information terminals (e.g., smartphones and wearable devices) with a photographing function and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operation.

[0077] The device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in the transportation equipment may be used as a moving device. The device 9191 as a transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) by using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0078] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental load, reducing costs, reducing size, and reducing weight.

[0079] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can be improved. For example, by mounting the semiconductor device 930 on a transport equipment, excellent performance can be obtained when photographing the outside of the transport equipment or measuring the external environment. Therefore, in manufacturing and selling the transport equipment, it is advantageous to decide to mount the semiconductor device according to this embodiment on the transport equipment in order to improve the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0080] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS.

[0081] FIG. 10(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 has a photoelectric conversion device 80. The photoelectric conversion device 80 is a photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 8 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion system 8. The photoelectric conversion system 8 also has a distance acquisition unit 803 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0082] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control device (control unit) that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the judgment result of the collision judgment unit 804. For example, when the judgment result of the collision judgment unit 804 indicates that there is a high possibility of a collision, the control ECU 820 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., and vibrating the seat belt or steering wheel.

[0083] In this embodiment, the surroundings of the vehicle, for example the front or rear, are imaged by the photoelectric conversion system 8. Fig. 10(c) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810 sends an instruction to the photoelectric conversion system 8 or the photoelectric conversion device 80. This configuration can further improve the accuracy of distance measurement.

[0084] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the photoelectric conversion system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0085] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0086] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also included in the embodiments of the present invention.

[0087] Furthermore, the equipment (photoelectric conversion system) shown in the above embodiment is an example of a photoelectric conversion system to which a photoelectric conversion device can be applied, and the photoelectric conversion system to which the photoelectric conversion device of the present invention can be applied is not limited to the configuration shown in Figure 10.

[0088] The present invention is not limited to the above-mentioned embodiments, and various modifications are possible. For example, an example in which a part of the configuration of any of the embodiments is added to another embodiment, or an example in which a part of the configuration of another embodiment is replaced with another embodiment is also an embodiment of the present invention. The disclosure of this specification includes not only what is described in this specification, but also all matters that can be understood from this specification and the drawings attached to this specification.

[0089] The disclosure of this embodiment also includes the following configurations and methods.

[0090] (Configuration 1) a first member having a photoelectric conversion unit and a transfer transistor that transfers charges generated in the photoelectric conversion unit in a first semiconductor layer; a second member having a readout circuit in a second semiconductor layer that outputs a signal based on the charge transferred from the transfer transistor; a third member having a signal processing circuit for processing the signal in a third semiconductor layer; The semiconductor devices are laminated such that a first wiring structure of the first member is provided between the first semiconductor layer and the second semiconductor layer, and a second wiring structure of the second member and a third wiring structure of the third member are provided between the second semiconductor layer and the third semiconductor layer; the readout circuit is configured to output the signal from the second member to the third member via an output line provided in the second wiring structure; a photoelectric conversion device having a salicide structure in a source region or a drain region of a transistor constituting the readout circuit;

[0091] (Configuration 2) a first member having a photoelectric conversion unit and a transfer transistor that transfers charges generated in the photoelectric conversion unit in a first semiconductor layer; a second member having a readout circuit in a second semiconductor layer that outputs a signal based on the charge transferred from the transfer transistor; a third member having a signal processing circuit for processing the signal in a third semiconductor layer; The semiconductor devices are laminated such that a first wiring structure of the first member is provided between the first semiconductor layer and the second semiconductor layer, and a second wiring structure of the second member and a third wiring structure of the third member are provided between the second semiconductor layer and the third semiconductor layer; the readout circuit is configured to output a signal from the second member to the third member via an output line provided in the second wiring structure; a silicide structure in a source region or a drain region of a transistor constituting the readout circuit, the silicide structure being in contact with an insulating film of the second wiring structure;

[0092] (Configuration 3) 3. The photoelectric conversion device according to claim 1, wherein the transistor is selected from a reset transistor, a selection transistor, and an amplification transistor.

[0093] (Configuration 4) 4. The photoelectric conversion device according to any one of configurations 1 to 3, wherein the transistor has a gate having a salicide structure.

[0094] (Configuration 5) 2. The photoelectric conversion device according to configuration 1, wherein the salicide structure is disposed between the second semiconductor layer and the third semiconductor layer.

[0095] (Configuration 6) 3. The photoelectric conversion device according to configuration 2, wherein the silicide structure is disposed between the second semiconductor layer and the third semiconductor layer.

[0096] (Configuration 7) The photoelectric conversion device of any one of configurations 1 to 6, characterized in that the first member and the second member are electrically connected by a through-hole wiring that penetrates an insulator of the second semiconductor layer and an insulating layer of the first wiring structure.

[0097] (Configuration 8) 8. The photoelectric conversion device according to any one of configurations 1 to 7, further comprising a diffusion prevention layer for the first metal between the second semiconductor layer and the second wiring structure.

[0098] (Configuration 9) 9. The photoelectric conversion device according to configuration 8, wherein the diffusion prevention layer for the first metal comprises silicon nitride.

[0099] (Configuration 10) 10. The photoelectric conversion device according to any one of configurations 1 to 9, further comprising a diffusion prevention layer for a second metal between the first semiconductor layer and the first wiring structure.

[0100] (Configuration 11) 11. The photoelectric conversion device according to claim 10, wherein the diffusion barrier layer for the second metal comprises silicon nitride.

[0101] (Configuration 12) 12. The photoelectric conversion device according to any one of configurations 1 to 11, wherein a diffusion region is formed in the second semiconductor layer, and no silicide is formed in the diffusion region.

[0102] (Configuration 13) 13. The photoelectric conversion device according to any one of configurations 1 to 12, wherein at least one of a source region, a drain region, and a gate of a transistor constituting the signal processing circuit has a salicide structure.

[0103] (Configuration 14) The photoelectric conversion device according to configuration 13, wherein a metal element contained in a salicide structure of a transistor constituting the readout circuit and a metal element contained in a salicide structure of a transistor constituting the signal processing circuit are different elements.

[0104] (Configuration 15) An apparatus including the photoelectric conversion device according to any one of configurations 1 to 14, an optical device corresponding to the photoelectric conversion device; A control device for controlling the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

[0105] (Configuration 16) A method for manufacturing a photoelectric conversion device, comprising the steps of: A step of preparing a member including a photoelectric conversion unit provided on a first semiconductor layer, a transfer transistor that transfers charges generated in the photoelectric conversion unit, and an insulating film provided on the photoelectric conversion unit and the transfer transistor; laminating the member and a second semiconductor layer; forming a readout circuit in the second semiconductor layer, the readout circuit outputting a signal based on the charge transferred from the transfer transistor; forming a silicide structure in a source region or a drain region of a transistor constituting the readout circuit, and then forming an insulating film on the silicide structure; forming a first wiring structure between the first semiconductor layer and the second semiconductor layer; forming a second wiring structure on the second semiconductor layer; forming a signal processing circuit for processing the signal on a third semiconductor layer; forming a third wiring structure on the third semiconductor layer; laminating the second semiconductor layer and the third semiconductor layer such that the second wiring structure and the third wiring structure face each other; The method for manufacturing a photoelectric conversion device, wherein the readout circuit is configured to output the signal via an output line provided in the second wiring structure. [Explanation of symbols]

[0106] 100 First semiconductor layer 200 Second semiconductor layer 300 Third Semiconductor Layer 111 Photoelectric conversion unit 112FD 120, 214 Gate electrode 121, 217 Diffusion prevention layer 130, 219, 230, 330 Insulating film 240, 250, 320, 350 Conductor 201 Element isolation region 202 Well Area 211 Source / Drain Region 212 Impurity Diffusion Region 213, 216 Low resistance region

Claims

Claim 1 A first member having a photoelectric conversion section and a transfer transistor that transfers charges generated in the photoelectric conversion section, in a first semiconductor layer; A second member having a readout circuit that outputs a signal based on the charges transferred from the transfer transistor, in a second semiconductor layer; A third member having a signal processing circuit that processes the signal, in a third semiconductor layer, and a first wiring structure of the first member is provided between the first semiconductor layer and the second semiconductor layer, and a second wiring structure of the second member and a third wiring structure of the third member are provided between the second semiconductor layer and the third semiconductor layer, and are laminated so as to be provided; the readout circuit is configured to output the signal from the second member to the third member via an output line provided in the second wiring structure; a salicide structure is provided in a source region or a drain region of a transistor constituting the readout circuit; and a diffusion prevention layer for the metal included in the salicide structure is provided between the first semiconductor layer and the second semiconductor layer. A photoelectric conversion device characterized by that. Claim 2 A first member having a photoelectric conversion section and a transfer transistor that transfers charges generated in the photoelectric conversion section, in a first semiconductor layer; A second member having a readout circuit that outputs a signal based on the charges transferred from the transfer transistor, in a second semiconductor layer; A third member having a signal processing circuit that processes the signal, in a third semiconductor layer, and a first wiring structure of the first member is provided between the first semiconductor layer and the second semiconductor layer, and a second wiring structure of the second member and a third wiring structure of the third member are provided between the second semiconductor layer and the third semiconductor layer, and are laminated so as to be provided; the readout circuit is configured to output a signal from the second member to the third member via an output line provided in the second wiring structure; a silicide structure is provided in a source region or a drain region of a transistor constituting the readout circuit, and the silicide structure is in contact with an insulating film included in the second wiring structure; and a diffusion prevention layer for the metal included in the silicide structure is provided between the first semiconductor layer and the second semiconductor layer. A photoelectric conversion device characterized by that. Claim 3 The photoelectric conversion device according to claim 1 or 2, wherein the transistor is selected from a reset transistor, a selection transistor, and an amplification transistor.

4. The photoelectric conversion device according to claim 1 or 2, wherein the gate of the transistor has a salicide structure.

5. The photoelectric conversion device according to claim 1 or 2, wherein the gate of the transistor has a silicide structure, and the silicide structure provided on the gate is in contact with an insulating film included in the second wiring structure.

6. The photoelectric conversion device according to claim 1, wherein the salicide structure is disposed between the second semiconductor layer and the third semiconductor layer.

7. The photoelectric conversion device according to claim 2, wherein the silicide structure is disposed between the second semiconductor layer and the third semiconductor layer.

8. The photoelectric conversion device according to claim 1 or 2, wherein the first member and the second member are electrically connected by a through wiring that penetrates an insulator included in the second semiconductor layer and an insulating layer included in the first wiring structure.

9. The photoelectric conversion device according to claim 1, further comprising another diffusion prevention layer for a metal included in the salicide structure between the second semiconductor layer and the second wiring structure.

10. The photoelectric conversion device according to claim 2, further comprising another diffusion prevention layer for a metal included in the silicide structure between the second semiconductor layer and the second wiring structure.

11. The photoelectric conversion device according to claim 1 or 2, wherein the diffusion prevention layer includes any one of silicon nitride, silicon oxynitride, and silicon carbide.

12. The photoelectric conversion device according to claim 9, wherein the another diffusion prevention layer includes any one of silicon nitride, silicon oxynitride, and silicon carbide.

13. The photoelectric conversion device according to claim 10, wherein the another diffusion prevention layer includes any one of silicon nitride, silicon oxynitride, and silicon carbide.

14. The photoelectric conversion device according to claim 1 or 2, wherein a diffusion region is formed in the second semiconductor layer, and the diffusion region does not have a silicide structure.

15. The photoelectric conversion device according to claim 1 or 2, characterized in that at least one of a source region, a drain region, and a gate of a transistor constituting the signal processing circuit has a salicide structure.

16. The photoelectric conversion device according to claim 15, characterized in that a metal element included in a salicide structure of a transistor constituting the readout circuit is different from a metal element included in a salicide structure of a transistor constituting the signal processing circuit.

17. An apparatus comprising the photoelectric conversion device according to claim 1 or 2, an optical device corresponding to the photoelectric conversion device, a control device for controlling the photoelectric conversion device, a processing device for processing a signal output from the photoelectric conversion device, a display device for displaying information obtained by the photoelectric conversion device, a storage device for storing information obtained by the photoelectric conversion device, and a mechanical device that operates based on information obtained by the photoelectric conversion device, characterized in that the apparatus further comprises at least any one of them.

18. A method for manufacturing a photoelectric conversion device, a step of preparing a member having a photoelectric conversion unit provided in a first semiconductor layer, a transfer transistor for transferring charges generated in the photoelectric conversion unit, and an insulating film provided on the photoelectric conversion unit and the transfer transistor, a step of laminating the member and a second semiconductor layer, a step of forming a readout circuit on the second semiconductor layer that outputs a signal based on charges transferred from the transfer transistor, a step of forming a silicide in a source region or a drain region of a transistor constituting the readout circuit, and then forming an insulating film on the silicide, a step of forming a first wiring structure between the first semiconductor layer and the second semiconductor layer, a step of forming a second wiring structure on the second semiconductor layer, a step of forming a signal processing circuit for processing the signal in a third semiconductor layer, a step of forming a third wiring structure on the third semiconductor layer, a step of laminating the second semiconductor layer and the third semiconductor layer with the second wiring structure and the third wiring structure facing each other, and The method for manufacturing a photoelectric conversion device, characterized in that the readout circuit is configured to output the signal via an output line provided in the second wiring structure.

Images