Method of manufacturing semiconductor device and semiconductor device

Abstract

To provide a semiconductor device in which a substrate on which a semiconductor element is mounted and a heat sink are bonded with each other by using a sintered body obtained by sintering a bonding base material containing metal particles, capable of suppressing reduction in heat radiation efficiency by the heat sink while preventing a cavity from being formed in the sintered body.SOLUTION: A method of manufacturing a semiconductor device includes: a base material installation step of providing a bonding base material containing metal particles on a bonding surface that is any one of one surface of a substrate on whose one surface a semiconductor element is mounted and a flat plate-like base part in a heat sink having the base part; a lamination step of laminating the substrate and the heat sink via the bonding base material; and a sintering step of sintering the bonding base material to form a sintered body that bonds the substrate and the heat sink. At the base material installation step, the bonding base material is provided on the bonding surface so as to form a non-installation part where no bonding base material is provided, in a region on the bonding surface where no semiconductor element is mounted when seen from the lamination direction of the substrate and the heat sink.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a technique for bonding a semiconductor chip to a die pad by using a sintered body of a metal paste. Patent Document 2 discloses a method for connecting a first member and a second member with a sintered copper body. In this method, a copper paste coating is formed in the connection area of ​​each member using a printing pattern consisting of a coating-film-formed area where the coating film is formed and a coating-non-film-formed area where the coating film is not formed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-17671 A [Patent Document 2] JP 2020-44480 A Summary of the Invention [Problem to be solved by the invention]

[0004] A substrate on which a semiconductor element is mounted and a heat sink that dissipates heat generated by the semiconductor element may be bonded using a sintered body obtained by sintering a bonding base material such as a metal paste containing metal particles. When the substrate and the heat sink are bonded using a sintered body, it is preferable to form a non-installed portion on the surface where the substrate and the heat sink are bonded, where no bonding base material is provided, and to exhaust the gas to the outside through the non-installed portion, in order to prevent the formation of voids in the sintered body due to the gas generated when the bonding base material is sintered. On the other hand, since the non-installed portion where no bonding base material is provided does not easily conduct heat from the substrate to the heat sink, depending on the relationship between the position of the semiconductor element loaded on the substrate and the non-installed portion, the heat dissipation efficiency of the heat sink may decrease.

[0005] The present invention aims to suppress the formation of voids in a sintered body while suppressing a decrease in heat dissipation efficiency caused by the heat sink in a semiconductor device in which a substrate carrying a semiconductor element and a heat sink are joined using a sintered body formed by sintering a joining base material containing metal particles. [Means for solving the problem]

[0006] According to the present invention, the following inventions (1) to (6) are provided. (1) providing a bonding base material containing metal particles on a bonding surface between a surface of a substrate (insulating substrate 11) on which a semiconductor element (semiconductor element 13) is mounted and a surface of a heat sink (heat sink 20) ​​having a flat base portion (base portion 21); a lamination step of laminating the substrate and the heat sink via the bonding base material; a sintering step of sintering the bonding base material to form a sintered body (sintered body layer 30, bonding portion 31) that bonds the substrate and the heat sink, The base material installation step includes providing the bonding base material on the bonding surface so that non-installation portions (non-coated portion 42, first groove 42a, second groove 42b) where the bonding base material is not provided are formed in the region of the bonding surface where the semiconductor element is not mounted as viewed from the stacking direction of the substrate and the heat sink. A method for manufacturing a semiconductor device. (2) The method for manufacturing a semiconductor device described in (1), wherein the substrate installation step provides the bonding substrate on the bonding surface such that the non-installation portion is not formed in the area of ​​the bonding surface on which the semiconductor element is mounted when viewed from the stacking direction, and in an area within a predetermined distance from the area on which the semiconductor element is mounted. (3) The method for manufacturing a semiconductor device according to (1) or (2), wherein the substrate installation step includes providing the bonding substrate on the bonding surface so that the non-installation portion is formed with a plurality of first grooves (first grooves 42a) extending in a first direction along the bonding surface and a plurality of second grooves (second grooves 42b) extending in a second direction along the bonding surface and intersecting the first direction, the non-installation portion being arranged in a lattice pattern, and the first grooves and the second grooves surrounding an area in which the semiconductor element is mounted when viewed from the stacking direction.

[0007] (4) a base material providing step of providing a bonding base material containing metal particles on a bonding surface which is either the other surface of a substrate (insulating substrate 11) having one surface and the other surface, or the base portion of a heat sink (heat sink 20) ​​having a flat base portion (base portion 21); a lamination step of laminating the substrate and the heat sink via the bonding base material; a sintering step of sintering the bonding base material to form a sintered body (sintered body layer 30, bonding portion 31) that bonds the substrate and the heat sink; A bonding step of bonding a semiconductor element (semiconductor element 13) to one surface of the substrate, The substrate installation step includes providing the bonding substrate on the bonding surface so as to form an installation portion (coating portion 41) where the bonding substrate is provided and a non-installation portion (non-coating portion 42, first groove 42a, second groove 42b) where the bonding substrate is not provided; The bonding step bonds the semiconductor element to a region of the one surface of the substrate that overlaps with the installation portion when viewed from a stacking direction of the substrate and the heat sink. A method for manufacturing a semiconductor device.

[0008] (5) a substrate (insulating substrate 11) having a semiconductor element (semiconductor element 13) mounted on one surface thereof; A heat sink (heat sink 20) ​​having a flat base portion (base portion 21) and laminated on the other surface of the substrate; a sintered body (sintered body layer 30, joint portion 31) that joins the other surface of the substrate and the base portion of the heat sink, The sintered body is a semiconductor device in which non-bonded portions (non-coated portion 42, first groove 42a, second groove 42b) where the substrate and the heat sink are not bonded are formed in an area where the semiconductor element is not mounted on the substrate when viewed from the stacking direction of the substrate and the heat sink. (6) The semiconductor device described in (5) is characterized in that the non-bonded portion is formed to surround the region where the semiconductor element is mounted on the substrate when viewed from the stacking direction, and the area of ​​the sintered body surrounded by the non-bonded portion is 1.1 to 5.0 times the area of ​​the semiconductor element. Effect of the Invention

[0009] According to the present invention, in a semiconductor device in which a substrate carrying a semiconductor element and a heat sink are joined using a sintered body made by sintering a metal paste, it is possible to suppress the formation of voids in the sintered body while suppressing a decrease in the heat dissipation efficiency caused by the heat sink. [Brief description of the drawings]

[0010] [Figure 1] 1 is a diagram showing an example of a configuration of a semiconductor device to which the present embodiment is applied; [Diagram 2] FIG. 2 is a diagram showing an example of a configuration of a semiconductor device, and is a diagram showing an example of a cross section of the semiconductor device taken along a part II in FIG. [Diagram 3] FIG. 3 is a diagram showing an example of a configuration of a semiconductor device, in which the semiconductor device is viewed from a direction III in FIG. 2. [Figure 4] 1 is a view of a sintered body layer in a semiconductor device to which the present embodiment is applied, as viewed from the side on which a semiconductor module is mounted. [Diagram 5] 1(a) to 1(c) are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 6] 1 is a diagram illustrating an area where a metal paste is applied to a coating surface of a heat sink. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. (Semiconductor device 1) FIG. 1 is a diagram showing an example of the configuration of a semiconductor device 1 to which the present embodiment is applied. FIG. 2 is a diagram showing an example of the configuration of the semiconductor device 1, and is a diagram showing an example of a cross section of the semiconductor device 1 taken along line II in FIG. FIG. 3 is a diagram showing an example of the configuration of the semiconductor device 1, and is a diagram showing the semiconductor device 1 as viewed from the direction III in FIG.

[0012] The semiconductor device 1 according to this embodiment includes a semiconductor module 10, a heat sink 20 that dissipates heat transferred from the semiconductor module 10, and a sintered body layer 30 that bonds the semiconductor module 10 and the heat sink 20 together. Although not shown in the drawings, the semiconductor device 1 of this embodiment is used by being attached to a case having an internal space through which a coolant flows, so that fins 22 (described later) of the heat sink 20 are in contact with the coolant. As a result, heat generated in the semiconductor module 10 and conducted to the heat sink 20 via the sintered body layer 30 is dissipated by the coolant.

[0013] The semiconductor module 10 comprises an insulating substrate 11 as an example of a substrate, a semiconductor element 13 mounted on one surface (the upper surface in FIG. 2) of the insulating substrate 11, and a bonding layer 15 that bonds the one surface of the insulating substrate 11 to the semiconductor element 13.

[0014] The insulating substrate 11 includes an insulating layer 111 that insulates the semiconductor element 13 from the heat sink 20, a wiring layer 112 formed on one side (the upper side in FIG. 2) of the insulating layer 111 and including wiring for supplying power to the semiconductor element 13, and a heat transfer layer 113 formed on the other side (the lower side in FIG. 2) of the insulating layer 111 and transferring heat generated from the semiconductor element 13 to the heat sink 20.

[0015] The insulating layer 111 may be, for example, a ceramic substrate made of alumina (Al2O3), silicon nitride (Si3N4), aluminum nitride (AlN), etc. The insulating layer 111 may have a thickness in the range of, for example, 0.1 mm to 2.0 mm.

[0016] The wiring layer 112 is formed in a predetermined region on one surface of the insulating layer 111 , and constitutes wiring for supplying power to the semiconductor element 13 . The heat transfer layer 113 is formed so as to cover substantially the entire other surface of the insulating layer 111 . The wiring layer 112 and the heat transfer layer 113 are made of a metal layer. Examples of metals used for the wiring layer 112 and the heat transfer layer 113 include copper, nickel, silver, palladium, gold, platinum, lead, cobalt, tin, aluminum, and alloys of two or more metals selected from these, and are preferably copper, nickel, silver, palladium, gold, and alloys of two or more metals selected from these, and more preferably copper, nickel, and silver. The wiring layer 112 and the heat transfer layer 113 may be made of the same type of metal or different types of metals. The thickness of the wiring layer 112 and the heat transfer layer 113 can be, for example, in the range of 0.05 mm or more and 2.0 mm or less.

[0017] Examples of such insulating substrates 11 include a DCB (Direct Copper Bond) substrate in which a wiring layer 112 and a heat transfer layer 113 made of copper are bonded to one side and the other side of an insulating layer 111 made of ceramic, and a DAB (Direct Aluminum Bond) substrate in which a wiring layer 112 and a heat transfer layer 113 made of aluminum are bonded to both sides of an insulating layer 111 made of a ceramic substrate. Insulating substrate 11 may include layers having electrical conductivity, such as wiring layer 112 and heat transfer layer 113, so long as insulating substrate 11 can insulate semiconductor element 13 from heat sink 20 as a whole.

[0018] The semiconductor element 13 is, for example, a power semiconductor used for power control, such as a transistor, a thyristor, or a diode. Examples of the material of the semiconductor element 13 include silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga2O3). In this embodiment, the semiconductor element 13 has a rectangular parallelepiped shape as a whole. Although not shown in the drawings, the semiconductor element 13 may be provided with a terminal or the like for supplying power to other devices such as a motor or a computer device.

[0019] The bonding layer 15 bonds the wiring layer 112 formed on the surface of the insulating substrate 11 to the semiconductor element 13. There are no particular limitations on the bonding layer 15 as long as it can electrically connect the wiring layer 112 to the semiconductor element 13. Examples of a method for bonding the insulating substrate 11 (wiring layer 112) to the semiconductor element 13 via the bonding layer 15 include soldering, brazing, sintering, and the like.

[0020] The heat sink 20 includes a flat base portion 21 and a plurality of fins 22 protruding from the base portion 21 . The base portion 21 is a rectangular member having a first direction (left-right direction in Figs. 2 and 3) and a second direction (up-down direction in Fig. 3) that are perpendicular to each other. The base portion 21 has a front surface 211 from which a plurality of fins 22 protrude, and a back surface 212 that faces the semiconductor module 10 via the sintered body layer 30. In this example, the area of ​​the base portion 21 is larger than the area of ​​the insulating substrate 11 in the semiconductor module 10. In the following description, the first direction and the second direction in the base portion 21 of the heat sink 20 may be simply referred to as the first direction and the second direction.

[0021] Each fin 22 of the heat sink 20 protrudes from the surface 211 of the base portion 21 in a direction perpendicular to the plate surface of the base portion 21. Each fin 22 is a flat plate-like member extending in a direction perpendicular to the plate surface of the base portion 21 and in a second direction of the base portion 21. The fins 22 are arranged side by side in the first direction with a gap between them and the surface 211 of the base portion 21. In addition, in the heat sink 20 , the insulating substrate 11 of the semiconductor module 10 is joined to the rear surface 212 of the base portion 21 by the sintered body layer 30 .

[0022] The material of the heat sink 20 is not particularly limited, but examples thereof include aluminum, an aluminum alloy, copper, and a copper alloy. Furthermore, the heat sink 20, particularly the rear surface 212 of the base portion 21 in the heat sink 20, may have a plating layer such as silver plating or gold plating formed thereon. By forming such a plating layer on the rear surface 212 of the base portion 21, the bonding strength with the insulating substrate 11 of the semiconductor module 10 via the sintered body layer 30 can be increased. The shape of the heat sink 20 is not limited to the above-mentioned form having the flat base portion 21 and the flat fins 22 protruding from the base portion 21, as long as the heat sink 20 has a surface bonded to the insulating substrate 11 via the sintered body layer 30, the bonded surface is made of metal, and has a function of dissipating heat conducted from the semiconductor module 10. The heat sink 20 may be, for example, box-shaped as a whole, having a space inside through which a coolant can flow. In addition, in the heat sink 20, examples of metals used for the surface to which the insulating substrate 11 is bonded include copper, nickel, silver, palladium, gold, platinum, lead, cobalt, tin, aluminum, or an alloy of two or more metals selected from these metals, and preferably copper, nickel, silver, palladium, gold, or an alloy of two or more metals selected from these metals, and more preferably copper, nickel, or silver.

[0023] The sintered body constituting the sintered body layer 30 is obtained, for example, by applying a metal paste in which metal particles are dispersed between the insulating substrate 11 and the heat sink 20, and sintering the metal paste. The sintered body constituting the sintered body layer 30 is obtained, for example, by stacking a sheet-like bonding sheet containing metal particles between the insulating substrate 11 and the heat sink 20, and sintering the sheet. Here, the metal paste and the bonding sheet are examples of bonding base materials containing metal particles. Examples of methods for sintering a bonding base material such as a metal paste or a bonding sheet to obtain a sintered body include pressureless sintering, pressure sintering, and electric sintering. The procedure for forming the sintered body layer 30, and the metal paste and bonding sheet used to form the sintered body layer 30 will be described in detail later. The bonding base material is not limited to a paste or sheet shape, as long as it contains metal particles and a sintered body in which the metal particles are sintered by heating can be obtained.

[0024] As the metal particles used for the sintered body constituting the sintered body layer 30, for example, particles of a metal selected from copper (Cu), silver (Ag), and an alloy of copper and silver (Cu-Ag) can be used. In addition, as the metal particles, for example, particles made of copper whose surface is coated with silver may be used. Among these metal particles, it is preferable to use copper particles. By using copper particles as the metal particles forming the sintered body, it is possible to improve the thermal conductivity between the semiconductor module 10 and the heat sink 20 via the sintered body layer 30. Furthermore, the sintered body constituting the sintered body layer 30 may contain components other than metals, such as intermetallic compounds, inorganic compounds, and resins.

[0025] The thickness of the sintered body layer 30 can be exemplified as being in the range of 10 μm or more and 500 μm or less. If the thickness of the sintered body layer 30 is less than 10 μm, the bonding strength between the semiconductor module 10 and the heat sink 20 by the sintered body layer 30 may be insufficient. If the thickness of the sintered body layer 30 exceeds 500 μm, the heat transfer from the semiconductor module 10 to the heat sink 20 via the sintered body layer 30 is likely to decrease. In this case, the heat dissipation efficiency of the heat generated in the semiconductor element 13 of the semiconductor module 10 may decrease. The thickness of the sintered body layer 30 is preferably in the range of 50 μm or more and 200 μm or less, and more preferably in the range of 60 μm or more and 180 μm or less.

[0026] The sintered body constituting the sintered body layer 30 has a structure in which metal particles melted by sintering are connected to each other. In addition, the sintered body constituting the sintered body layer 30 preferably has fine gaps formed between the metal particles. By forming gaps between the metal particles of the sintered body, the internal stress generated in the sintered body layer 30 is easily alleviated. The density of the metal in the sintered body constituting the sintered body layer 30 can be, for example, in the range of 40 volume % to 95 volume %, preferably in the range of 50 volume % to 95 volume %, and more preferably in the range of 60 volume % to 95 volume %. When the density of the metal in the sintered body constituting the sintered body layer 30 satisfies the above range, it becomes easier to achieve both the thermal conductivity between the semiconductor module 10 and the heat sink 20 via the sintered body layer 30 and the relaxation of internal stress by the sintered body layer 30.

[0027] The density of the metal in the sintered body was determined by measuring the volume of the sintered body and the mass of the sintered body measured with a precision balance, and the apparent density M1 (g / cm 3 ) is calculated. Next, the apparent density M1 calculated and the theoretical density Mx of the metal used in the sintered body (for example, in the case of copper particles, the theoretical density of copper is 8.96 g / cm 3 ) and the metal density (volume %) in the sintered body can be calculated from the following formula (1). Metal density in sintered body (volume %) = [(M1) / (Mx)] × 100 (1)

[0028] Fig. 4 is a view of the sintered body layer 30 in the semiconductor device 1 (see Fig. 1, etc.) to which this embodiment is applied, viewed from the side (upper side in Fig. 2) on which the semiconductor module 10 (see Fig. 1, etc.) is mounted. Additionally, Fig. 4 corresponds to a view in which the semiconductor module 10 is omitted from the semiconductor device 1 shown in Fig. 3. In Fig. 4, the position where the semiconductor element 13 is mounted on the insulating substrate 11 (see Fig. 3, etc.) in the semiconductor module 10 is indicated by a dashed line. 4, when viewed from the stacking direction, the sintered body layer 30 has a rectangular shape having sides facing each other in the first direction and the second direction corresponding to the shapes of the insulating substrate 11 and the base portion 21 of the heat sink 20. As shown in FIG. 4, the sintered body layer 30 has a joint portion 31 where the insulating substrate 11 and the heat sink 20 are joined, and a non-joint portion 32 where the insulating substrate 11 and the heat sink 20 are not joined.

[0029] The non-bonded portion 32 is a groove-shaped region where no sintered body is formed. In this embodiment, the non-bonded portion 32 is formed in a region where the semiconductor element 13 is not mounted on the insulating substrate 11 when viewed from the stacking direction of the semiconductor module 10 and the heat sink 20. The non-bonding portions 32 are arranged in a lattice pattern when viewed from the stacking direction in the sintered body layer 30. Specifically, the non-bonding portions 32 are arranged in a lattice pattern, with two first non-bonding portions 32a extending in a first direction (the left-right direction in FIG. 4) of the heat sink 20 and two second non-bonding portions 32b extending in a second direction (the up-down direction in FIG. 4). In this example, each of the first non-bonding portions 32a is provided continuously from one end (left side in FIG. 4) to the other end (right side in FIG. 4) in the first direction of the sintered body layer 30. Similarly, each of the second non-bonding portions 32b is provided continuously from one end (upper side in FIG. 4) to the other end (lower side in FIG. 4) in the second direction of the sintered body layer 30. In addition, both ends of each of the first non-bonding portions 32a and second non-bonding portions 32b are connected to the outside of the sintered body layer 30.

[0030] In addition, the distance between adjacent first non-bonding portions 32a, the distance between adjacent second non-bonding portions 32b, the distance from the periphery of the sintered body layer 30 to each first non-bonding portion 32a, and the distance from the periphery of the sintered body layer 30 to each second non-bonding portion 32b are all equal to each other. Furthermore, the width of the first non-bonding portion 32a (width along the second direction) and the width of the second non-bonding portion 32b (width along the first direction) are equal to each other. The width of the first non-bonding portion 32a and the width of the second non-bonding portion 32b may be equal to each other or different. The width of the first non-bonding portion 32a and the width of the second non-bonding portion 32b vary depending on the area of ​​the sintered body layer 30, but can be in the range of more than 0 μm and not more than 1000 μm, for example.

[0031] Here, since the non-bonded portion 32 does not have a sintered body, it has lower thermal conductivity than the bonded portion 31. In this embodiment, the non-bonded portion 32 is formed in an area of ​​the insulating substrate 11 where the semiconductor element 13 is not mounted, thereby preventing the non-bonded portion 32 from impeding the conduction of heat generated in the semiconductor element 13 to the heat sink 20. This improves the efficiency of dissipating heat generated in the semiconductor element 13 in the semiconductor device 1.

[0032] In addition, in the sintered body layer 30 of this embodiment, the sintered body constituting the sintered body layer 30 is divided into a plurality of regions (jointed regions 311 described later) by the non-jointed portions 32. This makes it easier to alleviate internal stress generated in the sintered body layer 30 compared to, for example, a case in which the sintered body layer 30 is composed of a single sintered body without the non-jointed portions 32 formed therein. In addition, since the sintered body layer 30 has the non-jointed portions 32 formed therein, internal stress generated in the sintered body layer 30 due to the difference in thermal expansion coefficient between the insulating substrate 11 and the heat sink 20 is easier to alleviate. This suppresses damage to the sintered body layer 30 caused by heat generated from the semiconductor element 13 during use of the semiconductor device 1, and peeling between the semiconductor module 10 and the heat sink 20.

[0033] In this example, the non-bonding portions 32 are provided in a lattice shape when viewed from the stacking direction, but the non-bonding portions 32 are not limited to a lattice shape. That is, from the viewpoint of alleviating internal stress generated in the sintered body layer 30, or from the viewpoint of discharging gas generated from the metal paste in the sintering step in the manufacturing method of the semiconductor device 1 described later, the non-bonding portions 32 may have groove-shaped regions in which no sintered body is formed that extend to the ends of the sintered body layer 30.

[0034] The joint portion 31 is a region where the insulating substrate 11 and the heat sink 20 are joined by the sintered body. The joint portion 31 is made up of a plurality of joint regions 311 surrounded by the periphery of the sintered body layer 30 and a lattice-shaped non-joint portion 32. In this example, the joint portion 31 includes a total of nine joint regions 311, three in the first direction and three in the second direction. When viewed from the stacking direction, each of the bonding regions 311 has a square shape. In this example, the shapes and sizes (areas when viewed from the stacking direction) of the bonding regions 311 are equal to each other.

[0035] In this embodiment, a part of the joint 31 is formed in a region where the semiconductor element 13 is mounted on the insulating substrate 11 when viewed from the stacking direction of the semiconductor module 10 and the heat sink 20. In this example, of the nine joint regions 311 of the joint 31, the first joint region 311 from the top and the second joint region 311 from the left is formed in the region where the semiconductor element 13 is mounted on the insulating substrate 11. In the following description, of the multiple joint regions 311 of the joint 31, the joint region 311 formed in the region where the semiconductor element 13 is mounted is referred to as joint region 311a. In this example, it should be noted that of the multiple bonding regions 311 of the bonding portion 31, the first bonding region 311 from the top and the second bonding region 311 from the left is a bonding region 311a formed in the region where the semiconductor element 13 is mounted.

[0036] In the sintered body layer 30 of this embodiment, the bonding region 311a of the bonding part 31 is formed in the region where the semiconductor element 13 is mounted on the insulating substrate 11, so that heat generated in the semiconductor element 13 is easily conducted to the heat sink 20 via the bonding region 311a. This improves the efficiency of dissipating heat generated in the semiconductor element 13 in the semiconductor device 1, compared to a case where the bonding part 31 is not formed in the region where the semiconductor element 13 is mounted on the insulating substrate 11.

[0037] Here, in the bonding portion 31 of this embodiment, the area of ​​the bonding region 311a as viewed from the stacking direction is larger than the area of ​​the semiconductor element 13 as viewed from the stacking direction. The bonding portion 31 is provided such that the area where the semiconductor element 13 is mounted overlaps the center of the bonding region 311a as viewed from the stacking direction. This makes it easier for heat generated from the semiconductor element 13 to be conducted to the heat sink 20 via the bonding region 311a, compared to a case where the area where the semiconductor element 13 is mounted overlaps an end of the bonding region 311a.

[0038] In addition, the area of ​​the bonding region 311a of the bonding portion 31 as viewed from the stacking direction is preferably 1.1 to 5.0 times the area of ​​the semiconductor element 13 as viewed from the stacking direction. In addition, in this embodiment, the area of ​​the sintered body in the bonding region 311 surrounded by the non-bonding portion 32 as viewed from the stacking direction is preferably 1.1 to 5.0 times the area of ​​the semiconductor element 13. When the area of ​​the bonding region 311 satisfies the above-mentioned range, the heat generated in the semiconductor element 13 is more easily conducted to the heat sink 20 via the bonding region 311, and the heat dissipation efficiency of the heat generated in the semiconductor element 13 is improved in the semiconductor device 1, compared to when the area of ​​the bonding region 311 is less than 1.1 times the area of ​​the semiconductor element 13. Furthermore, when the area of ​​the bonding region 311 satisfies the above-mentioned range, the sintered body constituting the bonding region 311 is less likely to be damaged by internal stress due to heat generated from the semiconductor element 13, compared to when the area of ​​the bonding region 311 exceeds 5.0 times the area of ​​the semiconductor element 13. It is more preferable that the area of ​​the bonding region 311 as viewed in the stacking direction is 1.3 to 4.0 times the area of ​​the semiconductor element 13 as viewed in the stacking direction.

[0039] In addition, in the sintered body layer 30, the number of bonded portions 31 (bonded regions 311) divided by non-bonded portions 32 can be exemplified as being in the range of 2 to 50, preferably in the range of 4 to 30, and more preferably in the range of 5 to 15. In the sintered body layer 30 of the present embodiment, the multiple bonding regions 311 of the bonding portion 31 have the same shape and area, but they may be different from each other. When the shapes of the respective bonding regions 311 are different from each other, it is sufficient that the area of ​​at least the bonding region 311a formed in the region where the semiconductor element 13 is mounted among the multiple bonding regions 311 satisfies the above-mentioned requirements.

[0040] Furthermore, in the sintered body layer 30 of this embodiment, the first non-bonding portion 32a and the second non-bonding portion 32b of the non-bonding portion 32 have a linear shape extending in the first direction or the second direction, but are not limited to this. The non-bonding portion 32 may be curved as long as it divides the sintered body layer 30 into a plurality of bonding portions 31 (bonding regions 311). In addition, when the sintered body layer 30 has a plurality of non-bonding portions 32, the shapes of the plurality of non-bonding portions 32 may be the same as each other or may be different from each other.

[0041] In addition, in the present embodiment, a case where one semiconductor element 13 is bonded onto the insulating substrate 11 of the semiconductor module 10 has been exemplified, but a plurality of semiconductor elements 13 may be bonded onto the insulating substrate 11. In this case, the sintered body layer 30 may have a non-bonded portion 32 formed in an area where at least one of the plurality of semiconductor elements 13 is not mounted on the insulating substrate 11 as viewed from the stacking direction. In this case, the non-bonded portion 32 is prevented from impeding the conduction of heat generated from the one semiconductor element 13 to the heat sink 20. From the viewpoint of improving the heat dissipation efficiency of the semiconductor device 1, it is more preferable that the sintered body layer 30 has a non-bonded portion 32 formed in an area where none of the semiconductor elements 13 is mounted on the insulating substrate 11 as viewed from the stacking direction.

[0042] (Method of Manufacturing Semiconductor Device 1) Next, a method for manufacturing the semiconductor device 1 will be described. 5(a) to 5(c) are diagrams illustrating an example of a method for manufacturing the semiconductor device 1. Here, an example will be described in which the sintered body constituting the sintered body layer 30 is formed using a metal paste, which is an example of a bonding base material. 5(a) to (c) show steps in a method for manufacturing the semiconductor device 1, and proceed in the order of FIG. 5(a) to (c). FIG. 5(a) to (c) show representative steps in a method for manufacturing the semiconductor device 1, and other steps may be included. FIG. 5(a) to (c) correspond to the cross-sectional view shown in FIG. 2.

[0043] The manufacturing method of the semiconductor device 1 of this embodiment includes a coating process of applying a metal paste to the coating surface between the semiconductor module 10 and the heat sink 20 to form a metal paste coating layer 40, a lamination process of stacking the semiconductor module 10 and the heat sink 20 via the metal paste coating layer 40, and a sintering process of sintering the metal paste coating layer 40 to form a sintered body layer 30.

[0044] <Coating process> In the application process, a metal paste is applied to a joining surface, which is either one of the surfaces (on the heat transfer layer 113) of the insulating substrate 11 on which the semiconductor element 13 is mounted (on the wiring layer 112) and the back surface 212 of the base portion 21 of the heat sink 20, to form a coating layer 40. In this example, as shown in FIG. 5(a), a coating layer 40 is formed by applying a metal paste to the rear surface 212 of the base portion 21 of the heat sink 20, which is an example of a joining surface. The method for applying the metal paste to the joining surface is not particularly limited, and examples thereof include screen printing, transfer printing, offset printing, inkjet printing, and printing methods using various dispensers or coaters.

[0045] Fig. 6 is a diagram illustrating the region where metal paste is applied to the joining surface of the heat sink 20. Fig. 6 corresponds to a view of the base portion 21 of the heat sink 20 viewed from the rear surface 212 side. Note that in Fig. 6, the region where the semiconductor element 13 is mounted on the insulating substrate 11 (see Fig. 5) in the semiconductor module 10 (see Fig. 5) which is laminated on the heat sink 20 via the coating layer 40 in the lamination process described below is shown by a dashed line. Furthermore, in Fig. 6, the range where the sintered body layer 30 is formed by the sintering process described below is shown by a dashed line.

[0046] In the application process, a metal paste is applied to a joining surface (in this example, the rear surface 212 of the base portion 21) in a rectangular area having sides facing in a first direction (the left-right direction in FIG. 6) and a second direction (the up-down direction in FIG. 6) when viewed from the stacking direction, to form a coating layer 40. In the coating process of this embodiment, a coating layer 40 is formed including a coating portion 41 to which the metal paste is applied and a non-coating portion 42 to which the metal paste is not applied. In other words, in the coating process, the metal paste is applied to an area corresponding to the coating portion 41 in FIG. 6 (a coating area 411 described later), thereby forming the coating layer 40 including the coating portion 41 and the non-coating portion 42. Also, in the coating process, a non-coating portion 42 to which the metal paste is not applied is provided in an area of ​​the bonding surface on which the semiconductor element 13 is not mounted as viewed from the stacking direction. In this example, the coating portion 41 is an example of an installation portion to which a bonding base material is provided, and the non-coating portion 42 is an example of a non-installation portion to which no bonding base material is provided.

[0047] In the coating layer 40 formed by the coating process, the non-coated portion 42 is provided in a lattice pattern when viewed from the stacking direction. Specifically, the non-coated portion 42 is provided with two first grooves 42a extending in a first direction and a second groove 42b extending in a second direction, in a lattice pattern. In addition, the non-coated portion 42 is provided with two first grooves 42a and two second grooves 42b in a lattice pattern so as not to overlap with the region where the semiconductor element 13 is mounted when viewed from the stacking direction.

[0048] In this example, each of the first grooves 42a is provided continuously from one end (the left side in FIG. 6) to the other end (the right side in FIG. 6) in the first direction in the coating layer 40. Similarly, each of the second grooves 42b is provided continuously from one end (the upper side in FIG. 6) to the other end (the lower side in FIG. 6) in the second direction in the coating layer 40. In addition, both ends of each of the first grooves 42a and second grooves 42b are connected to the outside of the coating layer 40. Although details will be described later, the non-coated portion 42 of the coating layer 40 is used to exhaust gas generated from the metal paste during the sintering process to the outside of the coating layer 40.

[0049] Moreover, in the coating layer 40 formed by the coating process, the coating portion 41 is made up of a plurality of coating regions 411 divided by the first grooves 42a and the second grooves 42b of the non-coating portion 42. In this example, the coating portion 41 includes a total of nine coating regions 411, three in the first direction and three in the second direction. Each coating region 411 has a square shape when viewed from the stacking direction. In this example, coating section 41 is formed so that each coating region 411 has the same shape and size (area when viewed from the stacking direction).

[0050] In the coating process of this embodiment, coated portion 41 (coated region 411) is formed in a region of the bonding surface where semiconductor element 13 is mounted on insulating substrate 11 as viewed from the stacking direction, and in a range that is a predetermined distance from the region where semiconductor element 13 is mounted. In other words, in the coating process of this embodiment, non-coated portion 42 (first groove 42a and second groove 42b) is not provided in a region of the bonding surface where semiconductor element 13 is mounted on insulating substrate 11 as viewed from the stacking direction, and in a range that is a predetermined distance from the region where semiconductor element 13 is mounted. In the coating step, by forming the coating layer 40 including the coated portion 41 and the non-coated portion 42 in this manner, in the semiconductor device 1 obtained by the manufacturing method of this embodiment, the non-bonded portion 32 where no sintered body is formed is not formed in the region where the semiconductor element is mounted on the insulating substrate 11 as viewed from the stacking direction, and in an area at a predetermined distance from the region where the semiconductor element 13 is mounted. This prevents the non-bonded portion 32 from interfering with the conduction of heat generated by the semiconductor element 13 to the heat sink 20 in the semiconductor device 1, improving the heat dissipation efficiency of the semiconductor device 1.

[0051] In the coating layer 40 formed in the coating step, the width of the non-coated portion 42 (first groove 42a and second groove 42b) and the area of ​​the coated portion 41 (coated region 411) are set so that the sintered body layer 30 obtained through the lamination step and sintering step described below has a desired shape. In addition, the width of the non-coated portion 42 and the area of ​​the coated portion 41 are set so that the sintered body layer 30 obtained has a desired shape, taking into consideration the viscosity of the metal paste used to form the coating layer 40, the pressing force when laminating the heat sink 20 and the insulating substrate 11 of the semiconductor module 10 via the coating layer 40 in the lamination step, the sintering conditions in the sintering step, etc. In this embodiment, in which a metal paste is used as the bonding base material, the application step corresponds to a base material providing step of providing a bonding base material containing metal particles on the bonding surface.

[0052] <Lamination process> 5(b), in the lamination process, the heat sink 20 and the insulating substrate 11 of the semiconductor module 10 are laminated via the metal paste of the coating layer 40 formed in the coating process. In this example, the heat transfer layer 113 of the insulating substrate 11 of the semiconductor module 10 is laminated on the coating layer 40 formed on the rear surface 212 of the base portion 21 of the heat sink 20. In the lamination process, the coating layer 40 is sandwiched between the heat sink 20 and the semiconductor module 10, so that the metal paste in the coating portion 41 (coating region 411) in the coating layer 40 spreads in the planar direction of the base portion 21 and the insulating substrate 11, and the area of ​​the coating portion 41 viewed from the lamination direction increases. Accordingly, the width of the non-coating portion 42 (first groove 42a, second groove 42b) provided between the coating regions 411 becomes narrower.

[0053] When the heat sink 20 and the insulating substrate 11 of the semiconductor module 10 are laminated via the coating layer 40, a pressing force may be applied to the heat sink 20 and the semiconductor module 10, or no pressing force may be applied. The pressing force applied to the heat sink 20 and the semiconductor module 10 is set so that the width of the first groove 42a and the second groove 42b does not become 0 even when the metal paste of the coating portion 41 spreads in the surface direction, in other words, so that the non-coated portion 42 remains in the coating layer 40. The pressing force varies depending on the viscosity of the metal paste used to form the coating layer 40, but can be exemplified as a range of 0.01 MPa or less, preferably 0.005 MPa or less. In addition, the method of applying the pressing force is not particularly limited, but can be exemplified as a method of placing a weight on the semiconductor module 10.

[0054] <Sintering process> In the sintering process, as shown in FIG. 5(c), the coating layer 40 (see FIG. 5(b)) is heated to sinter the metal paste constituting the coating layer 40, thereby forming a sintered body layer 30 consisting of a sintered body that joins the heat sink 20 and the insulating substrate 11 of the semiconductor module 10. In the sintering process, the metal paste constituting the coating portion 41 of the coating layer 40 is sintered to form the joint portion 31 of the sintered body layer 30. In addition, each of the coating regions 411 in the coating portion 41 of the coating layer 40 forms each of the joint regions 311 in the joint portion 31 of the sintered body layer 30. In addition, in the sintering process, each of the first grooves 42a and second grooves 42b in the non-coated portion 42 of the coating layer 40 forms a first non-joining portion 32a and a second non-joining portion 32b in the non-joining portion 32 of the sintered body layer 30.

[0055] Here, when the metal paste constituting the coating layer 40 is sintered in the sintering step, gas such as outgassing is generated due to the evaporation of the solvent contained in the metal paste. If the metal paste constituting the coating layer 40 is sintered with the generated gas remaining in the coating layer 40, voids due to the gas generated from the metal paste may be generated in the sintered body layer 30 formed from the coating layer 40. In this case, the bonding strength between the semiconductor module 10 and the heat sink 20 via the sintered body layer 30 may decrease.

[0056] In contrast, in the present embodiment, in the above-mentioned coating step, non-coated portions 42 where no metal paste is applied are provided on the coating layer 40. As a result, even if gas is generated from the metal paste of the coating layer 40 in the sintering step, the gas is easily discharged to the outside of the coating layer 40 via the non-coated portions 42. As a result, the metal paste is prevented from being sintered in a state where the gas generated from the metal paste remains in the coating layer 40, and a decrease in the bonding strength between the semiconductor module 10 and the heat sink 20 via the sintered body layer 30 is prevented. Particularly in this embodiment, in the above-mentioned coating step, the coating layer 40 is formed such that both ends of the first groove 42a and the second groove 42b of the non-coated portion 42 are connected to the outside of the coating layer 40. This makes it easier for gas generated from the metal paste of the coating layer 40 in the sintering step to be discharged to the outside of the coating layer 40 via the first groove 42a and the second groove 42b of the non-coated portion 42.

[0057] The temperature at which the coating layer 40 is heated in the sintering step varies depending on the type of metal particles contained in the metal paste, but can be, for example, in the range of 150° C. or more and 500° C. or less. In the sintering process, the semiconductor module 10 and the heat sink 20 may be sintered while being pressed in the stacking direction via the coating layer 40, or the semiconductor module 10 and the heat sink 20 may be sintered without pressing them. When the semiconductor module 10 and the heat sink 20 are pressed in the sintering process, the pressing force is preferably 25 MPa or less, and more preferably 10 MPa or less. When the pressing force for pressing the semiconductor module 10 and the heat sink 20 in the sintering process exceeds 10 MPa, the width of the non-coated portion 42 becomes narrow, and the gas generated from the metal paste is difficult to be discharged through the non-coated portion 42 of the coating layer 40. When the pressing force for pressing the semiconductor module 10 and the heat sink 20 in the sintering process exceeds 25 MPa, structures such as the insulating substrate 11 may be damaged.

[0058] As described above, in this embodiment, the coating process, lamination process and sintering process are used to obtain the semiconductor device 1 shown in Figures 1 to 4, which includes a semiconductor module 10, a heat sink 20, and a sintered body layer 30, and in which a non-bonded portion 32 where the insulating substrate 11 and the heat sink 20 are not bonded is formed in an area of ​​the insulating substrate 11 of the semiconductor module 10 where the semiconductor element 13 is not mounted.

[0059] In the above-mentioned manufacturing method of the semiconductor device 1, the coating layer 40 is formed between the heat sink 20 and the semiconductor module 10 in which the semiconductor element 13 is bonded onto the insulating substrate 11, but this is not limited to this. For example, the coating layer 40 may be formed between the insulating substrate 11 and the heat sink 20 before the semiconductor element 13 is bonded, and then sintered to form the sintered body layer 30, and the semiconductor element 13 may be bonded onto the insulating substrate 11 to form the semiconductor module 10. In this case, in the coating step of forming the coating layer 40 by applying a metal paste to the bonding surface, the coating portion 41 and the non-coating portion 42 are formed, and the sintered body layer 30 having the bonding portion 31 and the non-bonding portion 32 is formed by the lamination step and the sintering step. Then, in the subsequent bonding step of bonding the semiconductor element 13 to the insulating substrate 11, the semiconductor element 13 may be bonded to a region of the insulating substrate 11 that overlaps with the bonding portion 31 of the sintered body layer 30 corresponding to the coating portion 41 of the coating layer 40 when viewed from the lamination direction.

[0060] (Metal Paste) Next, an example of a metal paste used for forming the sintered body layer 30 in the semiconductor device 1 of the present embodiment will be described in detail. The metal paste contains metal particles and a solvent for dispersing the metal particles. The metal paste may also contain additives other than the metal particles and the solvent. Examples of such additives include a surfactant, an antifoaming agent, and an ion trapping agent.

[0061] <Metal particles> As described above, examples of the metal particles include particles of a metal selected from copper, silver, and an alloy of copper and silver. Furthermore, the metal particles may be particles made of copper whose surfaces are coated with silver. Among these, from the viewpoint of thermal conductivity between the semiconductor module 10 and the heat sink 20 via the sintered body layer 30, it is preferable to use copper particles as the metal particles.

[0062] The average particle size (50% deposition average particle size) of the metal particles is, for example, in the range of 0.1 μm to 500 μm, preferably in the range of 1 μm to 200 μm, and more preferably in the range of 10 μm to 100 μm. The average particle size of the metal particles can be determined by a method in which the solvent is removed from the metal paste, the dried metal particles are dispersed using a known dispersant, and the dispersed metal particles are measured using a light scattering particle size distribution measuring device.

[0063] The shape of the metal particles is not particularly limited, and examples thereof include a sphere, a roughly spherical shape such as a spheroid, a lump, a needle, a flake, and an aggregate thereof. These shapes of the metal particles may be used alone or in combination. From the viewpoint of the dispersibility of the metal particles in the metal paste and the packing property of the metal particles in the sintered body layer 30, the shape of the metal particles is preferably a sphere, a roughly spherical shape, or a flake shape. The metal particles may be surface-treated with a known surface treatment agent.

[0064] <Solvent> As the solvent, a volatile solvent known as a solvent for metal pastes can be used.Examples of such solvents include monohydric and polyhydric alcohols such as pentanol, hexanol, heptanol, octanol, decanol, ethylene glycol, diethylene glycol, propylene glycol, butylene glycol, terpineol, dihydrotapineol, and isobornylcyclohexanol (MTPH); ethylene glycol butyl ether, ethylene glycol phenyl ether, diethylene glycol methyl ether, diethylene glycol ethyl ether, diethylene glycol butyl ether, diethylene glycol isobutyl ether, diethylene glycol hexyl ether, triethylene glycol methyl ether, diethylene glycol dimethyl ether, diethylene glycol diethyl ether, diethylene glycol dibutyl ether, diethylene glycol butyl methyl ether, diethylene glycol isopropyl methyl ether, triethylene glycol dimethyl ether, triethylene glycol butyl methyl ether, propylene glycol propyl ether, dipropylene glycol methyl ether, dipropylene glycol ethyl ether, and the like. Ethers such as ethylene glycol ethyl ether acetate, ethylene glycol butyl ether acetate, diethylene glycol ethyl ether acetate, diethylene glycol butyl ether acetate, dipropylene glycol methyl ether, and tripropylene glycol dimethyl ether; ethers such as ethylene glycol ethyl ether acetate, ethylene glycol butyl ether acetate, diethylene glycol ethyl ether acetate, diethylene glycol butyl ether acetate, dipropylene glycol methyl ether acetate (DPMA), ethyl lactate, butyl ... Examples of the esters include butyrolactone, butyl stearate, squalane, dibutyl sebacate, bis(2-ethylhexyl) adipate, γ-butyrolactone, and propylene carbonate; acid amides such as N-methyl-2-pyrrolidone, N,N-dimethylacetamide, and N,N-dimethylformamide; aliphatic hydrocarbons such as cyclohexane, octane, nonane, decane, and undecane; aromatic hydrocarbons such as benzene, toluene, and xylene; mercaptans having an alkyl group having 1 to 18 carbon atoms; and mercaptans having a cycloalkyl group having 5 to 7 carbon atoms.

[0065] The content of the solvent in the metal paste can be, for example, in the range of 5 parts by mass or more and 50 parts by mass or less, assuming that the total mass of the metal particles is 100 parts by mass.

[0066] (Formation of sintered body using bonding sheet) As described above, the sintered body constituting the sintered body layer 30 of this embodiment may be formed using a bonding sheet containing metal particles as another example of a bonding base material containing metal particles. Specifically, instead of the coating step in the manufacturing method of the semiconductor device 1 when the above-mentioned metal paste is used, the following molding step and pasting step may be performed. Then, after the pasting step, the lamination step and sintering step may be performed in the same manner as in the above-mentioned example.

[0067] <Forming process> In the forming step, the bonding sheet containing metal particles is formed to match the shape of the region where the sintered body layer 30 is to be formed. In the forming step, the bonding sheet is formed, for example, to have the same shape as the coating portion 41 of the coating layer 40 in the above-mentioned coating step. In the lamination process and sintering process performed after the attachment process, the area of ​​the bonding sheet may increase as the bonding sheet is sandwiched between the heat sink 20 and the semiconductor module 10. Therefore, in the molding process, the bonding sheet is molded so that the shape of the sintered body layer 30 obtained through the lamination process and sintering process has a desired shape.

[0068] <Pasting process> In the attachment step, the bonding sheet formed in the molding step is attached to either one of the surfaces (on the heat transfer layer 113) of the insulating substrate 11 on which the semiconductor element 13 is mounted (on the wiring layer 112) or the back surface 212 of the base portion 21 of the heat sink 20. In this example, the bonding sheet is attached to the back surface 212 of the base portion 21 of the heat sink 20 as an example. The surface to which the bonding sheet is attached is the bonding surface. In the pasting step, a bonding sheet is pasted on a partial region of the back surface 212 of the base portion 21 when viewed from the stacking direction. Specifically, in the pasting step, the bonding sheet is pasted on a region corresponding to the coating portion 41 to which the metal paste is applied in the above-mentioned coating step. In addition, in the pasting step, the bonding sheet is not pasted on a region corresponding to the non-coating portion 42 to which the metal paste is not applied in the above-mentioned coating step. Note that in the pasting step, the region to which the bonding sheet is pasted on the bonding surface is an example of an installation portion provided with a bonding base material, and the region to which the bonding sheet is not pasted on the bonding surface is an example of a non-installation portion not provided with a bonding base material. In this embodiment in which a bonding sheet is used as the bonding base material, the attaching step corresponds to a base material providing step of providing a bonding base material containing metal particles on the bonding surface.

[0069] <Lamination process> In the lamination step, similarly to the above-described example, the heat sink 20 and the insulating substrate 11 of the semiconductor module 10 are laminated via the bonding sheet attached in the attachment step. In this example, the heat transfer layer 113 of the insulating substrate 11 of the semiconductor module 10 is placed on the bonding sheet attached onto the rear surface 212 of the base portion 21 of the heat sink 20.

[0070] <Sintering process> In the sintering step, as in the above-mentioned example, the bonding sheet is heated to sinter the metal particles contained in the bonding sheet, and a bonding portion 31 of the sintered body layer 30 made of a sintered body that bonds the heat sink 20 and the insulating substrate 11 of the semiconductor module 10 is formed. In the sintering step, gas such as outgassing caused by volatilization of the solvent contained in the bonding sheet is generated. In this embodiment, in the above-mentioned bonding step, a plurality of bonding sheets are bonded with gaps between them. As a result, even if gas is generated from the bonding sheets in the sintering step, the gas is easily discharged to the outside through the gaps between the bonding sheets.

[0071] As described above, when a bonding sheet containing metal particles is used, just like when a metal paste is used, a semiconductor device 1 is obtained which comprises a semiconductor module 10, a heat sink 20, and a sintered body layer 30, and in which a non-bonded portion 32 where the insulating substrate 11 and the heat sink 20 are not bonded is formed in an area of ​​the insulating substrate 11 of the semiconductor module 10 where the semiconductor element 13 is not mounted.

[0072] (Joint sheet) The bonding sheet contains metal particles. As the metal particles, the same metal particles as those used in the above-mentioned metal paste can be used. As the bonding sheet, the following three modes can be exemplified.

[0073] <First aspect> The bonding sheet of the first embodiment includes metal particles and a binder made of a heat-decomposable resin. The bonding sheet of the first embodiment has a sheet-like shape with the metal particles held by the binder made of a heat-decomposable resin. The thermally decomposable resin is a resin that can be thermally decomposed by heating in the sintering step described above. It is preferable that the thermally decomposable resin is thermally decomposed so that almost no resin remains in the sintered body layer 30 formed by the sintering step. As the thermally decomposable resin, for example, polycarbonate, acrylic resin, ethyl cellulose, polyvinyl alcohol, etc. can be used. These may be used alone or in combination. Among these, it is preferable to use polycarbonate, which has high thermal decomposition properties.

[0074] The content of the thermally decomposable resin in the bonding sheet of the first embodiment is preferably 30 volume % or more and 70 volume % or less, more preferably 35 volume % or more and 65 volume % or less, and even more preferably 40 volume % or more and 60 volume % or less, based on the entire bonding sheet. The bonding sheet of the first embodiment may contain other additives in addition to the metal particles and the thermally decomposable resin.

[0075] <Second aspect> The bonding sheet of the second aspect includes metal particles and a binder made of a solvent that is waxy or liquid at room temperature. The bonding sheet of the second aspect has a sheet-like shape because the metal particles are held by the binder made of the solvent. Examples of the solvent that can be used include ethylene glycol, polyethylene glycol, glycerin, butanetriol, polyoxypropylenetriol, etc. These may be used alone or in combination.

[0076] The content of the solvent in the bonding sheet of the second embodiment is preferably 1 mass % or more and 10 mass % or less based on the entire bonding sheet. The bonding sheet of the second embodiment may contain other additives in addition to the metal particles and the solvent.

[0077] <Third aspect> The bonding sheet of the third embodiment is made of a porous body in which adjacent metal particles are continuous with each other and voids are formed between the metal particles. The bonding sheet of the third embodiment is formed, for example, by sintering metal particles. Note that, in the bonding sheet of the third embodiment, the metal particles are not completely sintered, and the metal particles can be further sintered by the above-mentioned sintering process to bond the heat sink 20 and the insulating substrate 11 of the semiconductor module 10. The bonding sheet of the third embodiment preferably has a porosity of 15 volume % or more and 50 volume % or less, and more preferably 15 volume % or more and 30 volume % or less. Moreover, the bonding sheet of the third embodiment may contain other additives such as an adhesive assistant and a reducing agent in addition to the metal particles.

[0078] Although the embodiment of the present invention has been described above, the present invention is not limited to the embodiment, and various modifications and combinations may be made as long as they are not contrary to the spirit of the present invention. The present invention is also applied to a semiconductor device 1 as shown in FIGS. 1 to 4, which is produced by the present manufacturing method. [Explanation of symbols]

[0079] Reference Signs List 1...semiconductor device, 10...semiconductor module, 11...insulating substrate, 13...semiconductor element, 15...bonding layer, 20...heat sink, 21...base portion, 22...fin, 30...sintered body layer, 31...bonding portion, 32...non-bonding portion, 32a...first non-bonding portion, 32b...second non-bonding portion, 40...coating layer, 41...coated portion, 42...non-coated portion, 42a...first groove, 42b...second groove

Claims

1. a base material setting step of providing a bonding base material containing metal particles on a bonding surface which is either the other surface of a substrate on one surface of which a semiconductor element is mounted, or a surface of a heat sink having a flat base portion that faces the other surface of the base portion; a lamination step of laminating the substrate and the heat sink via the bonding base material; a sintering step of sintering the bonding base material to form a sintered body that bonds the substrate and the heat sink, The base material providing step provides the bonding base material on the bonding surface so that a non-mounting portion where the bonding base material is not provided is formed in a region of the bonding surface where the semiconductor element is not mounted as viewed from the stacking direction of the substrate and the heat sink. A method for manufacturing a semiconductor device.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate installation step provides the bonding substrate on the bonding surface so that the non-installation portion is not formed in the area of ​​the bonding surface where the semiconductor element is mounted when viewed from the stacking direction, and in an area within a predetermined distance from the area where the semiconductor element is mounted.

3. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate installation step comprises providing the bonding substrate on the bonding surface so that the non-installation portion is formed in a grid pattern with a plurality of first grooves extending in a first direction along the bonding surface and a plurality of second grooves extending in a second direction along the bonding surface and intersecting the first direction, and the first grooves and the second grooves surround an area where the semiconductor element is mounted when viewed from the stacking direction.

4. a base material setting step of providing a bonding base material containing metal particles on a bonding surface which is either one of the other surface of a substrate having one surface and the other surface, and the surface of a heat sink having a flat base portion, the surface facing the other surface of the base portion; a lamination step of laminating the substrate and the heat sink via the bonding base material; a sintering step of sintering the bonding base material to form a sintered body that bonds the substrate and the heat sink; a bonding step of bonding a semiconductor element to one surface of the substrate, The base material installation step includes providing the bonding base material on the bonding surface so as to form an installation portion where the bonding base material is provided and a non-installation portion where the bonding base material is not provided; The bonding step bonds the semiconductor element to a region of the one surface of the substrate that overlaps with the installation portion when viewed from a stacking direction of the substrate and the heat sink. A method for manufacturing a semiconductor device.

5. a substrate having a semiconductor element mounted on one surface; a heat sink having a flat base portion and stacked on the other surface of the substrate; a sintered body that joins the other surface of the substrate and the base portion of the heat sink, The sintered body has a non-bonded portion where the substrate and the heat sink are not bonded in an area where the semiconductor element is not mounted on the substrate when viewed from the stacking direction of the substrate and the heat sink.

6. The semiconductor device according to claim 5, characterized in that the non-bonded portion is formed so as to surround the region where the semiconductor element is mounted on the substrate when viewed from the stacking direction, and the area of ​​the sintered body surrounded by the non-bonded portion is 1.1 times or more and 5.0 times or less the area of ​​the semiconductor element.

Images