Imaging device

Abstract

To provide an imaging device suitable for detecting infrared light.SOLUTION: An imaging device includes a first layer, a second layer, a third layer, and a fourth layer that are stacked in this order. The first layer includes an infrared transmission filter. The second layer includes single-crystal silicon. The third layer includes a device formation layer. The fourth layer includes a support substrate. The second layer includes a photoelectric conversion device in which the single-crystal silicon is a light absorption layer. The third layer includes a transistor in which a channel formation region contains a metal oxide. The photoelectric conversion device and the transistor are electrically connected to each other. The photoelectric conversion device receives light having transmitted the infrared transmission filter.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification etc. relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, a driving method thereof, or a manufacturing method thereof.

[0003] Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. Further, a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device. [Background technology]

[0004] A technology for forming a transistor using an oxide semiconductor thin film formed over a substrate has attracted attention. For example, Patent Document 1 discloses an imaging device in which a transistor that includes an oxide semiconductor and has an extremely low off-state current is used in a pixel circuit. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2011-119711 A Summary of the Invention [Problem to be solved by the invention]

[0006] Imaging devices are not only used as a means of converting visible light into an image, but are also used for a variety of purposes, such as personal authentication, defect analysis, medical diagnosis, and security. In these applications, in addition to visible light, short-wavelength light such as X-rays and long-wavelength light such as infrared light are used according to the application.

[0007] An object of one embodiment of the present invention is to provide an imaging device suitable for detecting infrared light, to provide an imaging device suitable for biometric authentication, to provide an imaging device suitable for imaging a moving object, or to provide a manufacturing method of the imaging device.

[0008] Another object is to provide an imaging device with low power consumption. Another object is to provide an imaging device with high reliability. Another object is to provide a small imaging device. Another object is to provide a novel imaging device. Another object is to provide a method for operating the imaging device. Another object is to provide a novel semiconductor device or the like.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention relates to an imaging device including single crystal silicon in an imaging device and including metal oxide in a channel formation region of a transistor included in a circuit, and to a manufacturing method thereof.

[0011] One embodiment of the present invention is a method for manufacturing an imaging device having a single crystal silicon substrate and a supporting substrate, comprising the steps of: providing a region of an opposite conductivity type to the conductivity type of the single crystal silicon substrate on a first surface side of the single crystal silicon substrate to form a photoelectric conversion device; forming a transistor on the photoelectric conversion device that has a metal oxide in a channel formation region and is electrically connected to the photoelectric conversion device; forming a first insulating layer on the transistor; forming a second insulating layer on the supporting substrate; bonding the surface of the first insulating layer to the surface of the second insulating layer; and grinding and polishing a surface of the single crystal silicon substrate opposite to the first surface to thin a light absorption layer of the photoelectric conversion device.

[0012] Another embodiment of the present invention is a method for manufacturing an imaging device having a single crystal silicon substrate and a supporting substrate, comprising the steps of: providing a region having a conductivity type opposite to that of the single crystal silicon substrate on a first surface side of the single crystal silicon substrate to form a photoelectric conversion device; forming a first insulating layer on the photoelectric conversion device and a first conductive layer electrically connected to the photoelectric conversion device; forming a transistor having a metal oxide in a channel formation region on the supporting substrate; forming a second insulating layer on the transistor and a second conductive layer electrically connected to the transistor; bonding a surface of the first insulating layer to a surface of the second insulating layer and bonding a surface of the first conductive layer to a surface of the second conductive layer; and grinding and polishing a surface of the single crystal silicon substrate opposite to the first surface to thin a light absorption layer of the photoelectric conversion device.

[0013] Furthermore, a photoelectric conversion device may be formed by providing a region on the polished surface of the single crystal silicon substrate that has the same conductivity type as the single crystal silicon substrate and has a higher carrier concentration than the single crystal silicon substrate.

[0014] A third insulating layer may be formed in contact with the photoelectric conversion device, and an optical filter layer may be formed so as to overlap the photoelectric conversion device with the third insulating layer interposed therebetween.

[0015] Another embodiment of the present invention is an imaging device in which a first layer, a second layer, a third layer, and a fourth layer are stacked in this order, wherein the first layer, the second layer, the third layer, and the fourth layer each have an overlapping area, the first layer has an optical filter layer, the second layer has single crystal silicon, the third layer has a device formation layer, and the fourth layer has a supporting substrate, the second layer has a photoelectric conversion device having single crystal silicon as a light absorption layer, and the third layer has a transistor having a metal oxide in a channel formation region, the photoelectric conversion device and the transistor are electrically connected, and the photoelectric conversion device receives light that has passed through the optical filter layer.

[0016] The device formation layer has a first transistor, a second transistor, a third transistor, a fourth transistor, and a capacitor, and one electrode of the photoelectric conversion device is electrically connected to one of the source or drain of the first transistor, the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, one of the source or drain of the second transistor is electrically connected to one electrode of the capacitor, one electrode of the capacitor is electrically connected to the gate of the third transistor, and one of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor.

[0017] As the optical filter layer, a layer that blocks visible light and transmits infrared light can be used.

[0018] The metal oxide in the channel formation region of the transistor preferably contains In, Zn, and M (M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf). Effect of the Invention

[0019] By using one embodiment of the present invention, it is possible to provide an imaging device suitable for detecting infrared light, an imaging device suitable for biometric authentication, an imaging device suitable for imaging a moving object, or a manufacturing method of the imaging device.

[0020] Alternatively, it is possible to provide an imaging device with low power consumption. Alternatively, it is possible to provide an imaging device with high reliability. Alternatively, it is possible to provide a small-sized imaging device. Alternatively, it is possible to provide a novel imaging device. Alternatively, it is possible to provide a method for operating the imaging device. Alternatively, it is possible to provide a novel semiconductor device or the like. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 is a diagram illustrating an imaging device. [Diagram 2] 2A and 2B are diagrams illustrating a pixel circuit. [Diagram 3] Fig. 3A is a diagram for explaining the rolling shutter method, and Fig. 3B is a diagram for explaining the global shutter method. [Figure 4] 4A and 4B are diagrams illustrating a method for manufacturing an imaging device. [Diagram 5] 5A to 5C are diagrams illustrating a method for manufacturing an imaging device. [Figure 6] 6A and 6B are diagrams illustrating a method for manufacturing an imaging device. [Figure 7] 7A to 7C are diagrams illustrating a method for manufacturing an imaging device. [Figure 8] 8A and 8B are diagrams illustrating a method for manufacturing an imaging device. [Figure 9] 9A to 9D are diagrams illustrating a method for manufacturing an imaging device. [Figure 10] 10A to 10C are diagrams illustrating an imaging device. [Figure 11] 11A and 11B are timing charts illustrating the operation of the pixel circuit. [Figure 12] 12A and 12B are diagrams illustrating a pixel circuit. [Figure 13] FIG. 13 is a block diagram illustrating an imaging device. [Figure 14] 14A and 14B are diagrams for explaining the configuration of a pixel of an imaging device. [Figure 15] 15A to 15D are diagrams illustrating transistors. [Figure 16] 16A1 to 16A3 and 16B1 to 16B3 are perspective views for explaining a package that houses an imaging device and a camera module. [Figure 17] 17A to 17C are diagrams illustrating an electronic device. [Figure 18] 18A to 18C are diagrams illustrating an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, hatching of the same elements constituting the drawings may be omitted or changed as appropriate between different drawings.

[0023] In addition, even if a circuit diagram shows a single element, the element may be configured as a plurality of elements as long as there is no functional problem. For example, a plurality of transistors operating as a switch may be connected in series or parallel. A capacitor may also be divided and placed in multiple positions.

[0024] In addition, one conductor may have multiple functions such as wiring, an electrode, and a terminal, and in this specification, multiple names may be used for the same element. Even if elements are shown as being directly connected to each other on a circuit diagram, the elements may actually be connected to each other via multiple conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0025] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention and a manufacturing method thereof will be described with reference to the drawings.

[0026] One embodiment of the present invention is an imaging device compatible with infrared light. By converting received infrared light into image data, the imaging device can be used for applications such as biometric authentication, defect analysis of industrial products, and non-defective product selection. In addition, by using a pixel circuit capable of imaging by a global shutter system, an image without distortion can be obtained even for a moving subject.

[0027] <Imaging device> 1 is a diagram illustrating an imaging device according to one embodiment of the present invention. The imaging device has a layer 11, a layer 12, a layer 13, and a layer 14.

[0028] The layer 11 has an optical filter layer. As the optical filter layer, for example, a layer that blocks visible light and transmits infrared light (hereinafter, referred to as an infrared light transmission filter) can be used. In this specification, an infrared light transmission filter refers to a filter that mainly blocks light (mainly visible light) with a shorter wavelength than near-infrared light. By blocking visible light that becomes noise, a clear infrared light image can be obtained. Note that, as the optical filter layer, a layer that transmits light of another specific wavelength can be used to make an imaging device specialized for imaging using that light.

[0029] The layer 12 has a photoelectric conversion device (also referred to as a photoelectric conversion element). A photodiode can be used as the photoelectric conversion device. In one embodiment of the present invention, a photodiode capable of photoelectrically converting infrared light is used to perform imaging using infrared light. For example, a pn junction photodiode using single crystal silicon in a photoelectric conversion portion, a pin junction photodiode using polycrystalline silicon or microcrystalline silicon in a photoelectric conversion layer, or the like can be used. Alternatively, a material capable of photoelectrically converting light in the infrared region, such as a compound semiconductor, may be used. In this embodiment, an example in which a pn junction photodiode using single crystal silicon is used as the photoelectric conversion device will be described. In addition, the light receiving surface is on the layer 11 side.

[0030] The layer 13 includes a device formation layer. The device formation layer includes transistors that constitute a pixel circuit. As the transistors, it is preferable to use transistors that use metal oxide in the channel formation region (hereinafter, referred to as OS transistors). OS transistors have characteristics of extremely low off-state current, and are suitable as components of pixel circuits, for example, enabling long-term data retention in the pixel circuit.

[0031] The layer 14 has a support substrate. In one embodiment of the present invention, a photodiode is fabricated by forming a region of a conductivity type opposite to that of the single crystal silicon substrate on the first surface side of the single crystal silicon substrate. In this case, the single crystal silicon substrate needs to have a thickness (e.g., several hundred μm) that allows it to function as a support.

[0032] However, if the region that functions as the light absorption layer of the photodiode is too thick relative to the direction in which light penetrates, the photocarriers generated in the region where the distance from the depletion layer exceeds the diffusion length will recombine and cannot be extracted to the outside. Therefore, it is necessary to thin the single crystal silicon substrate and adjust the thickness so that the light absorption layer has an appropriate thickness. The support substrate is a necessary element in the thinning process (grinding, polishing). It also serves as the support substrate for the completed imaging device.

[0033] <Pixel circuit> 2A is a circuit diagram illustrating an example of a pixel circuit configured with a photoelectric conversion device included in layer 11 and transistors included in the device formation layer of layer 12. The pixel circuit can include a photoelectric conversion device 101, a transistor 103, a transistor 104, a transistor 105, a transistor 106, and a capacitor 108. Note that the capacitor 108 may not be provided.

[0034] One electrode (cathode) of the photoelectric conversion device 101 is electrically connected to one of the source or drain of the transistor 103. The other of the source or drain of the transistor 103 is electrically connected to one of the source or drain of the transistor 104. One of the source or drain of the transistor 104 is electrically connected to one electrode of the capacitor 108. One electrode of the capacitor 108 is electrically connected to the gate of the transistor 105. One of the source or drain of the transistor 105 is electrically connected to one of the source or drain of the transistor 106.

[0035] Here, a wiring that connects the other of the source and the drain of the transistor 103, one electrode of the capacitor 108, and the gate of the transistor 105 is referred to as a node FD. The node FD can function as a charge storage portion.

[0036] The other electrode (anode) of the photoelectric conversion device 101 is electrically connected to a wiring 121. The gate of the transistor 103 is electrically connected to a wiring 127. The other of the source and drain of the transistor 104 is electrically connected to a wiring 122. The other of the source and drain of the transistor 105 is electrically connected to a wiring 123. The gate of the transistor 104 is electrically connected to a wiring 126. The gate of the transistor 106 is electrically connected to a wiring 128. The other electrode of the capacitor 108 is electrically connected to a reference potential line such as a GND wiring. The other of the source and drain of the transistor 106 is electrically connected to a wiring 129.

[0037] The wirings 127, 126, and 128 can function as signal lines for controlling the conduction of each transistor. The wiring 129 can function as an output line.

[0038] 2A, the cathode side of the photoelectric conversion device 101 is electrically connected to the transistor 103, and the node FD is reset to a high potential for operation, so the wiring 122 has a high potential (a higher potential than the wiring 121).

[0039] FIG. 2A shows a configuration in which the cathode of the photoelectric conversion device 101 is electrically connected to the node FD, but the anode side of the photoelectric conversion device 101 may be electrically connected to either the source or drain of the transistor 103 as shown in FIG. 2B.

[0040] In this configuration, the node FD is reset to a low potential for operation, so the wiring 122 is set to a low potential (a lower potential than the wiring 121).

[0041] The transistor 103 has a function of controlling the potential of the node FD. The transistor 104 has a function of resetting the potential of the node FD. The transistor 105 functions as a source follower circuit and can output the potential of the node FD as image data to the wiring 129. The transistor 106 has a function of selecting a pixel to which image data is output.

[0042] It is preferable to use OS transistors as the transistors 103 and 104. OS transistors have characteristics of extremely low off-state current. By using OS transistors as the transistors 103 and 104, the period during which charge can be held at the node FD can be extremely long. Therefore, a global shutter system in which charge is accumulated simultaneously in all pixels can be applied without complicating the circuit configuration or operation method.

[0043] <Operation method of imaging device> Fig. 3A is a schematic diagram of the operation method of the rolling shutter method, and Fig. 3B is a schematic diagram of the global shutter method. En represents the exposure (accumulation operation) of the nth column (n is a natural number), and Rn represents the readout operation of the nth column. Figs. 3A and 3B show the operations from the 1st row to the Mth row (M is a natural number).

[0044] The rolling shutter method is an operation method in which exposure and data readout are performed sequentially, overlapping the readout period of one row with the exposure period of another row. Since the readout operation is performed immediately after exposure, imaging can be performed even with a circuit configuration in which the data retention period is relatively short. However, since one frame of image is composed of data that is not captured simultaneously, distortion occurs in the image when capturing a moving object.

[0045] On the other hand, the global shutter method is a method of operation in which all pixels are exposed simultaneously, data is stored in each pixel, and the data is read out row by row, making it possible to obtain images without distortion even when capturing a moving object.

[0046] When a pixel circuit uses a transistor with a relatively high off-state current, such as a transistor using Si in a channel formation region (hereinafter, Si transistor), a rolling shutter system is often used because a data potential is likely to flow out from a charge accumulation portion. To realize the global shutter system using a Si transistor, a separate memory circuit or the like must be provided, and further complicated operations must be performed at high speed. On the other hand, when an OS transistor is used in a pixel circuit, the global shutter system can be easily realized because there is almost no flow of data potential from a charge accumulation portion. Note that the imaging device according to one embodiment of the present invention can also be operated using the rolling shutter system.

[0047] Note that OS transistors may also be used for the transistors 105 and 106. Any combination of OS transistors and Si transistors may also be used. All the transistors may be OS transistors or Si transistors. Examples of Si transistors include transistors having amorphous silicon and transistors having crystalline silicon (typically, low-temperature polysilicon, single crystal silicon, or the like).

[0048] <Production method> Next, a method for manufacturing the imaging device of one embodiment of the present invention will be described. There are two manufacturing methods, a first method and a second method, and both methods use a bonding process.

[0049] <First Method> The first method is a method in which a transistor and the like are fabricated on a photoelectric conversion device provided on a single crystal silicon substrate, and a supporting substrate is attached to the photoelectric conversion device.

[0050] First, a photoelectric conversion device 101 is formed on the first surface side of a single crystal silicon substrate 21 (see FIG. 4A). In the figures explaining the method for fabricating an imaging device in this specification, a perspective view showing a part of the whole and a cross section of a part of the whole are shown. Also, the symbols of transistors and diodes shown in the figures simply indicate the positions of the devices and do not reflect the electrical connections or circuit configuration. FIG. 4A shows a plurality of photoelectric conversion devices 101 corresponding to a plurality of pixels, respectively.

[0051] The photoelectric conversion device 101 can be formed by bonding a partial region of a single crystal silicon substrate 21 to a region 22 provided on the single crystal silicon substrate. The region 22 is a region having a conductivity type opposite to that of the single crystal silicon substrate 21. Here, the conductivity type of the single crystal silicon substrate 21 is p-type, and the conductivity type of the region 22 is n-type. That is, the photoelectric conversion device 101 is a pn junction photodiode.

[0052] The region 22 can be formed by adding an n-type dopant (phosphorus, arsenic, etc.) to the first surface of the single crystal silicon substrate 21 by using a technique such as ion doping or ion implantation.

[0053] Next, a device formation layer 23 is formed on the photoelectric conversion device 101 (see FIG. 5A). In addition to the transistors and capacitors of the pixel circuit, a plurality of insulating films are provided on the device formation layer 23 as necessary. The photoelectric conversion device 101 and the transistors are electrically connected.

[0054] Since transistors and capacitors have a three-dimensional structure, unevenness occurs on the upper part of the device formation layer 23. Since the unevenness affects the subsequent processes, an insulating layer 24 is provided to flatten the unevenness of the surface (see FIG. 5B). Note that the insulating layer 24 is not limited to a single layer, and may be a laminate of multiple layers. For example, an inorganic film such as a silicon oxide film, or an organic film such as an acrylic resin or polyimide film can be used. Note that at least the outermost surface is an inorganic film, since bonding is performed to bond inorganic films together in the next process. Also, the surface may be flattened using CMP (chemical mechanical polishing) or the like, if necessary.

[0055] Next, insulating layer 26 is formed on supporting substrate 25, and the surface of insulating layer 26 is brought into close contact with the surface of insulating layer 24, followed by a bonding process (see FIG. 5C).

[0056] It is preferable to use a hard material with high flatness such as a glass substrate, a ceramic substrate, a semiconductor substrate, a metal substrate, etc. for the support substrate 25. It is preferable to use an inorganic film such as a silicon oxide film for the insulating layer 26, and it is preferable that at least the outermost surface of the insulating layer 24 and the outermost surface of the insulating layer 26 are formed of the same material.

[0057] It is preferable to hydrophilize the surfaces of the insulating layer 26 and the insulating layer 24 immediately before bonding. By hydrophilizing the bonding surfaces, strong adhesive strength at the atomic level can be obtained. Heat treatment or pressure treatment may also be performed as necessary.

[0058] Next, the surface of the single crystal silicon substrate 21 opposite to the first surface is ground and polished using a grinding and polishing tool 27 to thin the single crystal silicon substrate 21 (see FIG. 6A). As the grinding and polishing tool 27, a grinding device, a lapping device, a polishing device, a CMP device, or the like may be appropriately used as necessary. Wet etching may also be used in combination.

[0059] The thickness of the single crystal silicon substrate 21 may be determined in consideration of the penetration length of light, the diffusion length, the thickness of the depletion layer, etc. For example, when near-infrared light is to be imaged, the thickness is set to 3 μm or more and 100 μm or less, preferably 5 μm or more and 50 μm or less, and more preferably 10 μm or more and 25 μm or less.

[0060] After the single crystal silicon substrate 21 is thinned to a desired thickness, a p + A region 28 having a conductivity type of the ZnO type may be formed (see FIG. 6B). The region 28 has a higher carrier concentration and lower resistance than the single crystal silicon substrate 21, and acts as a carrier extraction electrode (common electrode) of the photoelectric conversion device 101. In addition, in the pixel circuit, the region 28 also acts as the wiring 121 or a part thereof. Note that a configuration in which the region 28 is not provided may be adopted.

[0061] Region 28 can be formed by adding a p-type dopant (boron, aluminum, etc.) to the surface opposite to the first surface of single crystal silicon substrate 21 by using a technique such as ion doping, ion implantation, vapor phase diffusion, solid phase diffusion, etc. This is the first method.

[0062] <Second method> The second method is a method in which a photoelectric conversion device provided on a single crystal silicon substrate is bonded to a transistor or the like provided on a support substrate. In the following description, descriptions that overlap with the first method will be omitted.

[0063] First, a photoelectric conversion device 101 is formed in the same manner as in the first method (see FIG. 4A). Then, an insulating layer 31 and a conductive layer 32 are formed on the photoelectric conversion device 101 (see FIG. 4B). The insulating layer 31 can be made of the same material as the insulating layer 26. The conductive layer 32 is a plug for electrically connecting the photoelectric conversion device 101 and a transistor, and one end of the conductive layer 32 is electrically connected to the photoelectric conversion device 101.

[0064] The conductive layer 32 can be formed by providing an opening in the insulating layer 31, and then providing one or more conductive materials such as titanium, tungsten, tantalum, or nitrides thereof so as to fill the opening, and removing excess conductive materials by CMP, etc. The conductive layer 32 is embedded in the insulating layer 31, and its surface is a flat surface that is continuous with the surface of the insulating layer 31.

[0065] Next, a device formation layer 23 is formed on a support substrate 25 (see FIG. 7A). In addition to the transistors and capacitors of the pixel circuits, a plurality of insulating films are provided in the device formation layer 23 as necessary. Then, an insulating layer 33 and a conductive layer 34 are formed (see FIG. 7B). The insulating layer 33 can be made of the same material as the insulating layer 24. The conductive layer 34 is a plug for electrically connecting the photoelectric conversion device 101 and the transistor, and one end is electrically connected to the transistor.

[0066] The conductive layer 34 can be formed by providing an opening in the insulating layer 33, and then providing one or more conductive materials such as titanium, tungsten, tantalum, and nitrides thereof so as to fill the opening, and removing excess conductive materials by CMP, etc. The conductive layer 34 is embedded in the insulating layer 33, and its surface is continuous with the surface of the insulating layer 33 to form a flat surface.

[0067] Next, the surfaces of insulating layer 31 and insulating layer 33, and the surfaces of conductive layer 32 and conductive layer are brought into close contact with each other, and a bonding process is performed (see FIG. 7C).

[0068] It is preferable to make the surfaces of the insulating layer 31 and the insulating layer 33 hydrophilic and to activate the surfaces of the conductive layer 32 and the conductive layer 34 immediately before bonding. By carrying out the above-mentioned treatments on the bonding surfaces, strong adhesive strength at the atomic level can be obtained. Furthermore, a heating treatment or a pressure treatment may be carried out as necessary.

[0069] Next, a grinding / polishing tool 27 is used to grind and polish the surface of the single crystal silicon substrate 21 opposite to the first surface, thereby thinning the single crystal silicon substrate 21 (see FIG. 8A).

[0070] After the single crystal silicon substrate 21 is thinned to a desired thickness, a p + Alternatively, a region 28 having a conductivity type of the above-mentioned type may be formed (see FIG. 8B). This completes the second method.

[0071] <Variation 1> The photoelectric conversion device 101 produced by the first method or the second method may be further processed. For example, as shown in Figures 9A to 9D, the region 28 of the photoelectric conversion device 101 and the region that becomes the light absorption layer may be divided into individual pixels.

[0072] First, grooves are provided to divide the single crystal silicon substrate 21 including the regions 28 into individual pixels (see FIG. 9A). Next, an insulating layer 35 such as silicon oxide is provided on the grooves and the regions 28 (see FIG. 9B). Next, an opening 36 is provided in the insulating layer 35 to reach the regions 28 (see FIG. 9C). Then, a conductive layer 37 that is transparent to light of a target wavelength is provided on the insulating layer 35 and the opening 36 (see FIG. 9D).

[0073] The conductive layer 37 acts as a carrier extraction electrode (common electrode) of the photoelectric conversion device 101. In addition, in the pixel circuit, it also acts as the wiring 121 or a part thereof. Note that, as the conductive layer 37, in addition to a conductive oxide such as indium tin oxide, a conductive organic film, a metal mesh, a semiconductor film having the same conductivity type as the region 28, or the like can be used.

[0074] Furthermore, by providing the insulating layer 35 in the grooves provided between the pixels, stray light entering from adjacent pixels can be suppressed, making it possible to obtain a clearer image.

[0075] <Variation 2> Further components may be added to the configurations produced by the first and second methods and the configurations shown as modified examples. For example, as shown in FIG. 10A, an insulating layer 38 may be provided on the region 28 as a protective layer. The insulating layer 38 may be a silicon oxide film or the like that is transparent to light in a wide wavelength range. Alternatively, a silicon nitride film that acts as a passivation film may be laminated. Alternatively, a dielectric film such as hafnium oxide may be laminated as an anti-reflection film.

[0076] A light-shielding layer 39 may be formed on the insulating layer 38. The light-shielding layer 30 has a function of suppressing the intrusion of light from an oblique direction. The light-shielding layer 39 may be a metal layer such as aluminum or tungsten. Alternatively, the metal layer may be laminated with a dielectric film that functions as an anti-reflection film. Alternatively, a resin layer may be used instead of the metal layer.

[0077] An insulating layer 40 may be provided as a planarizing film on the insulating layer 38 and the light-shielding layer 39. As the insulating layer 40, an organic resin film or the like may be used.

[0078] Furthermore, an optical filter layer 41 may be provided on the insulating layer 40. The optical filter layer 41 may be formed by selecting a material that transmits light according to the purpose. For example, an infrared light transmitting filter may be used as the optical filter layer. By using an infrared light transmitting filter, an imaging device having sensitivity only to infrared light can be obtained.

[0079] As the infrared light transmission filter, for example, a layer formed by dispersing a material that transmits infrared light and absorbs visible light in a base material that transmits infrared light, such as glass or resin, can be used. The wavelength of the transmitted infrared light can be adjusted by appropriately selecting the material to be dispersed in the base material. For example, when the purpose is to capture an image of veins used in biometric authentication, etc., it is sufficient to select a material that transmits at least near-infrared light that is absorbed by hemoglobin.

[0080] Furthermore, a microlens array 42 may be provided so that light collected by one lens is received by one pixel. By providing the microlens array 42, light can be received efficiently even in a configuration in which the light-shielding layer 39 is provided.

[0081] 10A to 10C may be omitted, or other components may be further provided.

[0082] <Pixel circuit operation>

[0083] Next, an example of the operation of the pixel circuit shown in Fig. 2A will be described with reference to the timing chart in Fig. 11A. In the description of the timing chart in this specification, a high potential is represented by "H" and a low potential is represented by "L." It is assumed that "L" is constantly supplied to the wiring 121, and "H" is constantly supplied to the wirings 122 and 123.

[0084] In a period T1, when the potential of the wiring 126 is set to "H", the potential of the wiring 127 is set to "H", and the potential of the wiring 128 is set to "L", the transistors 103 and 104 are turned on, and the potential of the wiring 123 is supplied to the node FD at "H" (reset operation).

[0085] In a period T2, when the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "H", and the potential of the wiring 128 is set to "L", the transistor 104 becomes non-conductive and the supply of the reset potential is cut off. Also, the potential of the node FD decreases in response to the operation of the photoelectric conversion device 101 (accumulation operation).

[0086] In the period T3, when the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "L", and the potential of the wiring 128 is set to "L", the transistor 103 is turned off, and the potential of the node FD is determined and held (holding operation). At this time, by using OS transistors with low off-state current as the transistors 103 and 104 connected to the node FD, unnecessary outflow of charge from the node FD can be suppressed, and the data retention time can be extended.

[0087] In a period T4, when the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "L", and the potential of the wiring 128 is set to "H", the transistor 106 is turned on, and the potential of the node FD is read to the wiring 129 by the source follower operation of the transistor 105 (read operation).

[0088] The above is an example of the operation of the pixel circuit shown in FIG. 2A.

[0089] The pixel circuit shown in Fig. 2B can be operated according to the timing chart of Fig. 11B. Note that "H" is constantly supplied to the wirings 121 and 123, and "L" is constantly supplied to the wiring 122. The basic operation is the same as that described above with reference to the timing chart of Fig. 11A.

[0090] In one embodiment of the present invention, a transistor may have a back gate as illustrated in Fig. 12A and Fig. 12B. Fig. 12A shows a structure in which the back gate is electrically connected to the front gate, which has the effect of increasing the on-state current. Fig. 12B shows a structure in which the back gate is electrically connected to a wiring that can supply a constant potential, which allows the threshold voltage of the transistor to be controlled.

[0091] 12A and 12B may be combined so that each transistor can operate appropriately. Also, the pixel circuit may have a transistor without a back gate.

[0092] 13 is a block diagram illustrating an imaging device according to one embodiment of the present invention. The imaging device includes a pixel array 51 having pixel circuits 50 according to one embodiment of the present invention arranged in a matrix, a circuit 52 (row driver) having a function of selecting a row of the pixel array 51, a circuit 53 having a function of reading data from the pixel circuits 50, and a circuit 58 that supplies a power supply potential.

[0093] The circuit 53 may include a circuit 54 (column driver) having a function of selecting a column of the pixel array 51, a circuit 55 (CDS circuit) for performing correlated double sampling processing on the output data of the pixel circuit 50, and a circuit 56 (A / D conversion circuit, etc.) having a function of converting the analog data output from the circuit 55 into digital data.

[0094] A shift register circuit or a decoder circuit can be used for the circuits 52 and 54. Some or all of the circuits 52, 53, and 58 may be formed of OS transistors provided in the layer 13 shown in Fig. 1. Alternatively, some of the circuits 52, 53, and 58 may be formed of Si transistors provided in the layer 12.

[0095] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0096] (Embodiment 2) In this embodiment, a structural example of an imaging device according to one embodiment of the present invention will be described in detail.

[0097] Fig. 14A is a diagram illustrating an example of a cross section of a pixel that can be fabricated by the first method, and Fig. 14B is a diagram illustrating an example of a cross section of a pixel that can be fabricated by the second method.

[0098] The layer 12 includes a region 22 having n-type conductivity, a region (single crystal silicon substrate 21) having p-type conductivity, and a region (single crystal silicon substrate 22) having p-type conductivity as the photoelectric conversion device 101. +A pn junction photodiode having a region 28 having a conductivity type of a pn-type photodiode is provided in the layer 13. An OS transistor is provided in the layer 13. In Fig. 14A and Fig. 14B, transistors 103, 105, and 106 are illustrated by way of example using the circuit configuration shown in Fig. 2A. A supporting substrate 25 and the like are provided in the layer 14.

[0099] 14A shows an example in which insulating layer 24 is made up of two layers, insulating layer 63 and insulating layer 64. Insulating layer 63 may be an organic film such as an acrylic resin or polyimide. Insulating layer 64 may be an inorganic film such as a silicon oxide film.

[0100] 14B shows an example in which insulating layer 31 is made up of three layers, insulating layer 63, insulating layer 65, and insulating layer 64. In FIG.

[0101] The insulating layer 65 has a function of preventing diffusion of hydrogen, and is provided between a region where an OS transistor is formed and a region where a Si device such as the photoelectric conversion device 101 is formed. Hydrogen in the insulating layer provided near the photoelectric conversion device 101 terminates dangling bonds of silicon. On the other hand, hydrogen in the insulating layer provided near the channel formation regions of the transistors 102, 105, and 106 is one of the factors that generate carriers in the oxide semiconductor layer.

[0102] The insulating layer 65 can improve the reliability of the Si device by confining hydrogen in one layer, and can also improve the reliability of the transistors 102, 105, and 106 by suppressing the diffusion of hydrogen from one layer to the other layer.

[0103] For example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used for the insulating layer 65.

[0104] The insulating layer 65 may be provided at any other position as long as the above-mentioned effect can be obtained. For example, the insulating layer 63 and the insulating layer 65 may be interchanged.

[0105] Fig. 15A shows details of an OS transistor. The OS transistor shown in Fig. 15A has a self-aligned structure in which an insulating layer is provided over a stack of an oxide semiconductor layer and a conductive layer, and a source electrode 205 and a drain electrode 206 are formed by providing grooves that reach the semiconductor layer.

[0106] The OS transistor can have a structure including a channel formation region, a source region 203, and a drain region 204 formed in an oxide semiconductor layer 207, as well as a gate electrode 201 and a gate insulating film 202. At least the gate insulating film 202 and the gate electrode 201 are provided in the groove. An oxide semiconductor layer 208 may be further provided in the groove.

[0107] As shown in FIG. 15B, the OS transistor may have a self-aligned structure in which a source region 203 and a drain region 204 are formed in a semiconductor layer using a gate electrode 201 as a mask.

[0108] Alternatively, as shown in FIG. 15C, it may be a non-self-aligned top-gate transistor having a region where the source electrode 205 or the drain electrode 206 overlaps with the gate electrode 201.

[0109] Although the transistors 103, 105, and 106 are shown to have a structure having a back gate 535, they may have a structure not having a back gate. The back gate 535 may be electrically connected to the front gate of the transistor provided opposite to it, as shown in the cross-sectional view of the transistor in the channel width direction shown in Fig. 15D. Note that Fig. 15D shows the A1-A2 cross section of the transistor in Fig. 15A, but the same applies to other transistors. In addition, a fixed potential different from that of the front gate may be supplied to the back gate 535.

[0110] As a semiconductor material used for an OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A typical example is an oxide semiconductor containing indium, for example, CAAC-OS or CAC-OS described later can be used. CAAC-OS has stable atoms constituting the crystal, and is suitable for transistors that emphasize reliability. In addition, CAC-OS has high mobility characteristics, and is suitable for transistors that operate at high speed.

[0111] OS transistors have a large energy gap in the semiconductor layer, and therefore exhibit extremely low off-current characteristics of a few yA / μm (current value per 1 μm of channel width). OS transistors also have characteristics different from Si transistors, such as the absence of impact ionization, avalanche breakdown, and short channel effects, and can form highly reliable circuits with high voltage resistance. OS transistors are also less susceptible to variations in electrical characteristics caused by non-uniformity in crystallinity, which is a problem with Si transistors.

[0112] A semiconductor layer included in an OS transistor can be, for example, a film expressed as an In-M-Zn-based oxide containing indium, zinc, and M (metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). The In-M-Zn-based oxide can be formed by, for example, a sputtering method, an atomic layer deposition (ALD) method, or a metal organic chemical vapor deposition (MOCVD) method.

[0113] When forming a film of an In-M-Zn oxide by a sputtering method, it is preferable that the atomic ratio of the metal elements of the sputtering target satisfies In≧M and Zn≧M. As the atomic ratio of the metal elements of such a sputtering target, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. are preferable. Note that the atomic ratio of the semiconductor layer to be formed includes a variation of ±40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0114] The semiconductor layer is made of an oxide semiconductor with a low carrier density. For example, the semiconductor layer has a carrier density of 1×10 17 / cm 3 Less than or equal to 1×10 15 / cm 3 Less than 1×10, more preferably 13 / cm 3 Less than or equal to 1×10 11 / cm 3 Less than 1×10, more preferably 10 / cm 3 Less than 1 x 10 -9 / cm 3 The above oxide semiconductors can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and has stable characteristics.

[0115] Note that the composition is not limited to these, and may be appropriate depending on the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. In order to obtain the required semiconductor characteristics of the transistor, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the semiconductor layer.

[0116] When silicon or carbon, which is one of the group 14 elements, is contained in the oxide semiconductor constituting the semiconductor layer, oxygen vacancies increase and the semiconductor layer becomes n-type. For this reason, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 Less than or equal to 2×10 17 atoms / cm 3 The following applies.

[0117] In addition, when an alkali metal or an alkaline earth metal is bonded to an oxide semiconductor, carriers may be generated, which may increase the off-state current of a transistor. For this reason, the concentration of an alkali metal or an alkaline earth metal in a semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 To the following:

[0118] In addition, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons that act as carriers are generated, which increases the carrier density and makes the semiconductor layer more likely to be n-type. As a result, a transistor using an oxide semiconductor that contains nitrogen is likely to have normally-on characteristics. For this reason, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0119] Furthermore, when hydrogen is contained in an oxide semiconductor constituting a semiconductor layer, it reacts with oxygen bonded to a metal atom to form water, which may form oxygen vacancies in the oxide semiconductor. When oxygen vacancies are present in a channel formation region in an oxide semiconductor, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen has entered the oxygen vacancies may function as donors and generate electrons that serve as carriers. In addition, some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor that contains a large amount of hydrogen is likely to have normally-on characteristics.

[0120] A defect in which hydrogen has entered an oxygen vacancy can function as a donor for an oxide semiconductor. However, it is difficult to quantitatively evaluate the defect. Thus, an oxide semiconductor may be evaluated by its carrier concentration instead of its donor concentration. Thus, in this specification and the like, a carrier concentration assuming a state in which no electric field is applied may be used as a parameter of an oxide semiconductor instead of the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration".

[0121] Therefore, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0122] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS), polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors. Among non-single-crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

[0123] An oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and does not include a crystalline component, or an oxide film having an amorphous structure has, for example, a completely amorphous structure and does not include a crystalline portion.

[0124] The semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have a single layer structure or a multilayer structure including two or more of the above-mentioned regions.

[0125] The following describes the structure of a cloud-aligned composite (CAC)-OS, which is one type of non-single crystal semiconductor layer.

[0126] CAC-OS is, for example, a material in which elements constituting an oxide semiconductor are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or thereabouts. Note that, hereinafter, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal elements are mixed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or thereabouts, is also referred to as a mosaic or patch shape.

[0127] The oxide semiconductor preferably contains at least indium, particularly indium and zinc, and may further contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0128] For example, the CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS may be specifically referred to as CAC-IGZO) is an indium oxide (hereinafter, InO X1 (X1 is a real number greater than 0).) or indium zinc oxide (hereinafter, In X2 Zinc Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0.) and gallium oxide (GaO X3 (X3 is a real number greater than 0). ) or gallium zinc oxide (Ga X4 Zinc Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0).) The material is separated into a mosaic shape, and the mosaic shape of InO X1 , or In X2 Zinc Y2 O Z2 However, the structure is such that the particles are uniformly distributed in the film (hereinafter, also referred to as a cloud-like structure).

[0129] In other words, CAC-OS is X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 In this specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the first region is said to have a higher In concentration than the second region.

[0130] IGZO is a common name and may refer to a compound made of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number).

[0131] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure, where multiple IGZO nanocrystals are aligned along the c-axis and connected without being aligned in the ab plane.

[0132] On the other hand, CAC-OS is a material composition of oxide semiconductor. CAC-OS is a material composition containing In, Ga, Zn, and O, in which some regions observed as nanoparticles mainly composed of Ga and some regions observed as nanoparticles mainly composed of In are randomly distributed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0133] Note that the CAC-OS does not include a laminated structure of two or more films with different compositions, such as a two-layer structure consisting of a film mainly containing In and a film mainly containing Ga.

[0134] In addition, GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 In some cases, it may be difficult to observe a clear boundary between the region in which the main component is the

[0135] In addition, when one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. are contained instead of gallium, the CAC-OS has a configuration in which some regions observed to be in the form of nanoparticles mainly composed of the metal element and some regions observed to be in the form of nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern.

[0136] CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not intentionally heated. When CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as a deposition gas. The lower the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition, the more preferable it is, for example, 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0137] CAC-OS has the characteristic that no clear peaks are observed when it is measured using the θ / 2θ scan by the out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. In other words, the X-ray diffraction measurement shows that there is no orientation in the ab plane direction or the c axis direction in the measurement area.

[0138] In addition, in the electron beam diffraction pattern obtained by irradiating CAC-OS with an electron beam (also called nano-beam electron beam) with a probe diameter of 1 nm, a ring-shaped region of high brightness (ring region) and multiple bright spots are observed in the ring region. Therefore, the electron beam diffraction pattern shows that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar direction and cross-sectional direction.

[0139] For example, in the case of CAC-OS of In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) revealed that GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 It can be seen that the region in which the main component is the crystalline silicon is unevenly distributed and mixed.

[0140] CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed, and has different properties from IGZO compounds. X3 The main components are In X2 Zinc Y2 O Z2 , or InO X1 The structure is such that the regions having each element as the main component are separated from each other in a mosaic pattern.

[0141] Here, In X2 Zinc Y2 O Z2 , or InO X1 The area where GaO is the main component X3 This region has a higher electrical conductivity than the region where In is the main component. X2 Zinc Y2 O Z2 , or InO X1 When carriers flow through the region where In is the main component, the conductivity of the oxide semiconductor is expressed. X2 Zinc Y2 O Z2 , or InO X1 When the region mainly composed of is distributed in a cloud shape in the oxide semiconductor, high field-effect mobility (μ) can be achieved.

[0142] On the other hand, GaO X3 The region where the main components are In X2 Zinc Y2 O Z2 , or InOX1 This region has higher insulating properties than the region where GaO is the main component. X3 When a region containing these as main components is distributed in an oxide semiconductor, leakage current can be suppressed and favorable switching operation can be achieved.

[0143] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by X2 Zinc Y2 O Z2 , or InO X1 The conductivity caused by the MOSFET and the MOSFET's resistance to the MOSFET's resistance work in a complementary manner, resulting in a high on-state current (I on ), and high field-effect mobility (μ).

[0144] In addition, semiconductor devices using CAC-OS have high reliability, making CAC-OS suitable as a constituent material for various semiconductor devices.

[0145] Fig. 14A shows a configuration example in which a mechanical connection between layers 13 and 14 is achieved by a bonding technique. Also, Fig. 14B shows a configuration example in which a mechanical connection and an electrical connection between layers 12 and 13 are achieved by a bonding technique. The bonding technique will be described below using Fig. 14B as an example.

[0146] Layer 12 is provided with an insulating layer 33 and a conductive layer 34. Conductive layer 34 has a region buried in insulating layer 33. Conductive layer 34 is electrically connected to region 22. Furthermore, the surfaces of insulating layer 33 and conductive layer 34 are planarized so that they are at the same height.

[0147] The layer 13 is provided with an insulating layer 31 and a conductive layer 32. The conductive layer 32 has a region buried in the insulating layer 31. The conductive layer 32 is electrically connected to the transistor 103. The surfaces of the insulating layer 31 and the conductive layer 32 are planarized so that they are at the same height.

[0148] Here, it is preferable that the conductive layer 32 and the conductive layer 34 have the same metal element as a main component. Also, it is preferable that the surfaces of the insulating layer 31 and the insulating layer 33 are composed of the same component.

[0149] For example, Cu, Al, Sn, Zn, W, Ag, Pt, Au, or the like can be used for the conductive layers 32 and 34. Cu, Al, W, or Au is preferably used in view of ease of bonding. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used for the surfaces of the insulating layers 31 and 33.

[0150] That is, it is preferable to use the same metal material as described above for the combination of conductive layer 32 and conductive layer 34. It is also preferable to use the same insulating material as described above for each of insulating layer 31 and insulating layer 33. With this configuration, it is possible to perform bonding with the boundary between layer 12 and layer 13 as the bonding position.

[0151] This bonding makes it possible to obtain electrical connection between the conductive layer 32 and the conductive layer 34. Also, it makes it possible to obtain a connection between the insulating layer 31 and the insulating layer 33 that has sufficient mechanical strength.

[0152] To bond metal layers together, a surface activation bonding method can be used, in which oxide films and adsorbed layers of impurities on the surfaces are removed by sputtering or other methods, and cleaned and activated surfaces are brought into contact with each other to bond them. Alternatively, a diffusion bonding method can be used, in which surfaces are bonded together using a combination of temperature and pressure. Both methods involve bonding at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0153] In addition, for bonding insulating layers, a hydrophilic bonding method can be used in which high flatness is achieved by polishing, etc., and then the surfaces that have been hydrophilically treated with oxygen plasma or the like are brought into contact with each other to form a temporary bond, and then the final bond is achieved by dehydrating them through heat treatment. Hydrophilic bonding also produces bonds at the atomic level, and therefore can provide mechanically excellent bonds.

[0154] When the layers 12 and 13 are bonded to each other, since an insulating layer and a metal layer are mixed on each bonding surface, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0155] For example, a method of cleaning the surface after polishing, subjecting the surface of the metal layer to an anti-oxidation treatment, and then subjecting it to a hydrophilic treatment and bonding can be used. The surface of the metal layer may be made of a resistant metal such as Au and then subjected to a hydrophilic treatment. Note that bonding methods other than the above-mentioned methods may also be used.

[0156] An example of a package containing an image sensor chip and a camera module will be described below. The image sensor chip can have the same configuration as the imaging device described above.

[0157] 16A1 is a perspective view showing the appearance of the upper surface of a package containing an image sensor chip. The package includes a package substrate 610 for fixing an image sensor chip 650, a cover glass 620, and an adhesive 630 for bonding the two together.

[0158] 16A2 is an external perspective view of the bottom surface of the package. The bottom surface of the package has a BGA (Ball grid array) with solder balls as bumps 640. Note that the package is not limited to a BGA, and may have an LGA (Land grid array) or a PGA (Pin Grid Array), etc.

[0159] 16A3 is a perspective view of the package with a portion of the cover glass 620 and the adhesive 630 omitted. Electrode pads 660 are formed on the package substrate 610, and the electrode pads 660 and the bumps 640 are electrically connected via through holes. The electrode pads 660 are electrically connected to the image sensor chip 650 by wires 670.

[0160] 16B1 is a perspective view of the appearance of the upper surface side of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module has a package substrate 611 for fixing an image sensor chip 651, a lens cover 621, a lens 635, and the like. In addition, an IC chip 690 having functions such as a drive circuit and a signal conversion circuit of the imaging device is also provided between the package substrate 611 and the image sensor chip 651, and the camera module has a configuration as a SiP (System in package).

[0161] 16B2 is a perspective view of the exterior of the bottom surface of the camera module. The bottom surface and side surfaces of the package substrate 611 are provided with lands 641 for mounting, forming a QFN (Quad flat no-lead package) configuration. Note that this configuration is merely an example, and a QFP (Quad flat package) or the above-mentioned BGA may also be provided.

[0162] 16B3 is a perspective view of the module in which a portion of the lens cover 621 and the lens 635 is omitted. The land 641 is electrically connected to the electrode pad 661, and the electrode pad 661 is electrically connected to the image sensor chip 651 or the IC chip 690 by a wire 671.

[0163] By housing the image sensor chip in a package of the above-mentioned type, mounting on a printed circuit board or the like becomes easy, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0164] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0165] (Embodiment 3) In this embodiment, an example of an electronic device in which an imaging device according to one embodiment of the present invention can be used will be described. The imaging device according to one embodiment of the present invention can be configured to eliminate the need for an infrared light transmission filter, and can be easily thinned and easily incorporated into various devices. Note that the infrared light transmission filter may be incorporated in the optical path of the electronic device instead of being incorporated in the imaging device.

[0166] FIG. 17A shows a biometric authentication device for finger veins, and includes a housing 911, a light source 912, a detection stage 913, and the like. By placing a finger on the detection stage 913, the shape of the veins can be imaged. A light source 912 is provided above the detection stage 913, and an imaging device 914 is provided below it. The detection stage 913 is made of a material that transmits infrared light, and the infrared light that is irradiated from the light source 912 and passes through the finger can be imaged by the imaging device 914. An optical system may be provided between the detection stage 913 and the imaging device 914. The above device configuration can also be used in a biometric authentication device for palm veins.

[0167] The light source 912 can be formed of a thin EL device. The EL device can be installed in a curved shape and can irradiate light uniformly onto an object. In particular, it is preferable that the EL device emits near-infrared light having a peak wavelength of 700 nm or more and 1200 nm or less. For example, light with a wavelength of 760 nm or thereabouts is easily absorbed by hemoglobin in veins, so the position of the veins can be detected by receiving light that has passed through a finger or palm and imaging it. This effect can be used for biometric authentication. In addition, by combining it with a global shutter method, highly accurate sensing is possible even if the subject moves.

[0168] Furthermore, the light source 912 can have a plurality of light emitting units, such as light emitting units 915, 916, and 917 shown in Fig. 17B. Each of the light emitting units 915, 916, and 917 may emit light of a different wavelength, and each can be irradiated at a different timing. Therefore, by changing the wavelength and angle of the irradiated light, different images can be captured continuously, and therefore multiple images can be used for authentication, thereby achieving high security.

[0169] FIG. 17C shows a biometric authentication device for palm veins, which includes a housing 921, an operation button 922, a detection unit 923, a light source 924, and the like. The shape of the veins in the palm can be recognized by holding the hand over the detection unit 923. A personal identification number or the like can also be input using the operation button. A light source 924 is disposed around the detection unit 923 and irradiates the target object (hand). Then, the reflected light from the target object is incident on the detection unit 923. The light source 924 is formed of a thin EL device that emits near-infrared light. An imaging device 925 is disposed directly below the detection unit 923, and can capture an image of the target object (the entire image of the hand). An optical system may be provided between the detection unit 923 and the imaging device 925. The above-mentioned device configuration can also be used in a biometric authentication device for finger veins.

[0170] 18A shows a non-destructive inspection device, which includes a housing 931, an operation panel 932, a transport mechanism 933, a monitor 934, a detection unit 935, a light source 938, and the like. An inspected member 936 is transported by the transport mechanism 933 to a position directly below the detection unit 935. The inspected member 936 is irradiated with infrared light from the light source 938, and the transmitted light is captured by an imaging device 937 according to one embodiment of the present invention provided in the detection unit 935. The captured image is displayed on the monitor 934. The inspected member is then transported to the exit of the housing 931, where defective products are separated and collected. By capturing images using near-infrared light, defective elements such as defects and foreign bodies inside the inspected member can be detected non-destructively and quickly.

[0171] FIG. 18B shows a surveillance camera, which includes a housing 951, a lens 952, a light source 953, a support 954, and the like. An object irradiated with infrared light emitted from a light source 953 can be imaged by an imaging device 955 according to one embodiment of the present invention. The surveillance camera may have a structured light configuration. In structured light, a light source 953 irradiates a subject with directional light such as a line or a point, and images of the light are taken from a different angle. Since the light irradiated to the subject is distorted depending on the shape of the subject, the light is acquired as an image, and information such as the shape and depth of the subject can be obtained from the image. The surveillance camera may have a ToF (Time of Flight) sensor configuration. The ToF sensor detects the time it takes for light emitted from the light source 953 to be reflected by the subject and reach a sensor (imaging device 955). By detecting the time for each pixel of the imaging device 955, detailed information on the distance to the subject can be obtained. That is, the surface shape and number of the subject can be recognized.

[0172] FIG. 18C illustrates a mobile phone including a housing 981, a display portion 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a first camera 987, a second camera 988, and the like. The mobile phone includes a touch sensor in the display portion 982. The housing 981 and the display portion 982 are flexible. Any operation, such as making a call or inputting characters, can be performed by touching the display portion 982 with a finger, a stylus, or the like. The first camera can acquire a visible light image, and the second camera can acquire an infrared light image. The imaging device of one embodiment of the present invention can be applied to an element for acquiring an infrared light image in the mobile phone.

[0173] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes. [Explanation of symbols]

[0174] 11: layer, 12: layer, 13: layer, 14: layer, 21: single crystal silicon substrate, 22: region, 23: device formation layer, 24: insulating layer, 25: support substrate, 26: insulating layer, 27: grinding / polishing tool, 28: region, 30: light-shielding layer, 31: insulating layer, 32: conductive layer, 33: insulating layer, 34: conductive layer, 35: insulating layer, 36: opening, 37: conductive layer, 38: insulating layer, 39: light-shielding layer, 40: insulating layer, 41: optical filter layer, 42: microlens array, 50: pixel circuit, 51: pixel array, 52: circuit, 53: circuit, 54: circuit, 55: circuit Path, 56: circuit, 58: circuit, 63: insulating layer, 64: insulating layer, 65: insulating layer, 101: photoelectric conversion device, 102: transistor, 103: transistor, 104: transistor, 105: transistor, 106: transistor, 108: capacitor, 121: wiring, 122: wiring, 123: wiring, 126: wiring, 127: wiring, 128: wiring, 129: wiring, 201: gate electrode, 202: gate insulating film, 203: source region, 204: drain region, 205: source electrode, 206: drain electrode, 207: oxide semiconductor layer, 208: oxide semiconductor layer, 535: back gate, 610: package substrate, 611: package substrate, 620: cover glass, 621: lens cover, 630: adhesive, 635: lens, 640: bump, 641: land, 650: image sensor chip, 651: image sensor chip, 660: electrode pad, 661: electrode pad, 670: wire, 671: wire, 690: IC chip, 911: housing, 912: light source, 913: detection stage, 914: imaging device, 915: light emitting section, 916: light emitting section Light unit, 917: light emitting unit, 921: housing, 922: operation button, 923: detection unit, 924: light source, 925: imaging device, 931: housing, 932: operation panel, 933: transport mechanism, 934: monitor, 935: detection unit, 936: inspected member, 937: imaging device, 938: light source, 951: housing, 952: lens, 953: light source, 954: support unit, 955: imaging device, 981: housing, 982: display unit, 983: operation button, 984: external connection port, 985: speaker, 986: microphone, 987: camera, 988: camera

Claims

1. A first layer having an optical filter layer; a second layer having a photovoltaic device; and a third layer having circuitry electrically connected to the photovoltaic device; the first layer is located above the second layer; the second layer is located above the third layer; an insulating layer having an opening above the photoelectric conversion device; a light-transmitting conductive layer is provided above the insulating layer and above the opening; the light-transmitting conductive layer is located below the first layer, and has a function as an electrode of the photoelectric conversion device and a function as a wiring of the circuit.

2. A first layer having an optical filter layer; a second layer having a photovoltaic device; and a third layer having circuitry electrically connected to the photovoltaic device; the first layer is located above the second layer; the second layer is located above the third layer; an insulating layer having an opening above the photoelectric conversion device; a light-transmitting conductive layer is provided above the insulating layer and above the opening; the light-transmitting conductive layer is located below the first layer and has a function as an electrode of the photoelectric conversion device and a function as wiring of the circuit; the circuit includes first to third transistors and a capacitor; one electrode of the photoelectric conversion device is electrically connected to one of the source and drain of the first transistor; the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor; one of a source and a drain of the second transistor is electrically connected to one electrode of the capacitor; an electrode of the capacitor electrically connected to a gate of the third transistor;

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