Output circuit, photoelectric conversion device, photoelectric conversion system and electronic apparatus

Abstract

To provide a technique advantageous to suppress voltage fluctuation on a power line.SOLUTION: An output circuit outputs an amplitude modulation signal having a voltage value chosen from voltage values of three or more. The output circuit includes a differential circuit arranged between a first power line and a second power line, a switch and a resistor connected in series so as to configure a path connecting the first power line and the second power line, the differential circuit includes a first differential output circuit having a first positive side output terminal and a first negative side output terminal, a second differential output circuit having a second positive side output terminal and a second negative side output terminal, a first output line for connecting the first positive side output terminal and the second positive side output terminal, and a second output line for connecting the first negative side output terminal and the second negative side output terminal, the amplitude modulation signal is outputted with the first output line and the second output line, the switch and the resistor suppress change of current value flowing between the first power line and the second power line due to operation state change of the differential circuit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an output circuit, a photoelectric conversion device, a photoelectric conversion system, and an electronic device. [Background technology]

[0002] There is a standard called PAM4 as one of the transmission methods for transmitting multi-value voltage signals. In PAM4, information is transmitted using four voltage values ​​corresponding to 00, 01, 10, and 11. Patent Document 1 describes an output circuit (transmitter) that can be applied to PAM4. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Publication No. 2016-0352315 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the configuration of the transmitter described in Patent Document 1, the current supplied from the power line varies according to the voltage value output by the transmitter, which may cause the potential of the power line to vary. This may lead to deterioration of the eye pattern of the output signal of the transmitter. To suppress this, a bypass capacitor (capacitor) with a large capacity may be connected to the power line, but this leads to an increase in the circuit area and an increase in costs.

[0005] An object of the present invention is to provide an advantageous technique for suppressing fluctuations in the potential of a power supply line. [Means for solving the problem]

[0006] One aspect of the present invention relates to an output circuit that outputs an amplitude modulated signal having a voltage value selected from three or more voltage values, the output circuit including a differential circuit arranged between a first power supply line and a second power supply line, and a switch and a resistor connected in series to form a path connecting the first power supply line and the second power supply line, the differential circuit including a first differential output circuit having a first positive output terminal and a first negative output terminal, a second differential output circuit having a second positive output terminal and a second negative output terminal, a first output line connecting the first positive output terminal and the second positive output terminal, and a second output line connecting the first negative output terminal and the second negative output terminal, the amplitude modulated signal is output by the first output line and the second output line, and the switch and the resistor suppress changes in the value of a current flowing between the first power supply line and the second power supply line due to changes in an operating state of the differential circuit. Effect of the Invention

[0007] According to the present invention, an advantageous technique for suppressing fluctuations in the potential of a power supply line is provided. [Brief description of the drawings]

[0008] [Figure 1] FIG. 2 is a diagram showing the configuration of an output circuit according to the first embodiment. [Diagram 2] FIG. 4 is a diagram for explaining the operation of the output circuit according to the first embodiment. [Diagram 3] FIG. 4 is a diagram for explaining the operation of the output circuit according to the first embodiment. [Figure 4] FIG. 4 is a diagram for explaining the operation of the output circuit according to the first embodiment. [Diagram 5] FIG. 4 is a diagram for explaining the operation of the output circuit according to the first embodiment. [Figure 6] FIG. 2 is a diagram showing the configuration of an output circuit according to the first embodiment. [Figure 7] FIG. 4 is a diagram showing a modified example of the output circuit according to the first embodiment. [Figure 8] FIG. 11 is a diagram showing the configuration of an output circuit according to a second embodiment. [Figure 9] FIG. 13 is a diagram showing a modified example of the output circuit according to the second embodiment. [Figure 10] FIG. 11 is a diagram for explaining the operation of the output circuit according to the second embodiment. [Figure 11] FIG. 11 is a diagram for explaining the operation of the output circuit according to the second embodiment. [Figure 12] FIG. 13 is a diagram showing the configuration of an output circuit according to a third embodiment. [Figure 13] 1A to 1C are diagrams illustrating a photoelectric conversion device, a photoelectric conversion system, and an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0010] FIG. 1 shows a configuration of an output circuit 100 of the first embodiment. The output circuit 100 can be understood as a transmitter or a differential signal output circuit. The output circuit 100 can be configured to output an amplitude modulated signal having a voltage value selected from any number of voltage values ​​equal to or greater than three (e.g., 4, 6, 8, etc.). In the example shown in FIG. 1, the output circuit 100 outputs an amplitude modulated signal having a voltage value selected from four voltage values. The amplitude modulated signal having a voltage value selected from the four voltage values ​​can transmit two bits of information (i.e., 00, 01, 10, 11). The four voltage values ​​can be assigned, for example, to a negative large amplitude value, a negative small amplitude value, a positive small amplitude value, and a positive small amplitude value. Here, the large amplitude value and the small amplitude value are relative expressions, and the absolute value of the large amplitude value is greater than the absolute value of the small amplitude value.

[0011] The output circuit 100 may include a differential circuit DC arranged between the first power supply line VS1 and the second power supply line VS2, and a switch S3 and a resistor R3 connected in series to configure (at least a part of) a path 30 connecting the first power supply line VS1 and the second power supply line VS2. Here, the resistor R3 may be arranged between the switch S3 and the second power supply line VS2, or the resistor R3 may be arranged between the switch S3 and the first power supply line VS1. A predetermined voltage is supplied between the first power supply line VS1 and the second power supply line VS2. Here, the potential of the first power supply line VS1 is higher than the potential of the second power supply line VS2. The second power supply line VS2 may be grounded, in which case the second power supply line VS2 is a ground line.

[0012] The differential circuit DC may include a first differential output circuit 10 having a first positive output terminal P1 and a first negative output terminal N1, and a second differential output circuit 20 having a second positive output terminal P2 and a second negative output terminal N2. The differential circuit DC may also include a first output line OUT1 connecting the first positive output terminal P1 and the second positive output terminal P2, and a second output line OUT2 connecting the first negative output terminal N1 and the second negative output terminal N2. An amplitude modulated signal is output as an output of the output circuit 100 by the first output line OUT1 and the second output line OUT2.

[0013] The switch S3 and resistor R3 arranged in the path 30 suppress a change in the value of the current flowing between the first power supply line VS1 and the second power supply line VS2 due to a change in the operating state of the differential circuit DC (a change in the voltage value output from the differential circuit DC). Preferably, the switch S3 and resistor R3 maintain the value of the current flowing between the first power supply line VS1 and the second power supply line VS2 at a constant value or within a predetermined tolerance range, regardless of a change in the operating state of the differential circuit DC (a change in the output voltage value). The operating state of the differential circuit DC may include a first state in which the first differential output circuit 10 and the second differential output circuit 20 drive the load R0 connected between the first output line OUT1 and the second output line OUT2, and a second state in which only the first differential output circuit 10 drives the load R0. The switch S3 may be controlled to be conductive in the second state. It is preferable that the value of the current flowing between the first power supply line VS1 and the second power supply line VS2 through the differential circuit DC in the first state is equal to the value of the current flowing between the first power supply line VS1 and the second power supply line VS2 through the differential circuit DC and path 30 in the second state.

[0014] The first differential output circuit 10 can operate when the output circuit 100 or the differential circuit DC outputs a voltage with a large amplitude on the negative or positive side between the first output line OUT1 and the second output line OUT2. The first differential output circuit 10 can also operate when the output circuit 100 or the differential circuit DC outputs a voltage with a small amplitude on the negative or positive side between the first output line OUT1 and the second output line OUT2. The operation of the first differential output circuit 10 means that the first differential output circuit 10 supplies a current between the first output line OUT1 and the second output line OUT2. Alternatively, the operation of the first differential output circuit 10 means that a substantial current flows from the first power supply line VS1 to the second power supply line VS2 through the first differential output circuit 10. The substantial current is a current whose value has a significant difference from the value of an unintended current such as a through current.

[0015] The second differential output circuit 20 may operate when the output circuit 100 or the differential circuit DC outputs a voltage with a large amplitude on the negative or positive side between the first output line OUT1 and the second output line OUT2. However, the second differential output circuit 20 may stop operating when the output circuit 100 or the differential circuit DC outputs a voltage with a small amplitude on the negative or positive side between the first output line OUT1 and the second output line OUT2. The operation of the second differential output circuit 20 means that the second differential output circuit 20 supplies a current between the first output line OUT1 and the second output line OUT2. Alternatively, the operation of the second differential output circuit 20 means that a substantial current flows from the first power supply line VS1 to the second power supply line VS2 through the second differential output circuit 20.

[0016] The first differential output circuit 10 may include an eleventh resistor element R11 arranged between the first power supply line VS1 and the first positive output terminal P1. The first differential output circuit 10 may also include an eleventh switch element S11 arranged between the eleventh resistor element R11 and the first positive output terminal P1, and a twelfth switch element S12 arranged between the eleventh resistor element R11 and the first negative output terminal N1. The first differential output circuit 10 may also include a twelfth resistor element R12 arranged between the second power supply line VS2 and the first negative output terminal N1. The first differential output circuit 10 may also include a thirteenth switch element S13 arranged between the twelfth resistor element R12 and the first positive output terminal P1, and a fourteenth switch element S14 arranged between the twelfth resistor element R12 and the first negative output terminal N1.

[0017] The second differential output circuit 20 may include a 21st resistor element R21 arranged between the first power supply line VS1 and the second positive output terminal P2. The second differential output circuit 20 may also include a 21st switch element S21 arranged between the 21st resistor element R21 and the second positive output terminal P2, and a 22nd switch element S22 arranged between the 21st resistor element R21 and the second negative output terminal N2. The second differential output circuit 20 may also include a 22nd resistor element R22 arranged between the second power supply line VS2 and the second positive output terminal P2. The second differential output circuit 20 may also include a 23rd switch element S23 arranged between the 22nd resistor element R22 and the second positive output terminal P2, and a 24th switch element S24 arranged between the 22nd resistor element R22 and the second negative output terminal N2.

[0018] The numerical value of xx in the xxth resistor element is for distinguishing a plurality of resistor elements from one another, and the numerical value itself has no other meaning. Similarly, the numerical value of xx in the xxth switch element is for distinguishing a plurality of switch elements from one another, and the numerical value itself has no other meaning. The above switch element may be composed of a transistor such as a MOS transistor. The transistor may be a P-type or an N-type, or both may be mixed as long as there is no contradiction in operation.

[0019] The first output line OUT1 and the second output line OUT2 can be connected to a first input terminal and a second input terminal of a receiver (receiving circuit), respectively. R0 in FIG. 1 is a load between the first input terminal and the second input terminal of the receiver (receiving circuit).

[0020] The output circuit 100 may further include a capacitor C1 disposed between the first power supply line VS1 and the second power supply line VS2. The capacitor C1 functions to smooth the voltage between the first power supply line VS1 and the second power supply line VS2, i.e., the power supply voltage. The capacitor C1 may be called a decoupling capacitor. It is advantageous to include a switch S3 and a resistor R3 connected in series to the path 30 in order to reduce the capacitance value required for the capacitor C1.

[0021] The output circuit 100 may further include a control circuit CNT that controls the differential circuit DC and the switch S3. The control circuit CNT controls each switch element of the differential circuit DC and the switch S3 of the path 30 according to the voltage values ​​(in this example, a positive large amplitude value, a negative large amplitude value, a positive small amplitude value, and a negative small amplitude value) that the output circuit 100 should output.

[0022] Hereinafter, with reference to FIG. 2, FIG. 3, FIG. 4, and FIG. 5, the control of each switch element of the differential circuit DC and the switch S3 of the path 30 by the control circuit CNT when the output circuit 100 outputs a positive large amplitude value, a negative large amplitude value, a positive small amplitude value, and a negative small amplitude value will be described by way of example. Here, as an example, the potential of the first power supply line VS1 (potential difference between the first power supply line VS1 and the second power supply line VS2) is 0.5V. Also, the resistance values ​​of R11 and R12 are 200Ω, the resistance values ​​of R21 and R22 are 40Ω, the resistance value of R3 is 250Ω, and the resistance value of R0 is 100Ω. Also, in FIG. 2, FIG. 3, FIG. 4, and FIG. 5, the thick gray lines indicate the current paths. The positive large amplitude value is +300mV, the negative large amplitude value is -300mV, the positive small amplitude value is +100mV, and the negative small amplitude value is -100mV.

[0023] FIG. 2 shows a schematic operation of the output circuit 100 outputting a positive large amplitude value (+300 mV). The control circuit CNT turns on (conducts) the switch elements S11, S14, S21, and S24, and turns off (non-conducts) the switch elements S12, S13, S22, S23, and the switch S3. The combined resistance between the first power supply line VS1 and the first output line OUT1 is 33 Ω, and the combined resistance between the second power supply line VS2 and the second output line OUT2 is 33 Ω. Therefore, the combined resistance between the first power supply line VS1 and the second power supply line VS2 is 166 Ω. A current of 3 mA flows from the first output line OUT1 to the second output line OUT2 in the load R0, and a voltage of +300 mV appears across the load R0. In addition, since the switch S3 is off, no current flows through the path 30. Therefore, a current of 3 mA flows from the first power supply line VS1 to the second power supply line VS1.

[0024] FIG. 3 shows a schematic operation of the output circuit 100 outputting a negative large amplitude value (−300 mV). The control circuit CNT turns on (conducts) the switch elements S12, S13, S22, and S23, and turns off (non-conducts) the switch elements S11, S14, S21, and S24 and the switch S3. The combined resistance between the first power supply line VS1 and the first output line OUT1 is 33Ω, and the combined resistance between the second power supply line VS2 and the second output line OUT2 is 33Ω. Therefore, the combined resistance between the first power supply line VS1 and the second power supply line VS2 is 166Ω. A current of 3 mA flows from the second output line OUT2 to the first output line OUT1 in the load R0, and a voltage of −300 mV appears across the load R0. In addition, since the switch S3 is off, no current flows through the path 30. Therefore, a current of 3 mA flows from the first power supply line VS1 to the second power supply line VS1.

[0025] FIG. 4 shows a schematic operation of the output circuit 100 outputting a positive small amplitude value (+100 mV). The control circuit CNT turns on (conducts) the switch elements S11, S14 and the switch S3, and turns off (non-conducts) the switch elements S12, S13, S21, S22, S23, and S24. The resistance between the first power supply line VS1 and the first output line OUT1 is 200Ω, and the resistance between the second power supply line VS2 and the second output line OUT2 is 200Ω. Therefore, the combined resistance between the first power supply line VS1 and the second power supply line VS2 is 500Ω. A current of 1 mA flows through the load R0 from the first output line OUT1 to the second output line OUT2, and a voltage of +100 mV appears across the load R0. In addition, a current of 2 mA flows through the path 30 from the first power supply line VS1 to the second power supply line VS1 through the switch S3 and the resistor R3. Therefore, a total current of 3 mA flows from the first power supply line VS1 to the second power supply line VS1.

[0026] FIG. 5 shows a schematic operation of the output circuit 100 outputting a negative small amplitude value (-100 mV). The control circuit CNT turns on (conducts) the switch elements S12, S13 and the switch S3, and turns off (non-conducts) the switch elements S11, S14, S21, S22, S23, and S24. The resistance between the first power supply line VS1 and the first output line OUT1 is 200 Ω, and the resistance between the second power supply line VS2 and the second output line OUT2 is 200 Ω. Therefore, the combined resistance between the first power supply line VS1 and the second power supply line VS2 is 500 Ω. A current of 1 mA flows from the second output line OUT2 to the first output line OUT1 in the load R0, and a voltage of -100 mV appears across the load R0. In addition, a current of 2 mA flows from the first power supply line VS1 to the second power supply line VS1 in the path 30 through the switch S3 and the resistor R3. Therefore, a total current of 3 mA flows from the first power supply line VS1 to the second power supply line VS1.

[0027] As described above, according to the first embodiment, regardless of the voltage value (in this example, the positive large amplitude value, the negative large amplitude value, the positive small amplitude value, and the negative small amplitude value) that the output circuit 100 should output, a current of 3 mA always flows from the first power supply line VS1 to the second power supply line VS1. This makes it possible to maintain the potential of the first power supply line VS1 (the potential difference between the first power supply line VS1 and the second power supply line VS2) constant. This is advantageous for reducing the capacitance value required for the capacitor C1. Reducing the capacitance value required for the capacitor C1 is advantageous for reducing the circuit area and reducing costs.

[0028] As illustrated in FIG. 6, the output circuit 100 may further include an ESD protection circuit 60 that protects the differential circuit DC. The ESD protection circuit 60 may include diodes D1, D2, D3, and D4. The anode of the diode D1 may be connected to the first output line OUT1, and the cathode of the diode D1 may be connected to the first power supply line VS1. The anode of the diode D2 may be connected to the second output line OUT2, and the cathode of the diode D2 may be connected to the first power supply line VS1. The anode of the diode D3 may be connected to the second power supply line VS2, and the cathode of the diode D3 may be connected to the first output line OUT1. The anode of the diode D4 may be connected to the second power supply line VS2, and the cathode of the diode D4 may be connected to the second output line OUT2. By providing the ESD protection circuit 60, the switch elements connected to the first output line OUT1 and the second output line OUT2 can be protected from ESD.

[0029] 7 shows an output circuit 100 according to a modification of the first embodiment. The differential circuit DC of the output circuit 100 may include one or more differential output circuits 20' in addition to the first differential output circuit 10 and the second differential output circuit 20. The differential output circuit 20' may have a similar configuration to the first differential output circuit 10 or the second differential output circuit 20. The addition of the differential output circuit 20' makes it possible to generate an amplitude modulated signal with more multiple values.

[0030] FIG. 8 shows the configuration of the output circuit 100 of the second embodiment. Matters not mentioned regarding the configuration and operation of the output circuit 100 of the second embodiment may follow the first embodiment. As illustrated in FIG. 8, the path 30 may be arranged to connect the 21st resistor element R21 and the 22nd resistor element R22. In other words, the switch S3 and the resistor R3 may be arranged to connect the 21st resistor element R21 and the 22nd resistor element R22. Here, the resistor R3 may be arranged between the switch S3 and the 21st resistor element R21, or the resistor R3 may be arranged between the switch S3 and the 22nd resistor element R22.

[0031] As illustrated in FIG. 8, the output circuit 100 may further include a disconnecting section 50 that disconnects the second differential output circuit 20 from the first differential output circuit 10 (or the first output line OUT1 and the second output line OUT2). The disconnecting section 50 may be controlled by a control circuit CNT. The control section CNT may control the disconnecting section 50 so that the second differential output circuit 20 is disconnected from the first differential output circuit 10 (or the first output line OUT1 and the second output line OUT2) during a period in which the second differential output circuit 20 is not operated. The control section CNT may control the disconnecting section 50 so that the second differential output circuit 20 is connected to the first differential output circuit 10 (or the first output line OUT1 and the second output line OUT2) during a period in which the second differential output circuit 20 is operated. The disconnection section 50 may include a first switch S51 arranged on the first output line OUT1 so as to be able to disconnect the second differential output circuit 20 from the first differential output circuit 10, and a second switch S52 arranged on the second output line OUT2 so as to be able to disconnect the second differential output circuit 20 from the first differential output circuit 10.

[0032] The output circuit 100 may further include a current path 40 provided in parallel with a load R0 connected between the first output line OUT1 and the second output line OUT2. A third switch S4 and a third resistor R4 may be arranged in series in the current path 40. The third switch S4 may be controlled by a control circuit CNT. The current path 40 may function to adjust the width of a small amplitude, for example, according to the ratio between the resistance value of the load R0 and the resistance value of the third resistor R4 when the amplitude is small.

[0033] FIG. 9 shows a configuration of a modified example of the output circuit 100 of the second embodiment shown in FIG. 8. In the modified example shown in FIG. 9, the first switch S51 is arranged between the node connecting the 21st switch element S21 and the 22nd switch element S22 and the 21st resistor element R21. Also, the second switch S52 is arranged between the node connecting the 23rd switch element S23 and the 24th switch element S24 and the 22nd resistor element R22. The first switch S51 and the second switch S52 disconnect the second differential output circuit 20 from the first differential output circuit 10 (or the first output line OUT1 and the second output line OUT2) by stopping the operation of the second differential output circuit 20. Alternatively, the first switch S51 and the second switch S52 may be simply understood as a circuit that stops the operation of the second differential output circuit 20. The path 30 may be arranged to connect the 21st resistor element R21 and the 22nd resistor element R22.

[0034] Hereinafter, with reference to FIG. 10 and FIG. 11, the control of each switch element of the differential circuit DC by the control circuit CNT and the switch S3 of the path 30 when the output circuit 100 outputs a positive large amplitude value, a negative large amplitude value, a positive small amplitude value, and a negative small amplitude value will be described by way of example. Here, as an example, the potential of the first power supply line VS1 (potential difference between the first power supply line VS1 and the second power supply line VS2) is 0.5V. The resistance values ​​of R11 and R12 are 100Ω, the resistance values ​​of R21 and R22 are 50Ω, the resistance value of R0 is 100Ω, the resistance value of R3 is 400Ω, and the resistance value of R4 is 100Ω. The positive large amplitude value is +300mV, the negative large amplitude value is -300mV, the positive small amplitude value is +100mV, and the negative small amplitude value is -100mV.

[0035] FIG. 10 shows a schematic operation of the output circuit 100 to output a positive or negative large amplitude value (+300 mV or -300 mV). When the output circuit 100 outputs a positive large amplitude value (+300 mV), the control circuit CNT turns on the switch elements S11, S14, S21, S24, and the switches S51 and S52, and turns off the switch elements S12, S13, S22, S23, and the switches S3 and S4. This operation is the same as the operation shown in FIG. 2. When the output circuit 100 outputs a negative large amplitude value (-300 mV), the control circuit CNT turns on the switch elements S12, S13, S22, S23, and the switches S51 and S52, and turns off the switch elements S11, S14, S21, S24, and the switches S3 and S4. This operation is the same as the operation shown in FIG. 3.

[0036] 11 shows a schematic diagram of the operation of the output circuit 100 to output a positive or negative small amplitude value (+100 mV or -100 mV). When the output circuit 100 outputs a positive small amplitude value (+100 mV), the control circuit CNT turns on the switch elements S11, S14, S21, S24, S3, and S4, and turns off the switch elements S12, S13, S22, S23, S51, and S52. The voltages appearing across the load R0 and the current flowing from the first power line VS1 to the second power line VS2 are the same as those shown in FIG. 4. On the other hand, when the output circuit 100 outputs a negative small amplitude value (-100mV), the control circuit CNT turns on the switch elements S12, S13, S22, S23, S3, and S4, and turns off the switch elements S11, S14, S21, S24, S51, and S52. The voltages appearing across the load R0 and the current flowing from the first power line VS1 to the second power line VS2 are the same as those in the operation shown in FIG.

[0037] FIG. 12 shows the configuration of the output circuit 100 of the third embodiment. Matters not mentioned regarding the configuration and operation of the output circuit 100 of the third embodiment may follow the first embodiment. As in the first embodiment, the output circuit 100 of the third embodiment may include a differential circuit DC arranged between the first power supply line VS1 and the second power supply line VS2, and a switch S3 and a resistor R3 connected in series to a path 30 connecting the first power supply line VS1 and the second power supply line VS2. Here, the resistor R3 may be arranged between the switch S3 and the second power supply line VS2, or the resistor R3 may be arranged between the switch S3 and the first power supply line VS1.

[0038] The differential circuit DC may include a first differential output circuit 10 having a first positive output terminal P1 and a first negative output terminal N1, and a second differential output circuit 20 having a second positive output terminal P2 and a second negative output terminal N2. The differential circuit DC may also include a first output line OUT1 connecting the first positive output terminal P1 and the second positive output terminal P2, and a second output line OUT2 connecting the first negative output terminal N1 and the second negative output terminal N2. An amplitude modulated signal is output as an output of the output circuit 100 by the first output line OUT1 and the second output line OUT2.

[0039] The configuration of the first differential output circuit 10 and the first differential output circuit 10 of the third embodiment is different from the configuration of the first differential output circuit 10 and the first differential output circuit 10 of the first embodiment. However, the output circuit 100 of the third embodiment can operate in the same manner as the output circuit 100 of the first embodiment. The 11th resistor element R11 of the first embodiment is replaced with the 101st resistor element R101 and the 111th resistor element R111, and the 12th resistor element R12 of the first embodiment is replaced with the 102nd resistor element R102 and the 112th resistor element R112. In addition, the 21st resistor element R21 of the first embodiment is replaced with the 201st resistor element R201 and the 211th resistor element R211, and the 22nd resistor element R22 of the first embodiment is replaced with the 202nd resistor element R202 and the 212th resistor element R212.

[0040] The 101st resistor element R101 and the 111th resistor element R111 may have a resistance value equal to that of the 11th resistor element R11. The 102nd resistor element R102 and the 112th resistor element R112 may have a resistance value equal to that of the 12th resistor element R12. The 201st resistor element R201 and the 211th resistor element R211 may have a resistance value equal to that of the 21st resistor element R21. The 202nd resistor element R202 and the 212th resistor element R212 may have a resistance value equal to that of the 22nd resistor element R22.

[0041] The first differential output circuit 10 may include an eleventh switch element S11 arranged between the first power supply line VS1 and the first positive output terminal P1, and a twelfth switch element S12 arranged between the first power supply line VS1 and the first negative output terminal N1. The first differential output circuit 10 may also include a 101st resistor element R101 arranged between the eleventh switch element S11 and the first positive output terminal P1, and a 111th resistor element R111 arranged between the twelfth switch element S12 and the first negative output terminal N1. The first differential output circuit 10 may also include a thirteenth switch element S13 arranged between the second power supply line VS2 and the first positive output terminal P1, and a fourteenth switch element S14 arranged between the second power supply line VS2 and the first negative output terminal N1. The first differential output circuit 10 may also include a 102nd resistor element R102 arranged between the 13th switch element S13 and the first positive side output terminal P1, and a 112th resistor element R112 arranged between the 14th switch element S14 and the first negative side output terminal N1.

[0042] The second differential output circuit 20 may include a 21st switch element S21 arranged between the first power supply line VS1 and the second positive output terminal P2, and a 22nd switch element S22 arranged between the first power supply line VS1 and the second negative output terminal N2. The second differential output circuit 20 may also include a 201st resistor element R201 arranged between the 21st switch element S21 and the second positive output terminal P2, and a 211th resistor element R211 arranged between the 22nd switch element S22 and the second negative output terminal N2. The second differential output circuit 20 may also include a 23rd switch element S23 arranged between the second power supply line VS2 and the second positive output terminal P2, and a 24th switch element S24 arranged between the second power supply line VS2 and the second negative output terminal N2. The second differential output circuit 20 may also include a 202 resistor element R202 arranged between the 23rd switch element S23 and the second positive side output terminal P2, and a 212 resistor element R212 arranged between the 24th switch element S24 and the second negative side output terminal N2.

[0043] In the third embodiment, since a resistive element is disposed between the output lines OUT1 and OUT2 and the switch element, this is advantageous for improving ESD resistance. Of course, an ESD protection circuit 60 may be provided in the same manner as in the first embodiment.

[0044] FIG. 13 shows a photoelectric conversion system SYS according to an application example of the output circuit 100 typified by the first to third embodiments. The photoelectric conversion system SYS may be understood as an example of an electronic device to which the output circuit 100 is applied. The photoelectric conversion system SYS may include a photoelectric conversion device 200. The photoelectric conversion device 200 may include a pixel array 210 having a plurality of pixels, and a signal processing unit 220 including an AD conversion unit that converts an analog signal output from the pixel array 210 into a digital signal. The photoelectric conversion device 200 may also include an output unit 230 configured to output an amplitude modulated signal having a voltage value selected from three or more voltage values ​​based on a signal output from the signal processing unit 220. The output unit 230 may have a configuration similar to that of the output circuit 100 typified by the first to third embodiments. The photoelectric conversion system SYS may include a processor 300 (second device) that processes a signal output by the photoelectric conversion device 200. The photoelectric conversion device 200 may be replaced with another device (first device) having the output unit 230.

[0045] The present disclosure includes the following disclosures. (Item 1) An output circuit that outputs an amplitude modulated signal having a voltage value selected from three or more voltage values, a differential circuit disposed between the first power supply line and the second power supply line; a switch and a resistor connected in series to configure a path connecting the first power supply line and the second power supply line; The differential circuit comprises: a first differential output circuit having a first positive output terminal and a first negative output terminal; a second differential output circuit having a second positive output terminal and a second negative output terminal; a first output line connecting the first positive output terminal and the second positive output terminal; a second output line connecting the first negative output terminal and the second negative output terminal, the amplitude modulated signal being output by the first output line and the second output line; the switch and the resistor suppress a change in a value of a current flowing between the first power supply line and the second power supply line due to a change in an operating state of the differential circuit. 2. An output circuit comprising: (Item 2) The operating state of the differential circuit is a first state in which the first differential output circuit and the second differential output circuit drive a load connected between the first output line and the second output line; and a second state in which only the first differential output circuit drives the load. 2. The output circuit according to item 1, (Item 3) The switch is conductive in the second state. 3. The output circuit according to item 2, (Item 4) a value of a current flowing between the first power supply line and the second power supply line through the differential circuit in the first state is equal to a value of a current flowing between the first power supply line and the second power supply line through the differential circuit and the path in the second state; 4. The output circuit according to item 3, (Item 5) a disconnection unit that disconnects the second differential output circuit from the first differential output circuit, 2. The output circuit according to item 1, (Item 6) The cutting portion is a first switch arranged on the first output line so as to be able to disconnect the second differential output circuit from the first differential output circuit; a second switch arranged on the second output line so as to be able to disconnect the second differential output circuit from the first differential output circuit; 6. The output circuit according to item 5, (Item 7) a current path provided in parallel with a load connected between the first output line and the second output line, a third switch and a third resistor are arranged in series in the current path; 7. The output circuit according to item 5 or 6, (Item 8) further comprising a capacitor disposed between the first power line and the second power line; 8. An output circuit according to any one of items 1 to 7, (Item 9) Further comprising an ESD protection circuit for protecting the differential circuit. 9. An output circuit according to any one of items 1 to 8, (Item 10) the first differential output circuit includes an eleventh resistor element arranged between the first power supply line and the first positive output terminal, an eleventh switch element arranged between the eleventh resistor element and the first positive output terminal, a twelfth switch element arranged between the eleventh resistor element and the first negative output terminal, a twelfth resistor element arranged between the second power supply line and the first positive output terminal, a thirteenth switch element arranged between the twelfth resistor element and the first positive output terminal, and a fourteenth switch element arranged between the twelfth resistor element and the first negative output terminal, the second differential output circuit includes a 21st resistor element arranged between the first power supply line and the second positive output terminal, a 21st switch element arranged between the 21st resistor element and the second positive output terminal, a 22nd switch element arranged between the 21st resistor element and the second negative output terminal, a 22nd resistor element arranged between the second power supply line and the second negative output terminal, a 23rd switch element arranged between the 22nd resistor element and the second positive output terminal, and a 24th switch element arranged between the 22nd resistor element and the second negative output terminal, 10. An output circuit according to any one of items 1 to 9, (Item 11) the path is arranged to connect the 21st resistor element and the 22nd resistor element. 11. The output circuit according to item 10, (Item 12) a first switch disposed between a node connecting the 21st switch element and the 22nd switch element and the 21st resistor element; a second switch disposed between a node connecting the 23rd switch element and the 24th switch element and the 22nd resistor element; 11. The output circuit according to item 10, further comprising: (Item 13) the path is arranged to connect the 21st resistor element and the 22nd resistor element. 13. The output circuit according to item 12, (Item 14) the first differential output circuit includes an 11th switch element arranged between the first power supply line and the first positive output terminal, a 12th switch element arranged between the first power supply line and the first negative output terminal, a 101st resistor element arranged between the 11th switch element and the first positive output terminal, a 111th resistor element arranged between the 12th switch element and the first negative output terminal, a 13th switch element arranged between the second power supply line and the first positive output terminal, a 14th switch element arranged between the second power supply line and the first negative output terminal, a 102nd resistor element arranged between the 13th switch element and the first positive output terminal, and a 112th resistor element arranged between the 14th switch element and the first negative output terminal, the second differential output circuit includes a 21st switch element arranged between the first power supply line and the second positive output terminal, a 22nd switch element arranged between the first power supply line and the second negative output terminal, a 201st resistor element arranged between the 21st switch element and the second positive output terminal, a 211th resistor element arranged between the 22nd switch element and the second negative output terminal, a 23rd switch element arranged between the second power supply line and the second positive output terminal, a 24th switch element arranged between the second power supply line and the second negative output terminal, a 202nd resistor element arranged between the 23rd switch element and the second positive output terminal, and a 212th resistor element arranged between the 24th switch element and the second negative output terminal. 10. An output circuit according to any one of items 1 to 9, (Item 15) A control circuit for controlling the differential circuit and the switch is further provided. 15. An output circuit according to any one of items 1 to 14, (Item 16) a pixel array having a plurality of pixels; a signal processing unit including an AD conversion unit that converts an analog signal output from the pixel array into a digital signal; An output circuit according to any one of claims 1 to 15, configured to output an amplitude modulated signal having a voltage value selected from three or more voltage values ​​based on a signal output from the signal processing unit; A photoelectric conversion device comprising: (Item 17) The photoelectric conversion device according to any one of items 1 to 16, A processor for processing a signal output by the photoelectric conversion device; A photoelectric conversion system comprising: (Item 18) 16. An electronic device comprising the output circuit according to any one of items 1 to 15.

[0046] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0047] DC: differential circuit, R3: resistor, S3: switch, VS1: first power supply line, VS2: second power supply line, OUT1: first output line, OUT2: second output line, P1: first positive output terminal, P2: second positive output terminal, N1: first negative output terminal, N2: first negative output terminal, 100: output circuit, 10: first differential output circuit, 20: second differential output circuit

Claims

1. An output circuit that outputs an amplitude modulated signal having a voltage value selected from three or more voltage values, a differential circuit disposed between the first power supply line and the second power supply line; a switch and a resistor connected in series to configure a path connecting the first power supply line and the second power supply line; The differential circuit comprises: a first differential output circuit having a first positive output terminal and a first negative output terminal; a second differential output circuit having a second positive output terminal and a second negative output terminal; a first output line connecting the first positive output terminal and the second positive output terminal; a second output line connecting the first negative output terminal and the second negative output terminal, the amplitude modulated signal being output by the first output line and the second output line; the switch and the resistor suppress a change in a value of a current flowing between the first power supply line and the second power supply line due to a change in an operating state of the differential circuit; the output circuit further includes a disconnection unit that disconnects the second differential output circuit from the first differential output circuit.

2. An output circuit comprising:

2. The cutting portion is a first switch disposed on the first output line so as to be capable of disconnecting the second differential output circuit from the first differential output circuit; a second switch disposed on the second output line so as to be able to disconnect the second differential output circuit from the first differential output circuit; 2. The output circuit according to claim 1 .

3. Further comprising a current path provided in parallel with a load connected between the first output line and the second output line, a third switch and a third resistor are disposed in series in the current path; 2. The output circuit according to claim 1 .

4. The operating state of the differential circuit is a first state in which the first differential output circuit and the second differential output circuit drive a load connected between the first output line and the second output line; and a second state in which only the first differential output circuit drives the load.

2. The output circuit according to claim 1 .

5. The switch is conductive in the second state.

5. The output circuit according to claim 4.

6. a value of a current flowing between the first power supply line and the second power supply line through the differential circuit in the first state is equal to a value of a current flowing between the first power supply line and the second power supply line through the differential circuit and the path in the second state; 6. The output circuit according to claim 5.

7. further comprising a capacitor disposed between the first power supply line and the second power supply line; 2. The output circuit according to claim 1 .

8. Further comprising an ESD protection circuit for protecting the differential circuit.

2. The output circuit according to claim 1 .

9. the first differential output circuit includes an eleventh resistor element arranged between the first power supply line and the first positive output terminal, an eleventh switch element arranged between the eleventh resistor element and the first positive output terminal, a twelfth switch element arranged between the eleventh resistor element and the first negative output terminal, a twelfth resistor element arranged between the second power supply line and the first positive output terminal, a thirteenth switch element arranged between the twelfth resistor element and the first positive output terminal, and a fourteenth switch element arranged between the twelfth resistor element and the first negative output terminal, the second differential output circuit includes a 21st resistor element arranged between the first power supply line and the second positive output terminal, a 21st switch element arranged between the 21st resistor element and the second positive output terminal, a 22nd switch element arranged between the 21st resistor element and the second negative output terminal, a 22nd resistor element arranged between the second power supply line and the second negative output terminal, a 23rd switch element arranged between the 22nd resistor element and the second positive output terminal, and a 24th switch element arranged between the 22nd resistor element and the second negative output terminal.

2. The output circuit according to claim 1 .

10. the path is arranged to connect the 21st resistor element and the 22nd resistor element; 10. The output circuit according to claim 9.

11. a first switch disposed between a node connecting the second switch element and the second switch element and the second resistor element; a second switch disposed between a node connecting the 23rd switch element and the 24th switch element and the 22nd resistor element; 10. The output circuit of claim 9, further comprising:

12. the path is arranged to connect the 21st resistor element and the 22nd resistor element; 12. The output circuit according to claim 11 .

13. the first differential output circuit includes: an eleventh switch element arranged between the first power supply line and the first positive output terminal, a twelfth switch element arranged between the first power supply line and the first negative output terminal, a 101st resistor element arranged between the eleventh switch element and the first positive output terminal, a 111th resistor element arranged between the 12th switch element and the first negative output terminal, a thirteenth switch element arranged between the second power supply line and the first positive output terminal, a fourteenth switch element arranged between the second power supply line and the first negative output terminal, a 102nd resistor element arranged between the 13th switch element and the first positive output terminal, and a 112th resistor element arranged between the 14th switch element and the first negative output terminal, the second differential output circuit includes a 21st switch element arranged between the first power supply line and the second positive output terminal, a 22nd switch element arranged between the first power supply line and the second negative output terminal, a 201 resistor element arranged between the 21st switch element and the second positive output terminal, a 211 resistor element arranged between the 22nd switch element and the second negative output terminal, a 23rd switch element arranged between the second power supply line and the second positive output terminal, a 24th switch element arranged between the second power supply line and the second negative output terminal, a 202 resistor element arranged between the 23rd switch element and the second positive output terminal, and a 212 resistor element arranged between the 24th switch element and the second negative output terminal.

2. The output circuit according to claim 1 .

14. A control circuit for controlling the differential circuit and the switch is further provided.

14. An output circuit according to claim 1, wherein the output circuit is a first input.

15. a pixel array having a plurality of pixels; a signal processing unit including an AD conversion unit that converts an analog signal output from the pixel array into a digital signal; an output circuit according to any one of claims 1 to 13, configured to output an amplitude modulated signal having a voltage value selected from three or more voltage values ​​based on a signal output from the signal processing unit; A photoelectric conversion device comprising:

16. The photoelectric conversion device according to claim 15 ; A processor for processing a signal output by the photoelectric conversion device; A photoelectric conversion system comprising:

17. An electronic device comprising the output circuit according to claim 1 .

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